* [PATCH v3] i.MX23/28 Framebuffer support
@ 2011-02-28 8:02 Sascha Hauer
2011-02-28 8:02 ` [PATCH 1/2] video: Add i.MX23/28 framebuffer driver Sascha Hauer
2011-02-28 8:02 ` [PATCH 2/2] ARM i.MX23/28: Add framebuffer device support Sascha Hauer
0 siblings, 2 replies; 24+ messages in thread
From: Sascha Hauer @ 2011-02-28 8:02 UTC (permalink / raw)
To: linux-arm-kernel
Third and hopefully last iteration of these patches.
Sascha
Sascha Hauer (2):
video: Add i.MX23/28 framebuffer driver
ARM i.MX23/28: Add framebuffer device support
arch/arm/mach-mxs/clock-mx23.c | 1 +
arch/arm/mach-mxs/clock-mx28.c | 1 +
arch/arm/mach-mxs/devices-mx23.h | 4 +
arch/arm/mach-mxs/devices-mx28.h | 4 +
arch/arm/mach-mxs/devices/Kconfig | 4 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-mxsfb.c | 46 ++
arch/arm/mach-mxs/include/mach/mxsfb.h | 48 ++
drivers/video/Kconfig | 9 +
drivers/video/Makefile | 1 +
drivers/video/mxsfb.c | 914 ++++++++++++++++++++++++++++
11 files changed, 1033 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-mxsfb.c
create mode 100644 arch/arm/mach-mxs/include/mach/mxsfb.h
create mode 100644 drivers/video/mxsfb.c
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-28 8:02 [PATCH v3] i.MX23/28 Framebuffer support Sascha Hauer @ 2011-02-28 8:02 ` Sascha Hauer 2011-02-28 8:02 ` [PATCH 2/2] ARM i.MX23/28: Add framebuffer device support Sascha Hauer 1 sibling, 0 replies; 24+ messages in thread From: Sascha Hauer @ 2011-02-28 8:02 UTC (permalink / raw) To: linux-arm-kernel changes since v2: - use v3 and v4 for specifying the ip version instead of i.MX23/28. This is a better namespace when future versions are added. - rename mach/fb.h to mach/mxsfb.h changes since v1: - Add a LCDC_ prefix to the register names. - use set/clear registers where appropriate - protect call to mxsfb_disable_controller() in mxsfb_remove() with a (host->enabled) as suggested by Lothar Wassmann Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: linux-fbdev at vger.kernel.org Cc: Shawn Guo <shawn.guo@freescale.com> --- arch/arm/mach-mxs/include/mach/mxsfb.h | 48 ++ drivers/video/Kconfig | 9 + drivers/video/Makefile | 1 + drivers/video/mxsfb.c | 914 ++++++++++++++++++++++++++++++++ 4 files changed, 972 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-mxs/include/mach/mxsfb.h create mode 100644 drivers/video/mxsfb.c diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h new file mode 100644 index 0000000..923f397 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/mxsfb.h @@ -0,0 +1,48 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_FB_H +#define __MACH_FB_H + +#include <linux/fb.h> + +#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ +#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ +#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ +#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ + +#define FB_SYNC_DATA_ENABLE_HIGH_ACT 64 + +struct mxsfb_platform_data { + struct fb_videomode *mode_list; + unsigned mode_count; + + unsigned default_bpp; + + unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ + unsigned ld_intf_width; /* refer STMLCDIF_* macros */ + + unsigned fb_size; /* Size of the video memory. If zero a + * default will be used + */ + unsigned long fb_phys; /* physical address for the video memory. If + * zero the framebuffer memory will be dynamically + * allocated. If specified,fb_size must also be specified. + * fb_phys must be unused by Linux. + */ +}; + +#endif /* __MACH_FB_H */ diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 6bafb51b..e0ea23f 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2365,6 +2365,15 @@ config FB_JZ4740 help Framebuffer support for the JZ4740 SoC. +config FB_MXS + tristate "MXS LCD framebuffer support" + depends on FB && ARCH_MXS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Framebuffer support for the MXS SoC. + source "drivers/video/omap/Kconfig" source "drivers/video/omap2/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 8c8fabd..9a096ae 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -153,6 +153,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o obj-$(CONFIG_FB_MX3) += mx3fb.o obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o +obj-$(CONFIG_FB_MXS) += mxsfb.o # the test framebuffer is last obj-$(CONFIG_FB_VIRTUAL) += vfb.o diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c new file mode 100644 index 0000000..a3b1179 --- /dev/null +++ b/drivers/video/mxsfb.c @@ -0,0 +1,914 @@ +/* + * Copyright (C) 2010 Juergen Beisert, Pengutronix + * + * This code is based on: + * Author: Vitaly Wool <vital@embeddedalley.com> + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DRIVER_NAME "mxsfb" + +/** + * @file + * @brief LCDIF driver for i.MX23 and i.MX28 + * + * The LCDIF support four modes of operation + * - MPU interface (to drive smart displays) -> not supported yet + * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet + * - Dotclock interface (to drive LC displays with RGB data and sync signals) + * - DVI (to drive ITU-R BT656) -> not supported yet + * + * This driver depends on a correct setup of the pins used for this purpose + * (platform specific). + * + * For the developer: Don't forget to set the data bus width to the display + * in the imx_fb_videomode structure. You will else end up with ugly colours. + * If you fight against jitter you can vary the clock delay. This is a feature + * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give + * the required value in the imx_fb_videomode structure. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/dma-mapping.h> +#include <linux/io.h> +#include <mach/mxsfb.h> + +#define REG_SET 4 +#define REG_CLR 8 + +#define LCDC_CTRL 0x00 +#define LCDC_CTRL1 0x10 +#define LCDC_V4_CTRL2 0x20 +#define LCDC_V3_TRANSFER_COUNT 0x20 +#define LCDC_V4_TRANSFER_COUNT 0x30 +#define LCDC_V4_CUR_BUF 0x40 +#define LCDC_V4_NEXT_BUF 0x50 +#define LCDC_V3_CUR_BUF 0x30 +#define LCDC_V3_NEXT_BUF 0x40 +#define LCDC_TIMING 0x60 +#define LCDC_VDCTRL0 0x70 +#define LCDC_VDCTRL1 0x80 +#define LCDC_VDCTRL2 0x90 +#define LCDC_VDCTRL3 0xa0 +#define LCDC_VDCTRL4 0xb0 +#define LCDC_DVICTRL0 0xc0 +#define LCDC_DVICTRL1 0xd0 +#define LCDC_DVICTRL2 0xe0 +#define LCDC_DVICTRL3 0xf0 +#define LCDC_DVICTRL4 0x100 +#define LCDC_V4_DATA 0x180 +#define LCDC_V3_DATA 0x1b0 +#define LCDC_V4_DEBUG0 0x1d0 +#define LCDC_V3_DEBUG0 0x1f0 + +#define CTRL_SFTRST (1 << 31) +#define CTRL_CLKGATE (1 << 30) +#define CTRL_BYPASS_COUNT (1 << 19) +#define CTRL_VSYNC_MODE (1 << 18) +#define CTRL_DOTCLK_MODE (1 << 17) +#define CTRL_DATA_SELECT (1 << 16) +#define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10) +#define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3) +#define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8) +#define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) +#define CTRL_MASTER (1 << 5) +#define CTRL_DF16 (1 << 3) +#define CTRL_DF18 (1 << 2) +#define CTRL_DF24 (1 << 1) +#define CTRL_RUN (1 << 0) + +#define CTRL1_FIFO_CLEAR (1 << 21) +#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) +#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) + +#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16) +#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff) +#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff) +#define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff) + + +#define VDCTRL0_ENABLE_PRESENT (1 << 28) +#define VDCTRL0_VSYNC_ACT_HIGH (1 << 27) +#define VDCTRL0_HSYNC_ACT_HIGH (1 << 26) +#define VDCTRL0_DOTCLK_ACTIVE_HIGH (1 << 25) +#define VDCTRL0_POL_ACTIVE_HIGH (1 << 24) +#define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) +#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) +#define VDCTRL0_HALF_LINE (1 << 19) +#define VDCTRL0_HALF_LINE_MODE (1 << 18) +#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) +#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) + +#define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) +#define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) + +#define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) +#define VDCTRL3_VSYNC_ONLY (1 << 28) +#define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) +#define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) +#define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) +#define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) + +#define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */ +#define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */ +#define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) +#define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) + +#define DEBUG0_HSYNC (1 < 26) +#define DEBUG0_VSYNC (1 < 25) + +#define MIN_XRES 120 +#define MIN_YRES 120 + +#define RED 0 +#define GREEN 1 +#define BLUE 2 +#define TRANSP 3 + +enum mxsfb_devtype { + MXSFB_V3, + MXSFB_V4, +}; + +/* CPU dependent register offsets */ +struct mxsfb_devdata { + unsigned transfer_count; + unsigned cur_buf; + unsigned next_buf; + unsigned debug0; + unsigned hs_wdth_mask; + unsigned hs_wdth_shift; + unsigned ipversion; +}; + +struct mxsfb_info { + struct fb_info fb_info; + struct platform_device *pdev; + struct clk *clk; + void __iomem *base; /* registers */ + unsigned allocated_size; + int enabled; + unsigned ld_intf_width; + unsigned dotclk_delay; + const struct mxsfb_devdata *devdata; + int mapped; +}; + +#define mxsfb_is_v3(host) (host->devdata->ipversion == 3) +#define mxsfb_is_v4(host) (host->devdata->ipversion == 4) + +static const struct mxsfb_devdata mxsfb_devdata[] = { + [MXSFB_V3] = { + .transfer_count = LCDC_V3_TRANSFER_COUNT, + .cur_buf = LCDC_V3_CUR_BUF, + .next_buf = LCDC_V3_NEXT_BUF, + .debug0 = LCDC_V3_DEBUG0, + .hs_wdth_mask = 0xff, + .hs_wdth_shift = 24, + .ipversion = 3, + }, + [MXSFB_V4] = { + .transfer_count = LCDC_V4_TRANSFER_COUNT, + .cur_buf = LCDC_V4_CUR_BUF, + .next_buf = LCDC_V4_NEXT_BUF, + .debug0 = LCDC_V4_DEBUG0, + .hs_wdth_mask = 0x3fff, + .hs_wdth_shift = 18, + .ipversion = 4, + }, +}; + +#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info)) + +/* mask and shift depends on architecture */ +static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val) +{ + return (val & host->devdata->hs_wdth_mask) << + host->devdata->hs_wdth_shift; +} + +static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val) +{ + return (val >> host->devdata->hs_wdth_shift) & + host->devdata->hs_wdth_mask; +} + +static const struct fb_bitfield def_rgb565[] = { + [RED] = { + .offset = 11, + .length = 5, + }, + [GREEN] = { + .offset = 5, + .length = 6, + }, + [BLUE] = { + .offset = 0, + .length = 5, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static const struct fb_bitfield def_rgb666[] = { + [RED] = { + .offset = 16, + .length = 6, + }, + [GREEN] = { + .offset = 8, + .length = 6, + }, + [BLUE] = { + .offset = 0, + .length = 6, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static const struct fb_bitfield def_rgb888[] = { + [RED] = { + .offset = 16, + .length = 8, + }, + [GREEN] = { + .offset = 8, + .length = 8, + }, + [BLUE] = { + .offset = 0, + .length = 8, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} + +static int mxsfb_check_var(struct fb_var_screeninfo *var, + struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + const struct fb_bitfield *rgb = NULL; + + if (var->xres < MIN_XRES) + var->xres = MIN_XRES; + if (var->yres < MIN_YRES) + var->yres = MIN_YRES; + + var->xres_virtual = var->xres; + + var->yres_virtual = var->yres; + + switch (var->bits_per_pixel) { + case 16: + /* always expect RGB 565 */ + rgb = def_rgb565; + break; + case 32: + switch (host->ld_intf_width) { + case STMLCDIF_8BIT: + pr_debug("Unsupported LCD bus width mapping\n"); + break; + case STMLCDIF_16BIT: + case STMLCDIF_18BIT: + /* 24 bit to 18 bit mapping */ + rgb = def_rgb666; + break; + case STMLCDIF_24BIT: + /* real 24 bit */ + rgb = def_rgb888; + break; + } + break; + default: + pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel); + return -EINVAL; + } + + /* + * Copy the RGB parameters for this display + * from the machine specific parameters. + */ + var->red = rgb[RED]; + var->green = rgb[GREEN]; + var->blue = rgb[BLUE]; + var->transp = rgb[TRANSP]; + + return 0; +} + +static void mxsfb_enable_controller(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + u32 reg; + + dev_dbg(&host->pdev->dev, "%s\n", __func__); + + clk_enable(host->clk); + clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U); + + /* if it was disabled, re-enable the mode again */ + writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET); + + /* enable the SYNC signals first, then the DMA engine */ + reg = readl(host->base + LCDC_VDCTRL4); + reg |= VDCTRL4_SYNC_SIGNALS_ON; + writel(reg, host->base + LCDC_VDCTRL4); + + writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET); + + host->enabled = 1; +} + +static void mxsfb_disable_controller(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + unsigned loop; + u32 reg; + + dev_dbg(&host->pdev->dev, "%s\n", __func__); + + /* + * Even if we disable the controller here, it will still continue + * until its FIFOs are running out of data + */ + writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR); + + loop = 1000; + while (loop) { + reg = readl(host->base + LCDC_CTRL); + if (!(reg & CTRL_RUN)) + break; + loop--; + } + + writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR); + + clk_disable(host->clk); + + host->enabled = 0; +} + +static int mxsfb_set_par(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + u32 ctrl, vdctrl0, vdctrl4; + int line_size, fb_size; + int reenable = 0; + + line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3); + fb_size = fb_info->var.yres_virtual * line_size; + + if (fb_size > fb_info->fix.smem_len) + return -ENOMEM; + + fb_info->fix.line_length = line_size; + + /* + * It seems, you can't re-program the controller if it is still running. + * This may lead into shifted pictures (FIFO issue?). + * So, first stop the controller and drain its FIFOs + */ + if (host->enabled) { + reenable = 1; + mxsfb_disable_controller(fb_info); + } + + /* clear the FIFOs */ + writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET); + + ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER | + CTRL_SET_BUS_WIDTH(host->ld_intf_width);; + + switch (fb_info->var.bits_per_pixel) { + case 16: + dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n"); + ctrl |= CTRL_SET_WORD_LENGTH(0); + writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1); + break; + case 32: + dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n"); + ctrl |= CTRL_SET_WORD_LENGTH(3); + switch (host->ld_intf_width) { + case STMLCDIF_8BIT: + dev_dbg(&host->pdev->dev, + "Unsupported LCD bus width mapping\n"); + return -EINVAL; + case STMLCDIF_16BIT: + case STMLCDIF_18BIT: + /* 24 bit to 18 bit mapping */ + ctrl |= CTRL_DF24; /* ignore the upper 2 bits in + * each colour component + */ + break; + case STMLCDIF_24BIT: + /* real 24 bit */ + break; + } + /* do not use packed pixels = one pixel per word instead */ + writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1); + break; + default: + dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n", + fb_info->var.bits_per_pixel); + return -EINVAL; + } + + writel(ctrl, host->base + LCDC_CTRL); + + writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) | + TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres), + host->base + host->devdata->transfer_count); + + vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */ + VDCTRL0_VSYNC_PERIOD_UNIT | + VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | + VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len); + if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT) + vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; + if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT) + vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; + if (fb_info->var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT) + vdctrl0 |= VDCTRL0_POL_ACTIVE_HIGH; + + writel(vdctrl0, host->base + LCDC_VDCTRL0); + + /* frame length in lines */ + writel(fb_info->var.upper_margin + fb_info->var.vsync_len + + fb_info->var.lower_margin + fb_info->var.yres, + host->base + LCDC_VDCTRL1); + + /* line length in units of clocks or pixels */ + writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) | + VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin + + fb_info->var.hsync_len + fb_info->var.right_margin + + fb_info->var.xres), + host->base + LCDC_VDCTRL2); + + writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin + + fb_info->var.hsync_len) | + SET_VERT_WAIT_CNT(fb_info->var.upper_margin + + fb_info->var.vsync_len), + host->base + LCDC_VDCTRL3); + + vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres); + if (mxsfb_is_v4(host)) + vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay); + writel(vdctrl4, host->base + LCDC_VDCTRL4); + + writel(fb_info->fix.smem_start + + fb_info->fix.line_length * fb_info->var.yoffset, + host->base + host->devdata->next_buf); + + if (reenable) + mxsfb_enable_controller(fb_info); + + return 0; +} + +static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + u_int transp, struct fb_info *fb_info) +{ + unsigned int val; + int ret = -EINVAL; + + /* + * If greyscale is true, then we convert the RGB value + * to greyscale no matter what visual we are using. + */ + if (fb_info->var.grayscale) + red = green = blue = (19595 * red + 38470 * green + + 7471 * blue) >> 16; + + switch (fb_info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + /* + * 12 or 16-bit True Colour. We encode the RGB value + * according to the RGB bitfield information. + */ + if (regno < 16) { + u32 *pal = fb_info->pseudo_palette; + + val = chan_to_field(red, &fb_info->var.red); + val |= chan_to_field(green, &fb_info->var.green); + val |= chan_to_field(blue, &fb_info->var.blue); + + pal[regno] = val; + ret = 0; + } + break; + + case FB_VISUAL_STATIC_PSEUDOCOLOR: + case FB_VISUAL_PSEUDOCOLOR: + break; + } + + return ret; +} + +static int mxsfb_blank(int blank, struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + + switch (blank) { + case FB_BLANK_POWERDOWN: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + if (host->enabled) + mxsfb_disable_controller(fb_info); + break; + + case FB_BLANK_UNBLANK: + if (!host->enabled) + mxsfb_enable_controller(fb_info); + break; + } + return 0; +} + +static int mxsfb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + unsigned offset; + + if (var->xoffset != 0) + return -EINVAL; + + offset = fb_info->fix.line_length * var->yoffset; + + /* update on next VSYNC */ + writel(fb_info->fix.smem_start + offset, + host->base + host->devdata->next_buf); + + return 0; +} + +static struct fb_ops mxsfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = mxsfb_check_var, + .fb_set_par = mxsfb_set_par, + .fb_setcolreg = mxsfb_setcolreg, + .fb_blank = mxsfb_blank, + .fb_pan_display = mxsfb_pan_display, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +}; + +static int __devinit mxsfb_restore_mode(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + unsigned line_count; + unsigned period; + unsigned long pa, fbsize; + int bits_per_pixel, ofs; + u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; + struct fb_videomode vmode; + + /* Only restore the mode when the controller is running */ + ctrl = readl(host->base + LCDC_CTRL); + if (!(ctrl & CTRL_RUN)) + return -EINVAL; + + vdctrl0 = readl(host->base + LCDC_VDCTRL0); + vdctrl2 = readl(host->base + LCDC_VDCTRL2); + vdctrl3 = readl(host->base + LCDC_VDCTRL3); + vdctrl4 = readl(host->base + LCDC_VDCTRL4); + + transfer_count = readl(host->base + host->devdata->transfer_count); + + vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count); + vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count); + + switch (CTRL_GET_WORD_LENGTH(ctrl)) { + case 0: + bits_per_pixel = 16; + break; + case 3: + bits_per_pixel = 32; + case 1: + default: + return -EINVAL; + } + + fb_info->var.bits_per_pixel = bits_per_pixel; + + vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U); + vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2); + vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len; + vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len - + vmode.left_margin - vmode.xres; + vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0); + period = readl(host->base + LCDC_VDCTRL1); + vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len; + vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres; + + vmode.vmode = FB_VMODE_NONINTERLACED; + + vmode.sync = 0; + if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH) + vmode.sync |= FB_SYNC_HOR_HIGH_ACT; + if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH) + vmode.sync |= FB_SYNC_VERT_HIGH_ACT; + + pr_debug("Reconstructed video mode:\n"); + pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n", + vmode.xres, vmode.yres, + vmode.hsync_len, vmode.left_margin, vmode.right_margin, + vmode.vsync_len, vmode.upper_margin, vmode.lower_margin); + pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock)); + + fb_add_videomode(&vmode, &fb_info->modelist); + + host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl); + host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4); + + fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3); + + pa = readl(host->base + host->devdata->cur_buf); + fbsize = fb_info->fix.line_length * vmode.yres; + if (pa < fb_info->fix.smem_start) + return -EINVAL; + if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) + return -EINVAL; + ofs = pa - fb_info->fix.smem_start; + if (ofs) { + memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize); + writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf); + } + + line_count = fb_info->fix.smem_len / fb_info->fix.line_length; + fb_info->fix.ypanstep = 1; + + clk_enable(host->clk); + host->enabled = 1; + + return 0; +} + +static int __devinit mxsfb_init_fbinfo(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + struct fb_var_screeninfo *var = &fb_info->var; + struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data; + dma_addr_t fb_phys; + void *fb_virt; + unsigned fb_size = pdata->fb_size; + + fb_info->fbops = &mxsfb_ops; + fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; + strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id)); + fb_info->fix.type = FB_TYPE_PACKED_PIXELS; + fb_info->fix.ypanstep = 1; + fb_info->fix.visual = FB_VISUAL_TRUECOLOR, + fb_info->fix.accel = FB_ACCEL_NONE; + + var->bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16; + var->nonstd = 0; + var->activate = FB_ACTIVATE_NOW; + var->accel_flags = 0; + var->vmode = FB_VMODE_NONINTERLACED; + + host->dotclk_delay = pdata->dotclk_delay; + host->ld_intf_width = pdata->ld_intf_width; + + /* Memory allocation for framebuffer */ + if (pdata->fb_phys) { + if (!fb_size) + return -EINVAL; + + fb_phys = pdata->fb_phys; + + if (!request_mem_region(fb_phys, fb_size, host->pdev->name)) + return -ENOMEM; + + fb_virt = ioremap(fb_phys, fb_size); + if (!fb_virt) { + release_mem_region(fb_phys, fb_size); + return -ENOMEM; + } + host->mapped = 1; + } else { + if (!fb_size) + fb_size = SZ_2M; /* default */ + fb_virt = alloc_pages_exact(fb_size, GFP_DMA); + if (!fb_info->screen_base) + return -ENOMEM; + + fb_phys = virt_to_phys(fb_virt); + } + + fb_info->fix.smem_start = fb_phys; + fb_info->screen_base = fb_virt; + fb_info->screen_size = fb_info->fix.smem_len = fb_size; + + if (mxsfb_restore_mode(host)) + memset(fb_virt, 0, fb_size); + + return 0; +} + +static void __devexit mxsfb_free_videomem(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + + if (host->mapped) { + iounmap(fb_info->screen_base); + release_mem_region(fb_info->fix.smem_start, + fb_info->screen_size); + } else { + free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len); + } +} + +static int __devinit mxsfb_probe(struct platform_device *pdev) +{ + struct mxsfb_platform_data *pdata = pdev->dev.platform_data; + struct resource *res; + struct mxsfb_info *host; + struct fb_info *fb_info; + struct fb_modelist *modelist; + int i, ret; + + if (!pdata) { + dev_err(&pdev->dev, "No platformdata. Giving up\n"); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Cannot get memory IO resource\n"); + return -ENODEV; + } + + if (!request_mem_region(res->start, resource_size(res), pdev->name)) + return -EBUSY; + + fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev); + if (!fb_info) { + dev_err(&pdev->dev, "Failed to allocate fbdev\n"); + ret = -ENOMEM; + goto error_alloc_info; + } + + host = to_imxfb_host(fb_info); + + host->base = ioremap(res->start, resource_size(res)); + if (!host->base) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto error_ioremap; + } + + host->pdev = pdev; + platform_set_drvdata(pdev, host); + + host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data]; + + host->clk = clk_get(&host->pdev->dev, NULL); + if (IS_ERR(host->clk)) { + ret = PTR_ERR(host->clk); + goto error_getclock; + } + + fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); + if (!fb_info->pseudo_palette) { + ret = -ENOMEM; + goto error_pseudo_pallette; + } + + INIT_LIST_HEAD(&fb_info->modelist); + + ret = mxsfb_init_fbinfo(host); + if (ret != 0) + goto error_init_fb; + + for (i = 0; i < pdata->mode_count; i++) + fb_add_videomode(&pdata->mode_list[i], &fb_info->modelist); + + modelist = list_first_entry(&fb_info->modelist, + struct fb_modelist, list); + fb_videomode_to_var(&fb_info->var, &modelist->mode); + + /* init the color fields */ + mxsfb_check_var(&fb_info->var, fb_info); + + platform_set_drvdata(pdev, fb_info); + + ret = register_framebuffer(fb_info); + if (ret != 0) { + dev_err(&pdev->dev,"Failed to register framebuffer\n"); + goto error_register; + } + + if (!host->enabled) { + writel(0, host->base + LCDC_CTRL); + mxsfb_set_par(fb_info); + mxsfb_enable_controller(fb_info); + } + + return 0; + +error_register: + if (host->enabled) + clk_disable(host->clk); + fb_destroy_modelist(&fb_info->modelist); +error_init_fb: + kfree(fb_info->pseudo_palette); +error_pseudo_pallette: + clk_put(host->clk); +error_getclock: + iounmap(host->base); +error_ioremap: + framebuffer_release(fb_info); +error_alloc_info: + release_mem_region(res->start, resource_size(res)); + + return ret; +} + +static int __devexit mxsfb_remove(struct platform_device *pdev) +{ + struct fb_info *fb_info = platform_get_drvdata(pdev); + struct mxsfb_info *host = to_imxfb_host(fb_info); + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (host->enabled) + mxsfb_disable_controller(fb_info); + + unregister_framebuffer(fb_info); + kfree(fb_info->pseudo_palette); + mxsfb_free_videomem(host); + iounmap(host->base); + clk_put(host->clk); + + framebuffer_release(fb_info); + release_mem_region(res->start, resource_size(res)); + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_device_id mxsfb_devtype[] = { + { + .name = "imx23-fb", + .driver_data = MXSFB_V3, + }, { + .name = "imx28-fb", + .driver_data = MXSFB_V4, + }, { + }, +}; +MODULE_DEVICE_TABLE(platform, mxsfb_devtype); + +static struct platform_driver mxsfb_driver = { + .probe = mxsfb_probe, + .remove = __devexit_p(mxsfb_remove), + .id_table = mxsfb_devtype, + .driver = { + .name = DRIVER_NAME, + }, +}; + +static int __init mxsfb_init(void) +{ + return platform_driver_register(&mxsfb_driver); +} + +static void __exit mxsfb_exit(void) +{ + platform_driver_unregister(&mxsfb_driver); +} + +module_init(mxsfb_init); +module_exit(mxsfb_exit); + +MODULE_DESCRIPTION("Freescale mxs framebuffer driver"); +MODULE_AUTHOR("Sascha Hauer, Pengutronix"); +MODULE_LICENSE("GPL"); -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/2] ARM i.MX23/28: Add framebuffer device support 2011-02-28 8:02 [PATCH v3] i.MX23/28 Framebuffer support Sascha Hauer 2011-02-28 8:02 ` [PATCH 1/2] video: Add i.MX23/28 framebuffer driver Sascha Hauer @ 2011-02-28 8:02 ` Sascha Hauer 1 sibling, 0 replies; 24+ messages in thread From: Sascha Hauer @ 2011-02-28 8:02 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawn.guo@freescale.com> --- arch/arm/mach-mxs/clock-mx23.c | 1 + arch/arm/mach-mxs/clock-mx28.c | 1 + arch/arm/mach-mxs/devices-mx23.h | 4 ++ arch/arm/mach-mxs/devices-mx28.h | 4 ++ arch/arm/mach-mxs/devices/Kconfig | 4 ++ arch/arm/mach-mxs/devices/Makefile | 1 + arch/arm/mach-mxs/devices/platform-mxsfb.c | 46 ++++++++++++++++++++++++++++ 7 files changed, 61 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-mxs/devices/platform-mxsfb.c diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index ca72a05..efd84f5 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -447,6 +447,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "usb", usb_clk) _REGISTER_CLOCK(NULL, "audio", audio_clk) _REGISTER_CLOCK(NULL, "pwm", pwm_clk) + _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk) }; static int clk_misc_init(void) diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index fd1c4c5..6a7ebcb 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -620,6 +620,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "pwm", pwm_clk) _REGISTER_CLOCK(NULL, "lradc", lradc_clk) _REGISTER_CLOCK(NULL, "spdif", spdif_clk) + _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk) }; static int clk_misc_init(void) diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index 1256788..88c00f2 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -10,7 +10,11 @@ */ #include <mach/mx23.h> #include <mach/devices-common.h> +#include <mach/mxsfb.h> extern const struct amba_device mx23_duart_device __initconst; #define mx23_add_duart() \ mxs_add_duart(&mx23_duart_device) + +struct platform_device *__init mx23_add_mxsfb( + const struct mxsfb_platform_data *pdata); diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 33773a6..64740cb 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -10,6 +10,7 @@ */ #include <mach/mx28.h> #include <mach/devices-common.h> +#include <mach/mxsfb.h> extern const struct amba_device mx28_duart_device __initconst; #define mx28_add_duart() \ @@ -18,3 +19,6 @@ extern const struct amba_device mx28_duart_device __initconst; extern const struct mxs_fec_data mx28_fec_data[] __initconst; #define mx28_add_fec(id, pdata) \ mxs_add_fec(&mx28_fec_data[id], pdata) + +struct platform_device *__init mx28_add_mxsfb( + const struct mxsfb_platform_data *pdata); diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index cf7dc1a..1538cb9 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig @@ -4,3 +4,7 @@ config MXS_HAVE_AMBA_DUART config MXS_HAVE_PLATFORM_FEC bool + +config MXS_HAVE_PLATFORM_MXSFB + bool + diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index d0a09f6..0cf8b48 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o +obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c new file mode 100644 index 0000000..bf72c9b --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/mx23.h> +#include <mach/mx28.h> +#include <mach/devices-common.h> +#include <mach/mxsfb.h> + +#ifdef CONFIG_SOC_IMX23 +struct platform_device *__init mx23_add_mxsfb( + const struct mxsfb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = MX23_LCDIF_BASE_ADDR, + .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return mxs_add_platform_device_dmamask("imx23-fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} +#endif /* ifdef CONFIG_SOC_IMX23 */ + +#ifdef CONFIG_SOC_IMX28 +struct platform_device *__init mx28_add_mxsfb( + const struct mxsfb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = MX28_LCDIF_BASE_ADDR, + .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return mxs_add_platform_device_dmamask("imx28-fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} +#endif /* ifdef CONFIG_SOC_IMX28 */ -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2] i.MX23/28 Framebuffer driver
@ 2011-02-16 9:56 Sascha Hauer
2011-02-16 9:56 ` [PATCH 1/2] video: Add i.MX23/28 framebuffer driver Sascha Hauer
0 siblings, 1 reply; 24+ messages in thread
From: Sascha Hauer @ 2011-02-16 9:56 UTC (permalink / raw)
To: linux-arm-kernel
This is the second version of the i.MX23/28 fb driver with
the changes integrated from the last review.
Sascha Hauer (2):
video: Add i.MX23/28 framebuffer driver
ARM i.MX23/28: Add framebuffer device support
arch/arm/mach-mxs/clock-mx23.c | 2 +-
arch/arm/mach-mxs/clock-mx28.c | 1 +
arch/arm/mach-mxs/devices-mx23.h | 4 +
arch/arm/mach-mxs/devices-mx28.h | 4 +
arch/arm/mach-mxs/devices/Kconfig | 4 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-mxsfb.c | 46 ++
arch/arm/mach-mxs/include/mach/fb.h | 48 ++
drivers/video/Kconfig | 9 +
drivers/video/Makefile | 1 +
drivers/video/mxsfb.c | 910 ++++++++++++++++++++++++++++
11 files changed, 1029 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-mxsfb.c
create mode 100644 arch/arm/mach-mxs/include/mach/fb.h
create mode 100644 drivers/video/mxsfb.c
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-16 9:56 [PATCH v2] i.MX23/28 Framebuffer driver Sascha Hauer @ 2011-02-16 9:56 ` Sascha Hauer 2011-02-18 5:24 ` Shawn Guo 2011-02-18 12:29 ` Shawn Guo 0 siblings, 2 replies; 24+ messages in thread From: Sascha Hauer @ 2011-02-16 9:56 UTC (permalink / raw) To: linux-arm-kernel changes since v1: - Add a LCDC_ prefix to the register names. - use set/clear registers where appropriate - protect call to mxsfb_disable_controller() in mxsfb_remove() with a (host->enabled) as suggested by Lothar Wassmann Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: linux-fbdev at vger.kernel.org Cc: Shawn Guo <shawn.guo@freescale.com> --- arch/arm/mach-mxs/include/mach/fb.h | 48 ++ drivers/video/Kconfig | 9 + drivers/video/Makefile | 1 + drivers/video/mxsfb.c | 910 +++++++++++++++++++++++++++++++++++ 4 files changed, 968 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-mxs/include/mach/fb.h create mode 100644 drivers/video/mxsfb.c diff --git a/arch/arm/mach-mxs/include/mach/fb.h b/arch/arm/mach-mxs/include/mach/fb.h new file mode 100644 index 0000000..923f397 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/fb.h @@ -0,0 +1,48 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_FB_H +#define __MACH_FB_H + +#include <linux/fb.h> + +#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ +#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ +#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ +#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ + +#define FB_SYNC_DATA_ENABLE_HIGH_ACT 64 + +struct mxsfb_platform_data { + struct fb_videomode *mode_list; + unsigned mode_count; + + unsigned default_bpp; + + unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ + unsigned ld_intf_width; /* refer STMLCDIF_* macros */ + + unsigned fb_size; /* Size of the video memory. If zero a + * default will be used + */ + unsigned long fb_phys; /* physical address for the video memory. If + * zero the framebuffer memory will be dynamically + * allocated. If specified,fb_size must also be specified. + * fb_phys must be unused by Linux. + */ +}; + +#endif /* __MACH_FB_H */ diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 6bafb51b..e0ea23f 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2365,6 +2365,15 @@ config FB_JZ4740 help Framebuffer support for the JZ4740 SoC. +config FB_MXS + tristate "MXS LCD framebuffer support" + depends on FB && ARCH_MXS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Framebuffer support for the MXS SoC. + source "drivers/video/omap/Kconfig" source "drivers/video/omap2/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 8c8fabd..9a096ae 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -153,6 +153,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o obj-$(CONFIG_FB_MX3) += mx3fb.o obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o +obj-$(CONFIG_FB_MXS) += mxsfb.o # the test framebuffer is last obj-$(CONFIG_FB_VIRTUAL) += vfb.o diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c new file mode 100644 index 0000000..ac9939b --- /dev/null +++ b/drivers/video/mxsfb.c @@ -0,0 +1,910 @@ +/* + * Copyright (C) 2010 Juergen Beisert, Pengutronix + * + * This code is based on: + * Author: Vitaly Wool <vital@embeddedalley.com> + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DRIVER_NAME "mxsfb" + +/** + * @file + * @brief LCDIF driver for i.MX23 and i.MX28 + * + * The LCDIF support four modes of operation + * - MPU interface (to drive smart displays) -> not supported yet + * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet + * - Dotclock interface (to drive LC displays with RGB data and sync signals) + * - DVI (to drive ITU-R BT656) -> not supported yet + * + * This driver depends on a correct setup of the pins used for this purpose + * (platform specific). + * + * For the developer: Don't forget to set the data bus width to the display + * in the imx_fb_videomode structure. You will else end up with ugly colours. + * If you fight against jitter you can vary the clock delay. This is a feature + * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give + * the required value in the imx_fb_videomode structure. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/dma-mapping.h> +#include <linux/io.h> +#include <mach/fb.h> +#include <mach/hardware.h> +#include <mach/mxs.h> + +#define REG_SET 4 +#define REG_CLR 8 + +#define LCDC_CTRL 0x00 +#define LCDC_CTRL1 0x10 +#define LCDC_MX28_CTRL2 0x20 +#define LCDC_MX23_TRANSFER_COUNT 0x20 +#define LCDC_MX28_TRANSFER_COUNT 0x30 +#define LCDC_MX28_CUR_BUF 0x40 +#define LCDC_MX28_NEXT_BUF 0x50 +#define LCDC_MX23_CUR_BUF 0x30 +#define LCDC_MX23_NEXT_BUF 0x40 +#define LCDC_TIMING 0x60 +#define LCDC_VDCTRL0 0x70 +#define LCDC_VDCTRL1 0x80 +#define LCDC_VDCTRL2 0x90 +#define LCDC_VDCTRL3 0xa0 +#define LCDC_VDCTRL4 0xb0 +#define LCDC_DVICTRL0 0xc0 +#define LCDC_DVICTRL1 0xd0 +#define LCDC_DVICTRL2 0xe0 +#define LCDC_DVICTRL3 0xf0 +#define LCDC_DVICTRL4 0x100 +#define LCDC_MX28_DATA 0x180 +#define LCDC_MX23_DATA 0x1b0 +#define LCDC_MX28_DEBUG0 0x1d0 +#define LCDC_MX23_DEBUG0 0x1f0 + +#define CTRL_SFTRST (1 << 31) +#define CTRL_CLKGATE (1 << 30) +#define CTRL_BYPASS_COUNT (1 << 19) +#define CTRL_VSYNC_MODE (1 << 18) +#define CTRL_DOTCLK_MODE (1 << 17) +#define CTRL_DATA_SELECT (1 << 16) +#define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10) +#define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3) +#define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8) +#define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) +#define CTRL_MASTER (1 << 5) +#define CTRL_DF16 (1 << 3) +#define CTRL_DF18 (1 << 2) +#define CTRL_DF24 (1 << 1) +#define CTRL_RUN (1 << 0) + +#define CTRL1_FIFO_CLEAR (1 << 21) +#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) +#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) + +#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16) +#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff) +#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff) +#define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff) + + +#define VDCTRL0_ENABLE_PRESENT (1 << 28) +#define VDCTRL0_VSYNC_ACT_HIGH (1 << 27) +#define VDCTRL0_HSYNC_ACT_HIGH (1 << 26) +#define VDCTRL0_DOTCLK_ACTIVE_HIGH (1 << 25) +#define VDCTRL0_POL_ACTIVE_HIGH (1 << 24) +#define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) +#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) +#define VDCTRL0_HALF_LINE (1 << 19) +#define VDCTRL0_HALF_LINE_MODE (1 << 18) +#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) +#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) + +#define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) +#define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) + +#define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) +#define VDCTRL3_VSYNC_ONLY (1 << 28) +#define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) +#define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) +#define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) +#define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) + +#define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* i.MX28 only */ +#define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* i.MX28 only */ +#define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) +#define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) + +#define DEBUG0_HSYNC (1 < 26) +#define DEBUG0_VSYNC (1 < 25) + +#define MIN_XRES 120 +#define MIN_YRES 120 + +#define RED 0 +#define GREEN 1 +#define BLUE 2 +#define TRANSP 3 + +enum mxsfb_devtype { + MXSFB_MX23, + MXSFB_MX28, +}; + +/* CPU dependent register offsets */ +struct mxsfb_devdata { + unsigned transfer_count; + unsigned cur_buf; + unsigned next_buf; + unsigned debug0; + unsigned hs_wdth_mask; + unsigned hs_wdth_shift; +}; + +struct mxsfb_info { + struct fb_info fb_info; + struct platform_device *pdev; + struct clk *clk; + void __iomem *base; /* registers */ + unsigned allocated_size; + int enabled; + unsigned ld_intf_width; + unsigned dotclk_delay; + const struct mxsfb_devdata *devdata; + int mapped; +}; + +static const struct mxsfb_devdata mxsfb_devdata[] = { + [MXSFB_MX23] = { + .transfer_count = LCDC_MX23_TRANSFER_COUNT, + .cur_buf = LCDC_MX23_CUR_BUF, + .next_buf = LCDC_MX23_NEXT_BUF, + .debug0 = LCDC_MX23_DEBUG0, + .hs_wdth_mask = 0xff, + .hs_wdth_shift = 24, + }, + [MXSFB_MX28] = { + .transfer_count = LCDC_MX28_TRANSFER_COUNT, + .cur_buf = LCDC_MX28_CUR_BUF, + .next_buf = LCDC_MX28_NEXT_BUF, + .debug0 = LCDC_MX28_DEBUG0, + .hs_wdth_mask = 0x3fff, + .hs_wdth_shift = 18, + }, +}; + +#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info)) + +/* mask and shift depends on architecture */ +static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val) +{ + return (val & host->devdata->hs_wdth_mask) << + host->devdata->hs_wdth_shift; +} + +static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val) +{ + return (val >> host->devdata->hs_wdth_shift) & + host->devdata->hs_wdth_mask; +} + +static const struct fb_bitfield def_rgb565[] = { + [RED] = { + .offset = 11, + .length = 5, + }, + [GREEN] = { + .offset = 5, + .length = 6, + }, + [BLUE] = { + .offset = 0, + .length = 5, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static const struct fb_bitfield def_rgb666[] = { + [RED] = { + .offset = 16, + .length = 6, + }, + [GREEN] = { + .offset = 8, + .length = 6, + }, + [BLUE] = { + .offset = 0, + .length = 6, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static const struct fb_bitfield def_rgb888[] = { + [RED] = { + .offset = 16, + .length = 8, + }, + [GREEN] = { + .offset = 8, + .length = 8, + }, + [BLUE] = { + .offset = 0, + .length = 8, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} + +static int mxsfb_check_var(struct fb_var_screeninfo *var, + struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + const struct fb_bitfield *rgb = NULL; + + if (var->xres < MIN_XRES) + var->xres = MIN_XRES; + if (var->yres < MIN_YRES) + var->yres = MIN_YRES; + + var->xres_virtual = var->xres; + + var->yres_virtual = var->yres; + + switch (var->bits_per_pixel) { + case 16: + /* always expect RGB 565 */ + rgb = def_rgb565; + break; + case 32: + switch (host->ld_intf_width) { + case STMLCDIF_8BIT: + pr_debug("Unsupported LCD bus width mapping\n"); + break; + case STMLCDIF_16BIT: + case STMLCDIF_18BIT: + /* 24 bit to 18 bit mapping */ + rgb = def_rgb666; + break; + case STMLCDIF_24BIT: + /* real 24 bit */ + rgb = def_rgb888; + break; + } + break; + default: + pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel); + return -EINVAL; + } + + /* + * Copy the RGB parameters for this display + * from the machine specific parameters. + */ + var->red = rgb[RED]; + var->green = rgb[GREEN]; + var->blue = rgb[BLUE]; + var->transp = rgb[TRANSP]; + + return 0; +} + +static void mxsfb_enable_controller(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + u32 reg; + + dev_dbg(&host->pdev->dev, "%s\n", __func__); + + clk_enable(host->clk); + clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U); + + /* if it was disabled, re-enable the mode again */ + writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET); + + /* enable the SYNC signals first, then the DMA engine */ + reg = readl(host->base + LCDC_VDCTRL4); + reg |= VDCTRL4_SYNC_SIGNALS_ON; + writel(reg, host->base + LCDC_VDCTRL4); + + writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET); + + host->enabled = 1; +} + +static void mxsfb_disable_controller(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + unsigned loop; + u32 reg; + + dev_dbg(&host->pdev->dev, "%s\n", __func__); + + /* + * Even if we disable the controller here, it will still continue + * until its FIFOs are running out of data + */ + writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR); + + loop = 1000; + while (loop) { + reg = readl(host->base + LCDC_CTRL); + if (!(reg & CTRL_RUN)) + break; + loop--; + } + + writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR); + + clk_disable(host->clk); + + host->enabled = 0; +} + +static int mxsfb_set_par(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + u32 ctrl, vdctrl0, vdctrl4; + int line_size, fb_size; + int reenable = 0; + + line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3); + fb_size = fb_info->var.yres_virtual * line_size; + + if (fb_size > fb_info->fix.smem_len) + return -ENOMEM; + + fb_info->fix.line_length = line_size; + + /* + * It seems, you can't re-program the controller if it is still running. + * This may lead into shifted pictures (FIFO issue?). + * So, first stop the controller and drain its FIFOs + */ + if (host->enabled) { + reenable = 1; + mxsfb_disable_controller(fb_info); + } + + /* clear the FIFOs */ + writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET); + + ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER | + CTRL_SET_BUS_WIDTH(host->ld_intf_width);; + + switch (fb_info->var.bits_per_pixel) { + case 16: + dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n"); + ctrl |= CTRL_SET_WORD_LENGTH(0); + writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1); + break; + case 32: + dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n"); + ctrl |= CTRL_SET_WORD_LENGTH(3); + switch (host->ld_intf_width) { + case STMLCDIF_8BIT: + dev_dbg(&host->pdev->dev, + "Unsupported LCD bus width mapping\n"); + return -EINVAL; + case STMLCDIF_16BIT: + case STMLCDIF_18BIT: + /* 24 bit to 18 bit mapping */ + ctrl |= CTRL_DF24; /* ignore the upper 2 bits in + * each colour component + */ + break; + case STMLCDIF_24BIT: + /* real 24 bit */ + break; + } + /* do not use packed pixels = one pixel per word instead */ + writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1); + break; + default: + dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n", + fb_info->var.bits_per_pixel); + return -EINVAL; + } + + writel(ctrl, host->base + LCDC_CTRL); + + writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) | + TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres), + host->base + host->devdata->transfer_count); + + vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */ + VDCTRL0_VSYNC_PERIOD_UNIT | + VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | + VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len); + if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT) + vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; + if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT) + vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; + if (fb_info->var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT) + vdctrl0 |= VDCTRL0_POL_ACTIVE_HIGH; + + writel(vdctrl0, host->base + LCDC_VDCTRL0); + + /* frame length in lines */ + writel(fb_info->var.upper_margin + fb_info->var.vsync_len + + fb_info->var.lower_margin + fb_info->var.yres, + host->base + LCDC_VDCTRL1); + + /* line length in units of clocks or pixels */ + writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) | + VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin + + fb_info->var.hsync_len + fb_info->var.right_margin + + fb_info->var.xres), + host->base + LCDC_VDCTRL2); + + writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin + + fb_info->var.hsync_len) | + SET_VERT_WAIT_CNT(fb_info->var.upper_margin + + fb_info->var.vsync_len), + host->base + LCDC_VDCTRL3); + + vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres); + if (cpu_is_mx28()) + vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay); + writel(vdctrl4, host->base + LCDC_VDCTRL4); + + writel(fb_info->fix.smem_start + + fb_info->fix.line_length * fb_info->var.yoffset, + host->base + host->devdata->next_buf); + + if (reenable) + mxsfb_enable_controller(fb_info); + + return 0; +} + +static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + u_int transp, struct fb_info *fb_info) +{ + unsigned int val; + int ret = -EINVAL; + + /* + * If greyscale is true, then we convert the RGB value + * to greyscale no matter what visual we are using. + */ + if (fb_info->var.grayscale) + red = green = blue = (19595 * red + 38470 * green + + 7471 * blue) >> 16; + + switch (fb_info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + /* + * 12 or 16-bit True Colour. We encode the RGB value + * according to the RGB bitfield information. + */ + if (regno < 16) { + u32 *pal = fb_info->pseudo_palette; + + val = chan_to_field(red, &fb_info->var.red); + val |= chan_to_field(green, &fb_info->var.green); + val |= chan_to_field(blue, &fb_info->var.blue); + + pal[regno] = val; + ret = 0; + } + break; + + case FB_VISUAL_STATIC_PSEUDOCOLOR: + case FB_VISUAL_PSEUDOCOLOR: + break; + } + + return ret; +} + +static int mxsfb_blank(int blank, struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + + switch (blank) { + case FB_BLANK_POWERDOWN: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + if (host->enabled) + mxsfb_disable_controller(fb_info); + break; + + case FB_BLANK_UNBLANK: + if (!host->enabled) + mxsfb_enable_controller(fb_info); + break; + } + return 0; +} + +static int mxsfb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + unsigned offset; + + if (var->xoffset != 0) + return -EINVAL; + + offset = fb_info->fix.line_length * var->yoffset; + + /* update on next VSYNC */ + writel(fb_info->fix.smem_start + offset, + host->base + host->devdata->next_buf); + + return 0; +} + +static struct fb_ops mxsfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = mxsfb_check_var, + .fb_set_par = mxsfb_set_par, + .fb_setcolreg = mxsfb_setcolreg, + .fb_blank = mxsfb_blank, + .fb_pan_display = mxsfb_pan_display, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +}; + +static int __devinit mxsfb_restore_mode(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + unsigned line_count; + unsigned period; + unsigned long pa, fbsize; + int bits_per_pixel, ofs; + u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; + struct fb_videomode vmode; + + /* Only restore the mode when the controller is running */ + ctrl = readl(host->base + LCDC_CTRL); + if (!(ctrl & CTRL_RUN)) + return -EINVAL; + + vdctrl0 = readl(host->base + LCDC_VDCTRL0); + vdctrl2 = readl(host->base + LCDC_VDCTRL2); + vdctrl3 = readl(host->base + LCDC_VDCTRL3); + vdctrl4 = readl(host->base + LCDC_VDCTRL4); + + transfer_count = readl(host->base + host->devdata->transfer_count); + + vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count); + vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count); + + switch (CTRL_GET_WORD_LENGTH(ctrl)) { + case 0: + bits_per_pixel = 16; + break; + case 3: + bits_per_pixel = 32; + case 1: + default: + return -EINVAL; + } + + fb_info->var.bits_per_pixel = bits_per_pixel; + + vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U); + vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2); + vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len; + vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len - + vmode.left_margin - vmode.xres; + vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0); + period = readl(host->base + LCDC_VDCTRL1); + vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len; + vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres; + + vmode.vmode = FB_VMODE_NONINTERLACED; + + vmode.sync = 0; + if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH) + vmode.sync |= FB_SYNC_HOR_HIGH_ACT; + if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH) + vmode.sync |= FB_SYNC_VERT_HIGH_ACT; + + pr_debug("Reconstructed video mode:\n"); + pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n", + vmode.xres, vmode.yres, + vmode.hsync_len, vmode.left_margin, vmode.right_margin, + vmode.vsync_len, vmode.upper_margin, vmode.lower_margin); + pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock)); + + fb_add_videomode(&vmode, &fb_info->modelist); + + host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl); + host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4); + + fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3); + + pa = readl(host->base + host->devdata->cur_buf); + fbsize = fb_info->fix.line_length * vmode.yres; + if (pa < fb_info->fix.smem_start) + return -EINVAL; + if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) + return -EINVAL; + ofs = pa - fb_info->fix.smem_start; + if (ofs) { + memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize); + writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf); + } + + line_count = fb_info->fix.smem_len / fb_info->fix.line_length; + fb_info->fix.ypanstep = 1; + + clk_enable(host->clk); + host->enabled = 1; + + return 0; +} + +static int __devinit mxsfb_init_fbinfo(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + struct fb_var_screeninfo *var = &fb_info->var; + struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data; + dma_addr_t fb_phys; + void *fb_virt; + unsigned fb_size = pdata->fb_size; + + fb_info->fbops = &mxsfb_ops; + fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; + strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id)); + fb_info->fix.type = FB_TYPE_PACKED_PIXELS; + fb_info->fix.ypanstep = 1; + fb_info->fix.visual = FB_VISUAL_TRUECOLOR, + fb_info->fix.accel = FB_ACCEL_NONE; + + var->bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16; + var->nonstd = 0; + var->activate = FB_ACTIVATE_NOW; + var->accel_flags = 0; + var->vmode = FB_VMODE_NONINTERLACED; + + host->dotclk_delay = pdata->dotclk_delay; + host->ld_intf_width = pdata->ld_intf_width; + + /* Memory allocation for framebuffer */ + if (pdata->fb_phys) { + if (!fb_size) + return -EINVAL; + + fb_phys = pdata->fb_phys; + + if (!request_mem_region(fb_phys, fb_size, host->pdev->name)) + return -ENOMEM; + + fb_virt = ioremap(fb_phys, fb_size); + if (!fb_virt) { + release_mem_region(fb_phys, fb_size); + return -ENOMEM; + } + host->mapped = 1; + } else { + if (!fb_size) + fb_size = SZ_2M; /* default */ + fb_virt = alloc_pages_exact(fb_size, GFP_DMA); + if (!fb_info->screen_base) + return -ENOMEM; + + fb_phys = virt_to_phys(fb_virt); + } + + fb_info->fix.smem_start = fb_phys; + fb_info->screen_base = fb_virt; + fb_info->screen_size = fb_info->fix.smem_len = fb_size; + + if (mxsfb_restore_mode(host)) + memset(fb_virt, 0, fb_size); + + return 0; +} + +static void __devexit mxsfb_free_videomem(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + + if (host->mapped) { + iounmap(fb_info->screen_base); + release_mem_region(fb_info->fix.smem_start, + fb_info->screen_size); + } else { + free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len); + } +} + +static int __devinit mxsfb_probe(struct platform_device *pdev) +{ + struct mxsfb_platform_data *pdata = pdev->dev.platform_data; + struct resource *res; + struct mxsfb_info *host; + struct fb_info *fb_info; + struct fb_modelist *modelist; + int i, ret; + + if (!pdata) { + dev_err(&pdev->dev, "No platformdata. Giving up\n"); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Cannot get memory IO resource\n"); + return -ENODEV; + } + + if (!request_mem_region(res->start, resource_size(res), pdev->name)) + return -EBUSY; + + fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev); + if (!fb_info) { + dev_err(&pdev->dev, "Failed to allocate fbdev\n"); + ret = -ENOMEM; + goto error_alloc_info; + } + + host = to_imxfb_host(fb_info); + + host->base = ioremap(res->start, resource_size(res)); + if (!host->base) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto error_ioremap; + } + + host->pdev = pdev; + platform_set_drvdata(pdev, host); + + host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data]; + + host->clk = clk_get(&host->pdev->dev, NULL); + if (IS_ERR(host->clk)) { + ret = PTR_ERR(host->clk); + goto error_getclock; + } + + fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); + if (!fb_info->pseudo_palette) { + ret = -ENOMEM; + goto error_pseudo_pallette; + } + + INIT_LIST_HEAD(&fb_info->modelist); + + ret = mxsfb_init_fbinfo(host); + if (ret != 0) + goto error_init_fb; + + for (i = 0; i < pdata->mode_count; i++) + fb_add_videomode(&pdata->mode_list[i], &fb_info->modelist); + + modelist = list_first_entry(&fb_info->modelist, + struct fb_modelist, list); + fb_videomode_to_var(&fb_info->var, &modelist->mode); + + /* init the color fields */ + mxsfb_check_var(&fb_info->var, fb_info); + + platform_set_drvdata(pdev, fb_info); + + ret = register_framebuffer(fb_info); + if (ret != 0) { + dev_err(&pdev->dev,"Failed to register framebuffer\n"); + goto error_register; + } + + if (!host->enabled) { + writel(0, host->base + LCDC_CTRL); + mxsfb_set_par(fb_info); + mxsfb_enable_controller(fb_info); + } + + return 0; + +error_register: + if (host->enabled) + clk_disable(host->clk); + fb_destroy_modelist(&fb_info->modelist); +error_init_fb: + kfree(fb_info->pseudo_palette); +error_pseudo_pallette: + clk_put(host->clk); +error_getclock: + iounmap(host->base); +error_ioremap: + framebuffer_release(fb_info); +error_alloc_info: + release_mem_region(res->start, resource_size(res)); + + return ret; +} + +static int __devexit mxsfb_remove(struct platform_device *pdev) +{ + struct fb_info *fb_info = platform_get_drvdata(pdev); + struct mxsfb_info *host = to_imxfb_host(fb_info); + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (host->enabled) + mxsfb_disable_controller(fb_info); + + unregister_framebuffer(fb_info); + kfree(fb_info->pseudo_palette); + mxsfb_free_videomem(host); + iounmap(host->base); + clk_put(host->clk); + + framebuffer_release(fb_info); + release_mem_region(res->start, resource_size(res)); + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_device_id mxsfb_devtype[] = { + { + .name = "imx23-fb", + .driver_data = MXSFB_MX23, + }, { + .name = "imx28-fb", + .driver_data = MXSFB_MX28, + }, { + }, +}; +MODULE_DEVICE_TABLE(platform, mxsfb_devtype); + +static struct platform_driver mxsfb_driver = { + .probe = mxsfb_probe, + .remove = __devexit_p(mxsfb_remove), + .id_table = mxsfb_devtype, + .driver = { + .name = DRIVER_NAME, + }, +}; + +static int __init mxsfb_init(void) +{ + return platform_driver_register(&mxsfb_driver); +} + +static void __exit mxsfb_exit(void) +{ + platform_driver_unregister(&mxsfb_driver); +} + +module_init(mxsfb_init); +module_exit(mxsfb_exit); + +MODULE_DESCRIPTION("Freescale mxs framebuffer driver"); +MODULE_AUTHOR("Sascha Hauer, Pengutronix"); +MODULE_LICENSE("GPL"); -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-16 9:56 ` [PATCH 1/2] video: Add i.MX23/28 framebuffer driver Sascha Hauer @ 2011-02-18 5:24 ` Shawn Guo 2011-02-18 8:30 ` Sascha Hauer 2011-02-18 12:29 ` Shawn Guo 1 sibling, 1 reply; 24+ messages in thread From: Shawn Guo @ 2011-02-18 5:24 UTC (permalink / raw) To: linux-arm-kernel Sorry, I did not catch up with v1 of the patch set. I have a overall comment on the driver. There is many occurrences of mx23, mx28 etc. throughout the file. IMHO, this is not a good idea. It may be better to use the IP version to handle the differences. In this way, if we have another SoC coming later using the same LCDIF revision as i.MX28. The driver could immediately fit in without code change, ideally. The only problem with version register is that the offset of LCDIF version register is different on i.MX28 from i.MX23. You still need cpu_is_mx23 to read the correct version. BTW, I would try to use cpu_is_mx23 than cpu_is_mx28, as the 'else' of cpu_is_mx23 could _possibly_ cover later SoC as well as i.MX28. -- Regards, Shawn On Wed, Feb 16, 2011 at 10:56:38AM +0100, Sascha Hauer wrote: > changes since v1: > - Add a LCDC_ prefix to the register names. > - use set/clear registers where appropriate > - protect call to mxsfb_disable_controller() in mxsfb_remove() > with a (host->enabled) as suggested by Lothar Wassmann > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Paul Mundt <lethal@linux-sh.org> > Cc: linux-fbdev at vger.kernel.org > Cc: Shawn Guo <shawn.guo@freescale.com> > --- > arch/arm/mach-mxs/include/mach/fb.h | 48 ++ > drivers/video/Kconfig | 9 + > drivers/video/Makefile | 1 + > drivers/video/mxsfb.c | 910 +++++++++++++++++++++++++++++++++++ > 4 files changed, 968 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/mach-mxs/include/mach/fb.h > create mode 100644 drivers/video/mxsfb.c > > diff --git a/arch/arm/mach-mxs/include/mach/fb.h b/arch/arm/mach-mxs/include/mach/fb.h > new file mode 100644 > index 0000000..923f397 > --- /dev/null > +++ b/arch/arm/mach-mxs/include/mach/fb.h > @@ -0,0 +1,48 @@ > +/* > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > + * MA 02110-1301, USA. > + */ > + > +#ifndef __MACH_FB_H > +#define __MACH_FB_H > + > +#include <linux/fb.h> > + > +#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ > +#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ > +#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ > +#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ > + > +#define FB_SYNC_DATA_ENABLE_HIGH_ACT 64 > + > +struct mxsfb_platform_data { > + struct fb_videomode *mode_list; > + unsigned mode_count; > + > + unsigned default_bpp; > + > + unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ > + unsigned ld_intf_width; /* refer STMLCDIF_* macros */ > + > + unsigned fb_size; /* Size of the video memory. If zero a > + * default will be used > + */ > + unsigned long fb_phys; /* physical address for the video memory. If > + * zero the framebuffer memory will be dynamically > + * allocated. If specified,fb_size must also be specified. > + * fb_phys must be unused by Linux. > + */ > +}; > + > +#endif /* __MACH_FB_H */ > diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig > index 6bafb51b..e0ea23f 100644 > --- a/drivers/video/Kconfig > +++ b/drivers/video/Kconfig > @@ -2365,6 +2365,15 @@ config FB_JZ4740 > help > Framebuffer support for the JZ4740 SoC. > > +config FB_MXS > + tristate "MXS LCD framebuffer support" > + depends on FB && ARCH_MXS > + select FB_CFB_FILLRECT > + select FB_CFB_COPYAREA > + select FB_CFB_IMAGEBLIT > + help > + Framebuffer support for the MXS SoC. > + > source "drivers/video/omap/Kconfig" > source "drivers/video/omap2/Kconfig" > > diff --git a/drivers/video/Makefile b/drivers/video/Makefile > index 8c8fabd..9a096ae 100644 > --- a/drivers/video/Makefile > +++ b/drivers/video/Makefile > @@ -153,6 +153,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o > obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o > obj-$(CONFIG_FB_MX3) += mx3fb.o > obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o > +obj-$(CONFIG_FB_MXS) += mxsfb.o > > # the test framebuffer is last > obj-$(CONFIG_FB_VIRTUAL) += vfb.o > diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c > new file mode 100644 > index 0000000..ac9939b > --- /dev/null > +++ b/drivers/video/mxsfb.c > @@ -0,0 +1,910 @@ > +/* > + * Copyright (C) 2010 Juergen Beisert, Pengutronix > + * > + * This code is based on: > + * Author: Vitaly Wool <vital@embeddedalley.com> > + * > + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. > + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#define DRIVER_NAME "mxsfb" > + > +/** > + * @file > + * @brief LCDIF driver for i.MX23 and i.MX28 > + * > + * The LCDIF support four modes of operation > + * - MPU interface (to drive smart displays) -> not supported yet > + * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet > + * - Dotclock interface (to drive LC displays with RGB data and sync signals) > + * - DVI (to drive ITU-R BT656) -> not supported yet > + * > + * This driver depends on a correct setup of the pins used for this purpose > + * (platform specific). > + * > + * For the developer: Don't forget to set the data bus width to the display > + * in the imx_fb_videomode structure. You will else end up with ugly colours. > + * If you fight against jitter you can vary the clock delay. This is a feature > + * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give > + * the required value in the imx_fb_videomode structure. > + */ > + > +#include <linux/kernel.h> > +#include <linux/platform_device.h> > +#include <linux/clk.h> > +#include <linux/dma-mapping.h> > +#include <linux/io.h> > +#include <mach/fb.h> > +#include <mach/hardware.h> > +#include <mach/mxs.h> > + > +#define REG_SET 4 > +#define REG_CLR 8 > + > +#define LCDC_CTRL 0x00 > +#define LCDC_CTRL1 0x10 > +#define LCDC_MX28_CTRL2 0x20 > +#define LCDC_MX23_TRANSFER_COUNT 0x20 > +#define LCDC_MX28_TRANSFER_COUNT 0x30 > +#define LCDC_MX28_CUR_BUF 0x40 > +#define LCDC_MX28_NEXT_BUF 0x50 > +#define LCDC_MX23_CUR_BUF 0x30 > +#define LCDC_MX23_NEXT_BUF 0x40 > +#define LCDC_TIMING 0x60 > +#define LCDC_VDCTRL0 0x70 > +#define LCDC_VDCTRL1 0x80 > +#define LCDC_VDCTRL2 0x90 > +#define LCDC_VDCTRL3 0xa0 > +#define LCDC_VDCTRL4 0xb0 > +#define LCDC_DVICTRL0 0xc0 > +#define LCDC_DVICTRL1 0xd0 > +#define LCDC_DVICTRL2 0xe0 > +#define LCDC_DVICTRL3 0xf0 > +#define LCDC_DVICTRL4 0x100 > +#define LCDC_MX28_DATA 0x180 > +#define LCDC_MX23_DATA 0x1b0 > +#define LCDC_MX28_DEBUG0 0x1d0 > +#define LCDC_MX23_DEBUG0 0x1f0 > + > +#define CTRL_SFTRST (1 << 31) > +#define CTRL_CLKGATE (1 << 30) > +#define CTRL_BYPASS_COUNT (1 << 19) > +#define CTRL_VSYNC_MODE (1 << 18) > +#define CTRL_DOTCLK_MODE (1 << 17) > +#define CTRL_DATA_SELECT (1 << 16) > +#define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10) > +#define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3) > +#define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8) > +#define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) > +#define CTRL_MASTER (1 << 5) > +#define CTRL_DF16 (1 << 3) > +#define CTRL_DF18 (1 << 2) > +#define CTRL_DF24 (1 << 1) > +#define CTRL_RUN (1 << 0) > + > +#define CTRL1_FIFO_CLEAR (1 << 21) > +#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) > +#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) > + > +#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16) > +#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff) > +#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff) > +#define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff) > + > + > +#define VDCTRL0_ENABLE_PRESENT (1 << 28) > +#define VDCTRL0_VSYNC_ACT_HIGH (1 << 27) > +#define VDCTRL0_HSYNC_ACT_HIGH (1 << 26) > +#define VDCTRL0_DOTCLK_ACTIVE_HIGH (1 << 25) > +#define VDCTRL0_POL_ACTIVE_HIGH (1 << 24) > +#define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) > +#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) > +#define VDCTRL0_HALF_LINE (1 << 19) > +#define VDCTRL0_HALF_LINE_MODE (1 << 18) > +#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) > +#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) > + > +#define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) > +#define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) > + > +#define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) > +#define VDCTRL3_VSYNC_ONLY (1 << 28) > +#define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) > +#define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) > +#define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) > +#define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) > + > +#define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* i.MX28 only */ > +#define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* i.MX28 only */ > +#define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) > +#define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) > + > +#define DEBUG0_HSYNC (1 < 26) > +#define DEBUG0_VSYNC (1 < 25) > + > +#define MIN_XRES 120 > +#define MIN_YRES 120 > + > +#define RED 0 > +#define GREEN 1 > +#define BLUE 2 > +#define TRANSP 3 > + > +enum mxsfb_devtype { > + MXSFB_MX23, > + MXSFB_MX28, > +}; > + > +/* CPU dependent register offsets */ > +struct mxsfb_devdata { > + unsigned transfer_count; > + unsigned cur_buf; > + unsigned next_buf; > + unsigned debug0; > + unsigned hs_wdth_mask; > + unsigned hs_wdth_shift; > +}; > + > +struct mxsfb_info { > + struct fb_info fb_info; > + struct platform_device *pdev; > + struct clk *clk; > + void __iomem *base; /* registers */ > + unsigned allocated_size; > + int enabled; > + unsigned ld_intf_width; > + unsigned dotclk_delay; > + const struct mxsfb_devdata *devdata; > + int mapped; > +}; > + > +static const struct mxsfb_devdata mxsfb_devdata[] = { > + [MXSFB_MX23] = { > + .transfer_count = LCDC_MX23_TRANSFER_COUNT, > + .cur_buf = LCDC_MX23_CUR_BUF, > + .next_buf = LCDC_MX23_NEXT_BUF, > + .debug0 = LCDC_MX23_DEBUG0, > + .hs_wdth_mask = 0xff, > + .hs_wdth_shift = 24, > + }, > + [MXSFB_MX28] = { > + .transfer_count = LCDC_MX28_TRANSFER_COUNT, > + .cur_buf = LCDC_MX28_CUR_BUF, > + .next_buf = LCDC_MX28_NEXT_BUF, > + .debug0 = LCDC_MX28_DEBUG0, > + .hs_wdth_mask = 0x3fff, > + .hs_wdth_shift = 18, > + }, > +}; > + > +#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info)) > + > +/* mask and shift depends on architecture */ > +static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val) > +{ > + return (val & host->devdata->hs_wdth_mask) << > + host->devdata->hs_wdth_shift; > +} > + > +static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val) > +{ > + return (val >> host->devdata->hs_wdth_shift) & > + host->devdata->hs_wdth_mask; > +} > + > +static const struct fb_bitfield def_rgb565[] = { > + [RED] = { > + .offset = 11, > + .length = 5, > + }, > + [GREEN] = { > + .offset = 5, > + .length = 6, > + }, > + [BLUE] = { > + .offset = 0, > + .length = 5, > + }, > + [TRANSP] = { /* no support for transparency */ > + .length = 0, > + } > +}; > + > +static const struct fb_bitfield def_rgb666[] = { > + [RED] = { > + .offset = 16, > + .length = 6, > + }, > + [GREEN] = { > + .offset = 8, > + .length = 6, > + }, > + [BLUE] = { > + .offset = 0, > + .length = 6, > + }, > + [TRANSP] = { /* no support for transparency */ > + .length = 0, > + } > +}; > + > +static const struct fb_bitfield def_rgb888[] = { > + [RED] = { > + .offset = 16, > + .length = 8, > + }, > + [GREEN] = { > + .offset = 8, > + .length = 8, > + }, > + [BLUE] = { > + .offset = 0, > + .length = 8, > + }, > + [TRANSP] = { /* no support for transparency */ > + .length = 0, > + } > +}; > + > +static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf) > +{ > + chan &= 0xffff; > + chan >>= 16 - bf->length; > + return chan << bf->offset; > +} > + > +static int mxsfb_check_var(struct fb_var_screeninfo *var, > + struct fb_info *fb_info) > +{ > + struct mxsfb_info *host = to_imxfb_host(fb_info); > + const struct fb_bitfield *rgb = NULL; > + > + if (var->xres < MIN_XRES) > + var->xres = MIN_XRES; > + if (var->yres < MIN_YRES) > + var->yres = MIN_YRES; > + > + var->xres_virtual = var->xres; > + > + var->yres_virtual = var->yres; > + > + switch (var->bits_per_pixel) { > + case 16: > + /* always expect RGB 565 */ > + rgb = def_rgb565; > + break; > + case 32: > + switch (host->ld_intf_width) { > + case STMLCDIF_8BIT: > + pr_debug("Unsupported LCD bus width mapping\n"); > + break; > + case STMLCDIF_16BIT: > + case STMLCDIF_18BIT: > + /* 24 bit to 18 bit mapping */ > + rgb = def_rgb666; > + break; > + case STMLCDIF_24BIT: > + /* real 24 bit */ > + rgb = def_rgb888; > + break; > + } > + break; > + default: > + pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel); > + return -EINVAL; > + } > + > + /* > + * Copy the RGB parameters for this display > + * from the machine specific parameters. > + */ > + var->red = rgb[RED]; > + var->green = rgb[GREEN]; > + var->blue = rgb[BLUE]; > + var->transp = rgb[TRANSP]; > + > + return 0; > +} > + > +static void mxsfb_enable_controller(struct fb_info *fb_info) > +{ > + struct mxsfb_info *host = to_imxfb_host(fb_info); > + u32 reg; > + > + dev_dbg(&host->pdev->dev, "%s\n", __func__); > + > + clk_enable(host->clk); > + clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U); > + > + /* if it was disabled, re-enable the mode again */ > + writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET); > + > + /* enable the SYNC signals first, then the DMA engine */ > + reg = readl(host->base + LCDC_VDCTRL4); > + reg |= VDCTRL4_SYNC_SIGNALS_ON; > + writel(reg, host->base + LCDC_VDCTRL4); > + > + writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET); > + > + host->enabled = 1; > +} > + > +static void mxsfb_disable_controller(struct fb_info *fb_info) > +{ > + struct mxsfb_info *host = to_imxfb_host(fb_info); > + unsigned loop; > + u32 reg; > + > + dev_dbg(&host->pdev->dev, "%s\n", __func__); > + > + /* > + * Even if we disable the controller here, it will still continue > + * until its FIFOs are running out of data > + */ > + writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR); > + > + loop = 1000; > + while (loop) { > + reg = readl(host->base + LCDC_CTRL); > + if (!(reg & CTRL_RUN)) > + break; > + loop--; > + } > + > + writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR); > + > + clk_disable(host->clk); > + > + host->enabled = 0; > +} > + > +static int mxsfb_set_par(struct fb_info *fb_info) > +{ > + struct mxsfb_info *host = to_imxfb_host(fb_info); > + u32 ctrl, vdctrl0, vdctrl4; > + int line_size, fb_size; > + int reenable = 0; > + > + line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3); > + fb_size = fb_info->var.yres_virtual * line_size; > + > + if (fb_size > fb_info->fix.smem_len) > + return -ENOMEM; > + > + fb_info->fix.line_length = line_size; > + > + /* > + * It seems, you can't re-program the controller if it is still running. > + * This may lead into shifted pictures (FIFO issue?). > + * So, first stop the controller and drain its FIFOs > + */ > + if (host->enabled) { > + reenable = 1; > + mxsfb_disable_controller(fb_info); > + } > + > + /* clear the FIFOs */ > + writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET); > + > + ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER | > + CTRL_SET_BUS_WIDTH(host->ld_intf_width);; > + > + switch (fb_info->var.bits_per_pixel) { > + case 16: > + dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n"); > + ctrl |= CTRL_SET_WORD_LENGTH(0); > + writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1); > + break; > + case 32: > + dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n"); > + ctrl |= CTRL_SET_WORD_LENGTH(3); > + switch (host->ld_intf_width) { > + case STMLCDIF_8BIT: > + dev_dbg(&host->pdev->dev, > + "Unsupported LCD bus width mapping\n"); > + return -EINVAL; > + case STMLCDIF_16BIT: > + case STMLCDIF_18BIT: > + /* 24 bit to 18 bit mapping */ > + ctrl |= CTRL_DF24; /* ignore the upper 2 bits in > + * each colour component > + */ > + break; > + case STMLCDIF_24BIT: > + /* real 24 bit */ > + break; > + } > + /* do not use packed pixels = one pixel per word instead */ > + writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1); > + break; > + default: > + dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n", > + fb_info->var.bits_per_pixel); > + return -EINVAL; > + } > + > + writel(ctrl, host->base + LCDC_CTRL); > + > + writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) | > + TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres), > + host->base + host->devdata->transfer_count); > + > + vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */ > + VDCTRL0_VSYNC_PERIOD_UNIT | > + VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | > + VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len); > + if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT) > + vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; > + if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT) > + vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; > + if (fb_info->var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT) > + vdctrl0 |= VDCTRL0_POL_ACTIVE_HIGH; > + > + writel(vdctrl0, host->base + LCDC_VDCTRL0); > + > + /* frame length in lines */ > + writel(fb_info->var.upper_margin + fb_info->var.vsync_len + > + fb_info->var.lower_margin + fb_info->var.yres, > + host->base + LCDC_VDCTRL1); > + > + /* line length in units of clocks or pixels */ > + writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) | > + VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin + > + fb_info->var.hsync_len + fb_info->var.right_margin + > + fb_info->var.xres), > + host->base + LCDC_VDCTRL2); > + > + writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin + > + fb_info->var.hsync_len) | > + SET_VERT_WAIT_CNT(fb_info->var.upper_margin + > + fb_info->var.vsync_len), > + host->base + LCDC_VDCTRL3); > + > + vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres); > + if (cpu_is_mx28()) > + vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay); > + writel(vdctrl4, host->base + LCDC_VDCTRL4); > + > + writel(fb_info->fix.smem_start + > + fb_info->fix.line_length * fb_info->var.yoffset, > + host->base + host->devdata->next_buf); > + > + if (reenable) > + mxsfb_enable_controller(fb_info); > + > + return 0; > +} > + > +static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, > + u_int transp, struct fb_info *fb_info) > +{ > + unsigned int val; > + int ret = -EINVAL; > + > + /* > + * If greyscale is true, then we convert the RGB value > + * to greyscale no matter what visual we are using. > + */ > + if (fb_info->var.grayscale) > + red = green = blue = (19595 * red + 38470 * green + > + 7471 * blue) >> 16; > + > + switch (fb_info->fix.visual) { > + case FB_VISUAL_TRUECOLOR: > + /* > + * 12 or 16-bit True Colour. We encode the RGB value > + * according to the RGB bitfield information. > + */ > + if (regno < 16) { > + u32 *pal = fb_info->pseudo_palette; > + > + val = chan_to_field(red, &fb_info->var.red); > + val |= chan_to_field(green, &fb_info->var.green); > + val |= chan_to_field(blue, &fb_info->var.blue); > + > + pal[regno] = val; > + ret = 0; > + } > + break; > + > + case FB_VISUAL_STATIC_PSEUDOCOLOR: > + case FB_VISUAL_PSEUDOCOLOR: > + break; > + } > + > + return ret; > +} > + > +static int mxsfb_blank(int blank, struct fb_info *fb_info) > +{ > + struct mxsfb_info *host = to_imxfb_host(fb_info); > + > + switch (blank) { > + case FB_BLANK_POWERDOWN: > + case FB_BLANK_VSYNC_SUSPEND: > + case FB_BLANK_HSYNC_SUSPEND: > + case FB_BLANK_NORMAL: > + if (host->enabled) > + mxsfb_disable_controller(fb_info); > + break; > + > + case FB_BLANK_UNBLANK: > + if (!host->enabled) > + mxsfb_enable_controller(fb_info); > + break; > + } > + return 0; > +} > + > +static int mxsfb_pan_display(struct fb_var_screeninfo *var, > + struct fb_info *fb_info) > +{ > + struct mxsfb_info *host = to_imxfb_host(fb_info); > + unsigned offset; > + > + if (var->xoffset != 0) > + return -EINVAL; > + > + offset = fb_info->fix.line_length * var->yoffset; > + > + /* update on next VSYNC */ > + writel(fb_info->fix.smem_start + offset, > + host->base + host->devdata->next_buf); > + > + return 0; > +} > + > +static struct fb_ops mxsfb_ops = { > + .owner = THIS_MODULE, > + .fb_check_var = mxsfb_check_var, > + .fb_set_par = mxsfb_set_par, > + .fb_setcolreg = mxsfb_setcolreg, > + .fb_blank = mxsfb_blank, > + .fb_pan_display = mxsfb_pan_display, > + .fb_fillrect = cfb_fillrect, > + .fb_copyarea = cfb_copyarea, > + .fb_imageblit = cfb_imageblit, > +}; > + > +static int __devinit mxsfb_restore_mode(struct mxsfb_info *host) > +{ > + struct fb_info *fb_info = &host->fb_info; > + unsigned line_count; > + unsigned period; > + unsigned long pa, fbsize; > + int bits_per_pixel, ofs; > + u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; > + struct fb_videomode vmode; > + > + /* Only restore the mode when the controller is running */ > + ctrl = readl(host->base + LCDC_CTRL); > + if (!(ctrl & CTRL_RUN)) > + return -EINVAL; > + > + vdctrl0 = readl(host->base + LCDC_VDCTRL0); > + vdctrl2 = readl(host->base + LCDC_VDCTRL2); > + vdctrl3 = readl(host->base + LCDC_VDCTRL3); > + vdctrl4 = readl(host->base + LCDC_VDCTRL4); > + > + transfer_count = readl(host->base + host->devdata->transfer_count); > + > + vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count); > + vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count); > + > + switch (CTRL_GET_WORD_LENGTH(ctrl)) { > + case 0: > + bits_per_pixel = 16; > + break; > + case 3: > + bits_per_pixel = 32; > + case 1: > + default: > + return -EINVAL; > + } > + > + fb_info->var.bits_per_pixel = bits_per_pixel; > + > + vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U); > + vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2); > + vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len; > + vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len - > + vmode.left_margin - vmode.xres; > + vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0); > + period = readl(host->base + LCDC_VDCTRL1); > + vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len; > + vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres; > + > + vmode.vmode = FB_VMODE_NONINTERLACED; > + > + vmode.sync = 0; > + if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH) > + vmode.sync |= FB_SYNC_HOR_HIGH_ACT; > + if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH) > + vmode.sync |= FB_SYNC_VERT_HIGH_ACT; > + > + pr_debug("Reconstructed video mode:\n"); > + pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n", > + vmode.xres, vmode.yres, > + vmode.hsync_len, vmode.left_margin, vmode.right_margin, > + vmode.vsync_len, vmode.upper_margin, vmode.lower_margin); > + pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock)); > + > + fb_add_videomode(&vmode, &fb_info->modelist); > + > + host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl); > + host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4); > + > + fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3); > + > + pa = readl(host->base + host->devdata->cur_buf); > + fbsize = fb_info->fix.line_length * vmode.yres; > + if (pa < fb_info->fix.smem_start) > + return -EINVAL; > + if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) > + return -EINVAL; > + ofs = pa - fb_info->fix.smem_start; > + if (ofs) { > + memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize); > + writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf); > + } > + > + line_count = fb_info->fix.smem_len / fb_info->fix.line_length; > + fb_info->fix.ypanstep = 1; > + > + clk_enable(host->clk); > + host->enabled = 1; > + > + return 0; > +} > + > +static int __devinit mxsfb_init_fbinfo(struct mxsfb_info *host) > +{ > + struct fb_info *fb_info = &host->fb_info; > + struct fb_var_screeninfo *var = &fb_info->var; > + struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data; > + dma_addr_t fb_phys; > + void *fb_virt; > + unsigned fb_size = pdata->fb_size; > + > + fb_info->fbops = &mxsfb_ops; > + fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; > + strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id)); > + fb_info->fix.type = FB_TYPE_PACKED_PIXELS; > + fb_info->fix.ypanstep = 1; > + fb_info->fix.visual = FB_VISUAL_TRUECOLOR, > + fb_info->fix.accel = FB_ACCEL_NONE; > + > + var->bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16; > + var->nonstd = 0; > + var->activate = FB_ACTIVATE_NOW; > + var->accel_flags = 0; > + var->vmode = FB_VMODE_NONINTERLACED; > + > + host->dotclk_delay = pdata->dotclk_delay; > + host->ld_intf_width = pdata->ld_intf_width; > + > + /* Memory allocation for framebuffer */ > + if (pdata->fb_phys) { > + if (!fb_size) > + return -EINVAL; > + > + fb_phys = pdata->fb_phys; > + > + if (!request_mem_region(fb_phys, fb_size, host->pdev->name)) > + return -ENOMEM; > + > + fb_virt = ioremap(fb_phys, fb_size); > + if (!fb_virt) { > + release_mem_region(fb_phys, fb_size); > + return -ENOMEM; > + } > + host->mapped = 1; > + } else { > + if (!fb_size) > + fb_size = SZ_2M; /* default */ > + fb_virt = alloc_pages_exact(fb_size, GFP_DMA); > + if (!fb_info->screen_base) > + return -ENOMEM; > + > + fb_phys = virt_to_phys(fb_virt); > + } > + > + fb_info->fix.smem_start = fb_phys; > + fb_info->screen_base = fb_virt; > + fb_info->screen_size = fb_info->fix.smem_len = fb_size; > + > + if (mxsfb_restore_mode(host)) > + memset(fb_virt, 0, fb_size); > + > + return 0; > +} > + > +static void __devexit mxsfb_free_videomem(struct mxsfb_info *host) > +{ > + struct fb_info *fb_info = &host->fb_info; > + > + if (host->mapped) { > + iounmap(fb_info->screen_base); > + release_mem_region(fb_info->fix.smem_start, > + fb_info->screen_size); > + } else { > + free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len); > + } > +} > + > +static int __devinit mxsfb_probe(struct platform_device *pdev) > +{ > + struct mxsfb_platform_data *pdata = pdev->dev.platform_data; > + struct resource *res; > + struct mxsfb_info *host; > + struct fb_info *fb_info; > + struct fb_modelist *modelist; > + int i, ret; > + > + if (!pdata) { > + dev_err(&pdev->dev, "No platformdata. Giving up\n"); > + return -ENODEV; > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + dev_err(&pdev->dev, "Cannot get memory IO resource\n"); > + return -ENODEV; > + } > + > + if (!request_mem_region(res->start, resource_size(res), pdev->name)) > + return -EBUSY; > + > + fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev); > + if (!fb_info) { > + dev_err(&pdev->dev, "Failed to allocate fbdev\n"); > + ret = -ENOMEM; > + goto error_alloc_info; > + } > + > + host = to_imxfb_host(fb_info); > + > + host->base = ioremap(res->start, resource_size(res)); > + if (!host->base) { > + dev_err(&pdev->dev, "ioremap failed\n"); > + ret = -ENOMEM; > + goto error_ioremap; > + } > + > + host->pdev = pdev; > + platform_set_drvdata(pdev, host); > + > + host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data]; > + > + host->clk = clk_get(&host->pdev->dev, NULL); > + if (IS_ERR(host->clk)) { > + ret = PTR_ERR(host->clk); > + goto error_getclock; > + } > + > + fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); > + if (!fb_info->pseudo_palette) { > + ret = -ENOMEM; > + goto error_pseudo_pallette; > + } > + > + INIT_LIST_HEAD(&fb_info->modelist); > + > + ret = mxsfb_init_fbinfo(host); > + if (ret != 0) > + goto error_init_fb; > + > + for (i = 0; i < pdata->mode_count; i++) > + fb_add_videomode(&pdata->mode_list[i], &fb_info->modelist); > + > + modelist = list_first_entry(&fb_info->modelist, > + struct fb_modelist, list); > + fb_videomode_to_var(&fb_info->var, &modelist->mode); > + > + /* init the color fields */ > + mxsfb_check_var(&fb_info->var, fb_info); > + > + platform_set_drvdata(pdev, fb_info); > + > + ret = register_framebuffer(fb_info); > + if (ret != 0) { > + dev_err(&pdev->dev,"Failed to register framebuffer\n"); > + goto error_register; > + } > + > + if (!host->enabled) { > + writel(0, host->base + LCDC_CTRL); > + mxsfb_set_par(fb_info); > + mxsfb_enable_controller(fb_info); > + } > + > + return 0; > + > +error_register: > + if (host->enabled) > + clk_disable(host->clk); > + fb_destroy_modelist(&fb_info->modelist); > +error_init_fb: > + kfree(fb_info->pseudo_palette); > +error_pseudo_pallette: > + clk_put(host->clk); > +error_getclock: > + iounmap(host->base); > +error_ioremap: > + framebuffer_release(fb_info); > +error_alloc_info: > + release_mem_region(res->start, resource_size(res)); > + > + return ret; > +} > + > +static int __devexit mxsfb_remove(struct platform_device *pdev) > +{ > + struct fb_info *fb_info = platform_get_drvdata(pdev); > + struct mxsfb_info *host = to_imxfb_host(fb_info); > + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + > + if (host->enabled) > + mxsfb_disable_controller(fb_info); > + > + unregister_framebuffer(fb_info); > + kfree(fb_info->pseudo_palette); > + mxsfb_free_videomem(host); > + iounmap(host->base); > + clk_put(host->clk); > + > + framebuffer_release(fb_info); > + release_mem_region(res->start, resource_size(res)); > + > + platform_set_drvdata(pdev, NULL); > + > + return 0; > +} > + > +static struct platform_device_id mxsfb_devtype[] = { > + { > + .name = "imx23-fb", > + .driver_data = MXSFB_MX23, > + }, { > + .name = "imx28-fb", > + .driver_data = MXSFB_MX28, > + }, { > + }, > +}; > +MODULE_DEVICE_TABLE(platform, mxsfb_devtype); > + > +static struct platform_driver mxsfb_driver = { > + .probe = mxsfb_probe, > + .remove = __devexit_p(mxsfb_remove), > + .id_table = mxsfb_devtype, > + .driver = { > + .name = DRIVER_NAME, > + }, > +}; > + > +static int __init mxsfb_init(void) > +{ > + return platform_driver_register(&mxsfb_driver); > +} > + > +static void __exit mxsfb_exit(void) > +{ > + platform_driver_unregister(&mxsfb_driver); > +} > + > +module_init(mxsfb_init); > +module_exit(mxsfb_exit); > + > +MODULE_DESCRIPTION("Freescale mxs framebuffer driver"); > +MODULE_AUTHOR("Sascha Hauer, Pengutronix"); > +MODULE_LICENSE("GPL"); > -- > 1.7.2.3 > > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-18 5:24 ` Shawn Guo @ 2011-02-18 8:30 ` Sascha Hauer 2011-02-18 8:57 ` Shawn Guo 0 siblings, 1 reply; 24+ messages in thread From: Sascha Hauer @ 2011-02-18 8:30 UTC (permalink / raw) To: linux-arm-kernel On Fri, Feb 18, 2011 at 01:24:20PM +0800, Shawn Guo wrote: > Sorry, I did not catch up with v1 of the patch set. > > I have a overall comment on the driver. There is many occurrences > of mx23, mx28 etc. throughout the file. IMHO, this is not a good > idea. It may be better to use the IP version to handle the > differences. In this way, if we have another SoC coming later > using the same LCDIF revision as i.MX28. The driver could > immediately fit in without code change, ideally. > > The only problem with version register is that the offset of LCDIF > version register is different on i.MX28 from i.MX23. Can opener inside can. I love it ;) > You still need > cpu_is_mx23 to read the correct version. > > BTW, I would try to use cpu_is_mx23 than cpu_is_mx28, as the 'else' > of cpu_is_mx23 could _possibly_ cover later SoC as well as i.MX28. There is only one cpu_is_mx28 in the driver without else. I can switch MXSFB_MX23 and MXSFB_MX28 to MXSFB_V3 and MXSFB_V4 if you like it better. -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-18 8:30 ` Sascha Hauer @ 2011-02-18 8:57 ` Shawn Guo 0 siblings, 0 replies; 24+ messages in thread From: Shawn Guo @ 2011-02-18 8:57 UTC (permalink / raw) To: linux-arm-kernel On Fri, Feb 18, 2011 at 09:30:55AM +0100, Sascha Hauer wrote: > On Fri, Feb 18, 2011 at 01:24:20PM +0800, Shawn Guo wrote: > > Sorry, I did not catch up with v1 of the patch set. > > > > I have a overall comment on the driver. There is many occurrences > > of mx23, mx28 etc. throughout the file. IMHO, this is not a good > > idea. It may be better to use the IP version to handle the > > differences. In this way, if we have another SoC coming later > > using the same LCDIF revision as i.MX28. The driver could > > immediately fit in without code change, ideally. > > > > The only problem with version register is that the offset of LCDIF > > version register is different on i.MX28 from i.MX23. > > Can opener inside can. I love it ;) > Well, that's the situation we have to deal with. > > You still need > > cpu_is_mx23 to read the correct version. > > > > BTW, I would try to use cpu_is_mx23 than cpu_is_mx28, as the 'else' > > of cpu_is_mx23 could _possibly_ cover later SoC as well as i.MX28. > > There is only one cpu_is_mx28 in the driver without else. I can switch > MXSFB_MX23 and MXSFB_MX28 to MXSFB_V3 and MXSFB_V4 if you like it > better. > Yes, I like it better. With it, if we have a new SoC using LCDIF v4, the driver needs no change. -- Regards, Shawn ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-16 9:56 ` [PATCH 1/2] video: Add i.MX23/28 framebuffer driver Sascha Hauer 2011-02-18 5:24 ` Shawn Guo @ 2011-02-18 12:29 ` Shawn Guo 2011-02-21 14:17 ` Sascha Hauer 1 sibling, 1 reply; 24+ messages in thread From: Shawn Guo @ 2011-02-18 12:29 UTC (permalink / raw) To: linux-arm-kernel On Wed, Feb 16, 2011 at 10:56:38AM +0100, Sascha Hauer wrote: > changes since v1: > - Add a LCDC_ prefix to the register names. > - use set/clear registers where appropriate > - protect call to mxsfb_disable_controller() in mxsfb_remove() > with a (host->enabled) as suggested by Lothar Wassmann > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Paul Mundt <lethal@linux-sh.org> > Cc: linux-fbdev at vger.kernel.org > Cc: Shawn Guo <shawn.guo@freescale.com> > --- > arch/arm/mach-mxs/include/mach/fb.h | 48 ++ > drivers/video/Kconfig | 9 + > drivers/video/Makefile | 1 + > drivers/video/mxsfb.c | 910 +++++++++++++++++++++++++++++++++++ > 4 files changed, 968 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/mach-mxs/include/mach/fb.h > create mode 100644 drivers/video/mxsfb.c > > diff --git a/arch/arm/mach-mxs/include/mach/fb.h b/arch/arm/mach-mxs/include/mach/fb.h > new file mode 100644 > index 0000000..923f397 > --- /dev/null > +++ b/arch/arm/mach-mxs/include/mach/fb.h > @@ -0,0 +1,48 @@ > +/* > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > + * MA 02110-1301, USA. > + */ > + > +#ifndef __MACH_FB_H > +#define __MACH_FB_H > + > +#include <linux/fb.h> > + > +#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ > +#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ > +#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ > +#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ > + > +#define FB_SYNC_DATA_ENABLE_HIGH_ACT 64 > + > +struct mxsfb_platform_data { > + struct fb_videomode *mode_list; > + unsigned mode_count; > + > + unsigned default_bpp; > + > + unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ > + unsigned ld_intf_width; /* refer STMLCDIF_* macros */ > + > + unsigned fb_size; /* Size of the video memory. If zero a > + * default will be used > + */ > + unsigned long fb_phys; /* physical address for the video memory. If > + * zero the framebuffer memory will be dynamically > + * allocated. If specified,fb_size must also be specified. > + * fb_phys must be unused by Linux. > + */ > +}; > + > +#endif /* __MACH_FB_H */ > diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig > index 6bafb51b..e0ea23f 100644 > --- a/drivers/video/Kconfig > +++ b/drivers/video/Kconfig > @@ -2365,6 +2365,15 @@ config FB_JZ4740 > help > Framebuffer support for the JZ4740 SoC. > > +config FB_MXS > + tristate "MXS LCD framebuffer support" > + depends on FB && ARCH_MXS > + select FB_CFB_FILLRECT > + select FB_CFB_COPYAREA > + select FB_CFB_IMAGEBLIT > + help > + Framebuffer support for the MXS SoC. > + > source "drivers/video/omap/Kconfig" > source "drivers/video/omap2/Kconfig" > > diff --git a/drivers/video/Makefile b/drivers/video/Makefile > index 8c8fabd..9a096ae 100644 > --- a/drivers/video/Makefile > +++ b/drivers/video/Makefile > @@ -153,6 +153,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o > obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o > obj-$(CONFIG_FB_MX3) += mx3fb.o > obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o > +obj-$(CONFIG_FB_MXS) += mxsfb.o > > # the test framebuffer is last > obj-$(CONFIG_FB_VIRTUAL) += vfb.o > diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c > new file mode 100644 > index 0000000..ac9939b > --- /dev/null > +++ b/drivers/video/mxsfb.c > @@ -0,0 +1,910 @@ > +/* > + * Copyright (C) 2010 Juergen Beisert, Pengutronix > + * > + * This code is based on: > + * Author: Vitaly Wool <vital@embeddedalley.com> > + * > + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. > + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#define DRIVER_NAME "mxsfb" > + > +/** > + * @file > + * @brief LCDIF driver for i.MX23 and i.MX28 > + * > + * The LCDIF support four modes of operation > + * - MPU interface (to drive smart displays) -> not supported yet > + * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet > + * - Dotclock interface (to drive LC displays with RGB data and sync signals) > + * - DVI (to drive ITU-R BT656) -> not supported yet > + * > + * This driver depends on a correct setup of the pins used for this purpose > + * (platform specific). > + * > + * For the developer: Don't forget to set the data bus width to the display > + * in the imx_fb_videomode structure. You will else end up with ugly colours. > + * If you fight against jitter you can vary the clock delay. This is a feature > + * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give > + * the required value in the imx_fb_videomode structure. > + */ > + > +#include <linux/kernel.h> > +#include <linux/platform_device.h> > +#include <linux/clk.h> > +#include <linux/dma-mapping.h> > +#include <linux/io.h> > +#include <mach/fb.h> > +#include <mach/hardware.h> > +#include <mach/mxs.h> > + > +#define REG_SET 4 > +#define REG_CLR 8 > + We already have these defined in mxs.h -- Regards, Shawn ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-18 12:29 ` Shawn Guo @ 2011-02-21 14:17 ` Sascha Hauer 0 siblings, 0 replies; 24+ messages in thread From: Sascha Hauer @ 2011-02-21 14:17 UTC (permalink / raw) To: linux-arm-kernel On Fri, Feb 18, 2011 at 08:29:47PM +0800, Shawn Guo wrote: > > + > > +#include <linux/kernel.h> > > +#include <linux/platform_device.h> > > +#include <linux/clk.h> > > +#include <linux/dma-mapping.h> > > +#include <linux/io.h> > > +#include <mach/fb.h> > > +#include <mach/hardware.h> > > +#include <mach/mxs.h> > > + > > +#define REG_SET 4 > > +#define REG_CLR 8 > > + > We already have these defined in mxs.h I know, but as Wolfram realized this makes the driver architecture specific. So I decided to duplicate this here and to remove mach/hardware.h and mach/mxs.h (obviously still present in the last posted version) Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH] i.MX23/28 framebuffer driver
@ 2011-02-09 13:20 Sascha Hauer
2011-02-09 13:20 ` [PATCH 1/2] video: Add " Sascha Hauer
0 siblings, 1 reply; 24+ messages in thread
From: Sascha Hauer @ 2011-02-09 13:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
The following patches add framebuffer support for Freescale i.MX23/28
processors.
Sascha Hauer (2):
video: Add i.MX23/28 framebuffer driver
ARM i.MX23/28: Add framebuffer device support
arch/arm/mach-mxs/clock-mx23.c | 2 +-
arch/arm/mach-mxs/clock-mx28.c | 1 +
arch/arm/mach-mxs/devices-mx23.h | 4 +
arch/arm/mach-mxs/devices-mx28.h | 4 +
arch/arm/mach-mxs/devices/Kconfig | 4 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-mxsfb.c | 46 ++
arch/arm/mach-mxs/include/mach/fb.h | 48 ++
drivers/video/Kconfig | 9 +
drivers/video/Makefile | 1 +
drivers/video/mxsfb.c | 914 ++++++++++++++++++++++++++++
11 files changed, 1033 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-mxsfb.c
create mode 100644 arch/arm/mach-mxs/include/mach/fb.h
create mode 100644 drivers/video/mxsfb.c
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-09 13:20 [PATCH] " Sascha Hauer @ 2011-02-09 13:20 ` Sascha Hauer 2011-02-09 13:35 ` Lothar Waßmann ` (2 more replies) 0 siblings, 3 replies; 24+ messages in thread From: Sascha Hauer @ 2011-02-09 13:20 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: linux-fbdev at vger.kernel.org Cc: Shawn Guo <shawn.guo@freescale.com> --- arch/arm/mach-mxs/include/mach/fb.h | 48 ++ drivers/video/Kconfig | 9 + drivers/video/Makefile | 1 + drivers/video/mxsfb.c | 914 +++++++++++++++++++++++++++++++++++ 4 files changed, 972 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-mxs/include/mach/fb.h create mode 100644 drivers/video/mxsfb.c diff --git a/arch/arm/mach-mxs/include/mach/fb.h b/arch/arm/mach-mxs/include/mach/fb.h new file mode 100644 index 0000000..923f397 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/fb.h @@ -0,0 +1,48 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_FB_H +#define __MACH_FB_H + +#include <linux/fb.h> + +#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ +#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ +#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ +#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ + +#define FB_SYNC_DATA_ENABLE_HIGH_ACT 64 + +struct mxsfb_platform_data { + struct fb_videomode *mode_list; + unsigned mode_count; + + unsigned default_bpp; + + unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ + unsigned ld_intf_width; /* refer STMLCDIF_* macros */ + + unsigned fb_size; /* Size of the video memory. If zero a + * default will be used + */ + unsigned long fb_phys; /* physical address for the video memory. If + * zero the framebuffer memory will be dynamically + * allocated. If specified,fb_size must also be specified. + * fb_phys must be unused by Linux. + */ +}; + +#endif /* __MACH_FB_H */ diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 6bafb51b..e0ea23f 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -2365,6 +2365,15 @@ config FB_JZ4740 help Framebuffer support for the JZ4740 SoC. +config FB_MXS + tristate "MXS LCD framebuffer support" + depends on FB && ARCH_MXS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Framebuffer support for the MXS SoC. + source "drivers/video/omap/Kconfig" source "drivers/video/omap2/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 8c8fabd..9a096ae 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -153,6 +153,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o obj-$(CONFIG_FB_MX3) += mx3fb.o obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o +obj-$(CONFIG_FB_MXS) += mxsfb.o # the test framebuffer is last obj-$(CONFIG_FB_VIRTUAL) += vfb.o diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c new file mode 100644 index 0000000..92a5804 --- /dev/null +++ b/drivers/video/mxsfb.c @@ -0,0 +1,914 @@ +/* + * Copyright (C) 2010 Juergen Beisert, Pengutronix + * + * This code is based on: + * Author: Vitaly Wool <vital@embeddedalley.com> + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DRIVER_NAME "mxsfb" + +/** + * @file + * @brief LCDIF driver for i.MX23 and i.MX28 + * + * The LCDIF support four modes of operation + * - MPU interface (to drive smart displays) -> not supported yet + * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet + * - Dotclock interface (to drive LC displays with RGB data and sync signals) + * - DVI (to drive ITU-R BT656) -> not supported yet + * + * This driver depends on a correct setup of the pins used for this purpose + * (platform specific). + * + * For the developer: Don't forget to set the data bus width to the display + * in the imx_fb_videomode structure. You will else end up with ugly colours. + * If you fight against jitter you can vary the clock delay. This is a feature + * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give + * the required value in the imx_fb_videomode structure. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/dma-mapping.h> +#include <linux/io.h> +#include <mach/fb.h> +#include <mach/hardware.h> +#include <mach/mxs.h> + +#define CTRL 0x00 +#define CTRL1 0x10 +#define MX28_CTRL2 0x20 +#define MX23_TRANSFER_COUNT 0x20 +#define MX28_TRANSFER_COUNT 0x30 +#define MX28_CUR_BUF 0x40 +#define MX28_NEXT_BUF 0x50 +#define MX23_CUR_BUF 0x30 +#define MX23_NEXT_BUF 0x40 +#define TIMING 0x60 +#define VDCTRL0 0x70 +#define VDCTRL1 0x80 +#define VDCTRL2 0x90 +#define VDCTRL3 0xa0 +#define VDCTRL4 0xb0 +#define DVICTRL0 0xc0 +#define DVICTRL1 0xd0 +#define DVICTRL2 0xe0 +#define DVICTRL3 0xf0 +#define DVICTRL4 0x100 +#define MX28_DATA 0x180 +#define MX23_DATA 0x1b0 +#define MX28_DEBUG0 0x1d0 +#define MX23_DEBUG0 0x1f0 + +#define CTRL_SFTRST (1 << 31) +#define CTRL_CLKGATE (1 << 30) +#define CTRL_BYPASS_COUNT (1 << 19) +#define CTRL_VSYNC_MODE (1 << 18) +#define CTRL_DOTCLK_MODE (1 << 17) +#define CTRL_DATA_SELECT (1 << 16) +#define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10) +#define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3) +#define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8) +#define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) +#define CTRL_MASTER (1 << 5) +#define CTRL_DF16 (1 << 3) +#define CTRL_DF18 (1 << 2) +#define CTRL_DF24 (1 << 1) +#define CTRL_RUN (1 << 0) + +#define CTRL1_FIFO_CLEAR (1 << 21) +#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) +#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) + +#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16) +#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff) +#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff) +#define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff) + + +#define VDCTRL0_ENABLE_PRESENT (1 << 28) +#define VDCTRL0_VSYNC_ACT_HIGH (1 << 27) +#define VDCTRL0_HSYNC_ACT_HIGH (1 << 26) +#define VDCTRL0_DOTCLK_ACTIVE_HIGH (1 << 25) +#define VDCTRL0_POL_ACTIVE_HIGH (1 << 24) +#define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) +#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) +#define VDCTRL0_HALF_LINE (1 << 19) +#define VDCTRL0_HALF_LINE_MODE (1 << 18) +#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) +#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) + +#define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) +#define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) + +#define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) +#define VDCTRL3_VSYNC_ONLY (1 << 28) +#define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) +#define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) +#define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) +#define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) + +#define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* i.MX28 only */ +#define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* i.MX28 only */ +#define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) +#define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) + +#define DEBUG0_HSYNC (1 < 26) +#define DEBUG0_VSYNC (1 < 25) + +#define MIN_XRES 120 +#define MIN_YRES 120 + +#define RED 0 +#define GREEN 1 +#define BLUE 2 +#define TRANSP 3 + +enum mxsfb_devtype { + MXSFB_MX23, + MXSFB_MX28, +}; + +/* CPU dependent register offsets */ +struct mxsfb_devdata { + unsigned transfer_count; + unsigned cur_buf; + unsigned next_buf; + unsigned debug0; + unsigned hs_wdth_mask; + unsigned hs_wdth_shift; +}; + +struct mxsfb_info { + struct fb_info fb_info; + struct platform_device *pdev; + struct clk *clk; + void __iomem *base; /* registers */ + unsigned allocated_size; + int enabled; + unsigned ld_intf_width; + unsigned dotclk_delay; + const struct mxsfb_devdata *devdata; + int mapped; +}; + +static const struct mxsfb_devdata mxsfb_devdata[] = { + [MXSFB_MX23] = { + .transfer_count = MX23_TRANSFER_COUNT, + .cur_buf = MX23_CUR_BUF, + .next_buf = MX23_NEXT_BUF, + .debug0 = MX23_DEBUG0, + .hs_wdth_mask = 0xff, + .hs_wdth_shift = 24, + }, + [MXSFB_MX28] = { + .transfer_count = MX28_TRANSFER_COUNT, + .cur_buf = MX28_CUR_BUF, + .next_buf = MX28_NEXT_BUF, + .debug0 = MX28_DEBUG0, + .hs_wdth_mask = 0x3fff, + .hs_wdth_shift = 18, + }, +}; + +#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info)) + +/* mask and shift depends on architecture */ +static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val) +{ + return (val & host->devdata->hs_wdth_mask) << + host->devdata->hs_wdth_shift; +} + +static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val) +{ + return (val >> host->devdata->hs_wdth_shift) & + host->devdata->hs_wdth_mask; +} + +static const struct fb_bitfield def_rgb565[] = { + [RED] = { + .offset = 11, + .length = 5, + }, + [GREEN] = { + .offset = 5, + .length = 6, + }, + [BLUE] = { + .offset = 0, + .length = 5, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static const struct fb_bitfield def_rgb666[] = { + [RED] = { + .offset = 16, + .length = 6, + }, + [GREEN] = { + .offset = 8, + .length = 6, + }, + [BLUE] = { + .offset = 0, + .length = 6, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static const struct fb_bitfield def_rgb888[] = { + [RED] = { + .offset = 16, + .length = 8, + }, + [GREEN] = { + .offset = 8, + .length = 8, + }, + [BLUE] = { + .offset = 0, + .length = 8, + }, + [TRANSP] = { /* no support for transparency */ + .length = 0, + } +}; + +static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} + +static int mxsfb_check_var(struct fb_var_screeninfo *var, + struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + const struct fb_bitfield *rgb = NULL; + + if (var->xres < MIN_XRES) + var->xres = MIN_XRES; + if (var->yres < MIN_YRES) + var->yres = MIN_YRES; + + var->xres_virtual = var->xres; + + var->yres_virtual = var->yres; + + switch (var->bits_per_pixel) { + case 16: + /* always expect RGB 565 */ + rgb = def_rgb565; + break; + case 32: + switch (host->ld_intf_width) { + case STMLCDIF_8BIT: + pr_debug("Unsupported LCD bus width mapping\n"); + break; + case STMLCDIF_16BIT: + case STMLCDIF_18BIT: + /* 24 bit to 18 bit mapping */ + rgb = def_rgb666; + break; + case STMLCDIF_24BIT: + /* real 24 bit */ + rgb = def_rgb888; + break; + } + break; + default: + pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel); + return -EINVAL; + } + + /* + * Copy the RGB parameters for this display + * from the machine specific parameters. + */ + var->red = rgb[RED]; + var->green = rgb[GREEN]; + var->blue = rgb[BLUE]; + var->transp = rgb[TRANSP]; + + return 0; +} + +static void mxsfb_enable_controller(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + u32 reg; + + dev_dbg(&host->pdev->dev, "%s\n", __func__); + + clk_enable(host->clk); + clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U); + + /* if it was disabled, re-enable the mode again */ + reg = readl(host->base + CTRL); + reg |= CTRL_DOTCLK_MODE; + writel(reg, host->base + CTRL); + + /* enable the SYNC signals first, then the DMA engine */ + reg = readl(host->base + VDCTRL4); + reg |= VDCTRL4_SYNC_SIGNALS_ON; + writel(reg, host->base + VDCTRL4); + + reg = readl(host->base + CTRL); + reg |= CTRL_RUN; + writel(reg, host->base + CTRL); + + host->enabled = 1; +} + +static void mxsfb_disable_controller(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + unsigned loop; + u32 reg; + + dev_dbg(&host->pdev->dev, "%s\n", __func__); + + /* + * Even if we disable the controller here, it will still continue + * until its FIFOs are running out of data + */ + reg = readl(host->base + CTRL); + reg &= ~CTRL_DOTCLK_MODE; + writel(reg, host->base + CTRL); + + loop = 1000; + while (loop) { + reg = readl(host->base + CTRL); + if (!(reg & CTRL_RUN)) + break; + loop--; + } + + reg = readl(host->base + VDCTRL4); + reg &= ~VDCTRL4_SYNC_SIGNALS_ON; + writel(reg, host->base + VDCTRL4); + + clk_disable(host->clk); + + host->enabled = 0; +} + +static int mxsfb_set_par(struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + u32 ctrl, vdctrl0, vdctrl4; + int line_size, fb_size; + int reenable = 0; + + line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3); + fb_size = fb_info->var.yres_virtual * line_size; + + if (fb_size > fb_info->fix.smem_len) + return -ENOMEM; + + fb_info->fix.line_length = line_size; + + /* + * It seems, you can't re-program the controller if it is still running. + * This may lead into shifted pictures (FIFO issue?). + * So, first stop the controller and drain its FIFOs + */ + if (host->enabled) { + reenable = 1; + mxsfb_disable_controller(fb_info); + } + + /* clear the FIFOs */ + writel(CTRL1_FIFO_CLEAR, host->base + CTRL1 + 4); + + ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER | + CTRL_SET_BUS_WIDTH(host->ld_intf_width);; + + switch (fb_info->var.bits_per_pixel) { + case 16: + dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n"); + ctrl |= CTRL_SET_WORD_LENGTH(0); + writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + CTRL1); + break; + case 32: + dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n"); + ctrl |= CTRL_SET_WORD_LENGTH(3); + switch (host->ld_intf_width) { + case STMLCDIF_8BIT: + dev_dbg(&host->pdev->dev, + "Unsupported LCD bus width mapping\n"); + return -EINVAL; + case STMLCDIF_16BIT: + case STMLCDIF_18BIT: + /* 24 bit to 18 bit mapping */ + ctrl |= CTRL_DF24; /* ignore the upper 2 bits in + * each colour component + */ + break; + case STMLCDIF_24BIT: + /* real 24 bit */ + break; + } + /* do not use packed pixels = one pixel per word instead */ + writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + CTRL1); + break; + default: + dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n", + fb_info->var.bits_per_pixel); + return -EINVAL; + } + + writel(ctrl, host->base + CTRL); + + writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) | + TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres), + host->base + host->devdata->transfer_count); + + vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */ + VDCTRL0_VSYNC_PERIOD_UNIT | + VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | + VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len); + if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT) + vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; + if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT) + vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; + if (fb_info->var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT) + vdctrl0 |= VDCTRL0_POL_ACTIVE_HIGH; + + writel(vdctrl0, host->base + VDCTRL0); + + /* frame length in lines */ + writel(fb_info->var.upper_margin + fb_info->var.vsync_len + + fb_info->var.lower_margin + fb_info->var.yres, + host->base + VDCTRL1); + + /* line length in units of clocks or pixels */ + writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) | + VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin + + fb_info->var.hsync_len + fb_info->var.right_margin + + fb_info->var.xres), + host->base + VDCTRL2); + + writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin + + fb_info->var.hsync_len) | + SET_VERT_WAIT_CNT(fb_info->var.upper_margin + + fb_info->var.vsync_len), + host->base + VDCTRL3); + + vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres); + if (cpu_is_mx28()) + vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay); + writel(vdctrl4, host->base + VDCTRL4); + + writel(fb_info->fix.smem_start + + fb_info->fix.line_length * fb_info->var.yoffset, + host->base + host->devdata->next_buf); + + if (reenable) + mxsfb_enable_controller(fb_info); + + return 0; +} + +static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + u_int transp, struct fb_info *fb_info) +{ + unsigned int val; + int ret = -EINVAL; + + /* + * If greyscale is true, then we convert the RGB value + * to greyscale no matter what visual we are using. + */ + if (fb_info->var.grayscale) + red = green = blue = (19595 * red + 38470 * green + + 7471 * blue) >> 16; + + switch (fb_info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + /* + * 12 or 16-bit True Colour. We encode the RGB value + * according to the RGB bitfield information. + */ + if (regno < 16) { + u32 *pal = fb_info->pseudo_palette; + + val = chan_to_field(red, &fb_info->var.red); + val |= chan_to_field(green, &fb_info->var.green); + val |= chan_to_field(blue, &fb_info->var.blue); + + pal[regno] = val; + ret = 0; + } + break; + + case FB_VISUAL_STATIC_PSEUDOCOLOR: + case FB_VISUAL_PSEUDOCOLOR: + break; + } + + return ret; +} + +static int mxsfb_blank(int blank, struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + + switch (blank) { + case FB_BLANK_POWERDOWN: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + if (host->enabled) + mxsfb_disable_controller(fb_info); + break; + + case FB_BLANK_UNBLANK: + if (!host->enabled) + mxsfb_enable_controller(fb_info); + break; + } + return 0; +} + +static int mxsfb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *fb_info) +{ + struct mxsfb_info *host = to_imxfb_host(fb_info); + unsigned offset; + + if (var->xoffset != 0) + return -EINVAL; + + offset = fb_info->fix.line_length * var->yoffset; + + /* update on next VSYNC */ + writel(fb_info->fix.smem_start + offset, + host->base + host->devdata->next_buf); + + return 0; +} + +static struct fb_ops mxsfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = mxsfb_check_var, + .fb_set_par = mxsfb_set_par, + .fb_setcolreg = mxsfb_setcolreg, + .fb_blank = mxsfb_blank, + .fb_pan_display = mxsfb_pan_display, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +}; + +static int __devinit mxsfb_restore_mode(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + unsigned line_count; + unsigned period; + unsigned long pa, fbsize; + int bits_per_pixel, ofs; + u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; + struct fb_videomode vmode; + + /* Only restore the mode when the controller is running */ + ctrl = readl(host->base + CTRL); + if (!(ctrl & CTRL_RUN)) + return -EINVAL; + + vdctrl0 = readl(host->base + VDCTRL0); + vdctrl2 = readl(host->base + VDCTRL2); + vdctrl3 = readl(host->base + VDCTRL3); + vdctrl4 = readl(host->base + VDCTRL4); + + transfer_count = readl(host->base + host->devdata->transfer_count); + + vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count); + vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count); + + switch (CTRL_GET_WORD_LENGTH(ctrl)) { + case 0: + bits_per_pixel = 16; + break; + case 3: + bits_per_pixel = 32; + case 1: + default: + return -EINVAL; + } + + fb_info->var.bits_per_pixel = bits_per_pixel; + + vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U); + vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2); + vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len; + vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len - + vmode.left_margin - vmode.xres; + vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0); + period = readl(host->base + VDCTRL1); + vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len; + vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres; + + vmode.vmode = FB_VMODE_NONINTERLACED; + + vmode.sync = 0; + if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH) + vmode.sync |= FB_SYNC_HOR_HIGH_ACT; + if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH) + vmode.sync |= FB_SYNC_VERT_HIGH_ACT; + + pr_debug("Reconstructed video mode:\n"); + pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n", + vmode.xres, vmode.yres, + vmode.hsync_len, vmode.left_margin, vmode.right_margin, + vmode.vsync_len, vmode.upper_margin, vmode.lower_margin); + pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock)); + + fb_add_videomode(&vmode, &fb_info->modelist); + + host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl); + host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4); + + fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3); + + pa = readl(host->base + host->devdata->cur_buf); + fbsize = fb_info->fix.line_length * vmode.yres; + if (pa < fb_info->fix.smem_start) + return -EINVAL; + if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) + return -EINVAL; + ofs = pa - fb_info->fix.smem_start; + if (ofs) { + memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize); + writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf); + } + + line_count = fb_info->fix.smem_len / fb_info->fix.line_length; + fb_info->fix.ypanstep = 1; + + clk_enable(host->clk); + host->enabled = 1; + + return 0; +} + +static int __devinit mxsfb_init_fbinfo(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + struct fb_var_screeninfo *var = &fb_info->var; + struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data; + dma_addr_t fb_phys; + void *fb_virt; + unsigned fb_size = pdata->fb_size; + + fb_info->fbops = &mxsfb_ops; + fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; + strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id)); + fb_info->fix.type = FB_TYPE_PACKED_PIXELS; + fb_info->fix.ypanstep = 1; + fb_info->fix.visual = FB_VISUAL_TRUECOLOR, + fb_info->fix.accel = FB_ACCEL_NONE; + + var->bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16; + var->nonstd = 0; + var->activate = FB_ACTIVATE_NOW; + var->accel_flags = 0; + var->vmode = FB_VMODE_NONINTERLACED; + + host->dotclk_delay = pdata->dotclk_delay; + host->ld_intf_width = pdata->ld_intf_width; + + /* Memory allocation for framebuffer */ + if (pdata->fb_phys) { + if (!fb_size) + return -EINVAL; + + fb_phys = pdata->fb_phys; + + if (!request_mem_region(fb_phys, fb_size, host->pdev->name)) + return -ENOMEM; + + fb_virt = ioremap(fb_phys, fb_size); + if (!fb_virt) { + release_mem_region(fb_phys, fb_size); + return -ENOMEM; + } + host->mapped = 1; + } else { + if (!fb_size) + fb_size = SZ_2M; /* default */ + fb_virt = alloc_pages_exact(fb_size, GFP_DMA); + if (!fb_info->screen_base) + return -ENOMEM; + + fb_phys = virt_to_phys(fb_virt); + } + + fb_info->fix.smem_start = fb_phys; + fb_info->screen_base = fb_virt; + fb_info->screen_size = fb_info->fix.smem_len = fb_size; + + if (mxsfb_restore_mode(host)) + memset(fb_virt, 0, fb_size); + + return 0; +} + +static void __devexit mxsfb_free_videomem(struct mxsfb_info *host) +{ + struct fb_info *fb_info = &host->fb_info; + + if (host->mapped) { + iounmap(fb_info->screen_base); + release_mem_region(fb_info->fix.smem_start, + fb_info->screen_size); + } else { + free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len); + } +} + +static int __devinit mxsfb_probe(struct platform_device *pdev) +{ + struct mxsfb_platform_data *pdata = pdev->dev.platform_data; + struct resource *res; + struct mxsfb_info *host; + struct fb_info *fb_info; + struct fb_modelist *modelist; + int i, ret; + + if (!pdata) { + dev_err(&pdev->dev, "No platformdata. Giving up\n"); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Cannot get memory IO resource\n"); + return -ENODEV; + } + + if (!request_mem_region(res->start, resource_size(res), pdev->name)) + return -EBUSY; + + fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev); + if (!fb_info) { + dev_err(&pdev->dev, "Failed to allocate fbdev\n"); + ret = -ENOMEM; + goto error_alloc_info; + } + + host = to_imxfb_host(fb_info); + + host->base = ioremap(res->start, resource_size(res)); + if (!host->base) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto error_ioremap; + } + + host->pdev = pdev; + platform_set_drvdata(pdev, host); + + host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data]; + + host->clk = clk_get(&host->pdev->dev, NULL); + if (IS_ERR(host->clk)) { + ret = PTR_ERR(host->clk); + goto error_getclock; + } + + fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); + if (!fb_info->pseudo_palette) { + ret = -ENOMEM; + goto error_pseudo_pallette; + } + + INIT_LIST_HEAD(&fb_info->modelist); + + ret = mxsfb_init_fbinfo(host); + if (ret != 0) + goto error_init_fb; + + for (i = 0; i < pdata->mode_count; i++) + fb_add_videomode(&pdata->mode_list[i], &fb_info->modelist); + + modelist = list_first_entry(&fb_info->modelist, + struct fb_modelist, list); + fb_videomode_to_var(&fb_info->var, &modelist->mode); + + /* init the color fields */ + mxsfb_check_var(&fb_info->var, fb_info); + + platform_set_drvdata(pdev, fb_info); + + ret = register_framebuffer(fb_info); + if (ret != 0) { + dev_err(&pdev->dev,"Failed to register framebuffer\n"); + goto error_register; + } + + if (!host->enabled) { + writel(0, host->base + CTRL); + mxsfb_set_par(fb_info); + mxsfb_enable_controller(fb_info); + } + + return 0; + +error_register: + if (host->enabled) + clk_disable(host->clk); + fb_destroy_modelist(&fb_info->modelist); +error_init_fb: + kfree(fb_info->pseudo_palette); +error_pseudo_pallette: + clk_put(host->clk); +error_getclock: + iounmap(host->base); +error_ioremap: + framebuffer_release(fb_info); +error_alloc_info: + release_mem_region(res->start, resource_size(res)); + + return ret; +} + +static int __devexit mxsfb_remove(struct platform_device *pdev) +{ + struct fb_info *fb_info = platform_get_drvdata(pdev); + struct mxsfb_info *host = to_imxfb_host(fb_info); + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + mxsfb_disable_controller(fb_info); + + unregister_framebuffer(fb_info); + kfree(fb_info->pseudo_palette); + mxsfb_free_videomem(host); + iounmap(host->base); + clk_put(host->clk); + + framebuffer_release(fb_info); + release_mem_region(res->start, resource_size(res)); + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_device_id mxsfb_devtype[] = { + { + .name = "imx23-fb", + .driver_data = MXSFB_MX23, + }, { + .name = "imx28-fb", + .driver_data = MXSFB_MX28, + }, { + }, +}; +MODULE_DEVICE_TABLE(platform, mxsfb_devtype); + +static struct platform_driver mxsfb_driver = { + .probe = mxsfb_probe, + .remove = __devexit_p(mxsfb_remove), + .id_table = mxsfb_devtype, + .driver = { + .name = DRIVER_NAME, + }, +}; + +static int __init mxsfb_init(void) +{ + return platform_driver_register(&mxsfb_driver); +} + +static void __exit mxsfb_exit(void) +{ + platform_driver_unregister(&mxsfb_driver); +} + +module_init(mxsfb_init); +module_exit(mxsfb_exit); + +MODULE_DESCRIPTION("Freescale mxs framebuffer driver"); +MODULE_AUTHOR("Sascha Hauer, Pengutronix"); +MODULE_LICENSE("GPL"); -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-09 13:20 ` [PATCH 1/2] video: Add " Sascha Hauer @ 2011-02-09 13:35 ` Lothar Waßmann 2011-02-10 3:16 ` Li Frank-B20596 2011-02-10 9:23 ` Li Frank-B20596 2 siblings, 0 replies; 24+ messages in thread From: Lothar Waßmann @ 2011-02-09 13:35 UTC (permalink / raw) To: linux-arm-kernel Hi Sascha, Sascha Hauer writes: > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Paul Mundt <lethal@linux-sh.org> > Cc: linux-fbdev at vger.kernel.org > Cc: Shawn Guo <shawn.guo@freescale.com> > --- > arch/arm/mach-mxs/include/mach/fb.h | 48 ++ > drivers/video/Kconfig | 9 + > drivers/video/Makefile | 1 + > drivers/video/mxsfb.c | 914 +++++++++++++++++++++++++++++++++++ > 4 files changed, 972 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/mach-mxs/include/mach/fb.h > create mode 100644 drivers/video/mxsfb.c > [...] > diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c > new file mode 100644 > index 0000000..92a5804 > --- /dev/null > +++ b/drivers/video/mxsfb.c [...] > +static int __devexit mxsfb_remove(struct platform_device *pdev) > +{ > + struct fb_info *fb_info = platform_get_drvdata(pdev); > + struct mxsfb_info *host = to_imxfb_host(fb_info); > + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + > + mxsfb_disable_controller(fb_info); > IMO this should also be guarded by an: | if (host->enabled) otherwise it may lead to an unbalanced clk_disable() call. Lothar Wa?mann -- ___________________________________________________________ Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10 Gesch?ftsf?hrer: Matthias Kaussen Handelsregistereintrag: Amtsgericht Aachen, HRB 4996 www.karo-electronics.de | info at karo-electronics.de ___________________________________________________________ ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-09 13:20 ` [PATCH 1/2] video: Add " Sascha Hauer 2011-02-09 13:35 ` Lothar Waßmann @ 2011-02-10 3:16 ` Li Frank-B20596 2011-02-10 8:51 ` Juergen Beisert 2011-02-10 9:23 ` Li Frank-B20596 2 siblings, 1 reply; 24+ messages in thread From: Li Frank-B20596 @ 2011-02-10 3:16 UTC (permalink / raw) To: linux-arm-kernel > +#define CTRL 0x00 > +#define CTRL1 0x10 > +#define MX28_CTRL2 0x20 > +#define MX23_TRANSFER_COUNT 0x20 > +#define MX28_TRANSFER_COUNT 0x30 > +#define MX28_CUR_BUF 0x40 > +#define MX28_NEXT_BUF 0x50 > +#define MX23_CUR_BUF 0x30 > +#define MX23_NEXT_BUF 0x40 > +#define TIMING 0x60 > +#define VDCTRL0 0x70 > +#define VDCTRL1 0x80 > +#define VDCTRL2 0x90 > +#define VDCTRL3 0xa0 > +#define VDCTRL4 0xb0 Why you give up mx23/mx28 register define role, which generate from SOC xml. There is a set header files for each mx23/mx28 module, which generate from xml. I know original header files affect run time one Image. But I think we can copy common part of such register definition because That keep consistent with mx23/mx28 data sheet. Data sheet and header file generate from one source xml. HW_<Module name>_<Register name>. BM_<Module name>_<Register name>_Bit name. ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 3:16 ` Li Frank-B20596 @ 2011-02-10 8:51 ` Juergen Beisert 2011-02-10 9:15 ` Li Frank-B20596 0 siblings, 1 reply; 24+ messages in thread From: Juergen Beisert @ 2011-02-10 8:51 UTC (permalink / raw) To: linux-arm-kernel Li Frank-B20596 wrote: > > +#define CTRL 0x00 > > +#define CTRL1 0x10 > > +#define MX28_CTRL2 0x20 > > +#define MX23_TRANSFER_COUNT 0x20 > > +#define MX28_TRANSFER_COUNT 0x30 > > +#define MX28_CUR_BUF 0x40 > > +#define MX28_NEXT_BUF 0x50 > > +#define MX23_CUR_BUF 0x30 > > +#define MX23_NEXT_BUF 0x40 > > +#define TIMING 0x60 > > +#define VDCTRL0 0x70 > > +#define VDCTRL1 0x80 > > +#define VDCTRL2 0x90 > > +#define VDCTRL3 0xa0 > > +#define VDCTRL4 0xb0 > > Why you give up mx23/mx28 register define role, which generate from SOC > xml. Your macros prevent me from writing short and compact code. If you need more than one of these macros you always have to split each line to follow the 80 columns rule. Unreadable. > There is a set header files for each mx23/mx28 module, which generate > from xml. I know original header files affect run time one Image. > But I think we can copy common part of such register definition because > That keep consistent with mx23/mx28 data sheet. Data sheet and header file > generate from one source xml. > > HW_<Module name>_<Register name>. > BM_<Module name>_<Register name>_Bit name. IMHO when I define the macros where they belong to, there is not need for this redundant HW_<Module name> or BW__<Module name> prefixes. They are just needless. Regards, Juergen -- Pengutronix e.K. | Juergen Beisert | Linux Solutions for Science and Industry | Phone: +49-8766-939 228 | Vertretung Sued/Muenchen, Germany | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 8:51 ` Juergen Beisert @ 2011-02-10 9:15 ` Li Frank-B20596 2011-02-10 9:52 ` Juergen Beisert 0 siblings, 1 reply; 24+ messages in thread From: Li Frank-B20596 @ 2011-02-10 9:15 UTC (permalink / raw) To: linux-arm-kernel > > > +#define VDCTRL1 0x80 > > > +#define VDCTRL2 0x90 > > > +#define VDCTRL3 0xa0 > > > +#define VDCTRL4 0xb0 > > > > Why you give up mx23/mx28 register define role, which generate from SOC > > xml. > > Your macros prevent me from writing short and compact code. If you need > more > than one of these macros you always have to split each line to follow the > 80 > columns rule. Unreadable. > > > There is a set header files for each mx23/mx28 module, which generate > > from xml. I know original header files affect run time one Image. > > But I think we can copy common part of such register definition because > > That keep consistent with mx23/mx28 data sheet. Data sheet and header > file > > generate from one source xml. > > > > HW_<Module name>_<Register name>. > > BM_<Module name>_<Register name>_Bit name. > > IMHO when I define the macros where they belong to, there is not need for > this > redundant HW_<Module name> or BW__<Module name> prefixes. They are just > needless. At first, someone complain name is longer. But during mx23/mx28 developing, Everyone start enjoy such definition because there are not error happen about register and bit position definition and identical map to silicon spec. Developer needn't look up register header file when coding, just write down Register name or bit name according to mx23/mx28 spec. If you still think it is too long, I suggest keep HW_ and BM_ prefix to distinguish Which one is register name, which one is bit mask. Imx23/imx28 register have consistent convention. HW_ is register name BM_ is bit mask BP_ is bit position. BF_(x) is ((x<<BP)&BM_) > > Regards, > Juergen > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 9:15 ` Li Frank-B20596 @ 2011-02-10 9:52 ` Juergen Beisert 2011-02-10 10:37 ` Li Frank-B20596 0 siblings, 1 reply; 24+ messages in thread From: Juergen Beisert @ 2011-02-10 9:52 UTC (permalink / raw) To: linux-arm-kernel Li Frank-B20596 wrote: > > > > +#define VDCTRL1 0x80 > > > > +#define VDCTRL2 0x90 > > > > +#define VDCTRL3 0xa0 > > > > +#define VDCTRL4 0xb0 > > > > > > Why you give up mx23/mx28 register define role, which generate from SOC > > > xml. > > > > Your macros prevent me from writing short and compact code. If you need > > more than one of these macros you always have to split each line to follow > > the 80 columns rule. Unreadable. > > > > > There is a set header files for each mx23/mx28 module, which generate > > > from xml. I know original header files affect run time one Image. > > > But I think we can copy common part of such register definition because > > > That keep consistent with mx23/mx28 data sheet. Data sheet and header > > > file > > > > > generate from one source xml. > > > > > > HW_<Module name>_<Register name>. > > > BM_<Module name>_<Register name>_Bit name. > > > > IMHO when I define the macros where they belong to, there is not need for > > this redundant HW_<Module name> or BW__<Module name> prefixes. They are > > just needless. > > At first, someone complain name is longer. But during mx23/mx28 developing, > Everyone start enjoy such definition because there are not error happen > about register and bit position definition and identical map to silicon > spec. This kind of macro encryption _may_ help when you are coding the driver the first time. But after reading and reading it again (while testing and debugging) all these prefixes and suffixes do not add any valuable information. They only fill up your lines, enlarges your source code and make you blind for the real bug... Everyone who wants to see how source code looks that uses these longs macros I can recommend reading the so called 'bootlets' source code. :-)) > Developer needn't look up register header file when coding, just That's why I add these macros into the source file instead into a header file. > write down Register name or bit name according to mx23/mx28 spec. And sometimes the spec is incomplete or just wrong and so on. Independent of any macro naming policy. > If you still think it is too long, I suggest keep HW_ and BM_ prefix to > distinguish Which one is register name, which one is bit mask. The used macro in the address part of the writel() must be an offset, while the macro used in the value part must be a bit definition. Anything else is redundant. Regards, Juergen -- Pengutronix e.K. | Juergen Beisert | Linux Solutions for Science and Industry | Phone: +49-8766-939 228 | Vertretung Sued/Muenchen, Germany | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 9:52 ` Juergen Beisert @ 2011-02-10 10:37 ` Li Frank-B20596 2011-02-10 11:12 ` Juergen Beisert 0 siblings, 1 reply; 24+ messages in thread From: Li Frank-B20596 @ 2011-02-10 10:37 UTC (permalink / raw) To: linux-arm-kernel > This kind of macro encryption _may_ help when you are coding the driver > the > first time. But after reading and reading it again (while testing and > debugging) all these prefixes and suffixes do not add any valuable > information. They only fill up your lines, enlarges your source code and > make > you blind for the real bug... > > Everyone who wants to see how source code looks that uses these longs > macros I > can recommend reading the so called 'bootlets' source code. :-)) The complex of bootlets is not long macro, but the work around to make sure Chip PMU work safely. If there are not such macro, power_prep will become more difficult to understand. > > > Developer needn't look up register header file when coding, just > > That's why I add these macros into the source file instead into a header > file. > > > write down Register name or bit name according to mx23/mx28 spec. > > And sometimes the spec is incomplete or just wrong and so on. Independent > of > any macro naming policy. Not at all. Mx23/mx28 can keep spec, header file and RTL consistent just because using one source and multiple output. During Freescale mx28 BSP develop, never happen bit and register definition error. > > > If you still think it is too long, I suggest keep HW_ and BM_ prefix to > > distinguish Which one is register name, which one is bit mask. > > The used macro in the address part of the writel() must be an offset, > while > the macro used in the value part must be a bit definition. Anything else > is > redundant. If name is too short, there are possible to cause name pollution. BM_, BP_, BF_ have their implication. VDCTRL4_SET_DOTCLK_DLY(x), according to our macro policy, it should be BF_VDCTRL4_SET_DOTCLK_DLY(x). Generally, you need Reg = readl(offset+VDCTRL4); Reg &=~ ((0x7)<<29); Reg |= VDCTRL4_SET_DOTCLK_DLY(value) Writel(reg, offset+VDCTRL4) Compared with our macro policy. Reg = readl(offset+HW_VDCTRL4); Reg &=~ BM_VDCTRL4_SET_DOTCLK_DLY; Reg |= BF_VDCTRL4_SET_DOTCLK_DLY(value) Writel(reg, offset+HW_VDCTRL4) > > Regards, > Juergen > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 10:37 ` Li Frank-B20596 @ 2011-02-10 11:12 ` Juergen Beisert 2011-02-10 12:23 ` Li Frank-B20596 0 siblings, 1 reply; 24+ messages in thread From: Juergen Beisert @ 2011-02-10 11:12 UTC (permalink / raw) To: linux-arm-kernel Li Frank-B20596 wrote: > > This kind of macro encryption _may_ help when you are coding the driver > > the > > first time. But after reading and reading it again (while testing and > > debugging) all these prefixes and suffixes do not add any valuable > > information. They only fill up your lines, enlarges your source code and > > make > > you blind for the real bug... > > > > Everyone who wants to see how source code looks that uses these longs > > macros I > > can recommend reading the so called 'bootlets' source code. :-)) > > The complex of bootlets is not long macro, but the work around to make sure > Chip PMU work safely. If there are not such macro, power_prep will become > more difficult to understand. Its your opinion... > > > Developer needn't look up register header file when coding, just > > > > That's why I add these macros into the source file instead into a header > > file. > > > > > write down Register name or bit name according to mx23/mx28 spec. > > > > And sometimes the spec is incomplete or just wrong and so on. Independent > > of any macro naming policy. > > Not at all. Mx23/mx28 can keep spec, header file and RTL consistent just > because using one source and multiple output. During Freescale mx28 BSP > develop, never happen bit and register definition error. > > > > If you still think it is too long, I suggest keep HW_ and BM_ prefix to > > > distinguish Which one is register name, which one is bit mask. > > > > The used macro in the address part of the writel() must be an offset, > > while > > the macro used in the value part must be a bit definition. Anything else > > is > > redundant. > > If name is too short, there are possible to cause name pollution. > BM_, BP_, BF_ have their implication. If you collect everything in header files: Yes. If you keep the macros where they are used, IMHO: No. > VDCTRL4_SET_DOTCLK_DLY(x), according to our macro policy, it should be > BF_VDCTRL4_SET_DOTCLK_DLY(x). > > Generally, you need > Reg = readl(offset+VDCTRL4); > Reg &=~ ((0x7)<<29); What about? > Reg &= ~VDCTRL4_SET_DOTCLK_DLY(0x7); Or? > Reg &= ~VDCTRL4_SET_DOTCLK_DLY_MASK; Okay, the even get longer and longer. > Reg |= VDCTRL4_SET_DOTCLK_DLY(value) > Writel(reg, offset+VDCTRL4) > > Compared with our macro policy. > > Reg = readl(offset+HW_VDCTRL4); > Reg &=~ BM_VDCTRL4_SET_DOTCLK_DLY; > Reg |= BF_VDCTRL4_SET_DOTCLK_DLY(value) > Writel(reg, offset+HW_VDCTRL4) Anywhere else such naming policy in the kernel? I have to deal with all kind of CPUs, not only i.MX23/28. Regards, Juergen -- Pengutronix e.K. | Juergen Beisert | Linux Solutions for Science and Industry | Phone: +49-8766-939 228 | Vertretung Sued/Muenchen, Germany | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 11:12 ` Juergen Beisert @ 2011-02-10 12:23 ` Li Frank-B20596 0 siblings, 0 replies; 24+ messages in thread From: Li Frank-B20596 @ 2011-02-10 12:23 UTC (permalink / raw) To: linux-arm-kernel > > What about? > > Reg &= ~VDCTRL4_SET_DOTCLK_DLY(0x7); > Or? > > Reg &= ~VDCTRL4_SET_DOTCLK_DLY_MASK; > Okay, the even get longer and longer. If use 0x7, you have to take care bit width. If use VDCTRL4_SET_DOTCLK_DLY_MASK, I think BF_ and BM_ is better. > > Reg |= VDCTRL4_SET_DOTCLK_DLY(value) > > Writel(reg, offset+VDCTRL4) > > > > Compared with our macro policy. > > > > Reg = readl(offset+HW_VDCTRL4); > > Reg &=~ BM_VDCTRL4_SET_DOTCLK_DLY; > > Reg |= BF_VDCTRL4_SET_DOTCLK_DLY(value) > > Writel(reg, offset+HW_VDCTRL4) > > Anywhere else such naming policy in the kernel? I have to deal with all > kind > of CPUs, not only i.MX23/28. This driver is for mx23/mx28. I have not found such policy in the kernel, otherwise I have generated that at beginning. It is better if all of mx23/mx28 driver follow the same role. ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-09 13:20 ` [PATCH 1/2] video: Add " Sascha Hauer 2011-02-09 13:35 ` Lothar Waßmann 2011-02-10 3:16 ` Li Frank-B20596 @ 2011-02-10 9:23 ` Li Frank-B20596 2011-02-10 9:46 ` Juergen Beisert 2 siblings, 1 reply; 24+ messages in thread From: Li Frank-B20596 @ 2011-02-10 9:23 UTC (permalink / raw) To: linux-arm-kernel > + > + /* if it was disabled, re-enable the mode again */ > + reg = readl(host->base + CTRL); > + reg |= CTRL_DOTCLK_MODE; > + writel(reg, host->base + CTRL); writel(CTRL_DOTCLK_MODE, host->base + CTRL_SET) CTRL_SET is CTRL+0x4 SET and CLR register is easier than Read and write back. ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 9:23 ` Li Frank-B20596 @ 2011-02-10 9:46 ` Juergen Beisert 2011-02-10 10:08 ` Li Frank-B20596 2011-02-10 10:47 ` Wolfram Sang 0 siblings, 2 replies; 24+ messages in thread From: Juergen Beisert @ 2011-02-10 9:46 UTC (permalink / raw) To: linux-arm-kernel Li Frank-B20596 wrote: > > + > > + /* if it was disabled, re-enable the mode again */ > > + reg = readl(host->base + CTRL); > > + reg |= CTRL_DOTCLK_MODE; > > + writel(reg, host->base + CTRL); > > writel(CTRL_DOTCLK_MODE, host->base + CTRL_SET) > CTRL_SET is CTRL+0x4 > SET and CLR register is easier than Read and write back. But you must always check, if the register really has such a SET and CLEAR feature. Not all registers have this feature... But in this case you are right. But I would prefer: #define SET 4 #define CLEAR 8 [...] writel(CTRL_DOTCLK_MODE, host->base + CTRL + SET) :-) Regards, Juergen -- Pengutronix e.K. | Juergen Beisert | Linux Solutions for Science and Industry | Phone: +49-8766-939 228 | Vertretung Sued/Muenchen, Germany | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 9:46 ` Juergen Beisert @ 2011-02-10 10:08 ` Li Frank-B20596 2011-02-10 10:47 ` Wolfram Sang 1 sibling, 0 replies; 24+ messages in thread From: Li Frank-B20596 @ 2011-02-10 10:08 UTC (permalink / raw) To: linux-arm-kernel > Li Frank-B20596 wrote: > > > + > > > + /* if it was disabled, re-enable the mode again */ > > > + reg = readl(host->base + CTRL); > > > + reg |= CTRL_DOTCLK_MODE; > > > + writel(reg, host->base + CTRL); > > > > writel(CTRL_DOTCLK_MODE, host->base + CTRL_SET) > > CTRL_SET is CTRL+0x4 > > SET and CLR register is easier than Read and write back. > > But you must always check, if the register really has such a SET and > CLEAR > feature. Not all registers have this feature... That's a reason why I suggest use register header that generate from xml. HW_XX_CTRL_SET will exist if there are such register in hardware. If hardware have not such register, there are not _SET and _CLR. Compiler will report error if user use _SET but hardware not such register. > > But in this case you are right. > > But I would prefer: > #define SET 4 > #define CLEAR 8 > [...] > writel(CTRL_DOTCLK_MODE, host->base + CTRL + SET) > :-) > > Regards, > Juergen ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 9:46 ` Juergen Beisert 2011-02-10 10:08 ` Li Frank-B20596 @ 2011-02-10 10:47 ` Wolfram Sang 2011-02-10 11:51 ` Sascha Hauer 1 sibling, 1 reply; 24+ messages in thread From: Wolfram Sang @ 2011-02-10 10:47 UTC (permalink / raw) To: linux-arm-kernel > But I would prefer: > #define SET 4 > #define CLEAR 8 > [...] > writel(CTRL_DOTCLK_MODE, host->base + CTRL + SET) NACK. This will indeed not be caught by the compiler. And while I like the shorter macros better as well, an MXSFB_ prefix should be added IMO. Macros like CTRL and TIMING are not too well protected. Regards, Wolfram -- Pengutronix e.K. | Wolfram Sang | Industrial Linux Solutions | http://www.pengutronix.de/ | -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 198 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20110210/d36ddd33/attachment.sig> ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 10:47 ` Wolfram Sang @ 2011-02-10 11:51 ` Sascha Hauer 2011-02-10 12:32 ` Li Frank-B20596 0 siblings, 1 reply; 24+ messages in thread From: Sascha Hauer @ 2011-02-10 11:51 UTC (permalink / raw) To: linux-arm-kernel On Thu, Feb 10, 2011 at 11:47:25AM +0100, Wolfram Sang wrote: > > But I would prefer: > > #define SET 4 > > #define CLEAR 8 > > [...] > > writel(CTRL_DOTCLK_MODE, host->base + CTRL + SET) For this we already have __mxs_setl. > > NACK. > > This will indeed not be caught by the compiler. > > And while I like the shorter macros better as well, an MXSFB_ prefix > should be added IMO. Macros like CTRL and TIMING are not too well > protected. +1 for a prefix, be it MXSFB_ or LCDIF_, will change this. Otherwise can we please stop about arguing about register defines? It's too much a matter of taste and there is no perfect way to solve this. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver 2011-02-10 11:51 ` Sascha Hauer @ 2011-02-10 12:32 ` Li Frank-B20596 0 siblings, 0 replies; 24+ messages in thread From: Li Frank-B20596 @ 2011-02-10 12:32 UTC (permalink / raw) To: linux-arm-kernel > On Thu, Feb 10, 2011 at 11:47:25AM +0100, Wolfram Sang wrote: > > > But I would prefer: > > > #define SET 4 > > > #define CLEAR 8 > > > [...] > > > writel(CTRL_DOTCLK_MODE, host->base + CTRL + SET) > > For this we already have __mxs_setl. > > > > > NACK. > > > > This will indeed not be caught by the compiler. > > > > And while I like the shorter macros better as well, an MXSFB_ prefix > > should be added IMO. Macros like CTRL and TIMING are not too well > > protected. > > +1 for a prefix, be it MXSFB_ or LCDIF_, will change this. > > Otherwise can we please stop about arguing about register defines? It's > too much a matter of taste and there is no perfect way to solve this. > > Sascha > Guo Shawn mmc driver's patch is good example to use mx23/mx28 register macro. Best regards Frank Li ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2011-02-28 8:02 UTC | newest] Thread overview: 24+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-02-28 8:02 [PATCH v3] i.MX23/28 Framebuffer support Sascha Hauer 2011-02-28 8:02 ` [PATCH 1/2] video: Add i.MX23/28 framebuffer driver Sascha Hauer 2011-02-28 8:02 ` [PATCH 2/2] ARM i.MX23/28: Add framebuffer device support Sascha Hauer -- strict thread matches above, loose matches on Subject: below -- 2011-02-16 9:56 [PATCH v2] i.MX23/28 Framebuffer driver Sascha Hauer 2011-02-16 9:56 ` [PATCH 1/2] video: Add i.MX23/28 framebuffer driver Sascha Hauer 2011-02-18 5:24 ` Shawn Guo 2011-02-18 8:30 ` Sascha Hauer 2011-02-18 8:57 ` Shawn Guo 2011-02-18 12:29 ` Shawn Guo 2011-02-21 14:17 ` Sascha Hauer 2011-02-09 13:20 [PATCH] " Sascha Hauer 2011-02-09 13:20 ` [PATCH 1/2] video: Add " Sascha Hauer 2011-02-09 13:35 ` Lothar Waßmann 2011-02-10 3:16 ` Li Frank-B20596 2011-02-10 8:51 ` Juergen Beisert 2011-02-10 9:15 ` Li Frank-B20596 2011-02-10 9:52 ` Juergen Beisert 2011-02-10 10:37 ` Li Frank-B20596 2011-02-10 11:12 ` Juergen Beisert 2011-02-10 12:23 ` Li Frank-B20596 2011-02-10 9:23 ` Li Frank-B20596 2011-02-10 9:46 ` Juergen Beisert 2011-02-10 10:08 ` Li Frank-B20596 2011-02-10 10:47 ` Wolfram Sang 2011-02-10 11:51 ` Sascha Hauer 2011-02-10 12:32 ` Li Frank-B20596
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).