[PATCH V2 1/2] AHCI Add the AHCI SATA feature on MX53 platforms

[PATCH V2 1/2] AHCI Add the AHCI SATA feature on MX53 platforms

[Richard Zhu]

Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com>
---
 arch/arm/mach-mx5/clock-mx51-mx53.c             |   11 +++++
 arch/arm/mach-mx5/devices-imx53.h               |    4 ++
 arch/arm/plat-mxc/devices/Kconfig               |    4 ++
 arch/arm/plat-mxc/devices/Makefile              |    1 +
 arch/arm/plat-mxc/devices/platform-ahci-imx.c   |   55 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/ahci_sata.h      |   51 +++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/devices-common.h |   10 ++++
 7 files changed, 136 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/devices/platform-ahci-imx.c
 create mode 100644 arch/arm/plat-mxc/include/mach/ahci_sata.h

diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 652ace4..8bf2bab 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1380,6 +1380,14 @@ static struct clk esdhc4_mx53_clk = {
 	.secondary = &esdhc4_ipg_clk,
 };
 
+static struct clk sata_clk = {
+	.parent = &ipg_clk,
+	.enable = _clk_max_enable,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+	.disable = _clk_max_disable,
+};
+
 DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
 DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
 DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1468,6 +1476,9 @@ static struct clk_lookup mx53_lookups[] = {
 	_REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
 	_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
 	_REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
+	_REGISTER_CLOCK("ahci.0", NULL, sata_clk)
+	_REGISTER_CLOCK(NULL, "usb_phy1", usb_phy1_clk)
+	_REGISTER_CLOCK(NULL, "ahb", ahb_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 9251008..09ebb43 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -33,3 +33,7 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
 extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
 #define imx53_add_imx2_wdt(id, pdata)	\
 	imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
+
+extern const struct imx_ahci_imx_data imx53_ahci_imx_data[] __initconst;
+#define imx53_add_ahci_imx(id, pdata)   \
+	imx_add_ahci_imx(&imx53_ahci_imx_data[id], pdata)
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index b9ab1d5..087595a 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -71,3 +71,7 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
 
 config IMX_HAVE_PLATFORM_SPI_IMX
 	bool
+
+config IMX_HAVE_PLATFORM_SATA_AHCI
+	bool
+	default y if SOC_IMX53
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 75cd2ec..e0b7fa3 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_SATA_AHCI) +=  platform-ahci-imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
new file mode 100644
index 0000000..d6da344
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_ahci_data_entry_single(soc)					\
+	{								\
+		.iobase = soc ## _SATA_BASE_ADDR,			\
+		.irq = soc ## _INT_SATA,				\
+	}
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
+	imx_ahci_data_entry_single(MX53);
+#endif
+
+struct platform_device *__init imx_add_ahci_imx(
+		const struct imx_ahci_imx_data *data,
+		const struct ahci_platform_data *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = data->iobase,
+			.end = data->iobase + SZ_4K - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = data->irq,
+			.end = data->irq,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	return imx_add_platform_device_dmamask("ahci", 0,
+			res, ARRAY_SIZE(res),
+			pdata, sizeof(*pdata),  DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/include/mach/ahci_sata.h b/arch/arm/plat-mxc/include/mach/ahci_sata.h
new file mode 100644
index 0000000..25df23e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/ahci_sata.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __PLAT_MXC_AHCI_SATA_H__
+#define __PLAT_MXC_AHCI_SATA_H__
+
+enum {
+	HOST_CAP = 0x00,
+	HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
+	HOST_PORTS_IMPL	= 0x0c,
+	HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
+	/* Offest used to control the MPLL input clk */
+	PHY_CR_CLOCK_FREQ_OVRD = 0x12,
+	/* Port0 SATA Status */
+	PORT_SATA_SR = 0x128,
+	/* Port0 PHY Control */
+	PORT_PHY_CTL = 0x178,
+	/* PORT_PHY_CTL bits */
+	PORT_PHY_CTL_CAP_ADR_LOC = 0x10000,
+	PORT_PHY_CTL_CAP_DAT_LOC = 0x20000,
+	PORT_PHY_CTL_WRITE_LOC = 0x40000,
+	PORT_PHY_CTL_READ_LOC = 0x80000,
+	/* Port0 PHY Status */
+	PORT_PHY_SR = 0x17c,
+	/* PORT_PHY_SR */
+	PORT_PHY_STAT_DATA_LOC = 0,
+	PORT_PHY_STAT_ACK_LOC = 18,
+	/* SATA PHY Register */
+	SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001,
+	SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008,
+	SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009,
+	SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A,
+	SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017,
+};
+
+#endif /* __PLAT_MXC_AHCI_SATA_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 8658c9c..81baca6 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -264,3 +264,13 @@ struct imx_spi_imx_data {
 struct platform_device *__init imx_add_spi_imx(
 		const struct imx_spi_imx_data *data,
 		const struct spi_imx_master *pdata);
+
+#include <linux/ahci_platform.h>
+struct imx_ahci_imx_data {
+	int id;
+	resource_size_t iobase;
+	resource_size_t irq;
+};
+struct platform_device *__init imx_add_ahci_imx(
+		const struct imx_ahci_imx_data *data,
+		const struct ahci_platform_data *pdata);
-- 
1.7.1

[PATCH V2 2/2] MX53 Enable the AHCI SATA on MX53 LOCO

[Richard Zhu]

Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com>
---
 arch/arm/mach-mx5/board-mx53_loco.c |   88 +++++++++++++++++++++++++++++++++++
 1 files changed, 88 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 0a18f8d..336273b 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -23,11 +23,13 @@
 #include <linux/fec.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/ahci_platform.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx53.h>
+#include <mach/ahci_sata.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -38,6 +40,8 @@
 
 #define LOCO_FEC_PHY_RST		IMX_GPIO_NR(7, 6)
 
+static struct clk *sata_clk, *sata_ref_clk;
+
 static iomux_v3_cfg_t mx53_loco_pads[] = {
 	/* FEC */
 	MX53_PAD_FEC_MDC__FEC_MDC,
@@ -203,6 +207,89 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
 	.bitrate = 100000,
 };
 
+/* HW Initialization, if return 0, initialization is successful. */
+static int sata_init(struct device *dev, void __iomem *addr)
+{
+	int ret = 0;
+	u32 tmpdata;
+	struct clk *clk;
+
+	sata_clk = clk_get(dev, NULL);
+	if (IS_ERR(sata_clk)) {
+		dev_err(dev, "no sata clock.\n");
+		return PTR_ERR(sata_clk);
+	}
+	ret = clk_enable(sata_clk);
+	if (ret) {
+		dev_err(dev, "can't enable sata clock.\n");
+		clk_put(sata_clk);
+		return ret;
+	}
+
+	/* FSL IMX AHCI SATA uses the internal usb phy1 clk on loco */
+	sata_ref_clk = clk_get(NULL, "usb_phy1");
+	if (IS_ERR(sata_ref_clk)) {
+		dev_err(dev, "no sata ref clock.\n");
+		ret = PTR_ERR(sata_ref_clk);
+		goto release_sata_clk;
+	}
+	ret = clk_enable(sata_ref_clk);
+	if (ret) {
+		dev_err(dev, "can't enable sata ref clock.\n");
+		clk_put(sata_ref_clk);
+		goto release_sata_clk;
+	}
+
+	/* Get the AHB clock rate, and configure the TIMER1MS reg later */
+	clk = clk_get(NULL, "ahb");
+	if (IS_ERR(clk)) {
+		dev_err(dev, "no ahb clock.\n");
+		ret = PTR_ERR(clk);
+		goto release_sata_ref_clk;
+	}
+
+	tmpdata = readl(addr + HOST_CAP);
+	if (!(tmpdata & HOST_CAP_SSS)) {
+		tmpdata |= HOST_CAP_SSS;
+		writel(tmpdata, addr + HOST_CAP);
+	}
+
+	if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
+		writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
+			addr + HOST_PORTS_IMPL);
+
+	tmpdata = clk_get_rate(clk) / 1000;
+	clk_put(clk);
+	writel(tmpdata, addr + HOST_TIMER1MS);
+
+	clk = NULL;
+	return ret;
+
+release_sata_ref_clk:
+	clk_disable(sata_ref_clk);
+	clk_put(sata_ref_clk);
+
+release_sata_clk:
+	clk_disable(sata_clk);
+	clk_put(sata_clk);
+
+	clk = NULL;
+	return ret;
+}
+
+static void sata_exit(struct device *dev)
+{
+	clk_disable(sata_ref_clk);
+	clk_put(sata_ref_clk);
+
+	clk_disable(sata_clk);
+	clk_put(sata_clk);
+}
+
+static struct ahci_platform_data sata_data = {
+	.init = sata_init,
+	.exit = sata_exit, };
+
 static void __init mx53_loco_board_init(void)
 {
 	mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
@@ -215,6 +302,7 @@ static void __init mx53_loco_board_init(void)
 	imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
 	imx53_add_sdhci_esdhc_imx(0, NULL);
 	imx53_add_sdhci_esdhc_imx(2, NULL);
+	imx53_add_ahci_imx(0, &sata_data);
 }
 
 static void __init mx53_loco_timer_init(void)
-- 
1.7.1

[PATCH V2 2/2] MX53 Enable the AHCI SATA on MX53 LOCO

[Sascha Hauer]

On Thu, Mar 17, 2011 at 05:58:03PM +0800, Richard Zhu wrote:
> Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> ---
>  arch/arm/mach-mx5/board-mx53_loco.c |   88 +++++++++++++++++++++++++++++++++++
>  1 files changed, 88 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
> index 0a18f8d..336273b 100644
> --- a/arch/arm/mach-mx5/board-mx53_loco.c
> +++ b/arch/arm/mach-mx5/board-mx53_loco.c
> @@ -23,11 +23,13 @@
>  #include <linux/fec.h>
>  #include <linux/delay.h>
>  #include <linux/gpio.h>
> +#include <linux/ahci_platform.h>
>  
>  #include <mach/common.h>
>  #include <mach/hardware.h>
>  #include <mach/imx-uart.h>
>  #include <mach/iomux-mx53.h>
> +#include <mach/ahci_sata.h>
>  
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
> @@ -38,6 +40,8 @@
>  
>  #define LOCO_FEC_PHY_RST		IMX_GPIO_NR(7, 6)
>  
> +static struct clk *sata_clk, *sata_ref_clk;
> +
>  static iomux_v3_cfg_t mx53_loco_pads[] = {
>  	/* FEC */
>  	MX53_PAD_FEC_MDC__FEC_MDC,
> @@ -203,6 +207,89 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
>  	.bitrate = 100000,
>  };
>  
> +/* HW Initialization, if return 0, initialization is successful. */
> +static int sata_init(struct device *dev, void __iomem *addr)
> +{
> +	int ret = 0;
> +	u32 tmpdata;
> +	struct clk *clk;
> +
> +	sata_clk = clk_get(dev, NULL);
> +	if (IS_ERR(sata_clk)) {
> +		dev_err(dev, "no sata clock.\n");
> +		return PTR_ERR(sata_clk);
> +	}
> +	ret = clk_enable(sata_clk);
> +	if (ret) {
> +		dev_err(dev, "can't enable sata clock.\n");
> +		clk_put(sata_clk);
> +		return ret;
> +	}
> +
> +	/* FSL IMX AHCI SATA uses the internal usb phy1 clk on loco */
> +	sata_ref_clk = clk_get(NULL, "usb_phy1");
> +	if (IS_ERR(sata_ref_clk)) {
> +		dev_err(dev, "no sata ref clock.\n");
> +		ret = PTR_ERR(sata_ref_clk);
> +		goto release_sata_clk;
> +	}
> +	ret = clk_enable(sata_ref_clk);
> +	if (ret) {
> +		dev_err(dev, "can't enable sata ref clock.\n");
> +		clk_put(sata_ref_clk);
> +		goto release_sata_clk;
> +	}
> +
> +	/* Get the AHB clock rate, and configure the TIMER1MS reg later */
> +	clk = clk_get(NULL, "ahb");
> +	if (IS_ERR(clk)) {
> +		dev_err(dev, "no ahb clock.\n");
> +		ret = PTR_ERR(clk);
> +		goto release_sata_ref_clk;
> +	}

When I read code like this I think that a devm_clk_get is overdue.

Also, the ahci driver should handle the regular

> +
> +	tmpdata = readl(addr + HOST_CAP);
> +	if (!(tmpdata & HOST_CAP_SSS)) {
> +		tmpdata |= HOST_CAP_SSS;
> +		writel(tmpdata, addr + HOST_CAP);
> +	}

According to the AHCI spec this bit is read only.

> +
> +	if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
> +		writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
> +			addr + HOST_PORTS_IMPL);

This is also readonly.

> +
> +	tmpdata = clk_get_rate(clk) / 1000;
> +	clk_put(clk);
> +	writel(tmpdata, addr + HOST_TIMER1MS);

This should be in a more generic place as it needs to be done for every
board. We can put this into some i.MX53 startup function.


-- 
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[PATCH V2 2/2] MX53 Enable the AHCI SATA on MX53 LOCO

[Zhu Richard-R65037]

Hi Sascha:
Thanks a lot for your comments.

please see my comments marked by [Richard]

Best Regards
Richard Zhu


> -----Original Message-----
> From: Sascha Hauer [mailto:s.hauer at pengutronix.de]
> Sent: Friday, April 08, 2011 3:36 PM
> To: Zhu Richard-R65037
> Cc: linux-arm-kernel at lists.infradead.org; jgarzik at pobox.com;
> kernel at pengutronix.de; linux-ide at vger.kernel.org;
> avorontsov at ru.mvista.com; eric at eukrea.com; eric.miao at linaro.org
> Subject: Re: [PATCH V2 2/2] MX53 Enable the AHCI SATA on MX53 LOCO
>
> On Thu, Mar 17, 2011 at 05:58:03PM +0800, Richard Zhu wrote:
> > Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> > ---
> >  arch/arm/mach-mx5/board-mx53_loco.c |   88
> +++++++++++++++++++++++++++++++++++
> >  1 files changed, 88 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-mx5/board-mx53_loco.c
> > b/arch/arm/mach-mx5/board-mx53_loco.c
> > index 0a18f8d..336273b 100644
> > --- a/arch/arm/mach-mx5/board-mx53_loco.c
> > +++ b/arch/arm/mach-mx5/board-mx53_loco.c
> > @@ -23,11 +23,13 @@
> >  #include <linux/fec.h>
> >  #include <linux/delay.h>
> >  #include <linux/gpio.h>
> > +#include <linux/ahci_platform.h>
> >
> >  #include <mach/common.h>
> >  #include <mach/hardware.h>
> >  #include <mach/imx-uart.h>
> >  #include <mach/iomux-mx53.h>
> > +#include <mach/ahci_sata.h>
> >
> >  #include <asm/mach-types.h>
> >  #include <asm/mach/arch.h>
> > @@ -38,6 +40,8 @@
> >
> >  #define LOCO_FEC_PHY_RST           IMX_GPIO_NR(7, 6)
> >
> > +static struct clk *sata_clk, *sata_ref_clk;
> > +
> >  static iomux_v3_cfg_t mx53_loco_pads[] = {
> >     /* FEC */
> >     MX53_PAD_FEC_MDC__FEC_MDC,
> > @@ -203,6 +207,89 @@ static const struct imxi2c_platform_data
> mx53_loco_i2c_data __initconst = {
> >     .bitrate = 100000,
> >  };
> >
> > +/* HW Initialization, if return 0, initialization is successful. */
> > +static int sata_init(struct device *dev, void __iomem *addr) {
> > +   int ret = 0;
> > +   u32 tmpdata;
> > +   struct clk *clk;
> > +
> > +   sata_clk = clk_get(dev, NULL);
> > +   if (IS_ERR(sata_clk)) {
> > +           dev_err(dev, "no sata clock.\n");
> > +           return PTR_ERR(sata_clk);
> > +   }
> > +   ret = clk_enable(sata_clk);
> > +   if (ret) {
> > +           dev_err(dev, "can't enable sata clock.\n");
> > +           clk_put(sata_clk);
> > +           return ret;
> > +   }
> > +
> > +   /* FSL IMX AHCI SATA uses the internal usb phy1 clk on loco */
> > +   sata_ref_clk = clk_get(NULL, "usb_phy1");
> > +   if (IS_ERR(sata_ref_clk)) {
> > +           dev_err(dev, "no sata ref clock.\n");
> > +           ret = PTR_ERR(sata_ref_clk);
> > +           goto release_sata_clk;
> > +   }
> > +   ret = clk_enable(sata_ref_clk);
> > +   if (ret) {
> > +           dev_err(dev, "can't enable sata ref clock.\n");
> > +           clk_put(sata_ref_clk);
> > +           goto release_sata_clk;
> > +   }
> > +
> > +   /* Get the AHB clock rate, and configure the TIMER1MS reg later */
> > +   clk = clk_get(NULL, "ahb");
> > +   if (IS_ERR(clk)) {
> > +           dev_err(dev, "no ahb clock.\n");
> > +           ret = PTR_ERR(clk);
> > +           goto release_sata_ref_clk;
> > +   }
>
> When I read code like this I think that a devm_clk_get is overdue.
>
> Also, the ahci driver should handle the regular
[Richard]Sorry, I can't catch what's the exact means of this comment.

>
> > +
> > +   tmpdata = readl(addr + HOST_CAP);
> > +   if (!(tmpdata & HOST_CAP_SSS)) {
> > +           tmpdata |= HOST_CAP_SSS;
> > +           writel(tmpdata, addr + HOST_CAP);
> > +   }
>
> According to the AHCI spec this bit is read only.
>
> > +
> > +   if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
> > +           writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
> > +                   addr + HOST_PORTS_IMPL);
>
> This is also readonly.
>
[Richard]:About the RO marked bits defined in the SPEC, there are used
 as R/W bits in MX53 AHCI implementation actually.
Here are the hack debug log:
----------Log--------------------
HOST_CAP: 0x6726ff80
HOST_CAP: 0x6f26ff80 <------------ After set the SSS bit.
HOST_PT_IMPL: 0x0
HOST_PT_IMPL: 0x1    <------------ After set the IMPL bit
ahci: SSS flag set, parallel bus scan disabled
ahci ahci.0: AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl platform mode
ahci ahci.0: flags: ncq sntf stag pm led clo only pmp pio slum part ccc
scsi0 : ahci
ata1: SATA max UDMA/133 irq_stat 0x00000040, connection status changed irq 28
MXC MTD nand Driver 3.0
----------End--------------------
> > +
> > +   tmpdata = clk_get_rate(clk) / 1000;
> > +   clk_put(clk);
> > +   writel(tmpdata, addr + HOST_TIMER1MS);
>
> This should be in a more generic place as it needs to be done for every
> board. We can put this into some i.MX53 startup function.
>
[Richard]How about put these codes into one standalone file in .../arch/arm/plat-mxc/ folder,
 and export the sata_init and sata_exit out for kinds of MX53 boards?

>
> --
> Pengutronix e.K.                           |
> |
> Industrial Linux Solutions                 | http://www.pengutronix.de/
> |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0
> |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555
> |

[PATCH V2 2/2] MX53 Enable the AHCI SATA on MX53 LOCO

[Sascha Hauer]

On Fri, Apr 08, 2011 at 08:49:28AM +0000, Zhu Richard-R65037 wrote:
> >
> > When I read code like this I think that a devm_clk_get is overdue.
> >
> > Also, the ahci driver should handle the regular
> [Richard]Sorry, I can't catch what's the exact means of this comment.

devm_* are a set of functions which track the resources a driver
allocates and frees them automatically when the driver exits. See for
example the ahci driver. It uses devm_kzalloc and devm_ioremap.
devm_clk_get would be nice to have also.

> 
> >
> > > +
> > > +   tmpdata = readl(addr + HOST_CAP);
> > > +   if (!(tmpdata & HOST_CAP_SSS)) {
> > > +           tmpdata |= HOST_CAP_SSS;
> > > +           writel(tmpdata, addr + HOST_CAP);
> > > +   }
> >
> > According to the AHCI spec this bit is read only.
> >
> > > +
> > > +   if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
> > > +           writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
> > > +                   addr + HOST_PORTS_IMPL);
> >
> > This is also readonly.
> >
> [Richard]:About the RO marked bits defined in the SPEC, there are used
>  as R/W bits in MX53 AHCI implementation actually.
> Here are the hack debug log:
> ----------Log--------------------
> HOST_CAP: 0x6726ff80
> HOST_CAP: 0x6f26ff80 <------------ After set the SSS bit.
> HOST_PT_IMPL: 0x0
> HOST_PT_IMPL: 0x1    <------------ After set the IMPL bit
> ahci: SSS flag set, parallel bus scan disabled
> ahci ahci.0: AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl platform mode
> ahci ahci.0: flags: ncq sntf stag pm led clo only pmp pio slum part ccc
> scsi0 : ahci
> ata1: SATA max UDMA/133 irq_stat 0x00000040, connection status changed irq 28
> MXC MTD nand Driver 3.0
> ----------End--------------------

Sigh. At least they tried to implement a standard...

> > > +
> > > +   tmpdata = clk_get_rate(clk) / 1000;
> > > +   clk_put(clk);
> > > +   writel(tmpdata, addr + HOST_TIMER1MS);
> >
> > This should be in a more generic place as it needs to be done for every
> > board. We can put this into some i.MX53 startup function.
> >
> [Richard]How about put these codes into one standalone file in .../arch/arm/plat-mxc/ folder,
>  and export the sata_init and sata_exit out for kinds of MX53 boards?

Yes, probably except the special clock usage on the loco board.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |