* [PATCH] ARM: Merge v6 and v7 DEBUG_LL DCC support
@ 2011-03-18 2:52 Stephen Boyd
2011-03-20 9:26 ` Russell King - ARM Linux
0 siblings, 1 reply; 3+ messages in thread
From: Stephen Boyd @ 2011-03-18 2:52 UTC (permalink / raw)
To: linux-arm-kernel
The inline assembly differences for v6 vs. v7 are purely
optimizations. On a v7 processor, an mrc with the pc sets the
condition codes to the 28-31 bits of the register being read. It
just so happens that the TX/RX full bits the DCC support code is
testing for are high enough in the register to be put into the
condition codes. On a v6 processor, this "feature" isn't
implemented and thus we have to do the usual read, mask, test
operations to check for TX/RX full. Thus, we can drop the v7
implementation and just use the v6 implementation for both.
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
arch/arm/boot/compressed/head.S | 10 +---------
arch/arm/boot/compressed/misc.c | 12 +-----------
arch/arm/kernel/debug.S | 19 +------------------
3 files changed, 3 insertions(+), 38 deletions(-)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 7193884..01448ba 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -21,20 +21,12 @@
#if defined(CONFIG_DEBUG_ICEDCC)
-#ifdef CONFIG_CPU_V6
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
.macro loadsp, rb, tmp
.endm
.macro writeb, ch, rb
mcr p14, 0, \ch, c0, c5, 0
.endm
-#elif defined(CONFIG_CPU_V7)
- .macro loadsp, rb, tmp
- .endm
- .macro writeb, ch, rb
-wait: mrc p14, 0, pc, c0, c1, 0
- bcs wait
- mcr p14, 0, \ch, c0, c5, 0
- .endm
#elif defined(CONFIG_CPU_XSCALE)
.macro loadsp, rb, tmp
.endm
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index e653a6d..23c67af 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -36,7 +36,7 @@ extern void error(char *x);
#ifdef CONFIG_DEBUG_ICEDCC
-#ifdef CONFIG_CPU_V6
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
static void icedcc_putc(int ch)
{
@@ -52,16 +52,6 @@ static void icedcc_putc(int ch)
asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
}
-#elif defined(CONFIG_CPU_V7)
-
-static void icedcc_putc(int ch)
-{
- asm(
- "wait: mrc p14, 0, pc, c0, c1, 0 \n\
- bcs wait \n\
- mcr p14, 0, %0, c0, c5, 0 "
- : : "r" (ch));
-}
#elif defined(CONFIG_CPU_XSCALE)
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index a0f0752..50d86b6 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -25,7 +25,7 @@
.macro addruart, rp, rv
.endm
-#if defined(CONFIG_CPU_V6)
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
.macro senduart, rd, rx
mcr p14, 0, \rd, c0, c5, 0
@@ -49,23 +49,6 @@
1002:
.endm
-#elif defined(CONFIG_CPU_V7)
-
- .macro senduart, rd, rx
- mcr p14, 0, \rd, c0, c5, 0
- .endm
-
- .macro busyuart, rd, rx
-busy: mrc p14, 0, pc, c0, c1, 0
- bcs busy
- .endm
-
- .macro waituart, rd, rx
-wait: mrc p14, 0, pc, c0, c1, 0
- bcs wait
-
- .endm
-
#elif defined(CONFIG_CPU_XSCALE)
.macro senduart, rd, rx
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH] ARM: Merge v6 and v7 DEBUG_LL DCC support
2011-03-18 2:52 [PATCH] ARM: Merge v6 and v7 DEBUG_LL DCC support Stephen Boyd
@ 2011-03-20 9:26 ` Russell King - ARM Linux
2011-03-21 7:20 ` [PATCHv2] " Stephen Boyd
0 siblings, 1 reply; 3+ messages in thread
From: Russell King - ARM Linux @ 2011-03-20 9:26 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 17, 2011 at 07:52:00PM -0700, Stephen Boyd wrote:
> The inline assembly differences for v6 vs. v7 are purely
> optimizations. On a v7 processor, an mrc with the pc sets the
> condition codes to the 28-31 bits of the register being read. It
> just so happens that the TX/RX full bits the DCC support code is
> testing for are high enough in the register to be put into the
> condition codes. On a v6 processor, this "feature" isn't
> implemented and thus we have to do the usual read, mask, test
> operations to check for TX/RX full. Thus, we can drop the v7
> implementation and just use the v6 implementation for both.
This patch needs updating for the changes that were in my tree for many
months, and are now in mainline.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCHv2] ARM: Merge v6 and v7 DEBUG_LL DCC support
2011-03-20 9:26 ` Russell King - ARM Linux
@ 2011-03-21 7:20 ` Stephen Boyd
0 siblings, 0 replies; 3+ messages in thread
From: Stephen Boyd @ 2011-03-21 7:20 UTC (permalink / raw)
To: linux-arm-kernel
The inline assembly differences for v6 vs. v7 are purely
optimizations. On a v7 processor, an mrc with the pc sets the
condition codes to the 28-31 bits of the register being read. It
just so happens that the TX/RX full bits the DCC support code is
testing for are high enough in the register to be put into the
condition codes. On a v6 processor, this "feature" isn't
implemented and thus we have to do the usual read, mask, test
operations to check for TX/RX full. Thus, we can drop the v7
implementation and just use the v6 implementation for both.
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
Russell King wrote:
> This patch needs updating for the changes that were in my tree for many
> months, and are now in mainline.
Yes sorry. I noticed this when rebasing against linus' tree. I'll base
patches of your for-next tree when sending to you next time.
Changes since v1:
* Refreshed against rmk/for-next
arch/arm/boot/compressed/head.S | 10 +---------
arch/arm/boot/compressed/misc.c | 12 +-----------
arch/arm/kernel/debug.S | 19 +------------------
3 files changed, 3 insertions(+), 38 deletions(-)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 84ac4d6..adf583c 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -21,20 +21,12 @@
#if defined(CONFIG_DEBUG_ICEDCC)
-#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
.macro loadsp, rb, tmp
.endm
.macro writeb, ch, rb
mcr p14, 0, \ch, c0, c5, 0
.endm
-#elif defined(CONFIG_CPU_V7)
- .macro loadsp, rb, tmp
- .endm
- .macro writeb, ch, rb
-wait: mrc p14, 0, pc, c0, c1, 0
- bcs wait
- mcr p14, 0, \ch, c0, c5, 0
- .endm
#elif defined(CONFIG_CPU_XSCALE)
.macro loadsp, rb, tmp
.endm
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 4657e87..2df3826 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -36,7 +36,7 @@ extern void error(char *x);
#ifdef CONFIG_DEBUG_ICEDCC
-#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
static void icedcc_putc(int ch)
{
@@ -52,16 +52,6 @@ static void icedcc_putc(int ch)
asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
}
-#elif defined(CONFIG_CPU_V7)
-
-static void icedcc_putc(int ch)
-{
- asm(
- "wait: mrc p14, 0, pc, c0, c1, 0 \n\
- bcs wait \n\
- mcr p14, 0, %0, c0, c5, 0 "
- : : "r" (ch));
-}
#elif defined(CONFIG_CPU_XSCALE)
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index d2d983b..bcd66e0 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -25,7 +25,7 @@
.macro addruart, rp, rv
.endm
-#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
.macro senduart, rd, rx
mcr p14, 0, \rd, c0, c5, 0
@@ -49,23 +49,6 @@
1002:
.endm
-#elif defined(CONFIG_CPU_V7)
-
- .macro senduart, rd, rx
- mcr p14, 0, \rd, c0, c5, 0
- .endm
-
- .macro busyuart, rd, rx
-busy: mrc p14, 0, pc, c0, c1, 0
- bcs busy
- .endm
-
- .macro waituart, rd, rx
-wait: mrc p14, 0, pc, c0, c1, 0
- bcs wait
-
- .endm
-
#elif defined(CONFIG_CPU_XSCALE)
.macro senduart, rd, rx
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2011-03-21 7:20 UTC | newest]
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2011-03-18 2:52 [PATCH] ARM: Merge v6 and v7 DEBUG_LL DCC support Stephen Boyd
2011-03-20 9:26 ` Russell King - ARM Linux
2011-03-21 7:20 ` [PATCHv2] " Stephen Boyd
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