[PATCH 0/4] Tegra irq cleanups

[PATCH 0/4] Tegra irq cleanups

[Colin Cross]

This patch series cleans up the Tegra irq subsystem, and allows
the GIC to be switched to the fasteoi handler.  The first three
patches have no dependencies on any other trees.  Patch 4 should
only go in at the same time as Will Deacon's fasteoi patches,
and could be squashed into his patch.

As part of this series, power management support is removed from
the Tegra irq subsystem.  PM support will be added back in a
future patch set along with PM support for the rest of the
platform.

Colin Cross (4):
      ARM: tegra: irq: convert to gic arch extensions
      ARM: tegra: irq: Remove PM support
      ARM: tegra: irq: Move legacy_irq.c into irq.c
      ARM: tegra: irq: Replace tegra_ack with tegra_eoi

 arch/arm/mach-tegra/Makefile                  |    2 +-
 arch/arm/mach-tegra/include/mach/legacy_irq.h |   35 ----
 arch/arm/mach-tegra/irq.c                     |  181 +++++++++------------
 arch/arm/mach-tegra/legacy_irq.c              |  215 -------------------------
 4 files changed, 77 insertions(+), 356 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/include/mach/legacy_irq.h
 delete mode 100644 arch/arm/mach-tegra/legacy_irq.c

[PATCH 1/4] ARM: tegra: irq: convert to gic arch extensions

[Colin Cross]

Replace the ugly hack that inserts legacy irq controller calls
into the irq call paths by reading and replacing the gic irq
chip with the new gic arch extensions.

Signed-off-by: Colin Cross <ccross@android.com>
---
 arch/arm/mach-tegra/irq.c |   54 +++++++++++++-------------------------------
 1 files changed, 16 insertions(+), 38 deletions(-)

diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4330d89..567b75c 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -1,8 +1,8 @@
 /*
- * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 Google, Inc.
  *
  * Author:
- *	Colin Cross <ccross@google.com>
+ *	Colin Cross <ccross@android.com>
  *
  * Copyright (C) 2010, NVIDIA Corporation
  *
@@ -46,10 +46,6 @@ static u32 tegra_lp0_wake_enb;
 static u32 tegra_lp0_wake_level;
 static u32 tegra_lp0_wake_level_any;
 
-static void (*tegra_gic_mask_irq)(struct irq_data *d);
-static void (*tegra_gic_unmask_irq)(struct irq_data *d);
-static void (*tegra_gic_ack_irq)(struct irq_data *d);
-
 /* ensures that sufficient time is passed for a register write to
  * serialize into the 32KHz domain */
 static void pmc_32kwritel(u32 val, unsigned long offs)
@@ -103,58 +99,40 @@ void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any)
 
 static void tegra_mask(struct irq_data *d)
 {
-	tegra_gic_mask_irq(d);
-	tegra_legacy_mask_irq(d->irq);
+	if (d->irq >= 32)
+		tegra_legacy_mask_irq(d->irq);
 }
 
 static void tegra_unmask(struct irq_data *d)
 {
-	tegra_gic_unmask_irq(d);
-	tegra_legacy_unmask_irq(d->irq);
+	if (d->irq >= 32)
+		tegra_legacy_unmask_irq(d->irq);
 }
 
 static void tegra_ack(struct irq_data *d)
 {
-	tegra_legacy_force_irq_clr(d->irq);
-	tegra_gic_ack_irq(d);
+	if (d->irq >= 32)
+		tegra_legacy_force_irq_clr(d->irq);
 }
 
 static int tegra_retrigger(struct irq_data *d)
 {
+	if (d->irq < 32)
+		return 0;
+
 	tegra_legacy_force_irq_set(d->irq);
 	return 1;
 }
 
-static struct irq_chip tegra_irq = {
-	.name			= "PPI",
-	.irq_ack		= tegra_ack,
-	.irq_mask		= tegra_mask,
-	.irq_unmask		= tegra_unmask,
-	.irq_retrigger		= tegra_retrigger,
-};
-
 void __init tegra_init_irq(void)
 {
-	struct irq_chip *gic;
-	unsigned int i;
-	int irq;
-
 	tegra_init_legacy_irq();
 
+	gic_arch_extn.irq_ack = tegra_ack;
+	gic_arch_extn.irq_mask = tegra_mask;
+	gic_arch_extn.irq_unmask = tegra_unmask;
+	gic_arch_extn.irq_retrigger = tegra_retrigger;
+
 	gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
 		 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
-
-	gic = irq_get_chip(29);
-	tegra_gic_unmask_irq = gic->irq_unmask;
-	tegra_gic_mask_irq = gic->irq_mask;
-	tegra_gic_ack_irq = gic->irq_ack;
-#ifdef CONFIG_SMP
-	tegra_irq.irq_set_affinity = gic->irq_set_affinity;
-#endif
-
-	for (i = 0; i < INT_MAIN_NR; i++) {
-		irq = INT_PRI_BASE + i;
-		irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
-		set_irq_flags(irq, IRQF_VALID);
-	}
 }
-- 
1.7.4.1

[PATCH 2/4] ARM: tegra: irq: Remove PM support

[Colin Cross]

Tegra PM irq support is being improved, remove it for now
until the rest of the platform gets PM support.

Signed-off-by: Colin Cross <ccross@android.com>
---
 arch/arm/mach-tegra/include/mach/legacy_irq.h |    3 -
 arch/arm/mach-tegra/irq.c                     |   66 ---------------------
 arch/arm/mach-tegra/legacy_irq.c              |   77 -------------------------
 3 files changed, 0 insertions(+), 146 deletions(-)

diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
index d898c0e..4c1f535 100644
--- a/arch/arm/mach-tegra/include/mach/legacy_irq.h
+++ b/arch/arm/mach-tegra/include/mach/legacy_irq.h
@@ -27,9 +27,6 @@ int tegra_legacy_force_irq_status(unsigned int irq);
 void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
 unsigned long tegra_legacy_vfiq(int nr);
 unsigned long tegra_legacy_class(int nr);
-int tegra_legacy_irq_set_wake(int irq, int enable);
-void tegra_legacy_irq_set_lp1_wake_mask(void);
-void tegra_legacy_irq_restore_mask(void);
 void tegra_init_legacy_irq(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 567b75c..4fa7a37 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -28,75 +28,9 @@
 
 #include <mach/iomap.h>
 #include <mach/legacy_irq.h>
-#include <mach/suspend.h>
 
 #include "board.h"
 
-#define PMC_CTRL		0x0
-#define PMC_CTRL_LATCH_WAKEUPS	(1 << 5)
-#define PMC_WAKE_MASK		0xc
-#define PMC_WAKE_LEVEL		0x10
-#define PMC_WAKE_STATUS		0x14
-#define PMC_SW_WAKE_STATUS	0x18
-#define PMC_DPD_SAMPLE		0x20
-
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-
-static u32 tegra_lp0_wake_enb;
-static u32 tegra_lp0_wake_level;
-static u32 tegra_lp0_wake_level_any;
-
-/* ensures that sufficient time is passed for a register write to
- * serialize into the 32KHz domain */
-static void pmc_32kwritel(u32 val, unsigned long offs)
-{
-	writel(val, pmc + offs);
-	udelay(130);
-}
-
-int tegra_set_lp1_wake(int irq, int enable)
-{
-	return tegra_legacy_irq_set_wake(irq, enable);
-}
-
-void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any)
-{
-	u32 temp;
-	u32 status;
-	u32 lvl;
-
-	wake_level &= wake_enb;
-	wake_any &= wake_enb;
-
-	wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb);
-	wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
-
-	wake_enb |= tegra_lp0_wake_enb;
-
-	pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
-	temp = readl(pmc + PMC_CTRL);
-	temp |= PMC_CTRL_LATCH_WAKEUPS;
-	pmc_32kwritel(temp, PMC_CTRL);
-	temp &= ~PMC_CTRL_LATCH_WAKEUPS;
-	pmc_32kwritel(temp, PMC_CTRL);
-	status = readl(pmc + PMC_SW_WAKE_STATUS);
-	lvl = readl(pmc + PMC_WAKE_LEVEL);
-
-	/* flip the wakeup trigger for any-edge triggered pads
-	 * which are currently asserting as wakeups */
-	lvl ^= status;
-	lvl &= wake_any;
-
-	wake_level |= lvl;
-
-	writel(wake_level, pmc + PMC_WAKE_LEVEL);
-	/* Enable DPD sample to trigger sampling pads data and direction
-	 * in which pad will be driven during lp0 mode*/
-	writel(0x1, pmc + PMC_DPD_SAMPLE);
-
-	writel(wake_enb, pmc + PMC_WAKE_MASK);
-}
-
 static void tegra_mask(struct irq_data *d)
 {
 	if (d->irq >= 32)
diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c
index 38eb719..cb31669 100644
--- a/arch/arm/mach-tegra/legacy_irq.c
+++ b/arch/arm/mach-tegra/legacy_irq.c
@@ -49,9 +49,6 @@ static void __iomem *ictlr_reg_base[] = {
 	IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
 };
 
-static u32 tegra_legacy_wake_mask[4];
-static u32 tegra_legacy_saved_mask[4];
-
 /* When going into deep sleep, the CPU is powered down, taking the GIC with it
    In order to wake, the wake interrupts need to be enabled in the legacy
    interrupt controller. */
@@ -129,40 +126,6 @@ unsigned long tegra_legacy_class(int nr)
 	return readl(base + ICTLR_CPU_IEP_CLASS);
 }
 
-int tegra_legacy_irq_set_wake(int irq, int enable)
-{
-	irq -= 32;
-	if (enable)
-		tegra_legacy_wake_mask[irq >> 5] |= 1 << (irq & 31);
-	else
-		tegra_legacy_wake_mask[irq >> 5] &= ~(1 << (irq & 31));
-
-	return 0;
-}
-
-void tegra_legacy_irq_set_lp1_wake_mask(void)
-{
-	void __iomem *base;
-	int i;
-
-	for (i = 0; i < NUM_ICTLRS; i++) {
-		base = ictlr_reg_base[i];
-		tegra_legacy_saved_mask[i] = readl(base + ICTLR_CPU_IER);
-		writel(tegra_legacy_wake_mask[i], base + ICTLR_CPU_IER);
-	}
-}
-
-void tegra_legacy_irq_restore_mask(void)
-{
-	void __iomem *base;
-	int i;
-
-	for (i = 0; i < NUM_ICTLRS; i++) {
-		base = ictlr_reg_base[i];
-		writel(tegra_legacy_saved_mask[i], base + ICTLR_CPU_IER);
-	}
-}
-
 void tegra_init_legacy_irq(void)
 {
 	int i;
@@ -173,43 +136,3 @@ void tegra_init_legacy_irq(void)
 		writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
 	}
 }
-
-#ifdef CONFIG_PM
-static u32 cop_ier[NUM_ICTLRS];
-static u32 cpu_ier[NUM_ICTLRS];
-static u32 cpu_iep[NUM_ICTLRS];
-
-void tegra_irq_suspend(void)
-{
-	unsigned long flags;
-	int i;
-
-	local_irq_save(flags);
-	for (i = 0; i < NUM_ICTLRS; i++) {
-		void __iomem *ictlr = ictlr_reg_base[i];
-		cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER);
-		cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS);
-		cop_ier[i] = readl(ictlr + ICTLR_COP_IER);
-		writel(~0, ictlr + ICTLR_COP_IER_CLR);
-	}
-	local_irq_restore(flags);
-}
-
-void tegra_irq_resume(void)
-{
-	unsigned long flags;
-	int i;
-
-	local_irq_save(flags);
-	for (i = 0; i < NUM_ICTLRS; i++) {
-		void __iomem *ictlr = ictlr_reg_base[i];
-		writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
-		writel(~0ul, ictlr + ICTLR_CPU_IER_CLR);
-		writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
-		writel(0, ictlr + ICTLR_COP_IEP_CLASS);
-		writel(~0ul, ictlr + ICTLR_COP_IER_CLR);
-		writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
-	}
-	local_irq_restore(flags);
-}
-#endif
-- 
1.7.4.1

[PATCH 3/4] ARM: tegra: irq: Move legacy_irq.c into irq.c

[Colin Cross]

Now that irq.c is just an interface layer between the gic
and legacy_irq.c, move the contents of legacy_irq.c into
irq.c.

Signed-off-by: Colin Cross <ccross@android.com>
---
 arch/arm/mach-tegra/Makefile                  |    2 +-
 arch/arm/mach-tegra/include/mach/legacy_irq.h |   32 ------
 arch/arm/mach-tegra/irq.c                     |   83 +++++++++++++--
 arch/arm/mach-tegra/legacy_irq.c              |  138 -------------------------
 4 files changed, 72 insertions(+), 183 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/include/mach/legacy_irq.h
 delete mode 100644 arch/arm/mach-tegra/legacy_irq.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 1afe050..823c703 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,7 +1,7 @@
 obj-y                                   += common.o
 obj-y                                   += devices.o
 obj-y                                   += io.o
-obj-y                                   += irq.o legacy_irq.o
+obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += gpio.o
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
deleted file mode 100644
index 4c1f535..0000000
--- a/arch/arm/mach-tegra/include/mach/legacy_irq.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/legacy_irq.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
-#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
-
-void tegra_legacy_mask_irq(unsigned int irq);
-void tegra_legacy_unmask_irq(unsigned int irq);
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
-void tegra_legacy_force_irq_set(unsigned int irq);
-void tegra_legacy_force_irq_clr(unsigned int irq);
-int tegra_legacy_force_irq_status(unsigned int irq);
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
-unsigned long tegra_legacy_vfiq(int nr);
-unsigned long tegra_legacy_class(int nr);
-void tegra_init_legacy_irq(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4fa7a37..1883203 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -18,8 +18,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
@@ -27,40 +25,101 @@
 #include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
-#include <mach/legacy_irq.h>
 
 #include "board.h"
 
+#define INT_SYS_NR	(INT_GPIO_BASE - INT_PRI_BASE)
+#define INT_SYS_SZ	(INT_SEC_BASE - INT_PRI_BASE)
+#define PPI_NR		((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
+
+#define ICTLR_CPU_IEP_VFIQ	0x08
+#define ICTLR_CPU_IEP_FIR	0x14
+#define ICTLR_CPU_IEP_FIR_SET	0x18
+#define ICTLR_CPU_IEP_FIR_CLR	0x1c
+
+#define ICTLR_CPU_IER		0x20
+#define ICTLR_CPU_IER_SET	0x24
+#define ICTLR_CPU_IER_CLR	0x28
+#define ICTLR_CPU_IEP_CLASS	0x2C
+
+#define ICTLR_COP_IER		0x30
+#define ICTLR_COP_IER_SET	0x34
+#define ICTLR_COP_IER_CLR	0x38
+#define ICTLR_COP_IEP_CLASS	0x3c
+
+#define NUM_ICTLRS 4
+#define FIRST_LEGACY_IRQ 32
+
+static void __iomem *ictlr_reg_base[] = {
+	IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
+	IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
+	IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
+	IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
+};
+
 static void tegra_mask(struct irq_data *d)
 {
-	if (d->irq >= 32)
-		tegra_legacy_mask_irq(d->irq);
+	void __iomem *base;
+	int leg_irq;
+
+	if (d->irq < FIRST_LEGACY_IRQ)
+		return;
+
+	leg_irq = d->irq - FIRST_LEGACY_IRQ;
+	base = ictlr_reg_base[leg_irq >> 5];
+	writel(1 << (leg_irq & 31), base + ICTLR_CPU_IER_CLR);
 }
 
 static void tegra_unmask(struct irq_data *d)
 {
-	if (d->irq >= 32)
-		tegra_legacy_unmask_irq(d->irq);
+	void __iomem *base;
+	int leg_irq;
+
+	if (d->irq < FIRST_LEGACY_IRQ)
+		return;
+
+	leg_irq = d->irq - FIRST_LEGACY_IRQ;
+	base = ictlr_reg_base[leg_irq >> 5];
+	writel(1 << (leg_irq & 31), base + ICTLR_CPU_IER_SET);
 }
 
 static void tegra_ack(struct irq_data *d)
 {
-	if (d->irq >= 32)
-		tegra_legacy_force_irq_clr(d->irq);
+	void __iomem *base;
+	int leg_irq;
+
+	if (d->irq < FIRST_LEGACY_IRQ)
+		return;
+
+	leg_irq = d->irq - FIRST_LEGACY_IRQ;
+	base = ictlr_reg_base[leg_irq >> 5];
+	writel(1 << (leg_irq & 31), base + ICTLR_CPU_IEP_FIR_CLR);
 }
 
 static int tegra_retrigger(struct irq_data *d)
 {
-	if (d->irq < 32)
+	void __iomem *base;
+	int leg_irq;
+
+	if (d->irq < FIRST_LEGACY_IRQ)
 		return 0;
 
-	tegra_legacy_force_irq_set(d->irq);
+	leg_irq = d->irq - FIRST_LEGACY_IRQ;
+	base = ictlr_reg_base[leg_irq >> 5];
+	writel(1 << (leg_irq & 31), base + ICTLR_CPU_IEP_FIR_SET);
+
 	return 1;
 }
 
 void __init tegra_init_irq(void)
 {
-	tegra_init_legacy_irq();
+	int i;
+
+	for (i = 0; i < NUM_ICTLRS; i++) {
+		void __iomem *ictlr = ictlr_reg_base[i];
+		writel(~0, ictlr + ICTLR_CPU_IER_CLR);
+		writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
+	}
 
 	gic_arch_extn.irq_ack = tegra_ack;
 	gic_arch_extn.irq_mask = tegra_mask;
diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c
deleted file mode 100644
index cb31669..0000000
--- a/arch/arm/mach-tegra/legacy_irq.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * arch/arm/mach-tegra/legacy_irq.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/legacy_irq.h>
-
-#define INT_SYS_NR	(INT_GPIO_BASE - INT_PRI_BASE)
-#define INT_SYS_SZ	(INT_SEC_BASE - INT_PRI_BASE)
-#define PPI_NR		((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
-
-#define ICTLR_CPU_IEP_VFIQ	0x08
-#define ICTLR_CPU_IEP_FIR	0x14
-#define ICTLR_CPU_IEP_FIR_SET	0x18
-#define ICTLR_CPU_IEP_FIR_CLR	0x1c
-
-#define ICTLR_CPU_IER		0x20
-#define ICTLR_CPU_IER_SET	0x24
-#define ICTLR_CPU_IER_CLR	0x28
-#define ICTLR_CPU_IEP_CLASS	0x2C
-
-#define ICTLR_COP_IER		0x30
-#define ICTLR_COP_IER_SET	0x34
-#define ICTLR_COP_IER_CLR	0x38
-#define ICTLR_COP_IEP_CLASS	0x3c
-
-#define NUM_ICTLRS 4
-
-static void __iomem *ictlr_reg_base[] = {
-	IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
-	IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
-	IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
-	IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
-};
-
-/* When going into deep sleep, the CPU is powered down, taking the GIC with it
-   In order to wake, the wake interrupts need to be enabled in the legacy
-   interrupt controller. */
-void tegra_legacy_unmask_irq(unsigned int irq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET);
-}
-
-void tegra_legacy_mask_irq(unsigned int irq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR);
-}
-
-void tegra_legacy_force_irq_set(unsigned int irq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET);
-}
-
-void tegra_legacy_force_irq_clr(unsigned int irq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR);
-}
-
-int tegra_legacy_force_irq_status(unsigned int irq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31)));
-}
-
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS);
-}
-
-unsigned long tegra_legacy_vfiq(int nr)
-{
-	void __iomem *base;
-	base = ictlr_reg_base[nr];
-	return readl(base + ICTLR_CPU_IEP_VFIQ);
-}
-
-unsigned long tegra_legacy_class(int nr)
-{
-	void __iomem *base;
-	base = ictlr_reg_base[nr];
-	return readl(base + ICTLR_CPU_IEP_CLASS);
-}
-
-void tegra_init_legacy_irq(void)
-{
-	int i;
-
-	for (i = 0; i < NUM_ICTLRS; i++) {
-		void __iomem *ictlr = ictlr_reg_base[i];
-		writel(~0, ictlr + ICTLR_CPU_IER_CLR);
-		writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
-	}
-}
-- 
1.7.4.1

[PATCH 4/4] ARM: tegra: irq: Replace tegra_ack with tegra_eoi

[Colin Cross]

When the GIC flow control function is replaced with
handle_fasteoi_irq, the eoi arch extension will be called
instead of ack.

Signed-off-by: Colin Cross <ccross@android.com>
---
 arch/arm/mach-tegra/irq.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1883203..35fb2f10 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -83,7 +83,7 @@ static void tegra_unmask(struct irq_data *d)
 	writel(1 << (leg_irq & 31), base + ICTLR_CPU_IER_SET);
 }
 
-static void tegra_ack(struct irq_data *d)
+static void tegra_eoi(struct irq_data *d)
 {
 	void __iomem *base;
 	int leg_irq;
@@ -121,7 +121,7 @@ void __init tegra_init_irq(void)
 		writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
 	}
 
-	gic_arch_extn.irq_ack = tegra_ack;
+	gic_arch_extn.irq_eoi = tegra_eoi;
 	gic_arch_extn.irq_mask = tegra_mask;
 	gic_arch_extn.irq_unmask = tegra_unmask;
 	gic_arch_extn.irq_retrigger = tegra_retrigger;
-- 
1.7.4.1

[PATCH 0/4] Tegra irq cleanups

[Colin Cross]

On Sun, May 1, 2011 at 2:10 PM, Colin Cross <ccross@android.com> wrote:
> This patch series cleans up the Tegra irq subsystem, and allows
> the GIC to be switched to the fasteoi handler. ?The first three
> patches have no dependencies on any other trees. ?Patch 4 should
> only go in at the same time as Will Deacon's fasteoi patches,
> and could be squashed into his patch.
>
> As part of this series, power management support is removed from
> the Tegra irq subsystem. ?PM support will be added back in a
> future patch set along with PM support for the rest of the
> platform.
>
> Colin Cross (4):
> ? ? ?ARM: tegra: irq: convert to gic arch extensions
> ? ? ?ARM: tegra: irq: Remove PM support
> ? ? ?ARM: tegra: irq: Move legacy_irq.c into irq.c
> ? ? ?ARM: tegra: irq: Replace tegra_ack with tegra_eoi
>
> ?arch/arm/mach-tegra/Makefile ? ? ? ? ? ? ? ? ?| ? ?2 +-
> ?arch/arm/mach-tegra/include/mach/legacy_irq.h | ? 35 ----
> ?arch/arm/mach-tegra/irq.c ? ? ? ? ? ? ? ? ? ? | ?181 +++++++++------------
> ?arch/arm/mach-tegra/legacy_irq.c ? ? ? ? ? ? ?| ?215 -------------------------
> ?4 files changed, 77 insertions(+), 356 deletions(-)
> ?delete mode 100644 arch/arm/mach-tegra/include/mach/legacy_irq.h
> ?delete mode 100644 arch/arm/mach-tegra/legacy_irq.c
>

Sorry Marc, forgot to CC you on this patch set.

I just noticed that you kept both tegra_ack as well as tegra_eoi in
your patch set.  That seems like a reasonable way to avoid merge order
problems between Will's fasteoi patches and these patches, at least in
one direction, so I'll add that in v2 (only affects the last patch in
the series).

[PATCHv2 3/4] ARM: tegra: irq: Move legacy_irq.c into irq.c

[Colin Cross]

Now that irq.c is just an interface layer between the gic
and legacy_irq.c, move the contents of legacy_irq.c into
irq.c.

Signed-off-by: Colin Cross <ccross@android.com>
---
v2: Remove duplicated code

 arch/arm/mach-tegra/Makefile                  |    2 +-
 arch/arm/mach-tegra/include/mach/legacy_irq.h |   32 ------
 arch/arm/mach-tegra/irq.c                     |   77 ++++++++++++--
 arch/arm/mach-tegra/legacy_irq.c              |  138 -------------------------
 4 files changed, 66 insertions(+), 183 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/include/mach/legacy_irq.h
 delete mode 100644 arch/arm/mach-tegra/legacy_irq.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 1afe050..823c703 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,7 +1,7 @@
 obj-y                                   += common.o
 obj-y                                   += devices.o
 obj-y                                   += io.o
-obj-y                                   += irq.o legacy_irq.o
+obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += gpio.o
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
deleted file mode 100644
index 4c1f535..0000000
--- a/arch/arm/mach-tegra/include/mach/legacy_irq.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/legacy_irq.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
-#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
-
-void tegra_legacy_mask_irq(unsigned int irq);
-void tegra_legacy_unmask_irq(unsigned int irq);
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
-void tegra_legacy_force_irq_set(unsigned int irq);
-void tegra_legacy_force_irq_clr(unsigned int irq);
-int tegra_legacy_force_irq_status(unsigned int irq);
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
-unsigned long tegra_legacy_vfiq(int nr);
-unsigned long tegra_legacy_class(int nr);
-void tegra_init_legacy_irq(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4fa7a37..da17491 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -18,8 +18,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
@@ -27,40 +25,95 @@
 #include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
-#include <mach/legacy_irq.h>
 
 #include "board.h"
 
+#define INT_SYS_NR	(INT_GPIO_BASE - INT_PRI_BASE)
+#define INT_SYS_SZ	(INT_SEC_BASE - INT_PRI_BASE)
+#define PPI_NR		((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
+
+#define ICTLR_CPU_IEP_VFIQ	0x08
+#define ICTLR_CPU_IEP_FIR	0x14
+#define ICTLR_CPU_IEP_FIR_SET	0x18
+#define ICTLR_CPU_IEP_FIR_CLR	0x1c
+
+#define ICTLR_CPU_IER		0x20
+#define ICTLR_CPU_IER_SET	0x24
+#define ICTLR_CPU_IER_CLR	0x28
+#define ICTLR_CPU_IEP_CLASS	0x2C
+
+#define ICTLR_COP_IER		0x30
+#define ICTLR_COP_IER_SET	0x34
+#define ICTLR_COP_IER_CLR	0x38
+#define ICTLR_COP_IEP_CLASS	0x3c
+
+#define NUM_ICTLRS 4
+#define FIRST_LEGACY_IRQ 32
+
+static void __iomem *ictlr_reg_base[] = {
+	IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
+	IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
+	IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
+	IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
+};
+
+static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
+{
+	void __iomem *base;
+	u32 mask;
+
+	BUG_ON(irq < FIRST_LEGACY_IRQ ||
+		irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
+
+	base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
+	mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
+
+	__raw_writel(mask, base + reg);
+}
+
 static void tegra_mask(struct irq_data *d)
 {
-	if (d->irq >= 32)
-		tegra_legacy_mask_irq(d->irq);
+	if (d->irq < FIRST_LEGACY_IRQ)
+		return;
+
+	tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
 }
 
 static void tegra_unmask(struct irq_data *d)
 {
-	if (d->irq >= 32)
-		tegra_legacy_unmask_irq(d->irq);
+	if (d->irq < FIRST_LEGACY_IRQ)
+		return;
+
+	tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
 }
 
 static void tegra_ack(struct irq_data *d)
 {
-	if (d->irq >= 32)
-		tegra_legacy_force_irq_clr(d->irq);
+	if (d->irq < FIRST_LEGACY_IRQ)
+		return;
+
+	tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
 }
 
 static int tegra_retrigger(struct irq_data *d)
 {
-	if (d->irq < 32)
+	if (d->irq < FIRST_LEGACY_IRQ)
 		return 0;
 
-	tegra_legacy_force_irq_set(d->irq);
+	tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
+
 	return 1;
 }
 
 void __init tegra_init_irq(void)
 {
-	tegra_init_legacy_irq();
+	int i;
+
+	for (i = 0; i < NUM_ICTLRS; i++) {
+		void __iomem *ictlr = ictlr_reg_base[i];
+		writel(~0, ictlr + ICTLR_CPU_IER_CLR);
+		writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
+	}
 
 	gic_arch_extn.irq_ack = tegra_ack;
 	gic_arch_extn.irq_mask = tegra_mask;
diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c
deleted file mode 100644
index cb31669..0000000
--- a/arch/arm/mach-tegra/legacy_irq.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * arch/arm/mach-tegra/legacy_irq.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/legacy_irq.h>
-
-#define INT_SYS_NR	(INT_GPIO_BASE - INT_PRI_BASE)
-#define INT_SYS_SZ	(INT_SEC_BASE - INT_PRI_BASE)
-#define PPI_NR		((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
-
-#define ICTLR_CPU_IEP_VFIQ	0x08
-#define ICTLR_CPU_IEP_FIR	0x14
-#define ICTLR_CPU_IEP_FIR_SET	0x18
-#define ICTLR_CPU_IEP_FIR_CLR	0x1c
-
-#define ICTLR_CPU_IER		0x20
-#define ICTLR_CPU_IER_SET	0x24
-#define ICTLR_CPU_IER_CLR	0x28
-#define ICTLR_CPU_IEP_CLASS	0x2C
-
-#define ICTLR_COP_IER		0x30
-#define ICTLR_COP_IER_SET	0x34
-#define ICTLR_COP_IER_CLR	0x38
-#define ICTLR_COP_IEP_CLASS	0x3c
-
-#define NUM_ICTLRS 4
-
-static void __iomem *ictlr_reg_base[] = {
-	IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
-	IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
-	IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
-	IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
-};
-
-/* When going into deep sleep, the CPU is powered down, taking the GIC with it
-   In order to wake, the wake interrupts need to be enabled in the legacy
-   interrupt controller. */
-void tegra_legacy_unmask_irq(unsigned int irq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET);
-}
-
-void tegra_legacy_mask_irq(unsigned int irq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR);
-}
-
-void tegra_legacy_force_irq_set(unsigned int irq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET);
-}
-
-void tegra_legacy_force_irq_clr(unsigned int irq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR);
-}
-
-int tegra_legacy_force_irq_status(unsigned int irq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31)));
-}
-
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq)
-{
-	void __iomem *base;
-	pr_debug("%s: %d\n", __func__, irq);
-
-	irq -= 32;
-	base = ictlr_reg_base[irq>>5];
-	writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS);
-}
-
-unsigned long tegra_legacy_vfiq(int nr)
-{
-	void __iomem *base;
-	base = ictlr_reg_base[nr];
-	return readl(base + ICTLR_CPU_IEP_VFIQ);
-}
-
-unsigned long tegra_legacy_class(int nr)
-{
-	void __iomem *base;
-	base = ictlr_reg_base[nr];
-	return readl(base + ICTLR_CPU_IEP_CLASS);
-}
-
-void tegra_init_legacy_irq(void)
-{
-	int i;
-
-	for (i = 0; i < NUM_ICTLRS; i++) {
-		void __iomem *ictlr = ictlr_reg_base[i];
-		writel(~0, ictlr + ICTLR_CPU_IER_CLR);
-		writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
-	}
-}
-- 
1.7.4.1

[PATCHv2 4/4] ARM: tegra: irq: Add tegra_eoi

[Colin Cross]

Implement irq_eoi to allow the GIC irq chip flow controller to
be changed to fasteoi.

Signed-off-by: Colin Cross <ccross@android.com>
---
v2: Add tegra_eoi without removing tegra_ack, patch can now be
    merged safely before Will Deacon's gic fasteoi patch

 arch/arm/mach-tegra/irq.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index da17491..4956c3c 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -95,6 +95,14 @@ static void tegra_ack(struct irq_data *d)
 	tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
 }
 
+static void tegra_eoi(struct irq_data *d)
+{
+	if (d->irq < FIRST_LEGACY_IRQ)
+		return;
+
+	tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
+}
+
 static int tegra_retrigger(struct irq_data *d)
 {
 	if (d->irq < FIRST_LEGACY_IRQ)
@@ -116,6 +124,7 @@ void __init tegra_init_irq(void)
 	}
 
 	gic_arch_extn.irq_ack = tegra_ack;
+	gic_arch_extn.irq_eoi = tegra_eoi;
 	gic_arch_extn.irq_mask = tegra_mask;
 	gic_arch_extn.irq_unmask = tegra_unmask;
 	gic_arch_extn.irq_retrigger = tegra_retrigger;
-- 
1.7.4.1

[PATCH 1/4] ARM: tegra: irq: convert to gic arch extensions

[Wolfgang Denk]

Dear Colin Cross,

In message <1304284213-11950-2-git-send-email-ccross@android.com> you wrote:
> Replace the ugly hack that inserts legacy irq controller calls
> into the irq call paths by reading and replacing the gic irq
> chip with the new gic arch extensions.
...
> - * Copyright (C) 2010 Google, Inc.
> + * Copyright (C) 2011 Google, Inc.

Sorry for nitpicking, but should this not be "(C) 2010-2011" instead?
You don't want to revoke the 2010 rights on the code, do you?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It usually takes more than three weeks to prepare  a  good  impromptu
speech.                                                  - Mark Twain

[PATCH 1/4] ARM: tegra: irq: convert to gic arch extensions

[Colin Cross]

On Sun, May 1, 2011 at 10:37 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Colin Cross,
>
> In message <1304284213-11950-2-git-send-email-ccross@android.com> you wrote:
>> Replace the ugly hack that inserts legacy irq controller calls
>> into the irq call paths by reading and replacing the gic irq
>> chip with the new gic arch extensions.
> ...
>> - * Copyright (C) 2010 Google, Inc.
>> + * Copyright (C) 2011 Google, Inc.
>
> Sorry for nitpicking, but should this not be "(C) 2010-2011" instead?
> You don't want to revoke the 2010 rights on the code, do you?

You're right, I'll fix it.

[PATCHv2 4/4] ARM: tegra: irq: Add tegra_eoi

[Will Deacon]

Hi Colin,

On Sun, 2011-05-01 at 23:27 +0100, Colin Cross wrote:
> Implement irq_eoi to allow the GIC irq chip flow controller to
> be changed to fasteoi.
> 
> Signed-off-by: Colin Cross <ccross@android.com>
> ---
> v2: Add tegra_eoi without removing tegra_ack, patch can now be
>     merged safely before Will Deacon's gic fasteoi patch
> 
>  arch/arm/mach-tegra/irq.c |    9 +++++++++
>  1 files changed, 9 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
> index da17491..4956c3c 100644
> --- a/arch/arm/mach-tegra/irq.c
> +++ b/arch/arm/mach-tegra/irq.c
> @@ -95,6 +95,14 @@ static void tegra_ack(struct irq_data *d)
>         tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
>  }
> 
> +static void tegra_eoi(struct irq_data *d)
> +{
> +       if (d->irq < FIRST_LEGACY_IRQ)
> +               return;
> +
> +       tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
> +}
> +
>  static int tegra_retrigger(struct irq_data *d)
>  {
>         if (d->irq < FIRST_LEGACY_IRQ)
> @@ -116,6 +124,7 @@ void __init tegra_init_irq(void)
>         }
> 
>         gic_arch_extn.irq_ack = tegra_ack;
> +       gic_arch_extn.irq_eoi = tegra_eoi;
>         gic_arch_extn.irq_mask = tegra_mask;
>         gic_arch_extn.irq_unmask = tegra_unmask;
>         gic_arch_extn.irq_retrigger = tegra_retrigger;
> --
> 1.7.4.1

Just the job!

Acked-by: Will Deacon <will.deacon@arm.com>

Thanks,

Will

[PATCHv2 4/4] ARM: tegra: irq: Add tegra_eoi

[Colin Cross]

On Tue, May 3, 2011 at 2:29 AM, Will Deacon <will.deacon@arm.com> wrote:
> Hi Colin,
>
> On Sun, 2011-05-01 at 23:27 +0100, Colin Cross wrote:
>> Implement irq_eoi to allow the GIC irq chip flow controller to
>> be changed to fasteoi.
>>
>> Signed-off-by: Colin Cross <ccross@android.com>
>> ---
>> v2: Add tegra_eoi without removing tegra_ack, patch can now be
>> ? ? merged safely before Will Deacon's gic fasteoi patch
>>
>> ?arch/arm/mach-tegra/irq.c | ? ?9 +++++++++
>> ?1 files changed, 9 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
>> index da17491..4956c3c 100644
>> --- a/arch/arm/mach-tegra/irq.c
>> +++ b/arch/arm/mach-tegra/irq.c
>> @@ -95,6 +95,14 @@ static void tegra_ack(struct irq_data *d)
>> ? ? ? ? tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
>> ?}
>>
>> +static void tegra_eoi(struct irq_data *d)
>> +{
>> + ? ? ? if (d->irq < FIRST_LEGACY_IRQ)
>> + ? ? ? ? ? ? ? return;
>> +
>> + ? ? ? tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
>> +}
>> +
>> ?static int tegra_retrigger(struct irq_data *d)
>> ?{
>> ? ? ? ? if (d->irq < FIRST_LEGACY_IRQ)
>> @@ -116,6 +124,7 @@ void __init tegra_init_irq(void)
>> ? ? ? ? }
>>
>> ? ? ? ? gic_arch_extn.irq_ack = tegra_ack;
>> + ? ? ? gic_arch_extn.irq_eoi = tegra_eoi;
>> ? ? ? ? gic_arch_extn.irq_mask = tegra_mask;
>> ? ? ? ? gic_arch_extn.irq_unmask = tegra_unmask;
>> ? ? ? ? gic_arch_extn.irq_retrigger = tegra_retrigger;
>> --
>> 1.7.4.1
>
> Just the job!
>
> Acked-by: Will Deacon <will.deacon@arm.com>
>
> Thanks,
>
> Will
>
>

What is your plan for merging the fasteoi patches?  If you are
planning to put them in 2.6.40, can you pull these patches into your
tree?  I don't have any other Tegra changes planned for 2.6.40, so
they shouldn't cause conflicts later.

[PATCHv2 4/4] ARM: tegra: irq: Add tegra_eoi

[Will Deacon]

On Tue, 2011-05-03 at 19:41 +0100, Colin Cross wrote:
> What is your plan for merging the fasteoi patches?  If you are
> planning to put them in 2.6.40, can you pull these patches into your
> tree?  I don't have any other Tegra changes planned for 2.6.40, so
> they shouldn't cause conflicts later.

Ok, since Santosh would like me to take his relaxed I/O stuff for the
GIC too then I guess I can put all of this into an irq branch along with
the fasteoi changes.

Russell - would you be happy pulling this from me if I put it together?

Cheers,

Will