[PATCH v3 00/40] ARM: mm: Add generic macros for declaring various CPU structs

[PATCH v3 00/40] ARM: mm: Add generic macros for declaring various CPU structs

[Dave Martin]

This series adds macros for declaring some CPU-related structured
defined in assembler, and ports the various processors, cache and
tlb implementations to use the macros.

Where multiple proc_info structures are defined by a single source
file, the common elements are collapsed out of these by defining
and invoking an additional local macro for this purpose.

A primary goal for this series is to introduce no API or binary
changes except for fixing the few obvious bugs which became apparent
when working on the series.

NOTE: There is an overlap between this series and Will/Pawel's patches
to include Cortex-A5 support (see
http://lists.arm.linux.org.uk/lurker/message/20110617.081930.2ed0934d.en.html).
Will has agreed to merge with my series in his tree so that it can all
be pulled from there, providing that my series has been accepted by
the community.


Anyone with an interest in any of the arch/arm/mm/{proc,cache,tlb}-*.S
files is invited to comment and/or test.

In particular, I'd like review from anyone interested in the mohawk or
xscale processor families, since this series causes non-trivial
"fixes" in both of these files.  (xscale may be fixed by this series;
mohawk is only partially fixed and still won't work unless a bit of
extra work is done to define a suitable flush_icache_all function.

Detailed notes follow.

Cheers
---Dave



General notes:

  - This patch supersedes Peter Chubb's patch for the typo in
    proc-arm7tdmi.S (see
http://lists.arm.linux.org.uk/lurker/message/20110530.235513.4e1a0d16.en.html),
which I believe hasn't been merged.  If it has merged or is
pending, I can easily rebase on top of it.

  - *_processor_functions structures are not referenced outside
    the proc-*.S in which they are defined and could all be
    demoted to local scope.  To minimise breakage risk, I've left
    these global for now.

  - Some cache_fns structures are not referenced outside the file
    in which they are defined and could be local.  To simplify
    the macro definition, these are currently all made global:
    this should be harmless.

  - Placement of the structures in sections appears somewhat
    inconsistent at present.  Possibly, everything should move
    to __CPUINITRODATA.  Currently, the data is mostly spread
    between __INIT, __TEXT and __INITDATA.  To avoid unintended
    breakage, this series does not automatically switch sections
    in the macros, leaving the preexisting section assignments
    completely unchanged for now.

  - This series introduces a few lines slightly longer than 80
    characters.  I don't think that splitting these lines will
    do a lot to help readability, but this can be done if
    people prefer.

Except as described below, I have confirmed that there is no change
in the objects which get built from any of these files, by diffing
disassembly and symbol tables, and by comparing binary section
dumps.  (Debug info sections do generally change, but this is
expected since they naturally depend on the exact characteristics
of the source code.  They don't end up in the kernel image.)

Under these criteria, the cache-*.S and tlb-*.S files are exactly
equivalent to the unpatched versions.

proc-*.S files change in the following ways: (mostly minor)

        proc-arm1020    a.cp. ..
        proc-arm1020e   a.cp. ..
        proc-arm1022    a.cp. ..
        proc-arm1022    a.cp. ..
        proc-arm6_7     ..... ..
        proc-arm720     ..... ..
        proc-arm740     a.... Z.
        proc-arm7tdmi   .n..u Z. 1
        proc-arm920     a.cp. ..
        proc-arm922     a.cp. ..
        proc-arm925     a.cp. .. 2
        proc-arm926     a.cp. ..
        proc-arm940     ..c.. Z.
        proc-arm946     ..c.. Z.
        proc-arm9tdmi   ....u ..
        proc-fa526      a..p. ..
        proc-feroceon   a.cp. ..
        proc-mohawk     a.c.. .X 34
        proc-sa110      ..... ..
        proc-sa1100     ..... ..
        proc-v6         ..... ..
        proc-v7         .n... ..
        proc-xsc3       ..c.. ..
        proc-xscale     ..c.. .X 5

Legend:

a       section alignment of .proc.info.init and/or .init.data increased
        from 1 to 4

n	one or more name string symbols promoted to STT_OBJECT
c       one or mote cache_fns symbols structured promoted to STT_OBJECT
p       one or more processor_functions symbols promoted to global scope

u       undefined symbol no longer referenced by .size
        directive (typo fix)

Z       missing string terminator added to one of more name
        strings.  In principle, the missing terminator could lead
        to overruns.  In practice, the effect appears to get hidden
        by .align directives; but it's safer to add them anyway.

X       missing flush_icache_all entry inserted at the start of
        one or more cache_fns structures.  The extra field was
        created in:

            commit 81d11955 (ARM: 6405/1: Handle
            __flush_icache_all for CONFIG_SMP_ON_UP),

        breaking various proc-*.S.  Some were fixed by subsequent
        patches, e.g.

            commit c8c90860 (ARM: 6466/1: implement
            flush_icache_all for the rest of the CPUs).

        A few proc-*.S files appear to have been missed.

Processor-specific notes:

1       proc-arm7tdmi: spurious undefined symbol
        cpu_s3c4510b (caused by misspelled .type directive)
        eliminated

2       proc-arm925: size of __arm915_proc_info and
        __arm925_proc_info symbols changed (typo'd duplicate .size
        directive in original)

3       proc-mohawk: mohawk_processor_functions became
        STT_OBJECT (missing .type directive in original)

4       proc-mohawk: missing mohawk_flush_icache_all now
        referenced and needs to be defined to un-break this file
        ** needs review **

5       proc-xscale: missing flush_icache_all funtion in
        xscale_80200_A0_A1_cache_fns assumed to be the same as for
        xscale_cache_fns **needs review**

---
------------------------------------------------------------------------

Dave Martin (40):
  Subject: ARM: mm: prop-macros Add generic proc/cache/tlb struct
    definition macros
  Subject: ARM: assembler.h: Add string declaration macro
  Subject: ARM: mm: cache-fa: Use the new processor struct macros
  Subject: ARM: mm: cache-v3: Use the new processor struct macros
  Subject: ARM: mm: cache-v4: Use the new processor struct macros
  Subject: ARM: mm: cache-v4wb: Use the new processor struct macros
  Subject: ARM: mm: cache-v4wt: Use the new processor struct macros
  Subject: ARM: mm: cache-v6: Use the new processor struct macros
  Subject: ARM: mm: cache-v7: Use the new processor struct macros
  Subject: ARM: mm: proc-arm1020: Use the new processor struct macros
  Subject: ARM: mm: proc-arm1020e: Use the new processor struct macros
  Subject: ARM: mm: proc-arm1022: Use the new processor struct macros
  Subject: ARM: mm: proc-arm1026: Use the new processor struct macros
  Subject: ARM: mm: proc-arm6_7: Use the new processor struct macros
  Subject: ARM: mm: proc-arm720: Use the new processor struct macros
  Subject: ARM: mm: proc-arm740: Use the new processor struct macros
  Subject: ARM: mm: proc-arm7tdmi: Use the new processor struct macros
  Subject: ARM: mm: proc-arm920: Use the new processor struct macros
  Subject: ARM: mm: proc-arm922: Use the new processor struct macros
  Subject: ARM: mm: proc-arm925: Use the new processor struct macros
  Subject: ARM: mm: proc-arm926: Use the new processor struct macros
  Subject: ARM: mm: proc-arm940: Use the new processor struct macros
  Subject: ARM: mm: proc-arm946: Use the new processor struct macros
  Subject: ARM: mm: proc-arm9tdmi: Use the new processor struct macros
  Subject: ARM: mm: proc-fa526: Use the new processor struct macros
  Subject: ARM: mm: proc-feroceon: Use the new processor struct macros
  Subject: ARM: mm: proc-mohawk: Use the new processor struct macros
  Subject: ARM: mm: proc-sa110: Use the new processor struct macros
  Subject: ARM: mm: proc-sa1100: Use the new processor struct macros
  Subject: ARM: mm: proc-v6: Use the new processor struct macros
  Subject: ARM: mm: proc-v7: Use the new processor struct macros
  Subject: ARM: mm: proc-xsc3: Use new generic struct definition macros
  Subject: ARM: mm: proc-xscale: Use new generic struct definition
    macros
  Subject: ARM: mm: tlb-fa: Use the new processor struct macros
  Subject: ARM: mm: tlb-v3: Use the new processor struct macros
  Subject: ARM: mm: tlb-v4: Use the new processor struct macros
  Subject: ARM: mm: tlb-v4wb: Use the new processor struct macros
  Subject: ARM: mm: tlb-v4wbi: Use the new processor struct macros
  Subject: ARM: mm: tlb-v6: Use the new processor struct macros
  Subject: ARM: mm: tlb-v7: Use the new processor struct macros

 arch/arm/include/asm/assembler.h |    8 +
 arch/arm/mm/cache-fa.S           |   15 +-
 arch/arm/mm/cache-v3.S           |   15 +-
 arch/arm/mm/cache-v4.S           |   15 +-
 arch/arm/mm/cache-v4wb.S         |   15 +-
 arch/arm/mm/cache-v4wt.S         |   15 +-
 arch/arm/mm/cache-v6.S           |   15 +-
 arch/arm/mm/cache-v7.S           |   15 +-
 arch/arm/mm/proc-arm1020.S       |   45 +---
 arch/arm/mm/proc-arm1020e.S      |   52 +----
 arch/arm/mm/proc-arm1022.S       |   52 +----
 arch/arm/mm/proc-arm1026.S       |   53 +----
 arch/arm/mm/proc-arm6_7.S        |  166 +++-----------
 arch/arm/mm/proc-arm720.S        |   85 ++------
 arch/arm/mm/proc-arm740.S        |   42 +---
 arch/arm/mm/proc-arm7tdmi.S      |  216 +++--------------
 arch/arm/mm/proc-arm920.S        |   53 +----
 arch/arm/mm/proc-arm922.S        |   53 +----
 arch/arm/mm/proc-arm925.S        |   88 ++------
 arch/arm/mm/proc-arm926.S        |   51 +----
 arch/arm/mm/proc-arm940.S        |   51 +----
 arch/arm/mm/proc-arm946.S        |   53 +----
 arch/arm/mm/proc-arm9tdmi.S      |   78 ++-----
 arch/arm/mm/proc-fa526.S         |   38 +---
 arch/arm/mm/proc-feroceon.S      |  186 +++------------
 arch/arm/mm/proc-macros.S        |   76 ++++++
 arch/arm/mm/proc-mohawk.S        |   50 +----
 arch/arm/mm/proc-sa110.S         |   39 +---
 arch/arm/mm/proc-sa1100.S        |   84 ++------
 arch/arm/mm/proc-v6.S            |   34 +---
 arch/arm/mm/proc-v7.S            |   31 +--
 arch/arm/mm/proc-xsc3.S          |   90 ++------
 arch/arm/mm/proc-xscale.S        |  484 +++++---------------------------------
 arch/arm/mm/tlb-fa.S             |    8 +-
 arch/arm/mm/tlb-v3.S             |    8 +-
 arch/arm/mm/tlb-v4.S             |    8 +-
 arch/arm/mm/tlb-v4wb.S           |    8 +-
 arch/arm/mm/tlb-v4wbi.S          |    8 +-
 arch/arm/mm/tlb-v6.S             |    8 +-
 arch/arm/mm/tlb-v7.S             |    9 +-
 40 files changed, 452 insertions(+), 1968 deletions(-)

-- 
1.7.4.1

[PATCH v3 01/40] Subject: ARM: mm: proc-macros Add generic proc/cache/tlb struct definition macros

[Dave Martin]

This patch adds some generic macros to reduce boilerplate when
declaring certain common structures in arch/arm/mm/*.S

Thanks to Russell King for outlining what the
define_processor_functions macro could look like.

Currently, only a few things can be overriden when invoking the
macros, based on the overrides actually required by the existing
CPUs.  More overrides arguments can be added in the future, if
needed.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-macros.S |   76 +++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 76 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 34261f9..fa28d6b 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -254,3 +254,79 @@
 	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
 	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
 	.endm
+
+.macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0
+	.type	\name\()_processor_functions, #object
+	.align 2
+ENTRY(\name\()_processor_functions)
+	.word	\dabort
+	.word	\pabort
+	.word	cpu_\name\()_proc_init
+	.word	cpu_\name\()_proc_fin
+	.word	cpu_\name\()_reset
+	.word	cpu_\name\()_do_idle
+	.word	cpu_\name\()_dcache_clean_area
+	.word	cpu_\name\()_switch_mm
+
+	.if \nommu
+	.word	0
+	.else
+	.word	cpu_\name\()_set_pte_ext
+	.endif
+
+	.if \suspend
+	.word	cpu_\name\()_suspend_size
+	.word	cpu_\name\()_do_suspend
+	.word	cpu_\name\()_do_resume
+	.else
+	.word	0
+	.word	0
+	.word	0
+	.endif
+
+	.size	\name\()_processor_functions, . - \name\()_processor_functions
+.endm
+
+.macro define_cache_functions name:req, default:req, \
+		flush_kern_dcache_area, dma_map_area, dma_flush_range
+	.align 2
+ 	.type	\name\()_cache_fns, #object
+ENTRY(\name\()_cache_fns)
+	.long	\default\()_flush_icache_all
+	.long	\default\()_flush_kern_cache_all
+	.long	\default\()_flush_user_cache_all
+	.long	\default\()_flush_user_cache_range
+	.long	\default\()_coherent_kern_range
+	.long	\default\()_coherent_user_range
+	.ifb \flush_kern_dcache_area
+		.long	\default\()_flush_kern_dcache_area
+	.else
+		.long	\flush_kern_dcache_area
+	.endif
+	.ifb \dma_map_area
+		.long	\default\()_dma_map_area
+	.else
+		.long	\dma_map_area
+	.endif
+	.long	\default\()_dma_unmap_area
+	.ifb \dma_flush_range
+		.long	\default\()_dma_flush_range
+	.else
+		.long	\dma_flush_range
+	.endif
+	.size	\name\()_cache_fns, . - \name\()_cache_fns
+.endm
+
+.macro define_tlb_functions name:req, flags_up:req, flags_smp
+	.type	\name\()_tlb_fns, #object
+ENTRY(\name\()_tlb_fns)
+	.long	\name\()_flush_user_tlb_range
+	.long	\name\()_flush_kern_tlb_range
+	.ifnb \flags_smp
+		ALT_SMP(.long	\flags_smp )
+		ALT_UP(.long	\flags_up )
+	.else
+		.long	\flags_up
+	.endif
+	.size	\name\()_tlb_fns, . - \name\()_tlb_fns
+.endm
-- 
1.7.4.1

[PATCH v3 01/40] Subject: ARM: mm: proc-macros Add generic proc/cache/tlb struct definition macros

[Russell King - ARM Linux]

On Thu, Jun 23, 2011 at 06:50:09PM +0100, Dave Martin wrote:
> +.macro define_cache_functions name:req, default:req, \
> +		flush_kern_dcache_area, dma_map_area, dma_flush_range
> +	.align 2
> + 	.type	\name\()_cache_fns, #object
> +ENTRY(\name\()_cache_fns)
> +	.long	\default\()_flush_icache_all
> +	.long	\default\()_flush_kern_cache_all
> +	.long	\default\()_flush_user_cache_all
> +	.long	\default\()_flush_user_cache_range
> +	.long	\default\()_coherent_kern_range
> +	.long	\default\()_coherent_user_range
> +	.ifb \flush_kern_dcache_area
> +		.long	\default\()_flush_kern_dcache_area
> +	.else
> +		.long	\flush_kern_dcache_area
> +	.endif
> +	.ifb \dma_map_area
> +		.long	\default\()_dma_map_area
> +	.else
> +		.long	\dma_map_area
> +	.endif
> +	.long	\default\()_dma_unmap_area
> +	.ifb \dma_flush_range
> +		.long	\default\()_dma_flush_range
> +	.else
> +		.long	\dma_flush_range
> +	.endif
> +	.size	\name\()_cache_fns, . - \name\()_cache_fns
> +.endm

This looks wrong.  The flush_kern_dcache_area and DMA stuff can't be
any different:

#define __cpuc_flush_icache_all         __glue(_CACHE,_flush_icache_all)
#define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
#define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
#define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
#define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
#define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
#define __cpuc_flush_dcache_area        __glue(_CACHE,_flush_kern_dcache_area)

#define dmac_map_area                   __glue(_CACHE,_dma_map_area)
#define dmac_unmap_area                 __glue(_CACHE,_dma_unmap_area)
#define dmac_flush_range                __glue(_CACHE,_dma_flush_range)

If they don't conform to the "<cachename>_<functionname>" pattern then
single-cache model kernels will not compile.

As these macros are supposed to be about correctness, they should be
enforcing that too, and not allowing certain functions to be overriden
by different names.

[PATCH v3 01/40] Subject: ARM: mm: proc-macros Add generic proc/cache/tlb struct definition macros

[Will Deacon]

Russell,

On Thu, Jul 07, 2011 at 09:22:51AM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 23, 2011 at 06:50:09PM +0100, Dave Martin wrote:
> > +.macro define_cache_functions name:req, default:req, \
> > +		flush_kern_dcache_area, dma_map_area, dma_flush_range
> > +	.align 2
> > + 	.type	\name\()_cache_fns, #object
> > +ENTRY(\name\()_cache_fns)
> > +	.long	\default\()_flush_icache_all
> > +	.long	\default\()_flush_kern_cache_all
> > +	.long	\default\()_flush_user_cache_all
> > +	.long	\default\()_flush_user_cache_range
> > +	.long	\default\()_coherent_kern_range
> > +	.long	\default\()_coherent_user_range
> > +	.ifb \flush_kern_dcache_area
> > +		.long	\default\()_flush_kern_dcache_area
> > +	.else
> > +		.long	\flush_kern_dcache_area
> > +	.endif
> > +	.ifb \dma_map_area
> > +		.long	\default\()_dma_map_area
> > +	.else
> > +		.long	\dma_map_area
> > +	.endif
> > +	.long	\default\()_dma_unmap_area
> > +	.ifb \dma_flush_range
> > +		.long	\default\()_dma_flush_range
> > +	.else
> > +		.long	\dma_flush_range
> > +	.endif
> > +	.size	\name\()_cache_fns, . - \name\()_cache_fns
> > +.endm
> 
> This looks wrong.  The flush_kern_dcache_area and DMA stuff can't be
> any different:

[...]

Would you be happy to pull from my tree if Dave fixes these issues this
week, or would you rather I drop this series for the coming merge window?

Cheers,

Will

[PATCH v3 01/40] Subject: ARM: mm: proc-macros Add generic proc/cache/tlb struct definition macros

[Dave Martin]

On Thu, Jul 07, 2011 at 09:22:51AM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 23, 2011 at 06:50:09PM +0100, Dave Martin wrote:
> > +.macro define_cache_functions name:req, default:req, \
> > +		flush_kern_dcache_area, dma_map_area, dma_flush_range
> > +	.align 2
> > + 	.type	\name\()_cache_fns, #object
> > +ENTRY(\name\()_cache_fns)
> > +	.long	\default\()_flush_icache_all
> > +	.long	\default\()_flush_kern_cache_all
> > +	.long	\default\()_flush_user_cache_all
> > +	.long	\default\()_flush_user_cache_range
> > +	.long	\default\()_coherent_kern_range
> > +	.long	\default\()_coherent_user_range
> > +	.ifb \flush_kern_dcache_area
> > +		.long	\default\()_flush_kern_dcache_area
> > +	.else
> > +		.long	\flush_kern_dcache_area
> > +	.endif
> > +	.ifb \dma_map_area
> > +		.long	\default\()_dma_map_area
> > +	.else
> > +		.long	\dma_map_area
> > +	.endif
> > +	.long	\default\()_dma_unmap_area
> > +	.ifb \dma_flush_range
> > +		.long	\default\()_dma_flush_range
> > +	.else
> > +		.long	\dma_flush_range
> > +	.endif
> > +	.size	\name\()_cache_fns, . - \name\()_cache_fns
> > +.endm
> 
> This looks wrong.  The flush_kern_dcache_area and DMA stuff can't be
> any different:
> 
> #define __cpuc_flush_icache_all         __glue(_CACHE,_flush_icache_all)
> #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
> #define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
> #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
> #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
> #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
> #define __cpuc_flush_dcache_area        __glue(_CACHE,_flush_kern_dcache_area)
> 
> #define dmac_map_area                   __glue(_CACHE,_dma_map_area)
> #define dmac_unmap_area                 __glue(_CACHE,_dma_unmap_area)
> #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
> 
> If they don't conform to the "<cachename>_<functionname>" pattern then
> single-cache model kernels will not compile.

I added this override capability purely because some proc-*.S define multiple
sets of cache functions which are mostly common but have some differences.
This facility is actually just used by feroceon and xscale, so you're probably
right -- it may be better to fix those than encourage deviation elsewhere.

If this makes any CPU broken, it must by definition be broken already since
I was very careful to ensure there was no change to symbols or generated
code as a result of these patches.

IIUC, these processors may already not work for a single cache model kernel.
In asm/glue-cache.h, this seems to be acknowledged for feroceon (which defines
MULTI_CACHE unconditionally if CONFIG_CPU_FEROCEON is defined).

For xscale, there is no unconditional MULTI_CACHE, so it looks as though if
a single cache model kernel is built, xscale_dma_map_area may get used
unconditionally instead of xscale_dma_a0_map_area even for the buggy A0/A1
processor revisions.  That won't result in a compile failure, just some
incorrect cache maintenance at runtime -- if so, it looks like a bug.

> As these macros are supposed to be about correctness, they should be
> enforcing that too, and not allowing certain functions to be overriden
> by different names.

I guess I agree with that -- making it too easy to override individual
functions may encourage people to do the wrong thing.  So yes, taking away
that generic override capability the forcing people to define appropriate
aliases in the proc-*.S files sounds like a better approach.

However, we also have the problem that any kenel containing multiple sets
of cache fns needs to have MULTI_CACHE defined; otherwise, a faulty
kernel may be built silently.  I think this only applies to xscale right now,
if I've understood correctly.

The easiest solution to that particular problem would be to define MULTI_CACHE
for xscale unconditionally, as is done for feroceon.

Do you think we need a generic check for such situations?

Cheers
---Dave

[PATCH v3 01/40] Subject: ARM: mm: proc-macros Add generic proc/cache/tlb struct definition macros

[Russell King - ARM Linux]

On Thu, Jul 07, 2011 at 11:07:15AM +0100, Dave Martin wrote:
> On Thu, Jul 07, 2011 at 09:22:51AM +0100, Russell King - ARM Linux wrote:
> > If they don't conform to the "<cachename>_<functionname>" pattern then
> > single-cache model kernels will not compile.
> 
> I added this override capability purely because some proc-*.S define multiple
> sets of cache functions which are mostly common but have some differences.
> This facility is actually just used by feroceon and xscale, so you're probably
> right -- it may be better to fix those than encourage deviation elsewhere.

I think so.

> For xscale, there is no unconditional MULTI_CACHE, so it looks as though if
> a single cache model kernel is built, xscale_dma_map_area may get used
> unconditionally instead of xscale_dma_a0_map_area even for the buggy A0/A1
> processor revisions.  That won't result in a compile failure, just some
> incorrect cache maintenance at runtime -- if so, it looks like a bug.

That sounds like there needs to be a separate patch preceding this series
which sets MULTI_CACHE unconditionally for Xscale.

> Do you think we need a generic check for such situations?

No, I think that would be incredibly hard, and for two processors out of
the number we already support, I don't think its worth it.

[PATCH v3 01/40] Subject: ARM: mm: proc-macros Add generic proc/cache/tlb struct definition macros

[Dave Martin]

On Thu, Jul 07, 2011 at 11:16:43AM +0100, Russell King - ARM Linux wrote:
> On Thu, Jul 07, 2011 at 11:07:15AM +0100, Dave Martin wrote:
> > On Thu, Jul 07, 2011 at 09:22:51AM +0100, Russell King - ARM Linux wrote:
> > > If they don't conform to the "<cachename>_<functionname>" pattern then
> > > single-cache model kernels will not compile.
> > 
> > I added this override capability purely because some proc-*.S define multiple
> > sets of cache functions which are mostly common but have some differences.
> > This facility is actually just used by feroceon and xscale, so you're probably
> > right -- it may be better to fix those than encourage deviation elsewhere.
> 
> I think so.
> 
> > For xscale, there is no unconditional MULTI_CACHE, so it looks as though if
> > a single cache model kernel is built, xscale_dma_map_area may get used
> > unconditionally instead of xscale_dma_a0_map_area even for the buggy A0/A1
> > processor revisions.  That won't result in a compile failure, just some
> > incorrect cache maintenance at runtime -- if so, it looks like a bug.
> 
> That sounds like there needs to be a separate patch preceding this series
> which sets MULTI_CACHE unconditionally for Xscale.

OK, I'll submit a separate patch for that.  It's an orthogonal issue really.

> > Do you think we need a generic check for such situations?
> 
> No, I think that would be incredibly hard, and for two processors out of
> the number we already support, I don't think its worth it.

OK -- that was my view too.

I'll rework the series and repost.  The changes shouldn't be invasive.

Cheers
---Dave

[PATCH v3 02/40] Subject: ARM: assembler.h: Add string declaration macro

[Dave Martin]

Declaring strings in assembler source involves a certain amount of
tedious boilerplate code in order to annotate the resulting symbol
correctly.

Encapsulating this boilerplate in a macro should help to avoid some
duplication and the occasional mistake.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/include/asm/assembler.h |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index bc2d2d7..9e1e952 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -290,3 +290,11 @@
 	.macro	ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
 	usracc	ldr, \reg, \ptr, \inc, \cond, \rept, \abort
 	.endm
+
+/* Utility macro for declaring string literals */
+	.macro	string name:req, string
+	.type \name , #object
+\name:
+	.asciz "\string"
+	.size \name , . - \name
+	.endm
-- 
1.7.4.1

[PATCH v3 03/40] Subject: ARM: mm: cache-fa: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/cache-fa.S |   15 ++-------------
 1 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index 1fa6f71..77509ef 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -242,16 +242,5 @@ ENDPROC(fa_dma_unmap_area)
 
 	__INITDATA
 
-	.type	fa_cache_fns, #object
-ENTRY(fa_cache_fns)
-	.long	fa_flush_icache_all
-	.long	fa_flush_kern_cache_all
-	.long	fa_flush_user_cache_all
-	.long	fa_flush_user_cache_range
-	.long	fa_coherent_kern_range
-	.long	fa_coherent_user_range
-	.long	fa_flush_kern_dcache_area
-	.long	fa_dma_map_area
-	.long	fa_dma_unmap_area
-	.long	fa_dma_flush_range
-	.size	fa_cache_fns, . - fa_cache_fns
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions fa, default=fa
-- 
1.7.4.1

[PATCH v3 04/40] Subject: ARM: mm: cache-v3: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/cache-v3.S |   15 ++-------------
 1 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 2e2bc40..1e1748f 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -129,16 +129,5 @@ ENDPROC(v3_dma_map_area)
 
 	__INITDATA
 
-	.type	v3_cache_fns, #object
-ENTRY(v3_cache_fns)
-	.long	v3_flush_icache_all
-	.long	v3_flush_kern_cache_all
-	.long	v3_flush_user_cache_all
-	.long	v3_flush_user_cache_range
-	.long	v3_coherent_kern_range
-	.long	v3_coherent_user_range
-	.long	v3_flush_kern_dcache_area
-	.long	v3_dma_map_area
-	.long	v3_dma_unmap_area
-	.long	v3_dma_flush_range
-	.size	v3_cache_fns, . - v3_cache_fns
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions v3, default=v3
-- 
1.7.4.1

[PATCH v3 05/40] Subject: ARM: mm: cache-v4: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/cache-v4.S |   15 ++-------------
 1 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index a8fefb5..8aa5a7f 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -141,16 +141,5 @@ ENDPROC(v4_dma_map_area)
 
 	__INITDATA
 
-	.type	v4_cache_fns, #object
-ENTRY(v4_cache_fns)
-	.long	v4_flush_icache_all
-	.long	v4_flush_kern_cache_all
-	.long	v4_flush_user_cache_all
-	.long	v4_flush_user_cache_range
-	.long	v4_coherent_kern_range
-	.long	v4_coherent_user_range
-	.long	v4_flush_kern_dcache_area
-	.long	v4_dma_map_area
-	.long	v4_dma_unmap_area
-	.long	v4_dma_flush_range
-	.size	v4_cache_fns, . - v4_cache_fns
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions v4, default=v4
-- 
1.7.4.1

[PATCH v3 06/40] Subject: ARM: mm: cache-v4wb: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/cache-v4wb.S |   15 ++-------------
 1 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index f40c696..99acac9 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -253,16 +253,5 @@ ENDPROC(v4wb_dma_unmap_area)
 
 	__INITDATA
 
-	.type	v4wb_cache_fns, #object
-ENTRY(v4wb_cache_fns)
-	.long	v4wb_flush_icache_all
-	.long	v4wb_flush_kern_cache_all
-	.long	v4wb_flush_user_cache_all
-	.long	v4wb_flush_user_cache_range
-	.long	v4wb_coherent_kern_range
-	.long	v4wb_coherent_user_range
-	.long	v4wb_flush_kern_dcache_area
-	.long	v4wb_dma_map_area
-	.long	v4wb_dma_unmap_area
-	.long	v4wb_dma_flush_range
-	.size	v4wb_cache_fns, . - v4wb_cache_fns
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions v4wb, default=v4wb
-- 
1.7.4.1

[PATCH v3 07/40] Subject: ARM: mm: cache-v4wt: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/cache-v4wt.S |   15 ++-------------
 1 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index a7b276d..16c5603 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -197,16 +197,5 @@ ENDPROC(v4wt_dma_map_area)
 
 	__INITDATA
 
-	.type	v4wt_cache_fns, #object
-ENTRY(v4wt_cache_fns)
-	.long	v4wt_flush_icache_all
-	.long	v4wt_flush_kern_cache_all
-	.long	v4wt_flush_user_cache_all
-	.long	v4wt_flush_user_cache_range
-	.long	v4wt_coherent_kern_range
-	.long	v4wt_coherent_user_range
-	.long	v4wt_flush_kern_dcache_area
-	.long	v4wt_dma_map_area
-	.long	v4wt_dma_unmap_area
-	.long	v4wt_dma_flush_range
-	.size	v4wt_cache_fns, . - v4wt_cache_fns
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions v4wt, default=v4wt
-- 
1.7.4.1

[PATCH v3 08/40] Subject: ARM: mm: cache-v6: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/cache-v6.S |   15 ++-------------
 1 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 73b4a8b..e14084a 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -330,16 +330,5 @@ ENDPROC(v6_dma_unmap_area)
 
 	__INITDATA
 
-	.type	v6_cache_fns, #object
-ENTRY(v6_cache_fns)
-	.long	v6_flush_icache_all
-	.long	v6_flush_kern_cache_all
-	.long	v6_flush_user_cache_all
-	.long	v6_flush_user_cache_range
-	.long	v6_coherent_kern_range
-	.long	v6_coherent_user_range
-	.long	v6_flush_kern_dcache_area
-	.long	v6_dma_map_area
-	.long	v6_dma_unmap_area
-	.long	v6_dma_flush_range
-	.size	v6_cache_fns, . - v6_cache_fns
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions v6, default=v6
-- 
1.7.4.1

[PATCH v3 09/40] Subject: ARM: mm: cache-v7: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/cache-v7.S |   15 ++-------------
 1 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index d32f02b..c2956cd 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -325,16 +325,5 @@ ENDPROC(v7_dma_unmap_area)
 
 	__INITDATA
 
-	.type	v7_cache_fns, #object
-ENTRY(v7_cache_fns)
-	.long	v7_flush_icache_all
-	.long	v7_flush_kern_cache_all
-	.long	v7_flush_user_cache_all
-	.long	v7_flush_user_cache_range
-	.long	v7_coherent_kern_range
-	.long	v7_coherent_user_range
-	.long	v7_flush_kern_dcache_area
-	.long	v7_dma_map_area
-	.long	v7_dma_unmap_area
-	.long	v7_dma_flush_range
-	.size	v7_cache_fns, . - v7_cache_fns
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions v7, default=v7
-- 
1.7.4.1

[PATCH v3 10/40] Subject: ARM: mm: proc-arm1020: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm1020.S |   45 +++++--------------------------------------
 1 files changed, 6 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 6c4e7fd..9cf3b4a 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -364,17 +364,8 @@ ENTRY(arm1020_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(arm1020_dma_unmap_area)
 
-ENTRY(arm1020_cache_fns)
-	.long	arm1020_flush_icache_all
-	.long	arm1020_flush_kern_cache_all
-	.long	arm1020_flush_user_cache_all
-	.long	arm1020_flush_user_cache_range
-	.long	arm1020_coherent_kern_range
-	.long	arm1020_coherent_user_range
-	.long	arm1020_flush_kern_dcache_area
-	.long	arm1020_dma_map_area
-	.long	arm1020_dma_unmap_area
-	.long	arm1020_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions arm1020, default=arm1020
 
 	.align	5
 ENTRY(cpu_arm1020_dcache_clean_area)
@@ -477,38 +468,14 @@ arm1020_crval:
 	crval	clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
 
 	__INITDATA
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm1020_processor_functions, #object
-arm1020_processor_functions:
-	.word	v4t_early_abort
-	.word	legacy_pabort
-	.word	cpu_arm1020_proc_init
-	.word	cpu_arm1020_proc_fin
-	.word	cpu_arm1020_reset
-	.word	cpu_arm1020_do_idle
-	.word	cpu_arm1020_dcache_clean_area
-	.word	cpu_arm1020_switch_mm
-	.word	cpu_arm1020_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	arm1020_processor_functions, . - arm1020_processor_functions
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5t"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5"
-	.size	cpu_elf_name, . - cpu_elf_name
+	string	cpu_arch_name, "armv5t"
+	string	cpu_elf_name, "v5"
 
 	.type	cpu_arm1020_name, #object
 cpu_arm1020_name:
-- 
1.7.4.1

[PATCH v3 11/40] Subject: ARM: mm: proc-arm1020e: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm1020e.S |   52 +++++-------------------------------------
 1 files changed, 7 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 4ce947c..e2869f1 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -350,17 +350,8 @@ ENTRY(arm1020e_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(arm1020e_dma_unmap_area)
 
-ENTRY(arm1020e_cache_fns)
-	.long	arm1020e_flush_icache_all
-	.long	arm1020e_flush_kern_cache_all
-	.long	arm1020e_flush_user_cache_all
-	.long	arm1020e_flush_user_cache_range
-	.long	arm1020e_coherent_kern_range
-	.long	arm1020e_coherent_user_range
-	.long	arm1020e_flush_kern_dcache_area
-	.long	arm1020e_dma_map_area
-	.long	arm1020e_dma_unmap_area
-	.long	arm1020e_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions arm1020e, default=arm1020e
 
 	.align	5
 ENTRY(cpu_arm1020e_dcache_clean_area)
@@ -458,43 +449,14 @@ arm1020e_crval:
 	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
 
 	__INITDATA
-
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm1020e_processor_functions, #object
-arm1020e_processor_functions:
-	.word	v4t_early_abort
-	.word	legacy_pabort
-	.word	cpu_arm1020e_proc_init
-	.word	cpu_arm1020e_proc_fin
-	.word	cpu_arm1020e_reset
-	.word	cpu_arm1020e_do_idle
-	.word	cpu_arm1020e_dcache_clean_area
-	.word	cpu_arm1020e_switch_mm
-	.word	cpu_arm1020e_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	arm1020e_processor_functions, . - arm1020e_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm1020e, dabort=v4t_early_abort, pabort=legacy_pabort
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5te"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_arm1020e_name, #object
-cpu_arm1020e_name:
-	.asciz	"ARM1020E"
-	.size	cpu_arm1020e_name, . - cpu_arm1020e_name
+	string	cpu_arch_name, "armv5te"
+	string	cpu_elf_name, "v5"
+	string	cpu_arm1020e_name, "ARM1020E"
 
 	.align
 
-- 
1.7.4.1

[PATCH v3 12/40] Subject: ARM: mm: proc-arm1022: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm1022.S |   52 ++++++--------------------------------------
 1 files changed, 7 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index c8884c5..e9d6f0a 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -339,17 +339,8 @@ ENTRY(arm1022_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(arm1022_dma_unmap_area)
 
-ENTRY(arm1022_cache_fns)
-	.long	arm1022_flush_icache_all
-	.long	arm1022_flush_kern_cache_all
-	.long	arm1022_flush_user_cache_all
-	.long	arm1022_flush_user_cache_range
-	.long	arm1022_coherent_kern_range
-	.long	arm1022_coherent_user_range
-	.long	arm1022_flush_kern_dcache_area
-	.long	arm1022_dma_map_area
-	.long	arm1022_dma_unmap_area
-	.long	arm1022_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions arm1022, default=arm1022
 
 	.align	5
 ENTRY(cpu_arm1022_dcache_clean_area)
@@ -441,43 +432,14 @@ arm1022_crval:
 	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
 
 	__INITDATA
-
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm1022_processor_functions, #object
-arm1022_processor_functions:
-	.word	v4t_early_abort
-	.word	legacy_pabort
-	.word	cpu_arm1022_proc_init
-	.word	cpu_arm1022_proc_fin
-	.word	cpu_arm1022_reset
-	.word	cpu_arm1022_do_idle
-	.word	cpu_arm1022_dcache_clean_area
-	.word	cpu_arm1022_switch_mm
-	.word	cpu_arm1022_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	arm1022_processor_functions, . - arm1022_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm1022, dabort=v4t_early_abort, pabort=legacy_pabort
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5te"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_arm1022_name, #object
-cpu_arm1022_name:
-	.asciz	"ARM1022"
-	.size	cpu_arm1022_name, . - cpu_arm1022_name
+	string	cpu_arch_name, "armv5te"
+	string	cpu_elf_name, "v5"
+	string	cpu_arm1022_name, "ARM1022"
 
 	.align
 
-- 
1.7.4.1

[PATCH v3 13/40] Subject: ARM: mm: proc-arm1026: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm1026.S |   53 +++++--------------------------------------
 1 files changed, 7 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 4136846..cccb912 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -333,17 +333,8 @@ ENTRY(arm1026_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(arm1026_dma_unmap_area)
 
-ENTRY(arm1026_cache_fns)
-	.long	arm1026_flush_icache_all
-	.long	arm1026_flush_kern_cache_all
-	.long	arm1026_flush_user_cache_all
-	.long	arm1026_flush_user_cache_range
-	.long	arm1026_coherent_kern_range
-	.long	arm1026_coherent_user_range
-	.long	arm1026_flush_kern_dcache_area
-	.long	arm1026_dma_map_area
-	.long	arm1026_dma_unmap_area
-	.long	arm1026_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions arm1026, default=arm1026
 
 	.align	5
 ENTRY(cpu_arm1026_dcache_clean_area)
@@ -436,45 +427,15 @@ arm1026_crval:
 	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
 
 	__INITDATA
-
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm1026_processor_functions, #object
-arm1026_processor_functions:
-	.word	v5t_early_abort
-	.word	legacy_pabort
-	.word	cpu_arm1026_proc_init
-	.word	cpu_arm1026_proc_fin
-	.word	cpu_arm1026_reset
-	.word	cpu_arm1026_do_idle
-	.word	cpu_arm1026_dcache_clean_area
-	.word	cpu_arm1026_switch_mm
-	.word	cpu_arm1026_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	arm1026_processor_functions, . - arm1026_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm1026, dabort=v5t_early_abort, pabort=legacy_pabort
 
 	.section .rodata
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5tej"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5"
-	.size	cpu_elf_name, . - cpu_elf_name
+	string	cpu_arch_name, "armv5tej"
+	string	cpu_elf_name, "v5"
 	.align
-
-	.type	cpu_arm1026_name, #object
-cpu_arm1026_name:
-	.asciz	"ARM1026EJ-S"
-	.size	cpu_arm1026_name, . - cpu_arm1026_name
-
+	string	cpu_arm1026_name, "ARM1026EJ-S"
 	.align
 
 	.section ".proc.info.init", #alloc, #execinstr
-- 
1.7.4.1

[PATCH v3 14/40] Subject: ARM: mm: proc-arm6_7: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm6_7.S |  166 +++++++++------------------------------------
 1 files changed, 32 insertions(+), 134 deletions(-)

diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 5f79dc4..03ec61e 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -269,159 +269,57 @@ __arm7_setup:	mov	r0, #0
 
 		__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-		.type	arm6_processor_functions, #object
-ENTRY(arm6_processor_functions)
-		.word	cpu_arm6_data_abort
-		.word	legacy_pabort
-		.word	cpu_arm6_proc_init
-		.word	cpu_arm6_proc_fin
-		.word	cpu_arm6_reset
-		.word	cpu_arm6_do_idle
-		.word	cpu_arm6_dcache_clean_area
-		.word	cpu_arm6_switch_mm
-		.word	cpu_arm6_set_pte_ext
-		.word	0
-		.word	0
-		.word	0
-		.size	arm6_processor_functions, . - arm6_processor_functions
-
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-		.type	arm7_processor_functions, #object
-ENTRY(arm7_processor_functions)
-		.word	cpu_arm7_data_abort
-		.word	legacy_pabort
-		.word	cpu_arm7_proc_init
-		.word	cpu_arm7_proc_fin
-		.word	cpu_arm7_reset
-		.word	cpu_arm7_do_idle
-		.word	cpu_arm7_dcache_clean_area
-		.word	cpu_arm7_switch_mm
-		.word	cpu_arm7_set_pte_ext
-		.word	0
-		.word	0
-		.word	0
-		.size	arm7_processor_functions, . - arm7_processor_functions
+		@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+		define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
+		define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort
 
 		.section ".rodata"
 
-		.type	cpu_arch_name, #object
-cpu_arch_name:	.asciz	"armv3"
-		.size	cpu_arch_name, . - cpu_arch_name
-
-		.type	cpu_elf_name, #object
-cpu_elf_name:	.asciz	"v3"
-		.size	cpu_elf_name, . - cpu_elf_name
-
-		.type	cpu_arm6_name, #object
-cpu_arm6_name:	.asciz	"ARM6"
-		.size	cpu_arm6_name, . - cpu_arm6_name
-
-		.type	cpu_arm610_name, #object
-cpu_arm610_name:
-		.asciz	"ARM610"
-		.size	cpu_arm610_name, . - cpu_arm610_name
-
-		.type	cpu_arm7_name, #object
-cpu_arm7_name:	.asciz	"ARM7"
-		.size	cpu_arm7_name, . - cpu_arm7_name
-
-		.type	cpu_arm710_name, #object
-cpu_arm710_name:
-		.asciz	"ARM710"
-		.size	cpu_arm710_name, . - cpu_arm710_name
+		string	cpu_arch_name, "armv3"
+		string	cpu_elf_name, "v3"
+		string	cpu_arm6_name, "ARM6"
+		string	cpu_arm610_name, "ARM610"
+		string	cpu_arm7_name, "ARM7"
+		string	cpu_arm710_name, "ARM710"
 
 		.align
 
 		.section ".proc.info.init", #alloc, #execinstr
 
-		.type	__arm6_proc_info, #object
-__arm6_proc_info:
-		.long	0x41560600
-		.long	0xfffffff0
-		.long	0x00000c1e
+.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
+	cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
+		.type	__\name\()_proc_info, #object
+__\name\()_proc_info:
+		.long	\cpu_val
+		.long	\cpu_mask
+		.long	\cpu_mm_mmu_flags
 		.long   PMD_TYPE_SECT | \
 			PMD_BIT4 | \
 			PMD_SECT_AP_WRITE | \
 			PMD_SECT_AP_READ
-		b	__arm6_setup
+		b	\cpu_flush
 		.long	cpu_arch_name
 		.long	cpu_elf_name
 		.long	HWCAP_SWP | HWCAP_26BIT
-		.long	cpu_arm6_name
-		.long	arm6_processor_functions
+		.long	\cpu_name\()
+		.long	\cpu_proc_funcs
 		.long	v3_tlb_fns
 		.long	v3_user_fns
 		.long	v3_cache_fns
-		.size	__arm6_proc_info, . - __arm6_proc_info
-
-		.type	__arm610_proc_info, #object
-__arm610_proc_info:
-		.long	0x41560610
-		.long	0xfffffff0
-		.long	0x00000c1e
-		.long   PMD_TYPE_SECT | \
-			PMD_BIT4 | \
-			PMD_SECT_AP_WRITE | \
-			PMD_SECT_AP_READ
-		b	__arm6_setup
-		.long	cpu_arch_name
-		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_26BIT
-		.long	cpu_arm610_name
-		.long	arm6_processor_functions
-		.long	v3_tlb_fns
-		.long	v3_user_fns
-		.long	v3_cache_fns
-		.size	__arm610_proc_info, . - __arm610_proc_info
-
-		.type	__arm7_proc_info, #object
-__arm7_proc_info:
-		.long	0x41007000
-		.long	0xffffff00
-		.long	0x00000c1e
-		.long   PMD_TYPE_SECT | \
-			PMD_BIT4 | \
-			PMD_SECT_AP_WRITE | \
-			PMD_SECT_AP_READ
-		b	__arm7_setup
-		.long	cpu_arch_name
-		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_26BIT
-		.long	cpu_arm7_name
-		.long	arm7_processor_functions
-		.long	v3_tlb_fns
-		.long	v3_user_fns
-		.long	v3_cache_fns
-		.size	__arm7_proc_info, . - __arm7_proc_info
-
-		.type	__arm710_proc_info, #object
-__arm710_proc_info:
-		.long	0x41007100
-		.long	0xfff8ff00
-		.long   PMD_TYPE_SECT | \
+		.size	__\name\()_proc_info, . - __\name\()_proc_info
+.endm
+
+	arm67_proc_info	arm6,	0x41560600, 0xfffffff0, cpu_arm6_name, \
+		0x00000c1e, __arm6_setup, arm6_processor_functions
+	arm67_proc_info	arm610,	0x41560610, 0xfffffff0, cpu_arm610_name, \
+		0x00000c1e, __arm6_setup, arm6_processor_functions
+	arm67_proc_info	arm7,	0x41007000, 0xffffff00, cpu_arm7_name, \
+		0x00000c1e, __arm7_setup, arm7_processor_functions
+	arm67_proc_info	arm710,	0x41007100, 0xfff8ff00, cpu_arm710_name, \
+			PMD_TYPE_SECT | \
 			PMD_SECT_BUFFERABLE | \
 			PMD_SECT_CACHEABLE | \
 			PMD_BIT4 | \
 			PMD_SECT_AP_WRITE | \
-			PMD_SECT_AP_READ
-		.long   PMD_TYPE_SECT | \
-			PMD_BIT4 | \
-			PMD_SECT_AP_WRITE | \
-			PMD_SECT_AP_READ
-		b	__arm7_setup
-		.long	cpu_arch_name
-		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_26BIT
-		.long	cpu_arm710_name
-		.long	arm7_processor_functions
-		.long	v3_tlb_fns
-		.long	v3_user_fns
-		.long	v3_cache_fns
-		.size	__arm710_proc_info, . - __arm710_proc_info
+			PMD_SECT_AP_READ, \
+		__arm7_setup, arm7_processor_functions
-- 
1.7.4.1

[PATCH v3 14/40] Subject: ARM: mm: proc-arm6_7: Use the new processor struct macros

[Russell King - ARM Linux]

On Thu, Jun 23, 2011 at 06:50:22PM +0100, Dave Martin wrote:
> +.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
> +	cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
> +		.type	__\name\()_proc_info, #object
> +__\name\()_proc_info:
> +		.long	\cpu_val
> +		.long	\cpu_mask
> +		.long	\cpu_mm_mmu_flags
>  		.long   PMD_TYPE_SECT | \
>  			PMD_BIT4 | \
>  			PMD_SECT_AP_WRITE | \
>  			PMD_SECT_AP_READ
> -		b	__arm6_setup
> +		b	\cpu_flush
>  		.long	cpu_arch_name
>  		.long	cpu_elf_name
>  		.long	HWCAP_SWP | HWCAP_26BIT
> -		.long	cpu_arm6_name
> -		.long	arm6_processor_functions
> +		.long	\cpu_name\()

I don't think you want the extra \() there.

[PATCH v3 14/40] Subject: ARM: mm: proc-arm6_7: Use the new processor struct macros

[Dave Martin]

On Thu, Jul 07, 2011 at 10:10:19AM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 23, 2011 at 06:50:22PM +0100, Dave Martin wrote:
> > +.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
> > +	cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
> > +		.type	__\name\()_proc_info, #object
> > +__\name\()_proc_info:
> > +		.long	\cpu_val
> > +		.long	\cpu_mask
> > +		.long	\cpu_mm_mmu_flags
> >  		.long   PMD_TYPE_SECT | \
> >  			PMD_BIT4 | \
> >  			PMD_SECT_AP_WRITE | \
> >  			PMD_SECT_AP_READ
> > -		b	__arm6_setup
> > +		b	\cpu_flush
> >  		.long	cpu_arch_name
> >  		.long	cpu_elf_name
> >  		.long	HWCAP_SWP | HWCAP_26BIT
> > -		.long	cpu_arm6_name
> > -		.long	arm6_processor_functions
> > +		.long	\cpu_name\()
> 
> I don't think you want the extra \() there.

Hmm, quite right.  Not sure where that come from.

I've fixed it locally for now pending repost.

Cheers
---Dave

[PATCH v3 15/40] Subject: ARM: mm: proc-arm720: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm720.S |   85 +++++++++------------------------------------
 1 files changed, 17 insertions(+), 68 deletions(-)

diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 7a06e59..55f4e29 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -169,46 +169,15 @@ arm720_crval:
 	crval	clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
 
 		__INITDATA
-
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-		.type	arm720_processor_functions, #object
-ENTRY(arm720_processor_functions)
-		.word	v4t_late_abort
-		.word	legacy_pabort
-		.word	cpu_arm720_proc_init
-		.word	cpu_arm720_proc_fin
-		.word	cpu_arm720_reset
-		.word	cpu_arm720_do_idle
-		.word	cpu_arm720_dcache_clean_area
-		.word	cpu_arm720_switch_mm
-		.word	cpu_arm720_set_pte_ext
-		.word	0
-		.word	0
-		.word	0
-		.size	arm720_processor_functions, . - arm720_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm720, dabort=v4t_late_abort, pabort=legacy_pabort
 
 		.section ".rodata"
 
-		.type	cpu_arch_name, #object
-cpu_arch_name:	.asciz	"armv4t"
-		.size	cpu_arch_name, . - cpu_arch_name
-
-		.type	cpu_elf_name, #object
-cpu_elf_name:	.asciz	"v4"
-		.size	cpu_elf_name, . - cpu_elf_name
-
-		.type	cpu_arm710_name, #object
-cpu_arm710_name:
-		.asciz	"ARM710T"
-		.size	cpu_arm710_name, . - cpu_arm710_name
-
-		.type	cpu_arm720_name, #object
-cpu_arm720_name:
-		.asciz	"ARM720T"
-		.size	cpu_arm720_name, . - cpu_arm720_name
+	string	cpu_arch_name, "armv4t"
+	string	cpu_elf_name, "v4"
+	string	cpu_arm710_name, "ARM710T"
+	string	cpu_arm720_name, "ARM720T"
 
 		.align
 
@@ -218,10 +187,11 @@ cpu_arm720_name:
 	
 		.section ".proc.info.init", #alloc, #execinstr
 
-		.type	__arm710_proc_info, #object
-__arm710_proc_info:
-		.long	0x41807100				@ cpu_val
-		.long	0xffffff00				@ cpu_mask
+.macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
+		.type	__\name\()_proc_info,#object
+__\name\()_proc_info:
+		.long	\cpu_val
+		.long	\cpu_mask
 		.long   PMD_TYPE_SECT | \
 			PMD_SECT_BUFFERABLE | \
 			PMD_SECT_CACHEABLE | \
@@ -232,38 +202,17 @@ __arm710_proc_info:
 			PMD_BIT4 | \
 			PMD_SECT_AP_WRITE | \
 			PMD_SECT_AP_READ
-		b	__arm710_setup				@ cpu_flush
+		b	\cpu_flush				@ cpu_flush
 		.long	cpu_arch_name				@ arch_name
 		.long	cpu_elf_name				@ elf_name
 		.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB	@ elf_hwcap
-		.long	cpu_arm710_name				@ name
+		.long	\cpu_name
 		.long	arm720_processor_functions
 		.long	v4_tlb_fns
 		.long	v4wt_user_fns
 		.long	v4_cache_fns
-		.size	__arm710_proc_info, . - __arm710_proc_info
+		.size	__\name\()_proc_info, . - __\name\()_proc_info
+.endm
 
-		.type	__arm720_proc_info, #object
-__arm720_proc_info:
-		.long	0x41807200				@ cpu_val
-		.long	0xffffff00				@ cpu_mask
-		.long   PMD_TYPE_SECT | \
-			PMD_SECT_BUFFERABLE | \
-			PMD_SECT_CACHEABLE | \
-			PMD_BIT4 | \
-			PMD_SECT_AP_WRITE | \
-			PMD_SECT_AP_READ
-		.long   PMD_TYPE_SECT | \
-			PMD_BIT4 | \
-			PMD_SECT_AP_WRITE | \
-			PMD_SECT_AP_READ
-		b	__arm720_setup				@ cpu_flush
-		.long	cpu_arch_name				@ arch_name
-		.long	cpu_elf_name				@ elf_name
-		.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB	@ elf_hwcap
-		.long	cpu_arm720_name				@ name
-		.long	arm720_processor_functions
-		.long	v4_tlb_fns
-		.long	v4wt_user_fns
-		.long	v4_cache_fns
-		.size	__arm720_proc_info, . - __arm720_proc_info
+	arm720_proc_info arm710, 0x41807100, 0xffffff00, cpu_arm710_name, __arm710_setup
+	arm720_proc_info arm720, 0x41807200, 0xffffff00, cpu_arm720_name, __arm720_setup
-- 
1.7.4.1

[PATCH v3 16/40] Subject: ARM: mm: proc-arm740: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm740.S |   42 +++++++-----------------------------------
 1 files changed, 7 insertions(+), 35 deletions(-)

diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 6f9d12e..4506be3 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -17,6 +17,8 @@
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
 
+#include "proc-macros.S"
+
 	.text
 /*
  * cpu_arm740_proc_init()
@@ -115,42 +117,14 @@ __arm740_setup:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm740_processor_functions, #object
-ENTRY(arm740_processor_functions)
-	.word	v4t_late_abort
-	.word	legacy_pabort
-	.word	cpu_arm740_proc_init
-	.word	cpu_arm740_proc_fin
-	.word	cpu_arm740_reset
-	.word   cpu_arm740_do_idle
-	.word	cpu_arm740_dcache_clean_area
-	.word	cpu_arm740_switch_mm
-	.word	0			@ cpu_*_set_pte
-	.word	0
-	.word	0
-	.word	0
-	.size	arm740_processor_functions, . - arm740_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm740, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv4"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v4"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_arm740_name, #object
-cpu_arm740_name:
-	.ascii	"ARM740T"
-	.size	cpu_arm740_name, . - cpu_arm740_name
+	string	cpu_arch_name, "armv4"
+	string	cpu_elf_name, "v4"
+	string	cpu_arm740_name, "ARM740T"
 
 	.align
 
@@ -170,5 +144,3 @@ __arm740_proc_info:
 	.long	0
 	.long	v3_cache_fns			@ cache model
 	.size	__arm740_proc_info, . - __arm740_proc_info
-
-
-- 
1.7.4.1

[PATCH v3 17/40] Subject: ARM: mm: proc-arm7tdmi: Use the new processor struct macros

[Dave Martin]

This patch also fixes a .size directive typo, which was causing a
reference to a nonexistent symbol.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm7tdmi.S |  216 ++++++++-----------------------------------
 1 files changed, 39 insertions(+), 177 deletions(-)

diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index e4c165c..7e0e1fe 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -17,6 +17,8 @@
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
 
+#include "proc-macros.S"
+
 	.text
 /*
  * cpu_arm7tdmi_proc_init()
@@ -55,197 +57,57 @@ __arm7tdmi_setup:
 
 		__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-		.type	arm7tdmi_processor_functions, #object
-ENTRY(arm7tdmi_processor_functions)
-		.word	v4t_late_abort
-		.word	legacy_pabort
-		.word	cpu_arm7tdmi_proc_init
-		.word	cpu_arm7tdmi_proc_fin
-		.word	cpu_arm7tdmi_reset
-		.word	cpu_arm7tdmi_do_idle
-		.word	cpu_arm7tdmi_dcache_clean_area
-		.word	cpu_arm7tdmi_switch_mm
-		.word	0		@ cpu_*_set_pte
-		.word	0
-		.word	0
-		.word	0
-		.size	arm7tdmi_processor_functions, . - arm7tdmi_processor_functions
+		@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+		define_processor_functions arm7tdmi, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1
 
 		.section ".rodata"
 
-		.type	cpu_arch_name, #object
-cpu_arch_name:
-		.asciz	"armv4t"
-		.size	cpu_arch_name, . - cpu_arch_name
-
-		.type	cpu_elf_name, #object
-cpu_elf_name:
-		.asciz	"v4"
-		.size	cpu_elf_name, . - cpu_elf_name
-
-		.type	cpu_arm7tdmi_name, #object
-cpu_arm7tdmi_name:
-		.asciz	"ARM7TDMI"
-		.size	cpu_arm7tdmi_name, . - cpu_arm7tdmi_name
-
-		.type	cpu_triscenda7_name, #object
-cpu_triscenda7_name:
-		.asciz	"Triscend-A7x"
-		.size	cpu_triscenda7_name, . - cpu_triscenda7_name
-
-		.type	cpu_at91_name, #object
-cpu_at91_name:
-		.asciz	"Atmel-AT91M40xxx"
-		.size	cpu_at91_name, . - cpu_at91_name
-
-		.type	cpu_s3c3410_name, #object
-cpu_s3c3410_name:
-		.asciz	"Samsung-S3C3410"
-		.size	cpu_s3c3410_name, . - cpu_s3c3410_name
-
-		.type	cpu_s3c44b0x_name, #object
-cpu_s3c44b0x_name:
-		.asciz	"Samsung-S3C44B0x"
-		.size	cpu_s3c44b0x_name, . - cpu_s3c44b0x_name
-
-		.type	cpu_s3c4510b, #object
-cpu_s3c4510b_name:
-		.asciz	"Samsung-S3C4510B"
-		.size	cpu_s3c4510b_name, . - cpu_s3c4510b_name
-
-		.type	cpu_s3c4530_name, #object
-cpu_s3c4530_name:
-		.asciz	"Samsung-S3C4530"
-		.size	cpu_s3c4530_name, . - cpu_s3c4530_name
-
-		.type	cpu_netarm_name, #object
-cpu_netarm_name:
-		.asciz	"NETARM"
-		.size	cpu_netarm_name, . - cpu_netarm_name
+		string	cpu_arch_name, "armv4t"
+		string	cpu_elf_name, "v4"
+		string	cpu_arm7tdmi_name, "ARM7TDMI"
+		string	cpu_triscenda7_name, "Triscend-A7x"
+		string	cpu_at91_name, "Atmel-AT91M40xxx"
+		string	cpu_s3c3410_name, "Samsung-S3C3410"
+		string	cpu_s3c44b0x_name, "Samsung-S3C44B0x"
+		string	cpu_s3c4510b_name, "Samsung-S3C4510B"
+		string	cpu_s3c4530_name, "Samsung-S3C4530"
+		string	cpu_netarm_name, "NETARM"
 
 		.align
 
 		.section ".proc.info.init", #alloc, #execinstr
 
-		.type	__arm7tdmi_proc_info, #object
-__arm7tdmi_proc_info:
-		.long	0x41007700
-		.long	0xfff8ff00
-		.long	0
-		.long	0
-		b	__arm7tdmi_setup
-		.long	cpu_arch_name
-		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_26BIT
-		.long	cpu_arm7tdmi_name
-		.long	arm7tdmi_processor_functions
-		.long	0
-		.long	0
-		.long	v4_cache_fns
-		.size	__arm7tdmi_proc_info, . - __arm7dmi_proc_info
-
-		.type	__triscenda7_proc_info, #object
-__triscenda7_proc_info:
-		.long	0x0001d2ff
-		.long	0x0001ffff
-		.long	0
-		.long	0
-		b	__arm7tdmi_setup
-		.long	cpu_arch_name
-		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
-		.long	cpu_triscenda7_name
-		.long	arm7tdmi_processor_functions
-		.long	0
-		.long	0
-		.long	v4_cache_fns
-		.size	__triscenda7_proc_info, . - __triscenda7_proc_info
-
-		.type	__at91_proc_info, #object
-__at91_proc_info:
-		.long	0x14000040
-		.long	0xfff000e0
-		.long	0
-		.long	0
-		b	__arm7tdmi_setup
-		.long	cpu_arch_name
-		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
-		.long	cpu_at91_name
-		.long	arm7tdmi_processor_functions
-		.long	0
-		.long	0
-		.long	v4_cache_fns
-		.size	__at91_proc_info, . - __at91_proc_info
-
-		.type	__s3c4510b_proc_info, #object
-__s3c4510b_proc_info:
-		.long	0x36365000
-		.long	0xfffff000
-		.long	0
-		.long	0
-		b	__arm7tdmi_setup
-		.long	cpu_arch_name
-		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
-		.long	cpu_s3c4510b_name
-		.long	arm7tdmi_processor_functions
-		.long	0
-		.long	0
-		.long	v4_cache_fns
-		.size	__s3c4510b_proc_info, . - __s3c4510b_proc_info
-
-		.type	__s3c4530_proc_info, #object
-__s3c4530_proc_info:
-		.long	0x4c000000
-		.long	0xfff000e0
-		.long	0
-		.long	0
-		b	__arm7tdmi_setup
-		.long	cpu_arch_name
-		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
-		.long	cpu_s3c4530_name
-		.long	arm7tdmi_processor_functions
-		.long	0
-		.long	0
-		.long	v4_cache_fns
-		.size	__s3c4530_proc_info, . - __s3c4530_proc_info
-
-		.type	__s3c3410_proc_info, #object
-__s3c3410_proc_info:
-		.long	0x34100000
-		.long	0xffff0000
-		.long	0
-		.long	0
-		b	__arm7tdmi_setup
-		.long	cpu_arch_name
-		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
-		.long	cpu_s3c3410_name
-		.long	arm7tdmi_processor_functions
-		.long	0
-		.long	0
-		.long	v4_cache_fns
-		.size	__s3c3410_proc_info, . - __s3c3410_proc_info
-
-		.type	__s3c44b0x_proc_info, #object
-__s3c44b0x_proc_info:
-		.long	0x44b00000
-		.long	0xffff0000
+.macro arm7tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
+	extra_hwcaps=0
+		.type	__\name\()_proc_info, #object
+__\name\()_proc_info:
+		.long	\cpu_val
+		.long	\cpu_mask
 		.long	0
 		.long	0
 		b	__arm7tdmi_setup
 		.long	cpu_arch_name
 		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
-		.long	cpu_s3c44b0x_name
+		.long	HWCAP_SWP | HWCAP_26BIT | ( \extra_hwcaps )
+		.long	\cpu_name
 		.long	arm7tdmi_processor_functions
 		.long	0
 		.long	0
 		.long	v4_cache_fns
-		.size	__s3c44b0x_proc_info, . - __s3c44b0x_proc_info
+		.size	__\name\()_proc_info, . - __\name\()_proc_info
+.endm
+
+		arm7tdmi_proc_info arm7tdmi, 0x41007700, 0xfff8ff00, \
+			cpu_arm7tdmi_name
+		arm7tdmi_proc_info triscenda7, 0x0001d2ff, 0x0001ffff, \
+			cpu_triscenda7_name, extra_hwcaps=HWCAP_THUMB
+		arm7tdmi_proc_info at91, 0x14000040, 0xfff000e0, \
+			cpu_at91_name, extra_hwcaps=HWCAP_THUMB
+		arm7tdmi_proc_info s3c4510b, 0x36365000, 0xfffff000, \
+			cpu_s3c4510b_name, extra_hwcaps=HWCAP_THUMB
+		arm7tdmi_proc_info s3c4530, 0x4c000000, 0xfff000e0, \
+			cpu_s3c4530_name, extra_hwcaps=HWCAP_THUMB
+		arm7tdmi_proc_info s3c3410, 0x34100000, 0xffff0000, \
+			cpu_s3c3410_name, extra_hwcaps=HWCAP_THUMB
+		arm7tdmi_proc_info s3c44b0x, 0x44b00000, 0xffff0000, \
+			cpu_s3c44b0x_name, extra_hwcaps=HWCAP_THUMB
-- 
1.7.4.1

[PATCH v3 18/40] Subject: ARM: mm: proc-arm920: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm920.S |   53 ++++++---------------------------------------
 1 files changed, 7 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index bf8a1d1..4d850ea 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -315,18 +315,8 @@ ENTRY(arm920_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(arm920_dma_unmap_area)
 
-ENTRY(arm920_cache_fns)
-	.long	arm920_flush_icache_all
-	.long	arm920_flush_kern_cache_all
-	.long	arm920_flush_user_cache_all
-	.long	arm920_flush_user_cache_range
-	.long	arm920_coherent_kern_range
-	.long	arm920_coherent_user_range
-	.long	arm920_flush_kern_dcache_area
-	.long	arm920_dma_map_area
-	.long	arm920_dma_unmap_area
-	.long	arm920_dma_flush_range
-
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions arm920, default=arm920
 #endif
 
 
@@ -450,43 +440,14 @@ arm920_crval:
 	crval	clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
 
 	__INITDATA
-
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm920_processor_functions, #object
-arm920_processor_functions:
-	.word	v4t_early_abort
-	.word	legacy_pabort
-	.word	cpu_arm920_proc_init
-	.word	cpu_arm920_proc_fin
-	.word	cpu_arm920_reset
-	.word   cpu_arm920_do_idle
-	.word	cpu_arm920_dcache_clean_area
-	.word	cpu_arm920_switch_mm
-	.word	cpu_arm920_set_pte_ext
-	.word	cpu_arm920_suspend_size
-	.word	cpu_arm920_do_suspend
-	.word	cpu_arm920_do_resume
-	.size	arm920_processor_functions, . - arm920_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv4t"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v4"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_arm920_name, #object
-cpu_arm920_name:
-	.asciz	"ARM920T"
-	.size	cpu_arm920_name, . - cpu_arm920_name
+	string	cpu_arch_name, "armv4t"
+	string	cpu_elf_name, "v4"
+	string	cpu_arm920_name, "ARM920T"
 
 	.align
 
-- 
1.7.4.1

[PATCH v3 19/40] Subject: ARM: mm: proc-arm922: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm922.S |   53 ++++++---------------------------------------
 1 files changed, 7 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 95ba1fc..41ae409 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -317,18 +317,8 @@ ENTRY(arm922_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(arm922_dma_unmap_area)
 
-ENTRY(arm922_cache_fns)
-	.long	arm922_flush_icache_all
-	.long	arm922_flush_kern_cache_all
-	.long	arm922_flush_user_cache_all
-	.long	arm922_flush_user_cache_range
-	.long	arm922_coherent_kern_range
-	.long	arm922_coherent_user_range
-	.long	arm922_flush_kern_dcache_area
-	.long	arm922_dma_map_area
-	.long	arm922_dma_unmap_area
-	.long	arm922_dma_flush_range
-
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions arm922, default=arm922
 #endif
 
 
@@ -420,43 +410,14 @@ arm922_crval:
 	crval	clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
 
 	__INITDATA
-
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm922_processor_functions, #object
-arm922_processor_functions:
-	.word	v4t_early_abort
-	.word	legacy_pabort
-	.word	cpu_arm922_proc_init
-	.word	cpu_arm922_proc_fin
-	.word	cpu_arm922_reset
-	.word   cpu_arm922_do_idle
-	.word	cpu_arm922_dcache_clean_area
-	.word	cpu_arm922_switch_mm
-	.word	cpu_arm922_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	arm922_processor_functions, . - arm922_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm922, dabort=v4t_early_abort, pabort=legacy_pabort
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv4t"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v4"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_arm922_name, #object
-cpu_arm922_name:
-	.asciz	"ARM922T"
-	.size	cpu_arm922_name, . - cpu_arm922_name
+	string	cpu_arch_name, "armv4t"
+	string	cpu_elf_name, "v4"
+	string	cpu_arm922_name, "ARM922T"
 
 	.align
 
-- 
1.7.4.1

[PATCH v3 20/40] Subject: ARM: mm: proc-arm925: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm925.S |   88 ++++++++------------------------------------
 1 files changed, 16 insertions(+), 72 deletions(-)

diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 541e477..8650aa3 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -372,17 +372,8 @@ ENTRY(arm925_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(arm925_dma_unmap_area)
 
-ENTRY(arm925_cache_fns)
-	.long	arm925_flush_icache_all
-	.long	arm925_flush_kern_cache_all
-	.long	arm925_flush_user_cache_all
-	.long	arm925_flush_user_cache_range
-	.long	arm925_coherent_kern_range
-	.long	arm925_coherent_user_range
-	.long	arm925_flush_kern_dcache_area
-	.long	arm925_dma_map_area
-	.long	arm925_dma_unmap_area
-	.long	arm925_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions arm925, default=arm925
 
 ENTRY(cpu_arm925_dcache_clean_area)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -487,52 +478,24 @@ arm925_crval:
 	crval	clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
 
 	__INITDATA
-
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm925_processor_functions, #object
-arm925_processor_functions:
-	.word	v4t_early_abort
-	.word	legacy_pabort
-	.word	cpu_arm925_proc_init
-	.word	cpu_arm925_proc_fin
-	.word	cpu_arm925_reset
-	.word   cpu_arm925_do_idle
-	.word	cpu_arm925_dcache_clean_area
-	.word	cpu_arm925_switch_mm
-	.word	cpu_arm925_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	arm925_processor_functions, . - arm925_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm925, dabort=v4t_early_abort, pabort=legacy_pabort
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv4t"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v4"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_arm925_name, #object
-cpu_arm925_name:
-	.asciz	"ARM925T"
-	.size	cpu_arm925_name, . - cpu_arm925_name
+	string	cpu_arch_name, "armv4t"
+	string	cpu_elf_name, "v4"
+	string	cpu_arm925_name, "ARM925T"
 
 	.align
 
 	.section ".proc.info.init", #alloc, #execinstr
 
-	.type	__arm925_proc_info,#object
-__arm925_proc_info:
-	.long	0x54029250
-	.long	0xfffffff0
+.macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
+	.type	__\name\()_proc_info,#object
+__\name\()_proc_info:
+	.long	\cpu_val
+	.long	\cpu_mask
 	.long   PMD_TYPE_SECT | \
 		PMD_BIT4 | \
 		PMD_SECT_AP_WRITE | \
@@ -550,27 +513,8 @@ __arm925_proc_info:
 	.long	v4wbi_tlb_fns
 	.long	v4wb_user_fns
 	.long	arm925_cache_fns
-	.size	__arm925_proc_info, . - __arm925_proc_info
+	.size	__\name\()_proc_info, . - __\name\()_proc_info
+.endm
 
-	.type	__arm915_proc_info,#object
-__arm915_proc_info:
-	.long	0x54029150
-	.long	0xfffffff0
-	.long   PMD_TYPE_SECT | \
-		PMD_BIT4 | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_BIT4 | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__arm925_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
-	.long	cpu_arm925_name
-	.long	arm925_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	v4wb_user_fns
-	.long	arm925_cache_fns
-	.size	__arm925_proc_info, . - __arm925_proc_info
+	arm925_proc_info arm925, 0x54029250, 0xfffffff0, cpu_arm925_name
+	arm925_proc_info arm915, 0x54029150, 0xfffffff0, cpu_arm925_name
-- 
1.7.4.1

[PATCH v3 21/40] Subject: ARM: mm: proc-arm926: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm926.S |   51 ++++++--------------------------------------
 1 files changed, 7 insertions(+), 44 deletions(-)

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 0ed85d9..78c2a0a 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -335,17 +335,8 @@ ENTRY(arm926_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(arm926_dma_unmap_area)
 
-ENTRY(arm926_cache_fns)
-	.long	arm926_flush_icache_all
-	.long	arm926_flush_kern_cache_all
-	.long	arm926_flush_user_cache_all
-	.long	arm926_flush_user_cache_range
-	.long	arm926_coherent_kern_range
-	.long	arm926_coherent_user_range
-	.long	arm926_flush_kern_dcache_area
-	.long	arm926_dma_map_area
-	.long	arm926_dma_unmap_area
-	.long	arm926_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions arm926, default=arm926
 
 ENTRY(cpu_arm926_dcache_clean_area)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -475,42 +466,14 @@ arm926_crval:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm926_processor_functions, #object
-arm926_processor_functions:
-	.word	v5tj_early_abort
-	.word	legacy_pabort
-	.word	cpu_arm926_proc_init
-	.word	cpu_arm926_proc_fin
-	.word	cpu_arm926_reset
-	.word	cpu_arm926_do_idle
-	.word	cpu_arm926_dcache_clean_area
-	.word	cpu_arm926_switch_mm
-	.word	cpu_arm926_set_pte_ext
-	.word	cpu_arm926_suspend_size
-	.word	cpu_arm926_do_suspend
-	.word	cpu_arm926_do_resume
-	.size	arm926_processor_functions, . - arm926_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5tej"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_arm926_name, #object
-cpu_arm926_name:
-	.asciz	"ARM926EJ-S"
-	.size	cpu_arm926_name, . - cpu_arm926_name
+	string	cpu_arch_name, "armv5tej"
+	string	cpu_elf_name, "v5"
+	string	cpu_arm926_name, "ARM926EJ-S"
 
 	.align
 
-- 
1.7.4.1

[PATCH v3 22/40] Subject: ARM: mm: proc-arm940: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm940.S |   51 ++++++--------------------------------------
 1 files changed, 7 insertions(+), 44 deletions(-)

diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 26aea3f..bd16721 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -264,17 +264,8 @@ ENTRY(arm940_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(arm940_dma_unmap_area)
 
-ENTRY(arm940_cache_fns)
-	.long	arm940_flush_icache_all
-	.long	arm940_flush_kern_cache_all
-	.long	arm940_flush_user_cache_all
-	.long	arm940_flush_user_cache_range
-	.long	arm940_coherent_kern_range
-	.long	arm940_coherent_user_range
-	.long	arm940_flush_kern_dcache_area
-	.long	arm940_dma_map_area
-	.long	arm940_dma_unmap_area
-	.long	arm940_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions arm940, default=arm940
 
 	__CPUINIT
 
@@ -348,42 +339,14 @@ __arm940_setup:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm940_processor_functions, #object
-ENTRY(arm940_processor_functions)
-	.word	nommu_early_abort
-	.word	legacy_pabort
-	.word	cpu_arm940_proc_init
-	.word	cpu_arm940_proc_fin
-	.word	cpu_arm940_reset
-	.word   cpu_arm940_do_idle
-	.word	cpu_arm940_dcache_clean_area
-	.word	cpu_arm940_switch_mm
-	.word	0		@ cpu_*_set_pte
-	.word	0
-	.word	0
-	.word	0
-	.size	arm940_processor_functions, . - arm940_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm940, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
 
 	.section ".rodata"
 
-.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv4t"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v4"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_arm940_name, #object
-cpu_arm940_name:
-	.ascii	"ARM940T"
-	.size	cpu_arm940_name, . - cpu_arm940_name
+	string	cpu_arch_name, "armv4t"
+	string	cpu_elf_name, "v4"
+	string	cpu_arm940_name, "ARM940T"
 
 	.align
 
-- 
1.7.4.1

[PATCH v3 23/40] Subject: ARM: mm: proc-arm946: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm946.S |   53 ++++++---------------------------------------
 1 files changed, 7 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 8063345..6e7e6a2 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -306,18 +306,8 @@ ENTRY(arm946_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(arm946_dma_unmap_area)
 
-ENTRY(arm946_cache_fns)
-	.long	arm946_flush_icache_all
-	.long	arm946_flush_kern_cache_all
-	.long	arm946_flush_user_cache_all
-	.long	arm946_flush_user_cache_range
-	.long	arm946_coherent_kern_range
-	.long	arm946_coherent_user_range
-	.long	arm946_flush_kern_dcache_area
-	.long	arm946_dma_map_area
-	.long	arm946_dma_unmap_area
-	.long	arm946_dma_flush_range
-
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions arm946, default=arm946
 
 ENTRY(cpu_arm946_dcache_clean_area)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -403,43 +393,14 @@ __arm946_setup:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	arm946_processor_functions, #object
-ENTRY(arm946_processor_functions)
-	.word	nommu_early_abort
-	.word	legacy_pabort
-	.word	cpu_arm946_proc_init
-	.word	cpu_arm946_proc_fin
-	.word	cpu_arm946_reset
-	.word   cpu_arm946_do_idle
-
-	.word	cpu_arm946_dcache_clean_area
-	.word	cpu_arm946_switch_mm
-	.word	0		@ cpu_*_set_pte
-	.word	0
-	.word	0
-	.word	0
-	.size	arm946_processor_functions, . - arm946_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions arm946, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5te"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5t"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_arm946_name, #object
-cpu_arm946_name:
-	.ascii	"ARM946E-S"
-	.size	cpu_arm946_name, . - cpu_arm946_name
+	string	cpu_arch_name, "armv5te"
+	string	cpu_elf_name, "v5t"
+	string	cpu_arm946_name, "ARM946E-S"
 
 	.align
 
-- 
1.7.4.1

[PATCH v3 24/40] Subject: ARM: mm: proc-arm9tdmi: Use the new processor struct macros

[Dave Martin]

This patch also fixes a .size directive typo, which was causing a
reference to a nonexistent symbol.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-arm9tdmi.S |   78 ++++++++++---------------------------------
 1 files changed, 18 insertions(+), 60 deletions(-)

diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 7b7ebd4..2120f9e 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -17,6 +17,8 @@
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
 
+#include "proc-macros.S"
+
 	.text
 /*
  * cpu_arm9tdmi_proc_init()
@@ -55,82 +57,38 @@ __arm9tdmi_setup:
 
 		__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-		.type	arm9tdmi_processor_functions, #object
-ENTRY(arm9tdmi_processor_functions)
-		.word	nommu_early_abort
-		.word	legacy_pabort
-		.word	cpu_arm9tdmi_proc_init
-		.word	cpu_arm9tdmi_proc_fin
-		.word	cpu_arm9tdmi_reset
-		.word	cpu_arm9tdmi_do_idle
-		.word	cpu_arm9tdmi_dcache_clean_area
-		.word	cpu_arm9tdmi_switch_mm
-		.word	0		@ cpu_*_set_pte
-		.word	0
-		.word	0
-		.word	0
-		.size	arm9tdmi_processor_functions, . - arm9tdmi_processor_functions
+		@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+		define_processor_functions arm9tdmi, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
 
 		.section ".rodata"
 
-		.type	cpu_arch_name, #object
-cpu_arch_name:
-		.asciz	"armv4t"
-		.size	cpu_arch_name, . - cpu_arch_name
-
-		.type	cpu_elf_name, #object
-cpu_elf_name:
-		.asciz	"v4"
-		.size	cpu_elf_name, . - cpu_elf_name
-
-		.type	cpu_arm9tdmi_name, #object
-cpu_arm9tdmi_name:
-		.asciz	"ARM9TDMI"
-		.size	cpu_arm9tdmi_name, . - cpu_arm9tdmi_name
-
-		.type	cpu_p2001_name, #object
-cpu_p2001_name:
-		.asciz	"P2001"
-		.size	cpu_p2001_name, . - cpu_p2001_name
+		string	cpu_arch_name, "armv4t"
+		string	cpu_elf_name, "v4"
+		string	cpu_arm9tdmi_name, "ARM9TDMI"
+		string	cpu_p2001_name, "P2001"
 
 		.align
 
 		.section ".proc.info.init", #alloc, #execinstr
 
-		.type	__arm9tdmi_proc_info, #object
-__arm9tdmi_proc_info:
-		.long	0x41009900
-		.long	0xfff8ff00
+.macro arm9tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
+		.type	__\name\()_proc_info, #object
+__\name\()_proc_info:
+		.long	\cpu_val
+		.long	\cpu_mask
 		.long	0
 		.long	0
 		b	__arm9tdmi_setup
 		.long	cpu_arch_name
 		.long	cpu_elf_name
 		.long	HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
-		.long	cpu_arm9tdmi_name
+		.long	\cpu_name
 		.long	arm9tdmi_processor_functions
 		.long	0
 		.long	0
 		.long	v4_cache_fns
-		.size	__arm9tdmi_proc_info, . - __arm9dmi_proc_info
+		.size	__\name\()_proc_info, . - __\name\()_proc_info
+.endm
 
-		.type	__p2001_proc_info, #object
-__p2001_proc_info:
-		.long	0x41029000
-		.long	0xffffffff
-		.long	0
-		.long	0
-		b	__arm9tdmi_setup
-		.long	cpu_arch_name
-		.long	cpu_elf_name
-		.long	HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
-		.long	cpu_p2001_name
-		.long	arm9tdmi_processor_functions
-		.long	0
-		.long	0
-		.long	v4_cache_fns
-		.size	__p2001_proc_info, . - __p2001_proc_info
+	arm9tdmi_proc_info arm9tdmi, 0x41009900, 0xfff8ff00, cpu_arm9tdmi_name
+	arm9tdmi_proc_info p2001, 0x41029000, 0xffffffff, cpu_p2001_name
-- 
1.7.4.1

[PATCH v3 25/40] Subject: ARM: mm: proc-fa526: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-fa526.S |   38 +++++---------------------------------
 1 files changed, 5 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index fc2a4ae..4c7a571 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -180,42 +180,14 @@ fa526_cr1_set:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	fa526_processor_functions, #object
-fa526_processor_functions:
-	.word	v4_early_abort
-	.word	legacy_pabort
-	.word	cpu_fa526_proc_init
-	.word	cpu_fa526_proc_fin
-	.word	cpu_fa526_reset
-	.word   cpu_fa526_do_idle
-	.word	cpu_fa526_dcache_clean_area
-	.word	cpu_fa526_switch_mm
-	.word	cpu_fa526_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	fa526_processor_functions, . - fa526_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv4"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v4"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_fa526_name, #object
-cpu_fa526_name:
-	.asciz	"FA526"
-	.size	cpu_fa526_name, . - cpu_fa526_name
+	string	cpu_arch_name, "armv4"
+	string	cpu_elf_name, "v4"
+	string	cpu_fa526_name, "FA526"
 
 	.align
 
-- 
1.7.4.1

[PATCH v3 26/40] Subject: ARM: mm: proc-feroceon: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-feroceon.S |  186 ++++++++-----------------------------------
 1 files changed, 33 insertions(+), 153 deletions(-)

diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index d3883ee..8b08e10 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -411,29 +411,12 @@ ENTRY(feroceon_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(feroceon_dma_unmap_area)
 
-ENTRY(feroceon_cache_fns)
-	.long	feroceon_flush_icache_all
-	.long	feroceon_flush_kern_cache_all
-	.long	feroceon_flush_user_cache_all
-	.long	feroceon_flush_user_cache_range
-	.long	feroceon_coherent_kern_range
-	.long	feroceon_coherent_user_range
-	.long	feroceon_flush_kern_dcache_area
-	.long	feroceon_dma_map_area
-	.long	feroceon_dma_unmap_area
-	.long	feroceon_dma_flush_range
-
-ENTRY(feroceon_range_cache_fns)
-	.long	feroceon_flush_icache_all
-	.long	feroceon_flush_kern_cache_all
-	.long	feroceon_flush_user_cache_all
-	.long	feroceon_flush_user_cache_range
-	.long	feroceon_coherent_kern_range
-	.long	feroceon_coherent_user_range
-	.long	feroceon_range_flush_kern_dcache_area
-	.long	feroceon_range_dma_map_area
-	.long	feroceon_dma_unmap_area
-	.long	feroceon_range_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions feroceon, default=feroceon
+	define_cache_functions feroceon_range, default=feroceon, \
+		flush_kern_dcache_area=feroceon_range_flush_kern_dcache_area, \
+		dma_map_area=feroceon_range_dma_map_area, \
+		dma_flush_range=feroceon_range_dma_flush_range
 
 	.align	5
 ENTRY(cpu_feroceon_dcache_clean_area)
@@ -539,93 +522,27 @@ feroceon_crval:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	feroceon_processor_functions, #object
-feroceon_processor_functions:
-	.word	v5t_early_abort
-	.word	legacy_pabort
-	.word	cpu_feroceon_proc_init
-	.word	cpu_feroceon_proc_fin
-	.word	cpu_feroceon_reset
-	.word	cpu_feroceon_do_idle
-	.word	cpu_feroceon_dcache_clean_area
-	.word	cpu_feroceon_switch_mm
-	.word	cpu_feroceon_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	feroceon_processor_functions, . - feroceon_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions feroceon, dabort=v5t_early_abort, pabort=legacy_pabort
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5te"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_feroceon_name, #object
-cpu_feroceon_name:
-	.asciz	"Feroceon"
-	.size	cpu_feroceon_name, . - cpu_feroceon_name
-
-	.type	cpu_88fr531_name, #object
-cpu_88fr531_name:
-	.asciz	"Feroceon 88FR531-vd"
-	.size	cpu_88fr531_name, . - cpu_88fr531_name
-
-	.type	cpu_88fr571_name, #object
-cpu_88fr571_name:
-	.asciz	"Feroceon 88FR571-vd"
-	.size	cpu_88fr571_name, . - cpu_88fr571_name
-
-	.type	cpu_88fr131_name, #object
-cpu_88fr131_name:
-	.asciz	"Feroceon 88FR131"
-	.size	cpu_88fr131_name, . - cpu_88fr131_name
+	string	cpu_arch_name, "armv5te"
+	string	cpu_elf_name, "v5"
+	string	cpu_feroceon_name, "Feroceon"
+	string	cpu_88fr531_name, "Feroceon 88FR531-vd"
+	string	cpu_88fr571_name, "Feroceon 88FR571-vd"
+	string	cpu_88fr131_name, "Feroceon 88FR131"
 
 	.align
 
 	.section ".proc.info.init", #alloc, #execinstr
 
-#ifdef CONFIG_CPU_FEROCEON_OLD_ID
-	.type	__feroceon_old_id_proc_info,#object
-__feroceon_old_id_proc_info:
-	.long	0x41009260
-	.long	0xff00fff0
-	.long	PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_BIT4 | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long	PMD_TYPE_SECT | \
-		PMD_BIT4 | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__feroceon_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_feroceon_name
-	.long	feroceon_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	feroceon_user_fns
-	.long	feroceon_cache_fns
-	.size	__feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
-#endif
-
-	.type	__88fr531_proc_info,#object
-__88fr531_proc_info:
-	.long	0x56055310
-	.long	0xfffffff0
+.macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req
+	.type	__\name\()_proc_info,#object
+__\name\()_proc_info:
+	.long	\cpu_val
+	.long	\cpu_mask
 	.long	PMD_TYPE_SECT | \
 		PMD_SECT_BUFFERABLE | \
 		PMD_SECT_CACHEABLE | \
@@ -640,59 +557,22 @@ __88fr531_proc_info:
 	.long	cpu_arch_name
 	.long	cpu_elf_name
 	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_88fr531_name
+	.long	\cpu_name
 	.long	feroceon_processor_functions
 	.long	v4wbi_tlb_fns
 	.long	feroceon_user_fns
-	.long	feroceon_cache_fns
-	.size	__88fr531_proc_info, . - __88fr531_proc_info
+	.long	\cache
+	 .size	__\name\()_proc_info, . - __\name\()_proc_info
+.endm
 
-	.type	__88fr571_proc_info,#object
-__88fr571_proc_info:
-	.long	0x56155710
-	.long	0xfffffff0
-	.long	PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_BIT4 | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long	PMD_TYPE_SECT | \
-		PMD_BIT4 | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__feroceon_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_88fr571_name
-	.long	feroceon_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	feroceon_user_fns
-	.long	feroceon_range_cache_fns
-	.size	__88fr571_proc_info, . - __88fr571_proc_info
+#ifdef CONFIG_CPU_FEROCEON_OLD_ID
+	feroceon_proc_info feroceon_old_id, 0x41009260, 0xff00fff0, \
+		cpu_name=cpu_feroceon_name, cache=feroceon_cache_fns
+#endif
 
-	.type	__88fr131_proc_info,#object
-__88fr131_proc_info:
-	.long	0x56251310
-	.long	0xfffffff0
-	.long	PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_BIT4 | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long	PMD_TYPE_SECT | \
-		PMD_BIT4 | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__feroceon_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_88fr131_name
-	.long	feroceon_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	feroceon_user_fns
-	.long	feroceon_range_cache_fns
-	.size	__88fr131_proc_info, . - __88fr131_proc_info
+	feroceon_proc_info 88fr531, 0x56055310, 0xfffffff0, cpu_88fr531_name, \
+		cache=feroceon_cache_fns
+	feroceon_proc_info 88fr571, 0x56155710, 0xfffffff0, cpu_88fr571_name, \
+		cache=feroceon_range_cache_fns
+	feroceon_proc_info 88fr131, 0x56251310, 0xfffffff0, cpu_88fr131_name, \
+		cache=feroceon_range_cache_fns
-- 
1.7.4.1

[PATCH v3 26/40] Subject: ARM: mm: proc-feroceon: Use the new processor struct macros

[Russell King - ARM Linux]

On Thu, Jun 23, 2011 at 06:50:34PM +0100, Dave Martin wrote:
> -ENTRY(feroceon_cache_fns)
> -	.long	feroceon_flush_icache_all
> -	.long	feroceon_flush_kern_cache_all
> -	.long	feroceon_flush_user_cache_all
> -	.long	feroceon_flush_user_cache_range
> -	.long	feroceon_coherent_kern_range
> -	.long	feroceon_coherent_user_range
> -	.long	feroceon_flush_kern_dcache_area
> -	.long	feroceon_dma_map_area
> -	.long	feroceon_dma_unmap_area
> -	.long	feroceon_dma_flush_range
> -
> -ENTRY(feroceon_range_cache_fns)
> -	.long	feroceon_flush_icache_all
> -	.long	feroceon_flush_kern_cache_all
> -	.long	feroceon_flush_user_cache_all
> -	.long	feroceon_flush_user_cache_range
> -	.long	feroceon_coherent_kern_range
> -	.long	feroceon_coherent_user_range
> -	.long	feroceon_range_flush_kern_dcache_area
> -	.long	feroceon_range_dma_map_area
> -	.long	feroceon_dma_unmap_area
> -	.long	feroceon_range_dma_flush_range
> +	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
> +	define_cache_functions feroceon, default=feroceon
> +	define_cache_functions feroceon_range, default=feroceon, \
> +		flush_kern_dcache_area=feroceon_range_flush_kern_dcache_area, \
> +		dma_map_area=feroceon_range_dma_map_area, \
> +		dma_flush_range=feroceon_range_dma_flush_range

That's unique enough that it can be left as-is I think, rather than
having to add that special knowledge into the macro.

A solution to this would be to alias (using .equ) the feroceon_xxx
functions to feroceon_range_xxx, and then use the standard
define_cache_functions macro, which would be more in keeping with
the way these things are supposed to work.

[PATCH v3 26/40] Subject: ARM: mm: proc-feroceon: Use the new processor struct macros

[Dave Martin]

On Thu, Jul 07, 2011 at 10:14:36AM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 23, 2011 at 06:50:34PM +0100, Dave Martin wrote:
> > -ENTRY(feroceon_cache_fns)
> > -	.long	feroceon_flush_icache_all
> > -	.long	feroceon_flush_kern_cache_all
> > -	.long	feroceon_flush_user_cache_all
> > -	.long	feroceon_flush_user_cache_range
> > -	.long	feroceon_coherent_kern_range
> > -	.long	feroceon_coherent_user_range
> > -	.long	feroceon_flush_kern_dcache_area
> > -	.long	feroceon_dma_map_area
> > -	.long	feroceon_dma_unmap_area
> > -	.long	feroceon_dma_flush_range
> > -
> > -ENTRY(feroceon_range_cache_fns)
> > -	.long	feroceon_flush_icache_all
> > -	.long	feroceon_flush_kern_cache_all
> > -	.long	feroceon_flush_user_cache_all
> > -	.long	feroceon_flush_user_cache_range
> > -	.long	feroceon_coherent_kern_range
> > -	.long	feroceon_coherent_user_range
> > -	.long	feroceon_range_flush_kern_dcache_area
> > -	.long	feroceon_range_dma_map_area
> > -	.long	feroceon_dma_unmap_area
> > -	.long	feroceon_range_dma_flush_range
> > +	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
> > +	define_cache_functions feroceon, default=feroceon
> > +	define_cache_functions feroceon_range, default=feroceon, \
> > +		flush_kern_dcache_area=feroceon_range_flush_kern_dcache_area, \
> > +		dma_map_area=feroceon_range_dma_map_area, \
> > +		dma_flush_range=feroceon_range_dma_flush_range
> 
> That's unique enough that it can be left as-is I think, rather than
> having to add that special knowledge into the macro.
> 
> A solution to this would be to alias (using .equ) the feroceon_xxx
> functions to feroceon_range_xxx, and then use the standard
> define_cache_functions macro, which would be more in keeping with
> the way these things are supposed to work.

Agreed.  That sounds sensible.

I'll await your views on

[PATCH v3 01/40] Subject: ARM: mm: proc-macros Add generic
	proc/cache/tlb struct definition macros

before addressing this, since the issues involved overlap.

Cheers
---Dave

[PATCH v3 27/40] Subject: ARM: mm: proc-mohawk: Use the new processor struct macros

[Dave Martin]

NOTE: Even with this patch, this CPU is still broken due the lack
of a suitable flush_icache_all function.

Without this patch, the entries in the cache functions struct are
off by one, which will result in the wrong functions being called
at run-time.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-mohawk.S |   50 ++++++--------------------------------------
 1 files changed, 7 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 9d4f2ae..e1fad39 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -288,16 +288,8 @@ ENTRY(mohawk_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(mohawk_dma_unmap_area)
 
-ENTRY(mohawk_cache_fns)
-	.long	mohawk_flush_kern_cache_all
-	.long	mohawk_flush_user_cache_all
-	.long	mohawk_flush_user_cache_range
-	.long	mohawk_coherent_kern_range
-	.long	mohawk_coherent_user_range
-	.long	mohawk_flush_kern_dcache_area
-	.long	mohawk_dma_map_area
-	.long	mohawk_dma_unmap_area
-	.long	mohawk_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions mohawk, default=mohawk
 
 ENTRY(cpu_mohawk_dcache_clean_area)
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -373,42 +365,14 @@ mohawk_crval:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-	.type	mohawk_processor_functions, #object
-mohawk_processor_functions:
-	.word	v5t_early_abort
-	.word	legacy_pabort
-	.word	cpu_mohawk_proc_init
-	.word	cpu_mohawk_proc_fin
-	.word	cpu_mohawk_reset
-	.word	cpu_mohawk_do_idle
-	.word	cpu_mohawk_dcache_clean_area
-	.word	cpu_mohawk_switch_mm
-	.word	cpu_mohawk_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	mohawk_processor_functions, . - mohawk_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions mohawk, dabort=v5t_early_abort, pabort=legacy_pabort
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5te"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_mohawk_name, #object
-cpu_mohawk_name:
-	.asciz	"Marvell 88SV331x"
-	.size	cpu_mohawk_name, . - cpu_mohawk_name
+	string	cpu_arch_name, "armv5te"
+	string	cpu_elf_name, "v5"
+	string	cpu_mohawk_name, "Marvell 88SV331x"
 
 	.align
 
-- 
1.7.4.1

[PATCH v3 27/40] Subject: ARM: mm: proc-mohawk: Use the new processor struct macros

[Russell King - ARM Linux]

On Thu, Jun 23, 2011 at 06:50:35PM +0100, Dave Martin wrote:
> NOTE: Even with this patch, this CPU is still broken due the lack
> of a suitable flush_icache_all function.

I assume that it now gets a build error rather than silently failing
at runtime?  If so, that's actually an improvement.

[PATCH v3 27/40] Subject: ARM: mm: proc-mohawk: Use the new processor struct macros

[Dave Martin]

On Thu, Jul 07, 2011 at 10:11:14AM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 23, 2011 at 06:50:35PM +0100, Dave Martin wrote:
> > NOTE: Even with this patch, this CPU is still broken due the lack
> > of a suitable flush_icache_all function.
> 
> I assume that it now gets a build error rather than silently failing
> at runtime?  If so, that's actually an improvement.

The answer should be yes.

In the branch referenced by Will's pull request, I've integrated a contribution
from Nico which supplies the missing flush function anyway ... so the combined
patch ought to fix that problem anyway:

+/*
+ *     flush_icache_all()
+ *
+ *     Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(mohawk_flush_icache_all)
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+       mov     pc, lr
+ENDPROC(mohawk_flush_icache_all)

Cheers
---Dave

[PATCH v3 28/40] Subject: ARM: mm: proc-sa110: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-sa110.S |   39 +++++----------------------------------
 1 files changed, 5 insertions(+), 34 deletions(-)

diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 46f09ed..d50ada2 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -187,43 +187,14 @@ sa110_crval:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-
-	.type	sa110_processor_functions, #object
-ENTRY(sa110_processor_functions)
-	.word	v4_early_abort
-	.word	legacy_pabort
-	.word	cpu_sa110_proc_init
-	.word	cpu_sa110_proc_fin
-	.word	cpu_sa110_reset
-	.word	cpu_sa110_do_idle
-	.word	cpu_sa110_dcache_clean_area
-	.word	cpu_sa110_switch_mm
-	.word	cpu_sa110_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	sa110_processor_functions, . - sa110_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions sa110, dabort=v4_early_abort, pabort=legacy_pabort
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv4"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v4"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_sa110_name, #object
-cpu_sa110_name:
-	.asciz	"StrongARM-110"
-	.size	cpu_sa110_name, . - cpu_sa110_name
+	string	cpu_arch_name, "armv4"
+	string	cpu_elf_name, "v4"
+	string	cpu_sa110_name, "StrongARM-110"
 
 	.align
 
-- 
1.7.4.1

[PATCH v3 29/40] Subject: ARM: mm: proc-sa1100: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-sa1100.S |   84 +++++++++-----------------------------------
 1 files changed, 17 insertions(+), 67 deletions(-)

diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 184a9c9..c7e08ca 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -236,59 +236,28 @@ sa1100_crval:
 	__INITDATA
 
 /*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-
-/*
  * SA1100 and SA1110 share the same function calls
  */
-	.type	sa1100_processor_functions, #object
-ENTRY(sa1100_processor_functions)
-	.word	v4_early_abort
-	.word	legacy_pabort
-	.word	cpu_sa1100_proc_init
-	.word	cpu_sa1100_proc_fin
-	.word	cpu_sa1100_reset
-	.word	cpu_sa1100_do_idle
-	.word	cpu_sa1100_dcache_clean_area
-	.word	cpu_sa1100_switch_mm
-	.word	cpu_sa1100_set_pte_ext
-	.word	cpu_sa1100_suspend_size
-	.word	cpu_sa1100_do_suspend
-	.word	cpu_sa1100_do_resume
-	.size	sa1100_processor_functions, . - sa1100_processor_functions
-
-	.section ".rodata"
-
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv4"
-	.size	cpu_arch_name, . - cpu_arch_name
 
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v4"
-	.size	cpu_elf_name, . - cpu_elf_name
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions sa1100, dabort=v4_early_abort, pabort=legacy_pabort, suspend=1
 
-	.type	cpu_sa1100_name, #object
-cpu_sa1100_name:
-	.asciz	"StrongARM-1100"
-	.size	cpu_sa1100_name, . - cpu_sa1100_name
+	.section ".rodata"
 
-	.type	cpu_sa1110_name, #object
-cpu_sa1110_name:
-	.asciz	"StrongARM-1110"
-	.size	cpu_sa1110_name, . - cpu_sa1110_name
+	string	cpu_arch_name, "armv4"
+	string	cpu_elf_name, "v4"
+	string	cpu_sa1100_name, "StrongARM-1100"
+	string	cpu_sa1110_name, "StrongARM-1110"
 
 	.align
 
 	.section ".proc.info.init", #alloc, #execinstr
 
-	.type	__sa1100_proc_info,#object
-__sa1100_proc_info:
-	.long	0x4401a110
-	.long	0xfffffff0
+.macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
+	.type	__\name\()_proc_info,#object
+__\name\()_proc_info:
+	.long	\cpu_val
+	.long	\cpu_mask
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_BUFFERABLE | \
 		PMD_SECT_CACHEABLE | \
@@ -301,32 +270,13 @@ __sa1100_proc_info:
 	.long	cpu_arch_name
 	.long	cpu_elf_name
 	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
-	.long	cpu_sa1100_name
+	.long	\cpu_name
 	.long	sa1100_processor_functions
 	.long	v4wb_tlb_fns
 	.long	v4_mc_user_fns
 	.long	v4wb_cache_fns
-	.size	__sa1100_proc_info, . - __sa1100_proc_info
+	.size	__\name\()_proc_info, . - __\name\()_proc_info
+.endm
 
-	.type	__sa1110_proc_info,#object
-__sa1110_proc_info:
-	.long	0x6901b110
-	.long	0xfffffff0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__sa1100_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
-	.long	cpu_sa1110_name
-	.long	sa1100_processor_functions
-	.long	v4wb_tlb_fns
-	.long	v4_mc_user_fns
-	.long	v4wb_cache_fns
-	.size	__sa1110_proc_info, . - __sa1110_proc_info
+	sa1100_proc_info sa1100, 0x4401a110, 0xfffffff0, cpu_sa1100_name
+	sa1100_proc_info sa1110, 0x6901b110, 0xfffffff0, cpu_sa1110_name
-- 
1.7.4.1

[PATCH v3 30/40] Subject: ARM: mm: proc-v6: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-v6.S |   34 +++++-----------------------------
 1 files changed, 5 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 1d2b845..5ec1543 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -169,11 +169,7 @@ cpu_resume_l1_flags:
 #define cpu_v6_do_resume 0
 #endif
 
-
-	.type	cpu_v6_name, #object
-cpu_v6_name:
-	.asciz	"ARMv6-compatible processor"
-	.size	cpu_v6_name, . - cpu_v6_name
+	string	cpu_v6_name, "ARMv6-compatible processor"
 
 	.align
 
@@ -239,33 +235,13 @@ v6_crval:
 
 	__INITDATA
 
-	.type	v6_processor_functions, #object
-ENTRY(v6_processor_functions)
-	.word	v6_early_abort
-	.word	v6_pabort
-	.word	cpu_v6_proc_init
-	.word	cpu_v6_proc_fin
-	.word	cpu_v6_reset
-	.word	cpu_v6_do_idle
-	.word	cpu_v6_dcache_clean_area
-	.word	cpu_v6_switch_mm
-	.word	cpu_v6_set_pte_ext
-	.word	cpu_v6_suspend_size
-	.word	cpu_v6_do_suspend
-	.word	cpu_v6_do_resume
-	.size	v6_processor_functions, . - v6_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv6"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v6"
-	.size	cpu_elf_name, . - cpu_elf_name
+	string	cpu_arch_name, "armv6"
+	string	cpu_elf_name, "v6"
 	.align
 
 	.section ".proc.info.init", #alloc, #execinstr
-- 
1.7.4.1

[PATCH v3 31/40] Subject: ARM: mm: proc-v7: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-v7.S |   31 +++++--------------------------
 1 files changed, 5 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b3b566e..929892b 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -171,8 +171,7 @@ ENTRY(cpu_v7_set_pte_ext)
 	mov	pc, lr
 ENDPROC(cpu_v7_set_pte_ext)
 
-cpu_v7_name:
-	.ascii	"ARMv7 Processor"
+	string	cpu_v7_name, "ARMv7 Processor"
 	.align
 
 	/*
@@ -405,33 +404,13 @@ __v7_setup_stack:
 
 	__INITDATA
 
-	.type	v7_processor_functions, #object
-ENTRY(v7_processor_functions)
-	.word	v7_early_abort
-	.word	v7_pabort
-	.word	cpu_v7_proc_init
-	.word	cpu_v7_proc_fin
-	.word	cpu_v7_reset
-	.word	cpu_v7_do_idle
-	.word	cpu_v7_dcache_clean_area
-	.word	cpu_v7_switch_mm
-	.word	cpu_v7_set_pte_ext
-	.word	0
-	.word	0
-	.word	0
-	.size	v7_processor_functions, . - v7_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv7"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v7"
-	.size	cpu_elf_name, . - cpu_elf_name
+	string	cpu_arch_name, "armv7"
+	string	cpu_elf_name, "v7"
 	.align
 
 	.section ".proc.info.init", #alloc, #execinstr
-- 
1.7.4.1

[PATCH v3 32/40] Subject: ARM: mm: proc-xsc3: Use new generic struct definition macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-xsc3.S |   90 +++++++++--------------------------------------
 1 files changed, 17 insertions(+), 73 deletions(-)

diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 5962136..87c99d1 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -335,17 +335,8 @@ ENTRY(xsc3_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(xsc3_dma_unmap_area)
 
-ENTRY(xsc3_cache_fns)
-	.long	xsc3_flush_icache_all
-	.long	xsc3_flush_kern_cache_all
-	.long	xsc3_flush_user_cache_all
-	.long	xsc3_flush_user_cache_range
-	.long	xsc3_coherent_kern_range
-	.long	xsc3_coherent_user_range
-	.long	xsc3_flush_kern_dcache_area
-	.long	xsc3_dma_map_area
-	.long	xsc3_dma_unmap_area
-	.long	xsc3_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions xsc3, default=xsc3
 
 ENTRY(cpu_xsc3_dcache_clean_area)
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
@@ -503,52 +494,24 @@ xsc3_crval:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-
-	.type	xsc3_processor_functions, #object
-ENTRY(xsc3_processor_functions)
-	.word	v5t_early_abort
-	.word	legacy_pabort
-	.word	cpu_xsc3_proc_init
-	.word	cpu_xsc3_proc_fin
-	.word	cpu_xsc3_reset
-	.word	cpu_xsc3_do_idle
-	.word	cpu_xsc3_dcache_clean_area
-	.word	cpu_xsc3_switch_mm
-	.word	cpu_xsc3_set_pte_ext
-	.word	cpu_xsc3_suspend_size
-	.word	cpu_xsc3_do_suspend
-	.word	cpu_xsc3_do_resume
-	.size	xsc3_processor_functions, . - xsc3_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions xsc3, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5te"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_xsc3_name, #object
-cpu_xsc3_name:
-	.asciz	"XScale-V3 based processor"
-	.size	cpu_xsc3_name, . - cpu_xsc3_name
+	string	cpu_arch_name, "armv5te"
+	string	cpu_elf_name, "v5"
+	string	cpu_xsc3_name, "XScale-V3 based processor"
 
 	.align
 
 	.section ".proc.info.init", #alloc, #execinstr
 
-	.type	__xsc3_proc_info,#object
-__xsc3_proc_info:
-	.long	0x69056000
-	.long	0xffffe000
+.macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req
+	.type	__\name\()_proc_info,#object
+__\name\()_proc_info:
+	.long	\cpu_val
+	.long	\cpu_mask
 	.long	PMD_TYPE_SECT | \
 		PMD_SECT_BUFFERABLE | \
 		PMD_SECT_CACHEABLE | \
@@ -566,29 +529,10 @@ __xsc3_proc_info:
 	.long	v4wbi_tlb_fns
 	.long	xsc3_mc_user_fns
 	.long	xsc3_cache_fns
-	.size	__xsc3_proc_info, . - __xsc3_proc_info
+	.size	__\name\()_proc_info, . - __\name\()_proc_info
+.endm
 
-/* Note: PXA935 changed its implementor ID from Intel to Marvell */
+	xsc3_proc_info xsc3, 0x69056000, 0xffffe000
 
-	.type	__xsc3_pxa935_proc_info,#object
-__xsc3_pxa935_proc_info:
-	.long	0x56056000
-	.long	0xffffe000
-	.long	PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long	PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__xsc3_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_xsc3_name
-	.long	xsc3_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xsc3_mc_user_fns
-	.long	xsc3_cache_fns
-	.size	__xsc3_pxa935_proc_info, . - __xsc3_pxa935_proc_info
+/* Note: PXA935 changed its implementor ID from Intel to Marvell */
+	xsc3_proc_info xsc3_pxa935, 0x56056000, 0xffffe000
-- 
1.7.4.1

[PATCH v3 33/40] Subject: ARM: mm: proc-xscale: Use new generic struct definition macros

[Dave Martin]

This patch assumes that xscale_icache_flush_all is the right thing
to put in the icache_flush_all entry of
xscale_80200_A0_A1_cache_fns.

Without this patch, xscale_80200_A0_A1 is missing the
icache_flush_all entry, which would result in the wrong functions
being called at run-time.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/proc-xscale.S |  484 +++++---------------------------------------
 1 files changed, 55 insertions(+), 429 deletions(-)

diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 42af976..ad73079 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -407,17 +407,8 @@ ENTRY(xscale_dma_unmap_area)
 	mov	pc, lr
 ENDPROC(xscale_dma_unmap_area)
 
-ENTRY(xscale_cache_fns)
-	.long	xscale_flush_icache_all
-	.long	xscale_flush_kern_cache_all
-	.long	xscale_flush_user_cache_all
-	.long	xscale_flush_user_cache_range
-	.long	xscale_coherent_kern_range
-	.long	xscale_coherent_user_range
-	.long	xscale_flush_kern_dcache_area
-	.long	xscale_dma_map_area
-	.long	xscale_dma_unmap_area
-	.long	xscale_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions xscale, default=xscale
 
 /*
  * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
@@ -432,16 +423,9 @@ ENTRY(xscale_cache_fns)
  * revision January 22, 2003, available at:
  *     http://www.intel.com/design/iio/specupdt/273415.htm
  */
-ENTRY(xscale_80200_A0_A1_cache_fns)
-	.long	xscale_flush_kern_cache_all
-	.long	xscale_flush_user_cache_all
-	.long	xscale_flush_user_cache_range
-	.long	xscale_coherent_kern_range
-	.long	xscale_coherent_user_range
-	.long	xscale_flush_kern_dcache_area
-	.long	xscale_dma_a0_map_area
-	.long	xscale_dma_unmap_area
-	.long	xscale_dma_flush_range
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions xscale_80200_A0_A1, default=xscale, \
+		dma_map_area=xscale_dma_a0_map_area
 
 ENTRY(cpu_xscale_dcache_clean_area)
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -587,432 +571,74 @@ xscale_crval:
 
 	__INITDATA
 
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *	     come through these
- */
-
-	.type	xscale_processor_functions, #object
-ENTRY(xscale_processor_functions)
-	.word	v5t_early_abort
-	.word	legacy_pabort
-	.word	cpu_xscale_proc_init
-	.word	cpu_xscale_proc_fin
-	.word	cpu_xscale_reset
-	.word	cpu_xscale_do_idle
-	.word	cpu_xscale_dcache_clean_area
-	.word	cpu_xscale_switch_mm
-	.word	cpu_xscale_set_pte_ext
-	.word	cpu_xscale_suspend_size
-	.word	cpu_xscale_do_suspend
-	.word	cpu_xscale_do_resume
-	.size	xscale_processor_functions, . - xscale_processor_functions
+	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+	define_processor_functions xscale, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1
 
 	.section ".rodata"
 
-	.type	cpu_arch_name, #object
-cpu_arch_name:
-	.asciz	"armv5te"
-	.size	cpu_arch_name, . - cpu_arch_name
-
-	.type	cpu_elf_name, #object
-cpu_elf_name:
-	.asciz	"v5"
-	.size	cpu_elf_name, . - cpu_elf_name
-
-	.type	cpu_80200_A0_A1_name, #object
-cpu_80200_A0_A1_name:
-	.asciz	"XScale-80200 A0/A1"
-	.size	cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
-
-	.type	cpu_80200_name, #object
-cpu_80200_name:
-	.asciz	"XScale-80200"
-	.size	cpu_80200_name, . - cpu_80200_name
-
-	.type	cpu_80219_name, #object
-cpu_80219_name:
-	.asciz	"XScale-80219"
-	.size	cpu_80219_name, . - cpu_80219_name
-
-	.type	cpu_8032x_name, #object
-cpu_8032x_name:
-	.asciz	"XScale-IOP8032x Family"
-	.size	cpu_8032x_name, . - cpu_8032x_name
-
-	.type	cpu_8033x_name, #object
-cpu_8033x_name:
-	.asciz	"XScale-IOP8033x Family"
-	.size	cpu_8033x_name, . - cpu_8033x_name
-
-	.type	cpu_pxa250_name, #object
-cpu_pxa250_name:
-	.asciz	"XScale-PXA250"
-	.size	cpu_pxa250_name, . - cpu_pxa250_name
-
-	.type	cpu_pxa210_name, #object
-cpu_pxa210_name:
-	.asciz	"XScale-PXA210"
-	.size	cpu_pxa210_name, . - cpu_pxa210_name
-
-	.type	cpu_ixp42x_name, #object
-cpu_ixp42x_name:
-	.asciz	"XScale-IXP42x Family"
-	.size	cpu_ixp42x_name, . - cpu_ixp42x_name
-
-	.type	cpu_ixp43x_name, #object
-cpu_ixp43x_name:
-	.asciz	"XScale-IXP43x Family"
-	.size	cpu_ixp43x_name, . - cpu_ixp43x_name
-
-	.type	cpu_ixp46x_name, #object
-cpu_ixp46x_name:
-	.asciz	"XScale-IXP46x Family"
-	.size	cpu_ixp46x_name, . - cpu_ixp46x_name
-
-	.type	cpu_ixp2400_name, #object
-cpu_ixp2400_name:
-	.asciz	"XScale-IXP2400"
-	.size	cpu_ixp2400_name, . - cpu_ixp2400_name
-
-	.type	cpu_ixp2800_name, #object
-cpu_ixp2800_name:
-	.asciz	"XScale-IXP2800"
-	.size	cpu_ixp2800_name, . - cpu_ixp2800_name
-
-	.type	cpu_pxa255_name, #object
-cpu_pxa255_name:
-	.asciz	"XScale-PXA255"
-	.size	cpu_pxa255_name, . - cpu_pxa255_name
-
-	.type	cpu_pxa270_name, #object
-cpu_pxa270_name:
-	.asciz	"XScale-PXA270"
-	.size	cpu_pxa270_name, . - cpu_pxa270_name
+	string	cpu_arch_name, "armv5te"
+	string	cpu_elf_name, "v5"
+
+	string	cpu_80200_A0_A1_name, "XScale-80200 A0/A1"
+	string	cpu_80200_name, "XScale-80200"
+	string	cpu_80219_name, "XScale-80219"
+	string	cpu_8032x_name, "XScale-IOP8032x Family"
+	string	cpu_8033x_name, "XScale-IOP8033x Family"
+	string	cpu_pxa250_name, "XScale-PXA250"
+	string	cpu_pxa210_name, "XScale-PXA210"
+	string	cpu_ixp42x_name, "XScale-IXP42x Family"
+	string	cpu_ixp43x_name, "XScale-IXP43x Family"
+	string	cpu_ixp46x_name, "XScale-IXP46x Family"
+	string	cpu_ixp2400_name, "XScale-IXP2400"
+	string	cpu_ixp2800_name, "XScale-IXP2800"
+	string	cpu_pxa255_name, "XScale-PXA255"
+	string	cpu_pxa270_name, "XScale-PXA270"
 
 	.align
 
 	.section ".proc.info.init", #alloc, #execinstr
 
-	.type	__80200_A0_A1_proc_info,#object
-__80200_A0_A1_proc_info:
-	.long	0x69052000
-	.long	0xfffffffe
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__xscale_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_80200_name
-	.long	xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_80200_A0_A1_cache_fns
-	.size	__80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
-
-	.type	__80200_proc_info,#object
-__80200_proc_info:
-	.long	0x69052000
-	.long	0xfffffff0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__xscale_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_80200_name
-	.long	xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size	__80200_proc_info, . - __80200_proc_info
-
-	.type	__80219_proc_info,#object
-__80219_proc_info:
-	.long	0x69052e20
-	.long	0xffffffe0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__xscale_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_80219_name
-	.long	xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size	__80219_proc_info, . - __80219_proc_info
-
-	.type	__8032x_proc_info,#object
-__8032x_proc_info:
-	.long	0x69052420
-	.long	0xfffff7e0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__xscale_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_8032x_name
-	.long	xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size	__8032x_proc_info, . - __8032x_proc_info
-
-	.type	__8033x_proc_info,#object
-__8033x_proc_info:
-	.long	0x69054010
-	.long	0xfffffd30
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__xscale_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_8033x_name
-	.long	xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size	__8033x_proc_info, . - __8033x_proc_info
-
-	.type	__pxa250_proc_info,#object
-__pxa250_proc_info:
-	.long	0x69052100
-	.long	0xfffff7f0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__xscale_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_pxa250_name
-	.long	xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size	__pxa250_proc_info, . - __pxa250_proc_info
-
-	.type	__pxa210_proc_info,#object
-__pxa210_proc_info:
-	.long	0x69052120
-	.long	0xfffff3f0
-	.long   PMD_TYPE_SECT | \
+.macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
+	.type	__\name\()_proc_info,#object
+__\name\()_proc_info:
+	.long	\cpu_val
+	.long	\cpu_mask
+	.long	PMD_TYPE_SECT | \
 		PMD_SECT_BUFFERABLE | \
 		PMD_SECT_CACHEABLE | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
+	.long	PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ
 	b	__xscale_setup
 	.long	cpu_arch_name
 	.long	cpu_elf_name
 	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_pxa210_name
+	.long	\cpu_name
 	.long	xscale_processor_functions
 	.long	v4wbi_tlb_fns
 	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size	__pxa210_proc_info, . - __pxa210_proc_info
-
-	.type	__ixp2400_proc_info, #object
-__ixp2400_proc_info:
-	.long   0x69054190
-	.long   0xfffffff0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b       __xscale_setup
-	.long   cpu_arch_name
-	.long   cpu_elf_name
-	.long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long   cpu_ixp2400_name
-	.long   xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size   __ixp2400_proc_info, . - __ixp2400_proc_info                
-
-	.type	__ixp2800_proc_info, #object
-__ixp2800_proc_info:
-	.long   0x690541a0
-	.long   0xfffffff0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b       __xscale_setup
-	.long   cpu_arch_name
-	.long   cpu_elf_name
-	.long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long   cpu_ixp2800_name
-	.long   xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size   __ixp2800_proc_info, . - __ixp2800_proc_info                
-
-	.type	__ixp42x_proc_info, #object
-__ixp42x_proc_info:
-	.long   0x690541c0
-	.long   0xffffffc0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b       __xscale_setup
-	.long   cpu_arch_name
-	.long   cpu_elf_name
-	.long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long   cpu_ixp42x_name
-	.long   xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size   __ixp42x_proc_info, . - __ixp42x_proc_info                
-
-	.type   __ixp43x_proc_info, #object
-__ixp43x_proc_info:
-	.long   0x69054040
-	.long   0xfffffff0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b       __xscale_setup
-	.long   cpu_arch_name
-	.long   cpu_elf_name
-	.long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long   cpu_ixp43x_name
-	.long   xscale_processor_functions
-	.long   v4wbi_tlb_fns
-	.long   xscale_mc_user_fns
-	.long   xscale_cache_fns
-	.size   __ixp43x_proc_info, . - __ixp43x_proc_info
-
-	.type	__ixp46x_proc_info, #object
-__ixp46x_proc_info:
-	.long   0x69054200
-	.long   0xffffff00
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b       __xscale_setup
-	.long   cpu_arch_name
-	.long   cpu_elf_name
-	.long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long   cpu_ixp46x_name
-	.long   xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size   __ixp46x_proc_info, . - __ixp46x_proc_info
-
-	.type	__pxa255_proc_info,#object
-__pxa255_proc_info:
-	.long	0x69052d00
-	.long	0xfffffff0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__xscale_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_pxa255_name
-	.long	xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size	__pxa255_proc_info, . - __pxa255_proc_info
-
-	.type	__pxa270_proc_info,#object
-__pxa270_proc_info:
-	.long	0x69054110
-	.long	0xfffffff0
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_BUFFERABLE | \
-		PMD_SECT_CACHEABLE | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	b	__xscale_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
-	.long	cpu_pxa270_name
-	.long	xscale_processor_functions
-	.long	v4wbi_tlb_fns
-	.long	xscale_mc_user_fns
-	.long	xscale_cache_fns
-	.size	__pxa270_proc_info, . - __pxa270_proc_info
-
+	.ifb \cache
+		.long	xscale_cache_fns
+	.else
+		.long	\cache
+	.endif
+	.size	__\name\()_proc_info, . - __\name\()_proc_info
+.endm
+
+	xscale_proc_info 80200_A0_A1, 0x69052000, 0xfffffffe, cpu_80200_name, \
+		cache=xscale_80200_A0_A1_cache_fns
+	xscale_proc_info 80200, 0x69052000, 0xfffffff0, cpu_80200_name
+	xscale_proc_info 80219, 0x69052e20, 0xffffffe0, cpu_80219_name
+	xscale_proc_info 8032x, 0x69052420, 0xfffff7e0, cpu_8032x_name
+	xscale_proc_info 8033x, 0x69054010, 0xfffffd30, cpu_8033x_name
+	xscale_proc_info pxa250, 0x69052100, 0xfffff7f0, cpu_pxa250_name
+	xscale_proc_info pxa210, 0x69052120, 0xfffff3f0, cpu_pxa210_name
+	xscale_proc_info ixp2400, 0x69054190, 0xfffffff0, cpu_ixp2400_name
+	xscale_proc_info ixp2800, 0x690541a0, 0xfffffff0, cpu_ixp2800_name
+	xscale_proc_info ixp42x, 0x690541c0, 0xffffffc0, cpu_ixp42x_name
+	xscale_proc_info ixp43x, 0x69054040, 0xfffffff0, cpu_ixp43x_name
+	xscale_proc_info ixp46x, 0x69054200, 0xffffff00, cpu_ixp46x_name
+	xscale_proc_info pxa255, 0x69052d00, 0xfffffff0, cpu_pxa255_name
+	xscale_proc_info pxa270, 0x69054110, 0xfffffff0, cpu_pxa270_name
-- 
1.7.4.1

[PATCH v3 34/40] Subject: ARM: mm: tlb-fa: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/tlb-fa.S |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/tlb-fa.S b/arch/arm/mm/tlb-fa.S
index 9694f1f..7a2e56c 100644
--- a/arch/arm/mm/tlb-fa.S
+++ b/arch/arm/mm/tlb-fa.S
@@ -67,9 +67,5 @@ ENTRY(fa_flush_kern_tlb_range)
 
 	__INITDATA
 
-	.type	fa_tlb_fns, #object
-ENTRY(fa_tlb_fns)
-	.long	fa_flush_user_tlb_range
-	.long	fa_flush_kern_tlb_range
-	.long	fa_tlb_flags
-	.size	fa_tlb_fns, . - fa_tlb_fns
+	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
+	define_tlb_functions fa, fa_tlb_flags
-- 
1.7.4.1

[PATCH v3 35/40] Subject: ARM: mm: tlb-v3: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/tlb-v3.S |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/tlb-v3.S b/arch/arm/mm/tlb-v3.S
index c10786e..d253995 100644
--- a/arch/arm/mm/tlb-v3.S
+++ b/arch/arm/mm/tlb-v3.S
@@ -44,9 +44,5 @@ ENTRY(v3_flush_kern_tlb_range)
 
 	__INITDATA
 
-	.type	v3_tlb_fns, #object
-ENTRY(v3_tlb_fns)
-	.long	v3_flush_user_tlb_range
-	.long	v3_flush_kern_tlb_range
-	.long	v3_tlb_flags
-	.size	v3_tlb_fns, . - v3_tlb_fns
+	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
+	define_tlb_functions v3, v3_tlb_flags
-- 
1.7.4.1

[PATCH v3 36/40] Subject: ARM: mm: tlb-v4: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/tlb-v4.S |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/tlb-v4.S b/arch/arm/mm/tlb-v4.S
index d6c9445..17a025a 100644
--- a/arch/arm/mm/tlb-v4.S
+++ b/arch/arm/mm/tlb-v4.S
@@ -57,9 +57,5 @@ ENTRY(v4_flush_user_tlb_range)
 
 	__INITDATA
 
-	.type	v4_tlb_fns, #object
-ENTRY(v4_tlb_fns)
-	.long	v4_flush_user_tlb_range
-	.long	v4_flush_kern_tlb_range
-	.long	v4_tlb_flags
-	.size	v4_tlb_fns, . - v4_tlb_fns
+	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
+	define_tlb_functions v4, v4_tlb_flags
-- 
1.7.4.1

[PATCH v3 37/40] Subject: ARM: mm: tlb-v4wb: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/tlb-v4wb.S |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/tlb-v4wb.S b/arch/arm/mm/tlb-v4wb.S
index cb829ca..c04598f 100644
--- a/arch/arm/mm/tlb-v4wb.S
+++ b/arch/arm/mm/tlb-v4wb.S
@@ -69,9 +69,5 @@ ENTRY(v4wb_flush_kern_tlb_range)
 
 	__INITDATA
 
-	.type	v4wb_tlb_fns, #object
-ENTRY(v4wb_tlb_fns)
-	.long	v4wb_flush_user_tlb_range
-	.long	v4wb_flush_kern_tlb_range
-	.long	v4wb_tlb_flags
-	.size	v4wb_tlb_fns, . - v4wb_tlb_fns
+	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
+	define_tlb_functions v4wb, v4wb_tlb_flags
-- 
1.7.4.1

[PATCH v3 38/40] Subject: ARM: mm: tlb-v4wbi: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/tlb-v4wbi.S |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/tlb-v4wbi.S b/arch/arm/mm/tlb-v4wbi.S
index 60cfc4a..1f6062b 100644
--- a/arch/arm/mm/tlb-v4wbi.S
+++ b/arch/arm/mm/tlb-v4wbi.S
@@ -60,9 +60,5 @@ ENTRY(v4wbi_flush_kern_tlb_range)
 
 	__INITDATA
 
-	.type	v4wbi_tlb_fns, #object
-ENTRY(v4wbi_tlb_fns)
-	.long	v4wbi_flush_user_tlb_range
-	.long	v4wbi_flush_kern_tlb_range
-	.long	v4wbi_tlb_flags
-	.size	v4wbi_tlb_fns, . - v4wbi_tlb_fns
+	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
+	define_tlb_functions v4wbi, v4wbi_tlb_flags
-- 
1.7.4.1

[PATCH v3 39/40] Subject: ARM: mm: tlb-v6: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/tlb-v6.S |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index 73d7d89..a685944 100644
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -90,9 +90,5 @@ ENTRY(v6wbi_flush_kern_tlb_range)
 
 	__INIT
 
-	.type	v6wbi_tlb_fns, #object
-ENTRY(v6wbi_tlb_fns)
-	.long	v6wbi_flush_user_tlb_range
-	.long	v6wbi_flush_kern_tlb_range
-	.long	v6wbi_tlb_flags
-	.size	v6wbi_tlb_fns, . - v6wbi_tlb_fns
+	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
+	define_tlb_functions v6wbi, v6wbi_tlb_flags
-- 
1.7.4.1

[PATCH v3 40/40] Subject: ARM: mm: tlb-v7: Use the new processor struct macros

[Dave Martin]

Signed-off-by: Dave Martin <dave.martin@linaro.org>
---
 arch/arm/mm/tlb-v7.S |    9 ++-------
 1 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index 53cd5b4..ebd4290 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -85,10 +85,5 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 
 	__INIT
 
-	.type	v7wbi_tlb_fns, #object
-ENTRY(v7wbi_tlb_fns)
-	.long	v7wbi_flush_user_tlb_range
-	.long	v7wbi_flush_kern_tlb_range
-	ALT_SMP(.long	v7wbi_tlb_flags_smp)
-	ALT_UP(.long	v7wbi_tlb_flags_up)
-	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
+	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
+	define_tlb_functions v7wbi, v7wbi_tlb_flags_up, flags_smp=v7wbi_tlb_flags_smp
-- 
1.7.4.1

[PATCH v3 00/40] ARM: mm: Add generic macros for declaring various CPU structs

[Nicolas Pitre]

On Thu, 23 Jun 2011, Dave Martin wrote:

> General notes:
> 
>   - This patch supersedes Peter Chubb's patch for the typo in
>     proc-arm7tdmi.S (see
> http://lists.arm.linux.org.uk/lurker/message/20110530.235513.4e1a0d16.en.html),
> which I believe hasn't been merged.  If it has merged or is
> pending, I can easily rebase on top of it.

See commit 9a819d8ac8 in mainline (v3.0-rc2).

>   - This series introduces a few lines slightly longer than 80
>     characters.  I don't think that splitting these lines will
>     do a lot to help readability, but this can be done if
>     people prefer.

Please don't.

> 4       proc-mohawk: missing mohawk_flush_icache_all now
>         referenced and needs to be defined to un-break this file
>         ** needs review **

mohawk_flush_icache_all:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mov	pc, lr

The "mov r0, #0" is probably unnecessary, but this is a common pattern.

> 5       proc-xscale: missing flush_icache_all funtion in
>         xscale_80200_A0_A1_cache_fns assumed to be the same as for
>         xscale_cache_fns **needs review**

ACK.

> Dave Martin (40):
>   Subject: ARM: mm: prop-macros Add generic proc/cache/tlb struct
>     definition macros

Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>

>   Subject: ARM: assembler.h: Add string declaration macro

Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>

>   Subject: ARM: mm: cache-fa: Use the new processor struct macros
>   Subject: ARM: mm: cache-v3: Use the new processor struct macros
>   Subject: ARM: mm: cache-v4: Use the new processor struct macros
> [...]

Something is wrong in your Git setup.  You have a spurious "Subject: " 
prefix everywhere.

>   Subject: ARM: mm: proc-feroceon: Use the new processor struct macros

Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>

>  40 files changed, 452 insertions(+), 1968 deletions(-)

Nice work!


Nicolas

[PATCH v3 00/40] ARM: mm: Add generic macros for declaring various CPU structs

[Dave Martin]

On Thu, Jun 23, 2011 at 07:44:44PM -0400, Nicolas Pitre wrote:
> On Thu, 23 Jun 2011, Dave Martin wrote:
> 
> > General notes:
> > 
> >   - This patch supersedes Peter Chubb's patch for the typo in
> >     proc-arm7tdmi.S (see
> > http://lists.arm.linux.org.uk/lurker/message/20110530.235513.4e1a0d16.en.html),
> > which I believe hasn't been merged.  If it has merged or is
> > pending, I can easily rebase on top of it.
> 
> See commit 9a819d8ac8 in mainline (v3.0-rc2).

Hmmm, I don't see this in -rc3, but it is in -rc4.  I'll rebase.

> 
> >   - This series introduces a few lines slightly longer than 80
> >     characters.  I don't think that splitting these lines will
> >     do a lot to help readability, but this can be done if
> >     people prefer.
> 
> Please don't.

You mean "don't split", right?  (Not "don't introduce"?)

The most heinous cases are already split in any case.

> 
> > 4       proc-mohawk: missing mohawk_flush_icache_all now
> >         referenced and needs to be defined to un-break this file
> >         ** needs review **
> 
> mohawk_flush_icache_all:
> 	mov	r0, #0
> 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
> 	mov	pc, lr
> 
> The "mov r0, #0" is probably unnecessary, but this is a common pattern.

Thanks, merged locally.

OK if I add your S-o-B to that patch?

> 
> > 5       proc-xscale: missing flush_icache_all funtion in
> >         xscale_80200_A0_A1_cache_fns assumed to be the same as for
> >         xscale_cache_fns **needs review**
> 
> ACK.

Thanks for checking that.  It lookes like the same icache_flush_all
should be appropriate for this case, but I thought it best to check.

> 
> > Dave Martin (40):
> >   Subject: ARM: mm: prop-macros Add generic proc/cache/tlb struct
> >     definition macros
> 
> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
> 
> >   Subject: ARM: assembler.h: Add string declaration macro
> 
> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>

Thanks for those.

> 
> >   Subject: ARM: mm: cache-fa: Use the new processor struct macros
> >   Subject: ARM: mm: cache-v3: Use the new processor struct macros
> >   Subject: ARM: mm: cache-v4: Use the new processor struct macros
> > [...]
> 
> Something is wrong in your Git setup.  You have a spurious "Subject: " 
> prefix everywhere.
> 
> >   Subject: ARM: mm: proc-feroceon: Use the new processor struct macros

Hmmm, I had some scripts sqashing this down from a local 106-patch series.
I guess my logic for pasting subject lines into the merged patches went
wrong somewhere.  I was pretty much a zombie by that stage...

Fixed locally now, but to cut down on spam I won't report immediately.

> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
> 
> >  40 files changed, 452 insertions(+), 1968 deletions(-)
> 
> Nice work!

Thanks for the review
---Dave

[PATCH v3 00/40] ARM: mm: Add generic macros for declaring various CPU structs

[Nicolas Pitre]

On Fri, 24 Jun 2011, Dave Martin wrote:

> On Thu, Jun 23, 2011 at 07:44:44PM -0400, Nicolas Pitre wrote:
> > On Thu, 23 Jun 2011, Dave Martin wrote:
> > 
> > >   - This series introduces a few lines slightly longer than 80
> > >     characters.  I don't think that splitting these lines will
> > >     do a lot to help readability, but this can be done if
> > >     people prefer.
> > 
> > Please don't.
> 
> You mean "don't split", right?  (Not "don't introduce"?)

Don't split if there is no obvious readability gain.  Human judgement is 
necessary here which can't be substituted by checkpatch.pl.

> > mohawk_flush_icache_all:
> > 	mov	r0, #0
> > 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
> > 	mov	pc, lr
> > 
> > The "mov r0, #0" is probably unnecessary, but this is a common pattern.
> 
> Thanks, merged locally.
> 
> OK if I add your S-o-B to that patch?

Sure.

> > >   Subject: ARM: mm: cache-fa: Use the new processor struct macros
> > >   Subject: ARM: mm: cache-v3: Use the new processor struct macros
> > >   Subject: ARM: mm: cache-v4: Use the new processor struct macros
> > > [...]
> > 
> > Something is wrong in your Git setup.  You have a spurious "Subject: " 
> > prefix everywhere.
> > 
> > >   Subject: ARM: mm: proc-feroceon: Use the new processor struct macros
> 
> Hmmm, I had some scripts sqashing this down from a local 106-patch series.
> I guess my logic for pasting subject lines into the merged patches went
> wrong somewhere.  I was pretty much a zombie by that stage...

:-)

Alternatively, using 'git rebase -i' and its squash and or fold commands 
(which can be abbreviated to the first letter) is pretty handy.  Might 
save you the time to write the script in the first place.


Nicolas

[PATCH v3 00/40] ARM: mm: Add generic macros for declaring various CPU structs

[Dave Martin]

On Fri, Jun 24, 2011 at 09:32:27AM -0400, Nicolas Pitre wrote:

[...]

> Don't split if there is no obvious readability gain.  Human judgement is 
> necessary here which can't be substituted by checkpatch.pl.

That's what I thought; just wanted to check I'd understood correctly.

> 
> > > mohawk_flush_icache_all:
> > > 	mov	r0, #0
> > > 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
> > > 	mov	pc, lr
> > > 
> > > The "mov r0, #0" is probably unnecessary, but this is a common pattern.
> > 
> > Thanks, merged locally.
> > 
> > OK if I add your S-o-B to that patch?

Done.  Thanks for the code.

[...]

> Alternatively, using 'git rebase -i' and its squash and or fold commands 
> (which can be abbreviated to the first letter) is pretty handy.  Might 
> save you the time to write the script in the first place.

I have just been "educated" on this point by someone else too -- autosquash
would have suited my purposes exactly in this case ... I'll definitely
do that next time.  Always good to learn something new :)


The above fixes have been applied and pushed to the branch referenced
below.

This should get merged via Will's tree for the next merge window,
providing that Russell is happy and nobody else objects.

Cheers
---Dave

The changes since commit 56299378726d5f2ba8d3c8cbbd13cb280ba45e4f:

  Linux 3.0-rc4 (2011-06-20 20:25:46 -0700)

are available in the git repository at:
  git://git.linaro.org/people/dmart/linux-2.6-arm.git arm/proc-macros

[PATCH v3 00/40] ARM: mm: Add generic macros for declaring various CPU structs

[Dave Martin]

Hi all,

I'd like to see these patches merged at the next merge window, if 
possible.

Now that we're at -rc5, Will Deacon offered to merge these patches via
his tree.

If anyone has any outstanding comments or objections on these patches,
please speak up now.

Once again, if anyone has an opportunity to test on their CPU and config,
it would be appreciated.

Thanks
---Dave

On Thu, Jun 23, 2011 at 06:50:08PM +0100, Dave Martin wrote:
> This series adds macros for declaring some CPU-related structured
> defined in assembler, and ports the various processors, cache and
> tlb implementations to use the macros.
> 
> Where multiple proc_info structures are defined by a single source
> file, the common elements are collapsed out of these by defining
> and invoking an additional local macro for this purpose.
> 
> A primary goal for this series is to introduce no API or binary
> changes except for fixing the few obvious bugs which became apparent
> when working on the series.
> 
> NOTE: There is an overlap between this series and Will/Pawel's patches
> to include Cortex-A5 support (see
> http://lists.arm.linux.org.uk/lurker/message/20110617.081930.2ed0934d.en.html).
> Will has agreed to merge with my series in his tree so that it can all
> be pulled from there, providing that my series has been accepted by
> the community.
> 
> 
> Anyone with an interest in any of the arch/arm/mm/{proc,cache,tlb}-*.S
> files is invited to comment and/or test.
> 
> In particular, I'd like review from anyone interested in the mohawk or
> xscale processor families, since this series causes non-trivial
> "fixes" in both of these files.  (xscale may be fixed by this series;
> mohawk is only partially fixed and still won't work unless a bit of
> extra work is done to define a suitable flush_icache_all function.
> 
> Detailed notes follow.
> 
> Cheers
> ---Dave
> 
> 
> 
> General notes:
> 
>   - This patch supersedes Peter Chubb's patch for the typo in
>     proc-arm7tdmi.S (see
> http://lists.arm.linux.org.uk/lurker/message/20110530.235513.4e1a0d16.en.html),
> which I believe hasn't been merged.  If it has merged or is
> pending, I can easily rebase on top of it.
> 
>   - *_processor_functions structures are not referenced outside
>     the proc-*.S in which they are defined and could all be
>     demoted to local scope.  To minimise breakage risk, I've left
>     these global for now.
> 
>   - Some cache_fns structures are not referenced outside the file
>     in which they are defined and could be local.  To simplify
>     the macro definition, these are currently all made global:
>     this should be harmless.
> 
>   - Placement of the structures in sections appears somewhat
>     inconsistent at present.  Possibly, everything should move
>     to __CPUINITRODATA.  Currently, the data is mostly spread
>     between __INIT, __TEXT and __INITDATA.  To avoid unintended
>     breakage, this series does not automatically switch sections
>     in the macros, leaving the preexisting section assignments
>     completely unchanged for now.
> 
>   - This series introduces a few lines slightly longer than 80
>     characters.  I don't think that splitting these lines will
>     do a lot to help readability, but this can be done if
>     people prefer.
> 
> Except as described below, I have confirmed that there is no change
> in the objects which get built from any of these files, by diffing
> disassembly and symbol tables, and by comparing binary section
> dumps.  (Debug info sections do generally change, but this is
> expected since they naturally depend on the exact characteristics
> of the source code.  They don't end up in the kernel image.)
> 
> Under these criteria, the cache-*.S and tlb-*.S files are exactly
> equivalent to the unpatched versions.
> 
> proc-*.S files change in the following ways: (mostly minor)
> 
>         proc-arm1020    a.cp. ..
>         proc-arm1020e   a.cp. ..
>         proc-arm1022    a.cp. ..
>         proc-arm1022    a.cp. ..
>         proc-arm6_7     ..... ..
>         proc-arm720     ..... ..
>         proc-arm740     a.... Z.
>         proc-arm7tdmi   .n..u Z. 1
>         proc-arm920     a.cp. ..
>         proc-arm922     a.cp. ..
>         proc-arm925     a.cp. .. 2
>         proc-arm926     a.cp. ..
>         proc-arm940     ..c.. Z.
>         proc-arm946     ..c.. Z.
>         proc-arm9tdmi   ....u ..
>         proc-fa526      a..p. ..
>         proc-feroceon   a.cp. ..
>         proc-mohawk     a.c.. .X 34
>         proc-sa110      ..... ..
>         proc-sa1100     ..... ..
>         proc-v6         ..... ..
>         proc-v7         .n... ..
>         proc-xsc3       ..c.. ..
>         proc-xscale     ..c.. .X 5
> 
> Legend:
> 
> a       section alignment of .proc.info.init and/or .init.data increased
>         from 1 to 4
> 
> n	one or more name string symbols promoted to STT_OBJECT
> c       one or mote cache_fns symbols structured promoted to STT_OBJECT
> p       one or more processor_functions symbols promoted to global scope
> 
> u       undefined symbol no longer referenced by .size
>         directive (typo fix)
> 
> Z       missing string terminator added to one of more name
>         strings.  In principle, the missing terminator could lead
>         to overruns.  In practice, the effect appears to get hidden
>         by .align directives; but it's safer to add them anyway.
> 
> X       missing flush_icache_all entry inserted at the start of
>         one or more cache_fns structures.  The extra field was
>         created in:
> 
>             commit 81d11955 (ARM: 6405/1: Handle
>             __flush_icache_all for CONFIG_SMP_ON_UP),
> 
>         breaking various proc-*.S.  Some were fixed by subsequent
>         patches, e.g.
> 
>             commit c8c90860 (ARM: 6466/1: implement
>             flush_icache_all for the rest of the CPUs).
> 
>         A few proc-*.S files appear to have been missed.
> 
> Processor-specific notes:
> 
> 1       proc-arm7tdmi: spurious undefined symbol
>         cpu_s3c4510b (caused by misspelled .type directive)
>         eliminated
> 
> 2       proc-arm925: size of __arm915_proc_info and
>         __arm925_proc_info symbols changed (typo'd duplicate .size
>         directive in original)
> 
> 3       proc-mohawk: mohawk_processor_functions became
>         STT_OBJECT (missing .type directive in original)
> 
> 4       proc-mohawk: missing mohawk_flush_icache_all now
>         referenced and needs to be defined to un-break this file
>         ** needs review **
> 
> 5       proc-xscale: missing flush_icache_all funtion in
>         xscale_80200_A0_A1_cache_fns assumed to be the same as for
>         xscale_cache_fns **needs review**
> 
> ---
> ------------------------------------------------------------------------
> 
> Dave Martin (40):
>   Subject: ARM: mm: prop-macros Add generic proc/cache/tlb struct
>     definition macros
>   Subject: ARM: assembler.h: Add string declaration macro
>   Subject: ARM: mm: cache-fa: Use the new processor struct macros
>   Subject: ARM: mm: cache-v3: Use the new processor struct macros
>   Subject: ARM: mm: cache-v4: Use the new processor struct macros
>   Subject: ARM: mm: cache-v4wb: Use the new processor struct macros
>   Subject: ARM: mm: cache-v4wt: Use the new processor struct macros
>   Subject: ARM: mm: cache-v6: Use the new processor struct macros
>   Subject: ARM: mm: cache-v7: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm1020: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm1020e: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm1022: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm1026: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm6_7: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm720: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm740: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm7tdmi: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm920: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm922: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm925: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm926: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm940: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm946: Use the new processor struct macros
>   Subject: ARM: mm: proc-arm9tdmi: Use the new processor struct macros
>   Subject: ARM: mm: proc-fa526: Use the new processor struct macros
>   Subject: ARM: mm: proc-feroceon: Use the new processor struct macros
>   Subject: ARM: mm: proc-mohawk: Use the new processor struct macros
>   Subject: ARM: mm: proc-sa110: Use the new processor struct macros
>   Subject: ARM: mm: proc-sa1100: Use the new processor struct macros
>   Subject: ARM: mm: proc-v6: Use the new processor struct macros
>   Subject: ARM: mm: proc-v7: Use the new processor struct macros
>   Subject: ARM: mm: proc-xsc3: Use new generic struct definition macros
>   Subject: ARM: mm: proc-xscale: Use new generic struct definition
>     macros
>   Subject: ARM: mm: tlb-fa: Use the new processor struct macros
>   Subject: ARM: mm: tlb-v3: Use the new processor struct macros
>   Subject: ARM: mm: tlb-v4: Use the new processor struct macros
>   Subject: ARM: mm: tlb-v4wb: Use the new processor struct macros
>   Subject: ARM: mm: tlb-v4wbi: Use the new processor struct macros
>   Subject: ARM: mm: tlb-v6: Use the new processor struct macros
>   Subject: ARM: mm: tlb-v7: Use the new processor struct macros
> 
>  arch/arm/include/asm/assembler.h |    8 +
>  arch/arm/mm/cache-fa.S           |   15 +-
>  arch/arm/mm/cache-v3.S           |   15 +-
>  arch/arm/mm/cache-v4.S           |   15 +-
>  arch/arm/mm/cache-v4wb.S         |   15 +-
>  arch/arm/mm/cache-v4wt.S         |   15 +-
>  arch/arm/mm/cache-v6.S           |   15 +-
>  arch/arm/mm/cache-v7.S           |   15 +-
>  arch/arm/mm/proc-arm1020.S       |   45 +---
>  arch/arm/mm/proc-arm1020e.S      |   52 +----
>  arch/arm/mm/proc-arm1022.S       |   52 +----
>  arch/arm/mm/proc-arm1026.S       |   53 +----
>  arch/arm/mm/proc-arm6_7.S        |  166 +++-----------
>  arch/arm/mm/proc-arm720.S        |   85 ++------
>  arch/arm/mm/proc-arm740.S        |   42 +---
>  arch/arm/mm/proc-arm7tdmi.S      |  216 +++--------------
>  arch/arm/mm/proc-arm920.S        |   53 +----
>  arch/arm/mm/proc-arm922.S        |   53 +----
>  arch/arm/mm/proc-arm925.S        |   88 ++------
>  arch/arm/mm/proc-arm926.S        |   51 +----
>  arch/arm/mm/proc-arm940.S        |   51 +----
>  arch/arm/mm/proc-arm946.S        |   53 +----
>  arch/arm/mm/proc-arm9tdmi.S      |   78 ++-----
>  arch/arm/mm/proc-fa526.S         |   38 +---
>  arch/arm/mm/proc-feroceon.S      |  186 +++------------
>  arch/arm/mm/proc-macros.S        |   76 ++++++
>  arch/arm/mm/proc-mohawk.S        |   50 +----
>  arch/arm/mm/proc-sa110.S         |   39 +---
>  arch/arm/mm/proc-sa1100.S        |   84 ++------
>  arch/arm/mm/proc-v6.S            |   34 +---
>  arch/arm/mm/proc-v7.S            |   31 +--
>  arch/arm/mm/proc-xsc3.S          |   90 ++------
>  arch/arm/mm/proc-xscale.S        |  484 +++++---------------------------------
>  arch/arm/mm/tlb-fa.S             |    8 +-
>  arch/arm/mm/tlb-v3.S             |    8 +-
>  arch/arm/mm/tlb-v4.S             |    8 +-
>  arch/arm/mm/tlb-v4wb.S           |    8 +-
>  arch/arm/mm/tlb-v4wbi.S          |    8 +-
>  arch/arm/mm/tlb-v6.S             |    8 +-
>  arch/arm/mm/tlb-v7.S             |    9 +-
>  40 files changed, 452 insertions(+), 1968 deletions(-)
> 
> -- 
> 1.7.4.1
> 

[PATCH v3 00/40] ARM: mm: Add generic macros for declaring various CPU structs

[Will Deacon]

Hi Dave,

On Thu, Jun 23, 2011 at 06:50:08PM +0100, Dave Martin wrote:
> This series adds macros for declaring some CPU-related structured
> defined in assembler, and ports the various processors, cache and
> tlb implementations to use the macros.
> 
> Where multiple proc_info structures are defined by a single source
> file, the common elements are collapsed out of these by defining
> and invoking an additional local macro for this purpose.
> 
> A primary goal for this series is to introduce no API or binary
> changes except for fixing the few obvious bugs which became apparent
> when working on the series.
> 
> NOTE: There is an overlap between this series and Will/Pawel's patches
> to include Cortex-A5 support (see
> http://lists.arm.linux.org.uk/lurker/message/20110617.081930.2ed0934d.en.html).
> Will has agreed to merge with my series in his tree so that it can all
> be pulled from there, providing that my series has been accepted by
> the community.

It looks like this has settled down now so I'll pull your arm/proc-macros
branch from git://git.linaro.org/people/dmart/linux-2.6-arm.git into my
tree and rebase the A5/A15 stuff on top of it.

Will