From: santosh.shilimkar@ti.com (Santosh Shilimkar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 20/25] OMAP4: PM: Add L2X0 cache lowpower support
Date: Sun, 4 Sep 2011 19:24:21 +0530 [thread overview]
Message-ID: <1315144466-9395-21-git-send-email-santosh.shilimkar@ti.com> (raw)
In-Reply-To: <1315144466-9395-1-git-send-email-santosh.shilimkar@ti.com>
When MPUSS hits off-mode e, L2 cache is lost. This patch adds L2X0
necessary maintenance operations and context restoration in the
low power code.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
arch/arm/mach-omap2/include/mach/omap-secure.h | 5 +
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 38 +++++++++-
arch/arm/mach-omap2/omap4-sar-layout.h | 4 +
arch/arm/mach-omap2/sleep44xx.S | 96 ++++++++++++++++++++++++
4 files changed, 142 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/include/mach/omap-secure.h
index 0062d49..6e929c5 100644
--- a/arch/arm/mach-omap2/include/mach/omap-secure.h
+++ b/arch/arm/mach-omap2/include/mach/omap-secure.h
@@ -37,8 +37,13 @@
/* Secure Monitor mode APIs */
#define OMAP4_MON_SCU_PWR_INDEX 0x108
+#define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100
+#define OMAP4_MON_L2X0_CTRL_INDEX 0x102
+#define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109
+#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
/* Secure PPA(Primary Protected Application) APIs */
+#define OMAP4_PPA_L2_POR_INDEX 0x23
#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
#ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 9f632fe..aea6deb 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -49,6 +49,7 @@
#include <asm/system.h>
#include <asm/pgalloc.h>
#include <asm/suspend.h>
+#include <asm/hardware/cache-l2x0.h>
#include <plat/omap44xx.h>
#include <mach/omap4-common.h>
@@ -63,10 +64,12 @@ struct omap4_cpu_pm_info {
struct powerdomain *pwrdm;
void __iomem *scu_sar_addr;
void __iomem *wkup_sar_addr;
+ void __iomem *l2x0_sar_addr;
};
static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
static struct powerdomain *mpuss_pd;
+static void __iomem *sar_base;
/*
* Program the wakeup routine address for the CPU0 and CPU1
@@ -135,6 +138,33 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
}
+/*
+ * Store the CPU cluster state for L2X0 low power operations.
+ */
+static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
+{
+ struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+
+ __raw_writel(save_state, pm_info->l2x0_sar_addr);
+}
+
+/*
+ * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
+ * in every restore MPUSS OFF path.
+ */
+static void save_l2x0_context(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+ u32 val;
+ void __iomem *l2x0_base = omap4_get_l2cache_base();
+
+ val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
+ __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
+ val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
+ __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+#endif
+}
+
/**
* omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
* The purpose of this function is to manage low power programming
@@ -182,6 +212,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
set_cpu_next_pwrst(cpu, power_state);
set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
scu_pwrst_prepare(cpu, power_state);
+ l2x0_pwrst_prepare(cpu, save_state);
/*
* Call low level function with targeted CPU id
@@ -241,17 +272,19 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
int __init omap4_mpuss_init(void)
{
struct omap4_cpu_pm_info *pm_info;
- void __iomem *sar_base = omap4_get_sar_ram_base();
if (omap_rev() == OMAP4430_REV_ES1_0) {
WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
return -ENODEV;
}
+ sar_base = omap4_get_sar_ram_base();
+
/* Initilaise per CPU PM information */
pm_info = &per_cpu(omap4_pm_info, 0x0);
pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
+ pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
if (!pm_info->pwrdm) {
pr_err("Lookup failed for CPU0 pwrdm\n");
@@ -267,6 +300,7 @@ int __init omap4_mpuss_init(void)
pm_info = &per_cpu(omap4_pm_info, 0x1);
pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
+ pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
if (!pm_info->pwrdm) {
pr_err("Lookup failed for CPU1 pwrdm\n");
@@ -292,6 +326,8 @@ int __init omap4_mpuss_init(void)
else
__raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
+ save_l2x0_context();
+
return 0;
}
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index aa14a8d..fe5b545 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -23,6 +23,10 @@
#define SCU_OFFSET0 0xd00
#define SCU_OFFSET1 0xd04
#define OMAP_TYPE_OFFSET 0xd10
+#define L2X0_SAVE_OFFSET0 0xd14
+#define L2X0_SAVE_OFFSET1 0xd18
+#define L2X0_AUXCTRL_OFFSET 0xd1c
+#define L2X0_PREFETCH_CTRL_OFFSET 0xd20
/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 230ab8c..a7cce0b 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -32,6 +32,9 @@
ppa_zero_params:
.word 0x0
+ppa_por_params:
+ .word 1, 0
+
/*
* =============================
* == CPU suspend finisher ==
@@ -130,6 +133,55 @@ skip_scu_gp_set:
mcrne p15, 0, r0, c1, c0, 1
isb
dsb
+#ifdef CONFIG_CACHE_L2X0
+ /*
+ * Clean and invalidate the L2 cache.
+ * Common cache-l2x0.c functions can't be used here since it
+ * uses spinlocks. We are out of coherency here with data cache
+ * disabled. The spinlock implementation uses exclusive load/store
+ * instruction which can fail without data cache being enabled.
+ * OMAP4 hardware doesn't support exclusive monitor which can
+ * overcome exclusive access issue. Because of this, CPU can
+ * lead to deadlock.
+ */
+l2x_clean_inv:
+ bl omap4_get_sar_ram_base
+ mov r8, r0
+ mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
+ ands r5, r5, #0x0f
+ ldreq r0, [r8, #L2X0_SAVE_OFFSET0]
+ ldrne r0, [r8, #L2X0_SAVE_OFFSET1]
+ cmp r0, #3
+ bne do_WFI
+#ifdef CONFIG_PL310_ERRATA_727915
+ mov r0, #0x03
+ mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+ DO_SMC
+#endif
+ bl omap4_get_l2cache_base
+ mov r2, r0
+ ldr r0, =0xffff
+ str r0, [r2, #L2X0_CLEAN_INV_WAY]
+wait:
+ ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
+ ldr r1, =0xffff
+ ands r0, r0, r1
+ bne wait
+#ifdef CONFIG_PL310_ERRATA_727915
+ mov r0, #0x00
+ mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+ DO_SMC
+#endif
+l2x_sync:
+ bl omap4_get_l2cache_base
+ mov r2, r0
+ mov r0, #0x0
+ str r0, [r2, #L2X0_CACHE_SYNC]
+sync:
+ ldr r0, [r2, #L2X0_CACHE_SYNC]
+ ands r0, r0, #0x1
+ bne sync
+#endif
do_WFI:
bl omap_do_wfi
@@ -222,6 +274,50 @@ enable_smp_bit:
mcreq p15, 0, r0, c1, c0, 1
isb
skip_ns_smp_enable:
+#ifdef CONFIG_CACHE_L2X0
+ /*
+ * Restore the L2 AUXCTRL and enable the L2 cache.
+ * OMAP4_MON_L2X0_AUXCTRL_INDEX = Program the L2X0 AUXCTRL
+ * OMAP4_MON_L2X0_CTRL_INDEX = Enable the L2 using L2X0 CTRL
+ * register r0 contains value to be programmed.
+ * L2 cache is already invalidate by ROM code as part
+ * of MPUSS OFF wakeup path.
+ */
+ ldr r2, =OMAP44XX_L2CACHE_BASE
+ ldr r0, [r2, #L2X0_CTRL]
+ and r0, #0x0f
+ cmp r0, #1
+ beq skip_l2en @ Skip if already enabled
+ ldr r3, =OMAP44XX_SAR_RAM_BASE
+ ldr r1, [r3, #OMAP_TYPE_OFFSET]
+ cmp r1, #0x1 @ Check for HS device
+ bne set_gp_por
+ ldr r0, =OMAP4_PPA_L2_POR_INDEX
+ ldr r1, =OMAP44XX_SAR_RAM_BASE
+ ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
+ adr r3, ppa_por_params
+ str r4, [r3, #0x04]
+ mov r1, #0x0 @ Process ID
+ mov r2, #0x4 @ Flag
+ mov r6, #0xff
+ mov r12, #0x00 @ Secure Service ID
+ DO_SMC
+ b set_aux_ctrl
+set_gp_por:
+ ldr r1, =OMAP44XX_SAR_RAM_BASE
+ ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
+ ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
+ DO_SMC
+set_aux_ctrl:
+ ldr r1, =OMAP44XX_SAR_RAM_BASE
+ ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
+ ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
+ DO_SMC
+ mov r0, #0x1
+ ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
+ DO_SMC
+skip_l2en:
+#endif
b cpu_resume @ Jump to generic resume
ENDPROC(omap4_cpu_resume)
--
1.7.4.1
next prev parent reply other threads:[~2011-09-04 13:54 UTC|newest]
Thread overview: 119+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-04 13:54 [PATCH 00/25] OMAP4: PM: suspend, CPU-hotplug and CPUilde support Santosh Shilimkar
2011-09-04 13:54 ` [PATCH 01/25] ARM: mm: Add strongly ordered descriptor support Santosh Shilimkar
2011-09-13 20:23 ` Tony Lindgren
2011-09-14 5:36 ` Shilimkar, Santosh
2011-09-04 13:54 ` [PATCH 02/25] OMAP4: Redefine mandatory barriers for OMAP to include interconnect barriers Santosh Shilimkar
2011-09-13 20:27 ` Tony Lindgren
2011-09-14 5:39 ` Shilimkar, Santosh
2011-09-14 10:24 ` Santosh
2011-09-15 17:17 ` Kevin Hilman
2011-09-15 17:24 ` Shilimkar, Santosh
2011-09-15 17:53 ` Tony Lindgren
2011-09-15 18:22 ` Shilimkar, Santosh
2011-09-15 19:43 ` Tony Lindgren
2011-09-15 20:00 ` Shilimkar, Santosh
2011-09-16 12:01 ` Shilimkar, Santosh
2011-09-04 13:54 ` [PATCH 03/25] OMAP4: PM: Use custom omap_do_wfi() for suspend and default idle Santosh Shilimkar
2011-09-04 13:54 ` [PATCH 04/25] OMAP4: Remove un-used do_wfi() macro Santosh Shilimkar
2011-09-04 13:54 ` [PATCH 05/25] OMAP4: Use WARN_ON() instead of BUG_ON() with graceful exit Santosh Shilimkar
2011-09-05 10:11 ` Sergei Shtylyov
2011-09-05 10:42 ` Santosh
2011-09-05 10:47 ` Russell King - ARM Linux
2011-09-05 10:51 ` Santosh
2011-09-08 18:51 ` Jean Pihet
2011-09-04 13:54 ` [PATCH 06/25] OMAP4: Export omap4_get_base*() rather than global address pointers Santosh Shilimkar
2011-09-04 13:54 ` [PATCH 07/25] OMAP4: PM: Add SAR RAM support Santosh Shilimkar
2011-09-04 13:54 ` [PATCH 08/25] OMAP4: PM: Keep static dep between MPUSS-EMIF and MPUSS-L3 and DUCATI-L3 Santosh Shilimkar
2011-09-08 18:06 ` Kevin Hilman
2011-09-09 4:21 ` Santosh
2011-09-04 13:54 ` [PATCH 09/25] OMAP4: PM: Avoid omap4_pm_init() on OMAP4430 ES1.0 Santosh Shilimkar
2011-09-04 13:54 ` [PATCH 10/25] OMAP4: PM: Initialise all the clockdomains to supported states Santosh Shilimkar
2011-09-04 13:54 ` [PATCH 11/25] OMAP: Add Secure HAL and monitor mode API infrastructure Santosh Shilimkar
2011-09-08 18:58 ` Jean Pihet
2011-09-09 4:22 ` Santosh
2011-09-04 13:54 ` [PATCH 12/25] OMAP: Add support to allocate the memory for secure RAM Santosh Shilimkar
2011-09-08 19:19 ` Jean Pihet
2011-09-09 9:43 ` Santosh
2011-09-09 12:54 ` Jean Pihet
2011-09-09 14:09 ` Shilimkar, Santosh
2011-09-04 13:54 ` [PATCH 13/25] OMAP4: PM: Add WakeupGen module as OMAP gic_arch_extn Santosh Shilimkar
2011-09-08 18:27 ` Kevin Hilman
2011-09-09 4:29 ` Santosh
2011-09-09 7:19 ` Thomas Gleixner
2011-09-09 8:07 ` Santosh
2011-09-09 8:18 ` Thomas Gleixner
2011-09-09 9:05 ` Santosh
2011-09-12 7:56 ` Thomas Gleixner
2011-09-12 8:44 ` Santosh
2011-09-08 19:16 ` Jean Pihet
2011-09-09 4:23 ` Santosh
2011-09-13 20:36 ` Tony Lindgren
2011-09-14 5:34 ` Shilimkar, Santosh
2011-09-14 15:21 ` Tony Lindgren
2011-09-14 16:49 ` Santosh
2011-09-14 17:08 ` Tony Lindgren
2011-09-14 17:13 ` Santosh
2011-09-14 17:18 ` Tony Lindgren
2011-09-14 17:21 ` Santosh
2011-09-14 17:22 ` Santosh
2011-09-14 19:04 ` Tony Lindgren
2011-09-15 2:57 ` Santosh
2011-09-15 9:36 ` Cousson, Benoit
2011-09-15 12:02 ` Shilimkar, Santosh
2011-09-15 13:29 ` Woodruff, Richard
2011-09-04 13:54 ` [PATCH 14/25] OMAP4: PM: Add CPUX OFF mode support Santosh Shilimkar
2011-09-08 19:39 ` Jean Pihet
2011-09-09 9:59 ` Santosh
2011-09-09 8:04 ` Shawn Guo
2011-09-09 8:09 ` Santosh
2011-09-09 14:13 ` Shawn Guo
2011-09-09 14:11 ` Shilimkar, Santosh
2011-09-09 15:27 ` Shawn Guo
2011-09-09 16:59 ` Santosh
2011-09-09 18:34 ` Kevin Hilman
2011-09-10 3:39 ` Shilimkar, Santosh
2011-09-09 23:34 ` Shawn Guo
2011-09-10 3:38 ` Shilimkar, Santosh
2011-09-10 4:54 ` Shawn Guo
2011-09-10 5:51 ` Santosh
2011-09-12 21:06 ` Kevin Hilman
2011-09-13 5:39 ` Santosh
2011-09-13 17:33 ` Kevin Hilman
2011-09-14 5:26 ` Shilimkar, Santosh
2011-09-04 13:54 ` [PATCH 15/25] OMAP4: Remove __INIT from omap_secondary_startup() to re-use it for hotplug Santosh Shilimkar
2011-09-04 13:54 ` [PATCH 16/25] OMAP4: PM: Program CPU1 to hit OFF when off-lined Santosh Shilimkar
2011-09-12 21:12 ` Kevin Hilman
2011-09-13 5:35 ` Santosh
2011-09-04 13:54 ` [PATCH 17/25] OMAP4: PM: CPU1 wakeup workaround from Low power modes Santosh Shilimkar
2011-09-04 13:54 ` [PATCH 18/25] OMAP4: suspend: Add MPUSS power domain RETENTION support Santosh Shilimkar
2011-09-15 0:27 ` Kevin Hilman
2011-09-15 3:19 ` Santosh
2011-09-04 13:54 ` [PATCH 19/25] OMAP4: PM: Add WakeupGen and secure GIC low power support Santosh Shilimkar
2011-09-04 13:54 ` Santosh Shilimkar [this message]
2011-09-05 14:01 ` [PATCH 20/25] OMAP4: PM: Add L2X0 cache lowpower support Lorenzo Pieralisi
2011-09-05 14:13 ` Santosh
2011-09-16 17:23 ` Kevin Hilman
2011-09-18 8:46 ` Santosh
2011-09-04 13:54 ` [PATCH 21/25] OMAP4: PM: Add MPUSS power domain OSWR support Santosh Shilimkar
2011-09-12 18:52 ` Kevin Hilman
2011-09-13 5:37 ` Santosh
2011-09-13 7:39 ` Jean Pihet
2011-09-13 8:25 ` Santosh
2011-09-04 13:54 ` [PATCH 22/25] OMAP4: PM: Add power domain statistics support Santosh Shilimkar
2011-09-05 10:08 ` Sergei Shtylyov
2011-09-05 10:43 ` Santosh
2011-09-04 13:54 ` [PATCH 23/25] OMAP4: PM: Add CPUidle support Santosh Shilimkar
2011-09-16 17:45 ` Kevin Hilman
2011-09-18 8:47 ` Santosh
2011-09-04 13:54 ` [PATCH 24/25] OMAP4: cpuidle: Switch to gptimer from twd in deeper C-states Santosh Shilimkar
2011-09-16 17:51 ` Kevin Hilman
2011-09-18 8:48 ` Santosh
2011-09-04 13:54 ` [PATCH 25/25] OMAP3: CPUidle: Make use of CPU PM notifiers Santosh Shilimkar
2011-09-08 17:57 ` Kevin Hilman
2011-09-09 4:20 ` Santosh
2011-09-09 7:17 ` Santosh
2011-09-08 20:15 ` [PATCH 00/25] OMAP4: PM: suspend, CPU-hotplug and CPUilde support Jean Pihet
2011-09-09 4:25 ` Santosh
2011-09-20 11:24 ` Vishwanath Sripathy
2011-09-20 11:37 ` Santosh
2011-09-20 11:57 ` Santosh
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