[RFC PATCH 00/34] msm: msm8660 and msm8960 clock support

[RFC PATCH 00/34] msm: msm8660 and msm8960 clock support

[David Brown]

The MSM8660 and MSM8960 have had out-of-tree clock drivers for quite
some time.  Since people can now order the Dragonboard with the
MSM8660, I thought it would be good to make sure these get sent out.
Saravana is actively working on this getting this code into the tree,
so this RFC is mostly to make the code available for people who get
the hardware before this work is done.

I'll also put these changes on top of a recent version of Linus'
master branch and make them available at

  git://codeaurora.org/quic/kernel/davidb/linux-msm.git msm-clock-rfc

David

David Brown (2):
  ARM: msm: fix names of UART clocks
  msm_serial: fix clock rate on DMA-based uarts

Matt Wagantall (8):
  msm: clock-local: Add support for 8x60 clock types
  msm: clock: Add 8x60 clock support
  msm: clock: Add list_rate debugfs nodes for locally-controlled clocks
  msm: clock: Add debugfs interface to measure clock rates
  msm: clock-8x60: Support measurement of CPU and L2 clocks
  msm: clock: Expand CLK_MIN, CLK_MAX and CLK_MINMAX macros
  msm: clock: Add EBI1 voter clocks for ADM on SoCs without them
  msm: clock-8x60: Add local control of vpe_axi_clk and vpe_axi_clk

Saravana Kannan (1):
  msm: clock: Add 7x30 local clock support

Stepan Moskovchenko (1):
  msm-8x60: Add serial support

Stephen Boyd (22):
  msm: clock-pcom: Mark functions static
  msm: clock: Always use an array to iterate over clocks
  msm: clock: Pass struct clk to the clk_ops
  msm: clock: Support one lock per clock
  msm: clock-pcom: Introduce a struct pcom_clk
  msm: clock: Support clk_[s|g]et_parent() clk_ops
  msm: clock-debug: Use clk_enable()/clk_disable() directly
  msm: clock: Enable/disable parent clocks generically
  msm: clock: Implement rate voting
  msm: clock-pcom: Add pbus specific clock ops
  msm: Migrate to clock rate voting
  msm: clock: Make most clk_*() operations optional
  msm: clock-debug: Implement a default is_enabled()
  msm: proc_comm: Add CLKCTL_RPC_SRC_REQUEST
  msm: clock: Add local clock control framework
  msm: clock-pcom: Expose pc_clk_reset
  msm: Unify iomap for clock regions
  msm: clock: Support dummy clocks
  msm: clock: Add 8960 clock support
  msm: 8660: Add FLUID support
  msm: clock: Invert CLKFLAG_AUTO_OFF
  msm: clock: Remove msm_clk_soc_init()

 arch/arm/mach-msm/Kconfig                       |    6 +
 arch/arm/mach-msm/Makefile                      |    5 +
 arch/arm/mach-msm/board-msm7x30.c               |    2 +-
 arch/arm/mach-msm/board-msm8960.c               |    9 +-
 arch/arm/mach-msm/board-msm8x60.c               |   69 +
 arch/arm/mach-msm/clock-7x30.c                  | 3001 +++++++++++++++++
 arch/arm/mach-msm/clock-7x30.h                  |  155 -
 arch/arm/mach-msm/clock-8960.c                  | 3930 +++++++++++++++++++++++
 arch/arm/mach-msm/clock-8x60.c                  | 3684 +++++++++++++++++++++
 arch/arm/mach-msm/clock-8x60.h                  |  293 ++
 arch/arm/mach-msm/clock-debug.c                 |   83 +-
 arch/arm/mach-msm/clock-dummy.c                 |   69 +
 arch/arm/mach-msm/clock-local.c                 |  969 ++++++
 arch/arm/mach-msm/clock-local.h                 |  316 ++
 arch/arm/mach-msm/clock-pcom-lookup.c           |  385 +++
 arch/arm/mach-msm/clock-pcom.c                  |   65 +-
 arch/arm/mach-msm/clock-pcom.h                  |   35 +-
 arch/arm/mach-msm/clock-voter.c                 |  187 ++
 arch/arm/mach-msm/clock-voter.h                 |   42 +
 arch/arm/mach-msm/clock.c                       |  150 +-
 arch/arm/mach-msm/clock.h                       |   63 +-
 arch/arm/mach-msm/devices-msm7x00.c             |  124 +-
 arch/arm/mach-msm/devices-msm7x30.c             |   82 -
 arch/arm/mach-msm/devices-qsd8x50.c             |  175 +-
 arch/arm/mach-msm/devices.h                     |    4 +-
 arch/arm/mach-msm/include/mach/board.h          |    2 -
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    5 +-
 arch/arm/mach-msm/include/mach/msm_iomap-7x30.h |    5 +-
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h |    9 +
 arch/arm/mach-msm/include/mach/msm_iomap-8x50.h |    5 +-
 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h |    9 +
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    3 +
 arch/arm/mach-msm/io.c                          |   12 +-
 arch/arm/mach-msm/proc_comm.h                   |    1 +
 drivers/tty/serial/msm_serial.c                 |    2 +-
 35 files changed, 13506 insertions(+), 450 deletions(-)
 create mode 100644 arch/arm/mach-msm/clock-7x30.c
 delete mode 100644 arch/arm/mach-msm/clock-7x30.h
 create mode 100644 arch/arm/mach-msm/clock-8960.c
 create mode 100644 arch/arm/mach-msm/clock-8x60.c
 create mode 100644 arch/arm/mach-msm/clock-8x60.h
 create mode 100644 arch/arm/mach-msm/clock-dummy.c
 create mode 100644 arch/arm/mach-msm/clock-local.c
 create mode 100644 arch/arm/mach-msm/clock-local.h
 create mode 100644 arch/arm/mach-msm/clock-pcom-lookup.c
 create mode 100644 arch/arm/mach-msm/clock-voter.c
 create mode 100644 arch/arm/mach-msm/clock-voter.h

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 01/34] msm: clock-pcom: Mark functions static

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

These functions are only used within clock-pcom.c, therefore mark
them as static.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-pcom.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index 63b7113..a52c970 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -25,7 +25,7 @@
 /*
  * glue for the proc_comm interface
  */
-int pc_clk_enable(unsigned id)
+static int pc_clk_enable(unsigned id)
 {
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
 	if (rc < 0)
@@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-void pc_clk_disable(unsigned id)
+static void pc_clk_disable(unsigned id)
 {
 	msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
 }
@@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_rate(unsigned id, unsigned rate)
+static int pc_clk_set_rate(unsigned id, unsigned rate)
 {
 	/* The rate _might_ be rounded off to the nearest KHz value by the
 	 * remote function. So a return value of 0 doesn't necessarily mean
@@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_min_rate(unsigned id, unsigned rate)
+static int pc_clk_set_min_rate(unsigned id, unsigned rate)
 {
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
 	if (rc < 0)
@@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_max_rate(unsigned id, unsigned rate)
+static int pc_clk_set_max_rate(unsigned id, unsigned rate)
 {
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
 	if (rc < 0)
@@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_flags(unsigned id, unsigned flags)
+static int pc_clk_set_flags(unsigned id, unsigned flags)
 {
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
 	if (rc < 0)
@@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-unsigned pc_clk_get_rate(unsigned id)
+static unsigned pc_clk_get_rate(unsigned id)
 {
 	if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
 		return 0;
@@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id)
 		return id;
 }
 
-unsigned pc_clk_is_enabled(unsigned id)
+static unsigned pc_clk_is_enabled(unsigned id)
 {
 	if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
 		return 0;
@@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id)
 		return id;
 }
 
-long pc_clk_round_rate(unsigned id, unsigned rate)
+static long pc_clk_round_rate(unsigned id, unsigned rate)
 {
 
 	/* Not really supported; pc_clk_set_rate() does rounding on it's own. */
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 02/34] msm: clock: Always use an array to iterate over clocks

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

If the array of clk_lookups contains aliases for the same struct
clk, msm_clock_init() will add the clock to the clocks list
twice.  This would cause list corruption so let's just remove the
clocks list and any associated code and iterate over the array
instead.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock.c              |   27 ++++++++++-----------------
 arch/arm/mach-msm/clock.h              |    1 -
 arch/arm/mach-msm/include/mach/board.h |    2 +-
 3 files changed, 11 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index d9145df..e23e4c2 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -15,7 +15,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/list.h>
 #include <linux/err.h>
 #include <linux/spinlock.h>
 #include <linux/pm_qos.h>
@@ -27,9 +26,7 @@
 
 #include "clock.h"
 
-static DEFINE_MUTEX(clocks_mutex);
 static DEFINE_SPINLOCK(clocks_lock);
-static LIST_HEAD(clocks);
 
 /*
  * Standard clock functions defined in include/linux/clk.h
@@ -135,21 +132,18 @@ EXPORT_SYMBOL(clk_set_flags);
  * generic to support different clocks.
  */
 static struct clk *ebi1_clk;
+static struct clk_lookup *msm_clocks;
+static unsigned msm_num_clocks;
 
-void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks)
+void __init msm_clock_init(struct clk_lookup *clock_tbl, size_t num_clocks)
 {
-	unsigned n;
-
-	mutex_lock(&clocks_mutex);
-	for (n = 0; n < num_clocks; n++) {
-		clkdev_add(&clock_tbl[n]);
-		list_add_tail(&clock_tbl[n].clk->list, &clocks);
-	}
-	mutex_unlock(&clocks_mutex);
+	clkdev_add_table(clock_tbl, num_clocks);
 
 	ebi1_clk = clk_get(NULL, "ebi1_clk");
 	BUG_ON(ebi1_clk == NULL);
 
+	msm_clocks = clock_tbl;
+	msm_num_clocks = num_clocks;
 }
 
 /* The bootloader and/or AMSS may have left various clocks enabled.
@@ -158,13 +152,13 @@ void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks)
  */
 static int __init clock_late_init(void)
 {
+	unsigned i, count = 0;
 	unsigned long flags;
-	struct clk *clk;
-	unsigned count = 0;
 
 	clock_debug_init();
-	mutex_lock(&clocks_mutex);
-	list_for_each_entry(clk, &clocks, list) {
+	for (i = 0; i < msm_num_clocks; i++) {
+		struct clk *clk = msm_clocks[i].clk;
+
 		clock_debug_add(clk);
 		if (clk->flags & CLKFLAG_AUTO_OFF) {
 			spin_lock_irqsave(&clocks_lock, flags);
@@ -175,7 +169,6 @@ static int __init clock_late_init(void)
 			spin_unlock_irqrestore(&clocks_lock, flags);
 		}
 	}
-	mutex_unlock(&clocks_mutex);
 	pr_info("clock_late_init() disabled %d unused clocks\n", count);
 	return 0;
 }
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 2c007f6..32a43d4 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -53,7 +53,6 @@ struct clk {
 	uint32_t flags;
 	struct clk_ops *ops;
 	const char *dbg_name;
-	struct list_head list;
 };
 
 #define OFF CLKFLAG_AUTO_OFF
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 2ce8f1f..1e4c50e 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -41,7 +41,7 @@ void __init msm_add_devices(void);
 void __init msm_map_common_io(void);
 void __init msm_init_irq(void);
 void __init msm_init_gpio(void);
-void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
+void __init msm_clock_init(struct clk_lookup *clock_tbl, size_t num_clocks);
 void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
 int __init msm_add_sdcc(unsigned int controller,
 			struct msm_mmc_platform_data *plat,
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 03/34] msm: clock: Pass struct clk to the clk_ops

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-debug.c |    8 ++++----
 arch/arm/mach-msm/clock-pcom.c  |   31 ++++++++++++++++++++-----------
 arch/arm/mach-msm/clock-pcom.h  |    2 +-
 arch/arm/mach-msm/clock.c       |   24 ++++++++++++------------
 arch/arm/mach-msm/clock.h       |   24 ++++++++++++------------
 5 files changed, 49 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index 4886404..bddcbc9 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -55,9 +55,9 @@ static int clock_debug_enable_set(void *data, u64 val)
 	int rc = 0;
 
 	if (val)
-		rc = clock->ops->enable(clock->id);
+		rc = clock->ops->enable(clock);
 	else
-		clock->ops->disable(clock->id);
+		clock->ops->disable(clock);
 
 	return rc;
 }
@@ -66,7 +66,7 @@ static int clock_debug_enable_get(void *data, u64 *val)
 {
 	struct clk *clock = data;
 
-	*val = clock->ops->is_enabled(clock->id);
+	*val = clock->ops->is_enabled(clock);
 
 	return 0;
 }
@@ -78,7 +78,7 @@ static int clock_debug_local_get(void *data, u64 *val)
 {
 	struct clk *clock = data;
 
-	*val = clock->ops->is_local(clock->id);
+	*val = clock->ops->is_local(clock);
 
 	return 0;
 }
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index a52c970..ee5f7fe 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -25,8 +25,9 @@
 /*
  * glue for the proc_comm interface
  */
-static int pc_clk_enable(unsigned id)
+static int pc_clk_enable(struct clk *clk)
 {
+	unsigned id = clk->id;
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
 	if (rc < 0)
 		return rc;
@@ -34,14 +35,16 @@ static int pc_clk_enable(unsigned id)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-static void pc_clk_disable(unsigned id)
+static void pc_clk_disable(struct clk *clk)
 {
+	unsigned id = clk->id;
 	msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
 }
 
-int pc_clk_reset(unsigned id, enum clk_reset_action action)
+int pc_clk_reset(struct clk *clk, enum clk_reset_action action)
 {
 	int rc;
+	unsigned id = clk->id;
 
 	if (action == CLK_RESET_ASSERT)
 		rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
@@ -54,12 +57,13 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-static int pc_clk_set_rate(unsigned id, unsigned rate)
+static int pc_clk_set_rate(struct clk *clk, unsigned rate)
 {
 	/* The rate _might_ be rounded off to the nearest KHz value by the
 	 * remote function. So a return value of 0 doesn't necessarily mean
 	 * that the exact rate was set successfully.
 	 */
+	unsigned id = clk->id;
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
 	if (rc < 0)
 		return rc;
@@ -67,8 +71,9 @@ static int pc_clk_set_rate(unsigned id, unsigned rate)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-static int pc_clk_set_min_rate(unsigned id, unsigned rate)
+static int pc_clk_set_min_rate(struct clk *clk, unsigned rate)
 {
+	unsigned id = clk->id;
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
 	if (rc < 0)
 		return rc;
@@ -76,8 +81,9 @@ static int pc_clk_set_min_rate(unsigned id, unsigned rate)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-static int pc_clk_set_max_rate(unsigned id, unsigned rate)
+static int pc_clk_set_max_rate(struct clk *clk, unsigned rate)
 {
+	unsigned id = clk->id;
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
 	if (rc < 0)
 		return rc;
@@ -85,8 +91,9 @@ static int pc_clk_set_max_rate(unsigned id, unsigned rate)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-static int pc_clk_set_flags(unsigned id, unsigned flags)
+static int pc_clk_set_flags(struct clk *clk, unsigned flags)
 {
+	unsigned id = clk->id;
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
 	if (rc < 0)
 		return rc;
@@ -94,30 +101,32 @@ static int pc_clk_set_flags(unsigned id, unsigned flags)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-static unsigned pc_clk_get_rate(unsigned id)
+static unsigned pc_clk_get_rate(struct clk *clk)
 {
+	unsigned id = clk->id;
 	if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
 		return 0;
 	else
 		return id;
 }
 
-static unsigned pc_clk_is_enabled(unsigned id)
+static unsigned pc_clk_is_enabled(struct clk *clk)
 {
+	unsigned id = clk->id;
 	if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
 		return 0;
 	else
 		return id;
 }
 
-static long pc_clk_round_rate(unsigned id, unsigned rate)
+static long pc_clk_round_rate(struct clk *clk, unsigned rate)
 {
 
 	/* Not really supported; pc_clk_set_rate() does rounding on it's own. */
 	return rate;
 }
 
-static bool pc_clk_is_local(unsigned id)
+static bool pc_clk_is_local(struct clk *clk)
 {
 	return false;
 }
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
index 974d003..9a695f9 100644
--- a/arch/arm/mach-msm/clock-pcom.h
+++ b/arch/arm/mach-msm/clock-pcom.h
@@ -123,7 +123,7 @@
 struct clk_ops;
 extern struct clk_ops clk_ops_pcom;
 
-int pc_clk_reset(unsigned id, enum clk_reset_action action);
+int pc_clk_reset(struct clk *clk, enum clk_reset_action action);
 
 #define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) {	\
 	.con_id = clk_name, \
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index e23e4c2..a9dabde 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -37,7 +37,7 @@ int clk_enable(struct clk *clk)
 	spin_lock_irqsave(&clocks_lock, flags);
 	clk->count++;
 	if (clk->count == 1)
-		clk->ops->enable(clk->id);
+		clk->ops->enable(clk);
 	spin_unlock_irqrestore(&clocks_lock, flags);
 	return 0;
 }
@@ -50,20 +50,20 @@ void clk_disable(struct clk *clk)
 	BUG_ON(clk->count == 0);
 	clk->count--;
 	if (clk->count == 0)
-		clk->ops->disable(clk->id);
+		clk->ops->disable(clk);
 	spin_unlock_irqrestore(&clocks_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
 int clk_reset(struct clk *clk, enum clk_reset_action action)
 {
-	return clk->ops->reset(clk->remote_id, action);
+	return clk->ops->reset(clk, action);
 }
 EXPORT_SYMBOL(clk_reset);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
-	return clk->ops->get_rate(clk->id);
+	return clk->ops->get_rate(clk);
 }
 EXPORT_SYMBOL(clk_get_rate);
 
@@ -71,12 +71,12 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 {
 	int ret;
 	if (clk->flags & CLKFLAG_MAX) {
-		ret = clk->ops->set_max_rate(clk->id, rate);
+		ret = clk->ops->set_max_rate(clk, rate);
 		if (ret)
 			return ret;
 	}
 	if (clk->flags & CLKFLAG_MIN) {
-		ret = clk->ops->set_min_rate(clk->id, rate);
+		ret = clk->ops->set_min_rate(clk, rate);
 		if (ret)
 			return ret;
 	}
@@ -84,25 +84,25 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 	if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN)
 		return ret;
 
-	return clk->ops->set_rate(clk->id, rate);
+	return clk->ops->set_rate(clk, rate);
 }
 EXPORT_SYMBOL(clk_set_rate);
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
-	return clk->ops->round_rate(clk->id, rate);
+	return clk->ops->round_rate(clk, rate);
 }
 EXPORT_SYMBOL(clk_round_rate);
 
 int clk_set_min_rate(struct clk *clk, unsigned long rate)
 {
-	return clk->ops->set_min_rate(clk->id, rate);
+	return clk->ops->set_min_rate(clk, rate);
 }
 EXPORT_SYMBOL(clk_set_min_rate);
 
 int clk_set_max_rate(struct clk *clk, unsigned long rate)
 {
-	return clk->ops->set_max_rate(clk->id, rate);
+	return clk->ops->set_max_rate(clk, rate);
 }
 EXPORT_SYMBOL(clk_set_max_rate);
 
@@ -122,7 +122,7 @@ int clk_set_flags(struct clk *clk, unsigned long flags)
 {
 	if (clk == NULL || IS_ERR(clk))
 		return -EINVAL;
-	return clk->ops->set_flags(clk->id, flags);
+	return clk->ops->set_flags(clk, flags);
 }
 EXPORT_SYMBOL(clk_set_flags);
 
@@ -164,7 +164,7 @@ static int __init clock_late_init(void)
 			spin_lock_irqsave(&clocks_lock, flags);
 			if (!clk->count) {
 				count++;
-				clk->ops->auto_off(clk->id);
+				clk->ops->auto_off(clk);
 			}
 			spin_unlock_irqrestore(&clocks_lock, flags);
 		}
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 32a43d4..7fe1598 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -32,18 +32,18 @@
 #define CLKFLAG_MAX			0x00000800
 
 struct clk_ops {
-	int (*enable)(unsigned id);
-	void (*disable)(unsigned id);
-	void (*auto_off)(unsigned id);
-	int (*reset)(unsigned id, enum clk_reset_action action);
-	int (*set_rate)(unsigned id, unsigned rate);
-	int (*set_min_rate)(unsigned id, unsigned rate);
-	int (*set_max_rate)(unsigned id, unsigned rate);
-	int (*set_flags)(unsigned id, unsigned flags);
-	unsigned (*get_rate)(unsigned id);
-	unsigned (*is_enabled)(unsigned id);
-	long (*round_rate)(unsigned id, unsigned rate);
-	bool (*is_local)(unsigned id);
+	int (*enable)(struct clk *clk);
+	void (*disable)(struct clk *clk);
+	void (*auto_off)(struct clk *clk);
+	int (*reset)(struct clk *clk, enum clk_reset_action action);
+	int (*set_rate)(struct clk *clk, unsigned rate);
+	int (*set_min_rate)(struct clk *clk, unsigned rate);
+	int (*set_max_rate)(struct clk *clk, unsigned rate);
+	int (*set_flags)(struct clk *clk, unsigned flags);
+	unsigned (*get_rate)(struct clk *clk);
+	unsigned (*is_enabled)(struct clk *clk);
+	long (*round_rate)(struct clk *clk, unsigned rate);
+	bool (*is_local)(struct clk *clk);
 };
 
 struct clk {
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 04/34] msm: clock: Support one lock per clock

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock.c |   19 +++++++++++--------
 arch/arm/mach-msm/clock.h |    2 ++
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index a9dabde..aa4a450 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -26,19 +26,17 @@
 
 #include "clock.h"
 
-static DEFINE_SPINLOCK(clocks_lock);
-
 /*
  * Standard clock functions defined in include/linux/clk.h
  */
 int clk_enable(struct clk *clk)
 {
 	unsigned long flags;
-	spin_lock_irqsave(&clocks_lock, flags);
+	spin_lock_irqsave(&clk->lock, flags);
 	clk->count++;
 	if (clk->count == 1)
 		clk->ops->enable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
+	spin_unlock_irqrestore(&clk->lock, flags);
 	return 0;
 }
 EXPORT_SYMBOL(clk_enable);
@@ -46,12 +44,12 @@ EXPORT_SYMBOL(clk_enable);
 void clk_disable(struct clk *clk)
 {
 	unsigned long flags;
-	spin_lock_irqsave(&clocks_lock, flags);
+	spin_lock_irqsave(&clk->lock, flags);
 	BUG_ON(clk->count == 0);
 	clk->count--;
 	if (clk->count == 0)
 		clk->ops->disable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
+	spin_unlock_irqrestore(&clk->lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
@@ -137,8 +135,13 @@ static unsigned msm_num_clocks;
 
 void __init msm_clock_init(struct clk_lookup *clock_tbl, size_t num_clocks)
 {
+	unsigned n;
+
 	clkdev_add_table(clock_tbl, num_clocks);
 
+	for (n = 0; n < num_clocks; n++)
+		spin_lock_init(&clock_tbl[n].clk->lock);
+
 	ebi1_clk = clk_get(NULL, "ebi1_clk");
 	BUG_ON(ebi1_clk == NULL);
 
@@ -161,12 +164,12 @@ static int __init clock_late_init(void)
 
 		clock_debug_add(clk);
 		if (clk->flags & CLKFLAG_AUTO_OFF) {
-			spin_lock_irqsave(&clocks_lock, flags);
+			spin_lock_irqsave(&clk->lock, flags);
 			if (!clk->count) {
 				count++;
 				clk->ops->auto_off(clk);
 			}
-			spin_unlock_irqrestore(&clocks_lock, flags);
+			spin_unlock_irqrestore(&clk->lock, flags);
 		}
 	}
 	pr_info("clock_late_init() disabled %d unused clocks\n", count);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 7fe1598..89506a8 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -19,6 +19,7 @@
 
 #include <linux/init.h>
 #include <linux/list.h>
+#include <linux/spinlock.h>
 #include <mach/clk.h>
 
 #define CLKFLAG_INVERT			0x00000001
@@ -53,6 +54,7 @@ struct clk {
 	uint32_t flags;
 	struct clk_ops *ops;
 	const char *dbg_name;
+	spinlock_t lock;
 };
 
 #define OFF CLKFLAG_AUTO_OFF
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 05/34] msm: clock-pcom: Introduce a struct pcom_clk

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Move the unsigned id member out of struct clk since its only
really useful for proc_comm clocks. This means we have to define
all the struct clk's before hand, but we actually want to do this
so we can point voter clocks at the struct clk directly.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-7x30.h      |   12 --
 arch/arm/mach-msm/clock-pcom.c      |   18 ++--
 arch/arm/mach-msm/clock-pcom.h      |   32 ++++--
 arch/arm/mach-msm/clock.h           |    2 +-
 arch/arm/mach-msm/devices-msm7x00.c |  124 ++++++++++++++-------
 arch/arm/mach-msm/devices-msm7x30.c |  213 +++++++++++++++++++++++------------
 arch/arm/mach-msm/devices-qsd8x50.c |  154 +++++++++++++++++---------
 7 files changed, 360 insertions(+), 195 deletions(-)

diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h
index 1410445..3eaaee1 100644
--- a/arch/arm/mach-msm/clock-7x30.h
+++ b/arch/arm/mach-msm/clock-7x30.h
@@ -140,16 +140,4 @@ extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
 	}, \
 	}
 
-#define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) {	\
-	.con_id = clk_name, \
-	.dev_id = clk_dev, \
-	.clk = &(struct clk){ \
-		.id = L_7X30_##l_id, \
-		.remote_id = P_##r_id, \
-		.flags = clk_flags, \
-		.dbg_name = #l_id, \
-		.ops = &clk_ops_pcom, \
-	}, \
-	}
-
 #endif
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index ee5f7fe..24ddfd8 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -27,7 +27,7 @@
  */
 static int pc_clk_enable(struct clk *clk)
 {
-	unsigned id = clk->id;
+	unsigned id = to_pcom_clk(clk)->id;
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
 	if (rc < 0)
 		return rc;
@@ -37,14 +37,14 @@ static int pc_clk_enable(struct clk *clk)
 
 static void pc_clk_disable(struct clk *clk)
 {
-	unsigned id = clk->id;
+	unsigned id = to_pcom_clk(clk)->id;
 	msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
 }
 
 int pc_clk_reset(struct clk *clk, enum clk_reset_action action)
 {
 	int rc;
-	unsigned id = clk->id;
+	unsigned id = to_pcom_clk(clk)->id;
 
 	if (action == CLK_RESET_ASSERT)
 		rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
@@ -63,7 +63,7 @@ static int pc_clk_set_rate(struct clk *clk, unsigned rate)
 	 * remote function. So a return value of 0 doesn't necessarily mean
 	 * that the exact rate was set successfully.
 	 */
-	unsigned id = clk->id;
+	unsigned id = to_pcom_clk(clk)->id;
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
 	if (rc < 0)
 		return rc;
@@ -73,7 +73,7 @@ static int pc_clk_set_rate(struct clk *clk, unsigned rate)
 
 static int pc_clk_set_min_rate(struct clk *clk, unsigned rate)
 {
-	unsigned id = clk->id;
+	unsigned id = to_pcom_clk(clk)->id;
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
 	if (rc < 0)
 		return rc;
@@ -83,7 +83,7 @@ static int pc_clk_set_min_rate(struct clk *clk, unsigned rate)
 
 static int pc_clk_set_max_rate(struct clk *clk, unsigned rate)
 {
-	unsigned id = clk->id;
+	unsigned id = to_pcom_clk(clk)->id;
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
 	if (rc < 0)
 		return rc;
@@ -93,7 +93,7 @@ static int pc_clk_set_max_rate(struct clk *clk, unsigned rate)
 
 static int pc_clk_set_flags(struct clk *clk, unsigned flags)
 {
-	unsigned id = clk->id;
+	unsigned id = to_pcom_clk(clk)->id;
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
 	if (rc < 0)
 		return rc;
@@ -103,7 +103,7 @@ static int pc_clk_set_flags(struct clk *clk, unsigned flags)
 
 static unsigned pc_clk_get_rate(struct clk *clk)
 {
-	unsigned id = clk->id;
+	unsigned id = to_pcom_clk(clk)->id;
 	if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
 		return 0;
 	else
@@ -112,7 +112,7 @@ static unsigned pc_clk_get_rate(struct clk *clk)
 
 static unsigned pc_clk_is_enabled(struct clk *clk)
 {
-	unsigned id = clk->id;
+	unsigned id = to_pcom_clk(clk)->id;
 	if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
 		return 0;
 	else
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
index 9a695f9..955c917 100644
--- a/arch/arm/mach-msm/clock-pcom.h
+++ b/arch/arm/mach-msm/clock-pcom.h
@@ -123,18 +123,30 @@
 struct clk_ops;
 extern struct clk_ops clk_ops_pcom;
 
-int pc_clk_reset(struct clk *clk, enum clk_reset_action action);
+/**
+ * struct pcom_clk - proc_comm controlled clock
+ * @id: proc_comm identifier
+ * @c: clk
+ */
+struct pcom_clk {
+	unsigned id;
+	struct clk c;
+};
+
+static inline struct pcom_clk *to_pcom_clk(struct clk *clk)
+{
+	return container_of(clk, struct pcom_clk, c);
+}
 
-#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) {	\
-	.con_id = clk_name, \
-	.dev_id = clk_dev, \
-	.clk = &(struct clk){ \
+#define DEFINE_CLK_PCOM(clk_name, clk_id, clk_flags) \
+	struct pcom_clk clk_name = { \
 		.id = P_##clk_id, \
-		.remote_id = P_##clk_id, \
-		.ops = &clk_ops_pcom, \
-		.flags = clk_flags, \
-		.dbg_name = #clk_id, \
-	}, \
+		.c = { \
+			.ops = &clk_ops_pcom, \
+			.flags = clk_flags, \
+			.dbg_name = #clk_id, \
+			.lock = __SPIN_LOCK_UNLOCKED(clk_name.c), \
+		}, \
 	}
 
 #endif
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 89506a8..ab14f15 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -48,7 +48,6 @@ struct clk_ops {
 };
 
 struct clk {
-	uint32_t id;
 	uint32_t remote_id;
 	uint32_t count;
 	uint32_t flags;
@@ -70,4 +69,5 @@ static inline int __init clock_debug_init(void) { return 0; }
 static inline int __init clock_debug_add(struct clk *clock) { return 0; }
 #endif
 
+#define CLK_LOOKUP(con, c, dev) { .con_id = con, .clk = &c, .dev_id = dev }
 #endif
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 993780f..1cef1e2 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -394,48 +394,90 @@ struct platform_device msm_device_mdp = {
 	.resource = resources_mdp,
 };
 
+static DEFINE_CLK_PCOM(adm_clk,		ADM_CLK,	0);
+static DEFINE_CLK_PCOM(adsp_clk,	ADSP_CLK,	0);
+static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,	0);
+static DEFINE_CLK_PCOM(ebi2_clk,	EBI2_CLK,	0);
+static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,	0);
+static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	OFF);
+static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,		0);
+static DEFINE_CLK_PCOM(grp_3d_clk,	GRP_3D_CLK,	OFF);
+static DEFINE_CLK_PCOM(i2c_clk,		I2C_CLK,	0);
+static DEFINE_CLK_PCOM(icodec_rx_clk,	ICODEC_RX_CLK,	0);
+static DEFINE_CLK_PCOM(icodec_tx_clk,	ICODEC_TX_CLK,	0);
+static DEFINE_CLK_PCOM(imem_clk,	IMEM_CLK,	OFF);
+static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,	0);
+static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,	OFF);
+static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,	0);
+static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,	0);
+static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	OFF | CLK_MINMAX);
+static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc1_clk,	SDC1_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc1_p_clk,	SDC1_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc2_clk,	SDC2_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc2_p_clk,	SDC2_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc3_clk,	SDC3_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc3_p_clk,	SDC3_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc4_clk,	SDC4_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc4_p_clk,	SDC4_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(tsif_clk,	TSIF_CLK,	0);
+static DEFINE_CLK_PCOM(tsif_ref_clk,	TSIF_REF_CLK,	0);
+static DEFINE_CLK_PCOM(tv_dac_clk,	TV_DAC_CLK,	0);
+static DEFINE_CLK_PCOM(tv_enc_clk,	TV_ENC_CLK,	0);
+static DEFINE_CLK_PCOM(uart1_clk,	UART1_CLK,	OFF);
+static DEFINE_CLK_PCOM(uart2_clk,	UART2_CLK,	0);
+static DEFINE_CLK_PCOM(uart3_clk,	UART3_CLK,	OFF);
+static DEFINE_CLK_PCOM(uart1dm_clk,	UART1DM_CLK,	OFF);
+static DEFINE_CLK_PCOM(uart2dm_clk,	UART2DM_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs_clk,	USB_HS_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_otg_clk,	USB_OTG_CLK,	0);
+static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	OFF);
+static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,	OFF);
+static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,	OFF);
+
 struct clk_lookup msm_clocks_7x01a[] = {
-	CLK_PCOM("adm_clk",	ADM_CLK,	NULL, 0),
-	CLK_PCOM("adsp_clk",	ADSP_CLK,	NULL, 0),
-	CLK_PCOM("ebi1_clk",	EBI1_CLK,	NULL, 0),
-	CLK_PCOM("ebi2_clk",	EBI2_CLK,	NULL, 0),
-	CLK_PCOM("ecodec_clk",	ECODEC_CLK,	NULL, 0),
-	CLK_PCOM("emdh_clk",	EMDH_CLK,	NULL, OFF),
-	CLK_PCOM("gp_clk",		GP_CLK,		NULL, 0),
-	CLK_PCOM("grp_clk",	GRP_3D_CLK,	NULL, OFF),
-	CLK_PCOM("i2c_clk",	I2C_CLK,	"msm_i2c.0", 0),
-	CLK_PCOM("icodec_rx_clk",	ICODEC_RX_CLK,	NULL, 0),
-	CLK_PCOM("icodec_tx_clk",	ICODEC_TX_CLK,	NULL, 0),
-	CLK_PCOM("imem_clk",	IMEM_CLK,	NULL, OFF),
-	CLK_PCOM("mdc_clk",	MDC_CLK,	NULL, 0),
-	CLK_PCOM("mdp_clk",	MDP_CLK,	NULL, OFF),
-	CLK_PCOM("pbus_clk",	PBUS_CLK,	NULL, 0),
-	CLK_PCOM("pcm_clk",	PCM_CLK,	NULL, 0),
-	CLK_PCOM("mddi_clk",	PMDH_CLK,	NULL, OFF | CLK_MINMAX),
-	CLK_PCOM("sdac_clk",	SDAC_CLK,	NULL, OFF),
-	CLK_PCOM("sdc_clk",	SDC1_CLK,	"msm_sdcc.1", OFF),
-	CLK_PCOM("sdc_pclk",	SDC1_P_CLK,	"msm_sdcc.1", OFF),
-	CLK_PCOM("sdc_clk",	SDC2_CLK,	"msm_sdcc.2", OFF),
-	CLK_PCOM("sdc_pclk",	SDC2_P_CLK,	"msm_sdcc.2", OFF),
-	CLK_PCOM("sdc_clk",	SDC3_CLK,	"msm_sdcc.3", OFF),
-	CLK_PCOM("sdc_pclk",	SDC3_P_CLK,	"msm_sdcc.3", OFF),
-	CLK_PCOM("sdc_clk",	SDC4_CLK,	"msm_sdcc.4", OFF),
-	CLK_PCOM("sdc_pclk",	SDC4_P_CLK,	"msm_sdcc.4", OFF),
-	CLK_PCOM("tsif_clk",	TSIF_CLK,	NULL, 0),
-	CLK_PCOM("tsif_ref_clk",	TSIF_REF_CLK,	NULL, 0),
-	CLK_PCOM("tv_dac_clk",	TV_DAC_CLK,	NULL, 0),
-	CLK_PCOM("tv_enc_clk",	TV_ENC_CLK,	NULL, 0),
-	CLK_PCOM("uart_clk",	UART1_CLK,	"msm_serial.0", OFF),
-	CLK_PCOM("uart_clk",	UART2_CLK,	"msm_serial.1", 0),
-	CLK_PCOM("uart_clk",	UART3_CLK,	"msm_serial.2", OFF),
-	CLK_PCOM("uart1dm_clk",	UART1DM_CLK,	NULL, OFF),
-	CLK_PCOM("uart2dm_clk",	UART2DM_CLK,	NULL, 0),
-	CLK_PCOM("usb_hs_clk",	USB_HS_CLK,	"msm_hsusb", OFF),
-	CLK_PCOM("usb_hs_pclk",	USB_HS_P_CLK,	"msm_hsusb", OFF),
-	CLK_PCOM("usb_otg_clk",	USB_OTG_CLK,	NULL, 0),
-	CLK_PCOM("vdc_clk",	VDC_CLK,	NULL, OFF ),
-	CLK_PCOM("vfe_clk",	VFE_CLK,	NULL, OFF),
-	CLK_PCOM("vfe_mdc_clk",	VFE_MDC_CLK,	NULL, OFF),
+	CLK_LOOKUP("adm_clk",		adm_clk.c,	"msm_dmov"),
+	CLK_LOOKUP("adsp_clk",		adsp_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_clk.c,	NULL),
+	CLK_LOOKUP("ebi2_clk",		ebi2_clk.c,	NULL),
+	CLK_LOOKUP("ecodec_clk",	ecodec_clk.c,	NULL),
+	CLK_LOOKUP("emdh_clk",		emdh_clk.c,	NULL),
+	CLK_LOOKUP("gp_clk",		gp_clk.c,	NULL),
+	CLK_LOOKUP("grp_clk",		grp_3d_clk.c,	NULL),
+	CLK_LOOKUP("i2c_clk",		i2c_clk.c,	"msm_i2c.0"),
+	CLK_LOOKUP("icodec_rx_clk",	icodec_rx_clk.c,	NULL),
+	CLK_LOOKUP("icodec_tx_clk",	icodec_tx_clk.c,	NULL),
+	CLK_LOOKUP("imem_clk",		imem_clk.c,	NULL),
+	CLK_LOOKUP("mdc_clk",		mdc_clk.c,	NULL),
+	CLK_LOOKUP("mdp_clk",		mdp_clk.c,	NULL),
+	CLK_LOOKUP("pbus_clk",		pbus_clk.c,	NULL),
+	CLK_LOOKUP("pcm_clk",		pcm_clk.c,	NULL),
+	CLK_LOOKUP("mddi_clk",		pmdh_clk.c,	NULL),
+	CLK_LOOKUP("sdac_clk",		sdac_clk.c,	NULL),
+	CLK_LOOKUP("sdc_clk",		sdc1_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_pclk",		sdc1_p_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_clk",		sdc2_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_pclk",		sdc2_p_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_clk",		sdc3_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_pclk",		sdc3_p_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_clk",		sdc4_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("sdc_pclk",		sdc4_p_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("tsif_clk",		tsif_clk.c,	NULL),
+	CLK_LOOKUP("tsif_ref_clk",	tsif_ref_clk.c,	NULL),
+	CLK_LOOKUP("tv_dac_clk",	tv_dac_clk.c,	NULL),
+	CLK_LOOKUP("tv_enc_clk",	tv_enc_clk.c,	NULL),
+	CLK_LOOKUP("uart_clk",		uart1_clk.c,	"msm_serial.0"),
+	CLK_LOOKUP("uart_clk",		uart2_clk.c,	"msm_serial.1"),
+	CLK_LOOKUP("uart_clk",		uart3_clk.c,	"msm_serial.2"),
+	CLK_LOOKUP("uart1dm_clk",	uart1dm_clk.c,	NULL),
+	CLK_LOOKUP("uart2dm_clk",	uart2dm_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs_clk",	usb_hs_clk.c,	"msm_hsusb"),
+	CLK_LOOKUP("usb_hs_pclk",	usb_hs_p_clk.c,	"msm_hsusb"),
+	CLK_LOOKUP("usb_otg_clk",	usb_otg_clk.c,	NULL),
+	CLK_LOOKUP("vdc_clk",		vdc_clk.c,	NULL),
+	CLK_LOOKUP("vfe_clk",		vfe_clk.c,	NULL),
+	CLK_LOOKUP("vfe_mdc_clk",	vfe_mdc_clk.c,	NULL),
 };
 
 unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a);
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 09b4f14..1ebb22d 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -130,80 +130,151 @@ struct platform_device msm_device_hsusb_host = {
 	},
 };
 
+static DEFINE_CLK_PCOM(adm_clk,		ADM_CLK,		0);
+static DEFINE_CLK_PCOM(adsp_clk,	ADSP_CLK,		0);
+static DEFINE_CLK_PCOM(cam_m_clk,	CAM_M_CLK,		0);
+static DEFINE_CLK_PCOM(camif_pad_p_clk,	CAMIF_PAD_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(ce_clk,		CE_CLK,			0);
+static DEFINE_CLK_PCOM(codec_ssbi_clk,	CODEC_SSBI_CLK,		0);
+static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,		CLK_MIN);
+static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,		0);
+static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	OFF | CLK_MINMAX);
+static DEFINE_CLK_PCOM(emdh_p_clk,	EMDH_P_CLK,		OFF);
+static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,			0);
+static DEFINE_CLK_PCOM(grp_2d_clk,	GRP_2D_CLK,		0);
+static DEFINE_CLK_PCOM(grp_2d_p_clk,	GRP_2D_P_CLK,		0);
+static DEFINE_CLK_PCOM(grp_3d_clk,	GRP_3D_CLK,		0);
+static DEFINE_CLK_PCOM(grp_3d_p_clk,	GRP_3D_P_CLK,		0);
+static DEFINE_CLK_PCOM(hdmi_clk,	HDMI_CLK,		0);
+static DEFINE_CLK_PCOM(imem_clk,	IMEM_CLK,		OFF);
+static DEFINE_CLK_PCOM(jpeg_clk,	JPEG_CLK,		OFF);
+static DEFINE_CLK_PCOM(jpeg_p_clk,	JPEG_P_CLK,		OFF);
+static DEFINE_CLK_PCOM(lpa_codec_clk,	LPA_CODEC_CLK,		0);
+static DEFINE_CLK_PCOM(lpa_core_clk,	LPA_CORE_CLK,		0);
+static DEFINE_CLK_PCOM(lpa_p_clk,	LPA_P_CLK,		0);
+static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,		0);
+static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	OFF | CLK_MINMAX);
+static DEFINE_CLK_PCOM(pmdh_p_clk,	PMDH_P_CLK,		0);
+static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,		OFF);
+static DEFINE_CLK_PCOM(mdp_p_clk,	MDP_P_CLK,		0);
+static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK,	0);
+static DEFINE_CLK_PCOM(mdp_lcdc_pad_pclk_clk, MDP_LCDC_PAD_PCLK_CLK, 0);
+static DEFINE_CLK_PCOM(mdp_vsync_clk,	MDP_VSYNC_CLK,		0);
+static DEFINE_CLK_PCOM(mfc_clk,		MFC_CLK,		0);
+static DEFINE_CLK_PCOM(mfc_div2_clk,	MFC_DIV2_CLK,		0);
+static DEFINE_CLK_PCOM(mfc_p_clk,	MFC_P_CLK,		0);
+static DEFINE_CLK_PCOM(mi2s_m_clk,	MI2S_M_CLK,  		0);
+static DEFINE_CLK_PCOM(mi2s_s_clk,	MI2S_S_CLK,  		0);
+static DEFINE_CLK_PCOM(mi2s_codec_rx_m_clk,	MI2S_CODEC_RX_M_CLK,  0);
+static DEFINE_CLK_PCOM(mi2s_codec_rx_s_clk,	MI2S_CODEC_RX_S_CLK,  0);
+static DEFINE_CLK_PCOM(mi2s_codec_tx_m_clk,	MI2S_CODEC_TX_M_CLK,  0);
+static DEFINE_CLK_PCOM(mi2s_codec_tx_s_clk,	MI2S_CODEC_TX_S_CLK,  0);
+static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,		CLK_MIN);
+static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,		0);
+static DEFINE_CLK_PCOM(axi_rotator_clk,	AXI_ROTATOR_CLK,	0);
+static DEFINE_CLK_PCOM(rotator_imem_clk, ROTATOR_IMEM_CLK,	OFF);
+static DEFINE_CLK_PCOM(rotator_p_clk,	ROTATOR_P_CLK,		OFF);
+static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,		OFF);
+static DEFINE_CLK_PCOM(spi_clk,		SPI_CLK,		0);
+static DEFINE_CLK_PCOM(spi_p_clk,	SPI_P_CLK,		0);
+static DEFINE_CLK_PCOM(tv_dac_clk,	TV_DAC_CLK,		0);
+static DEFINE_CLK_PCOM(tv_enc_clk,	TV_ENC_CLK,		0);
+static DEFINE_CLK_PCOM(uart2_clk,	UART2_CLK,		0);
+static DEFINE_CLK_PCOM(usb_phy_clk,	USB_PHY_CLK,		0);
+static DEFINE_CLK_PCOM(usb_hs_clk,	USB_HS_CLK,		OFF);
+static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,		OFF);
+static DEFINE_CLK_PCOM(usb_hs_core_clk,	USB_HS_CORE_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_hs2_clk,	USB_HS2_CLK,		OFF);
+static DEFINE_CLK_PCOM(usb_hs2_p_clk,	USB_HS2_P_CLK,		OFF);
+static DEFINE_CLK_PCOM(usb_hs2_core_clk,USB_HS2_CORE_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_hs3_clk,	USB_HS3_CLK,		OFF);
+static DEFINE_CLK_PCOM(usb_hs3_p_clk,	USB_HS3_P_CLK,		OFF);
+static DEFINE_CLK_PCOM(usb_hs3_core_clk,USB_HS3_CORE_CLK,	OFF);
+static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,		OFF | CLK_MIN);
+static DEFINE_CLK_PCOM(vfe_camif_clk,	VFE_CAMIF_CLK, 		0);
+static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,		0);
+static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,		0);
+static DEFINE_CLK_PCOM(vfe_p_clk,	VFE_P_CLK,		OFF);
+static DEFINE_CLK_PCOM(vpe_clk,		VPE_CLK,		0);
+
+static DEFINE_CLK_PCOM(csi0_clk,	CSI0_CLK,		0);
+static DEFINE_CLK_PCOM(csi0_p_clk,	CSI0_P_CLK,		0);
+static DEFINE_CLK_PCOM(csi0_vfe_clk,	CSI0_VFE_CLK,		0);
+
 struct clk_lookup msm_clocks_7x30[] = {
-	CLK_PCOM("adm_clk",	ADM_CLK,	NULL, 0),
-	CLK_PCOM("adsp_clk",	ADSP_CLK,	NULL, 0),
-	CLK_PCOM("cam_m_clk",	CAM_M_CLK,	NULL, 0),
-	CLK_PCOM("camif_pad_pclk",	CAMIF_PAD_P_CLK,	NULL, OFF),
-	CLK_PCOM("ce_clk",	CE_CLK,	NULL, 0),
-	CLK_PCOM("codec_ssbi_clk",	CODEC_SSBI_CLK,	NULL, 0),
-	CLK_PCOM("ebi1_clk",	EBI1_CLK,	NULL, CLK_MIN),
-	CLK_PCOM("ecodec_clk",	ECODEC_CLK,	NULL, 0),
-	CLK_PCOM("emdh_clk",	EMDH_CLK,	NULL, OFF | CLK_MINMAX),
-	CLK_PCOM("emdh_pclk",	EMDH_P_CLK,	NULL, OFF),
-	CLK_PCOM("gp_clk",	GP_CLK,		NULL, 0),
-	CLK_PCOM("grp_2d_clk",	GRP_2D_CLK,	NULL, 0),
-	CLK_PCOM("grp_2d_pclk",	GRP_2D_P_CLK,	NULL, 0),
-	CLK_PCOM("grp_clk",	GRP_3D_CLK,	NULL, 0),
-	CLK_PCOM("grp_pclk",	GRP_3D_P_CLK,	NULL, 0),
-	CLK_7X30S("grp_src_clk", GRP_3D_SRC_CLK, GRP_3D_CLK,	NULL, 0),
-	CLK_PCOM("hdmi_clk",	HDMI_CLK,	NULL, 0),
-	CLK_PCOM("imem_clk",	IMEM_CLK,	NULL, OFF),
-	CLK_PCOM("jpeg_clk",	JPEG_CLK,	NULL, OFF),
-	CLK_PCOM("jpeg_pclk",	JPEG_P_CLK,	NULL, OFF),
-	CLK_PCOM("lpa_codec_clk",	LPA_CODEC_CLK,		NULL, 0),
-	CLK_PCOM("lpa_core_clk",	LPA_CORE_CLK,		NULL, 0),
-	CLK_PCOM("lpa_pclk",		LPA_P_CLK,		NULL, 0),
-	CLK_PCOM("mdc_clk",	MDC_CLK,	NULL, 0),
-	CLK_PCOM("mddi_clk",	PMDH_CLK,	NULL, OFF | CLK_MINMAX),
-	CLK_PCOM("mddi_pclk",	PMDH_P_CLK,	NULL, 0),
-	CLK_PCOM("mdp_clk",	MDP_CLK,	NULL, OFF),
-	CLK_PCOM("mdp_pclk",	MDP_P_CLK,	NULL, 0),
-	CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
-	CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
-	CLK_PCOM("mdp_vsync_clk",	MDP_VSYNC_CLK,  NULL, 0),
-	CLK_PCOM("mfc_clk",		MFC_CLK,		NULL, 0),
-	CLK_PCOM("mfc_div2_clk",	MFC_DIV2_CLK,		NULL, 0),
-	CLK_PCOM("mfc_pclk",		MFC_P_CLK,		NULL, 0),
-	CLK_PCOM("mi2s_m_clk",		MI2S_M_CLK,  		NULL, 0),
-	CLK_PCOM("mi2s_s_clk",		MI2S_S_CLK,  		NULL, 0),
-	CLK_PCOM("mi2s_codec_rx_m_clk",	MI2S_CODEC_RX_M_CLK,  NULL, 0),
-	CLK_PCOM("mi2s_codec_rx_s_clk",	MI2S_CODEC_RX_S_CLK,  NULL, 0),
-	CLK_PCOM("mi2s_codec_tx_m_clk",	MI2S_CODEC_TX_M_CLK,  NULL, 0),
-	CLK_PCOM("mi2s_codec_tx_s_clk",	MI2S_CODEC_TX_S_CLK,  NULL, 0),
-	CLK_PCOM("pbus_clk",	PBUS_CLK,	NULL, CLK_MIN),
-	CLK_PCOM("pcm_clk",	PCM_CLK,	NULL, 0),
-	CLK_PCOM("rotator_clk",	AXI_ROTATOR_CLK,		NULL, 0),
-	CLK_PCOM("rotator_imem_clk",	ROTATOR_IMEM_CLK,	NULL, OFF),
-	CLK_PCOM("rotator_pclk",	ROTATOR_P_CLK,		NULL, OFF),
-	CLK_PCOM("sdac_clk",	SDAC_CLK,	NULL, OFF),
-	CLK_PCOM("spi_clk",	SPI_CLK,	NULL, 0),
-	CLK_PCOM("spi_pclk",	SPI_P_CLK,	NULL, 0),
-	CLK_7X30S("tv_src_clk",	TV_CLK, 	TV_ENC_CLK,	NULL, 0),
-	CLK_PCOM("tv_dac_clk",	TV_DAC_CLK,	NULL, 0),
-	CLK_PCOM("tv_enc_clk",	TV_ENC_CLK,	NULL, 0),
-	CLK_PCOM("uart_clk",	UART2_CLK,	"msm_serial.1", 0),
-	CLK_PCOM("usb_phy_clk",	USB_PHY_CLK,	NULL, 0),
-	CLK_PCOM("usb_hs_clk",		USB_HS_CLK,		NULL, OFF),
-	CLK_PCOM("usb_hs_pclk",		USB_HS_P_CLK,		NULL, OFF),
-	CLK_PCOM("usb_hs_core_clk",	USB_HS_CORE_CLK,	NULL, OFF),
-	CLK_PCOM("usb_hs2_clk",		USB_HS2_CLK,		NULL, OFF),
-	CLK_PCOM("usb_hs2_pclk",	USB_HS2_P_CLK,		NULL, OFF),
-	CLK_PCOM("usb_hs2_core_clk",	USB_HS2_CORE_CLK,	NULL, OFF),
-	CLK_PCOM("usb_hs3_clk",		USB_HS3_CLK,		NULL, OFF),
-	CLK_PCOM("usb_hs3_pclk",	USB_HS3_P_CLK,		NULL, OFF),
-	CLK_PCOM("usb_hs3_core_clk",	USB_HS3_CORE_CLK,	NULL, OFF),
-	CLK_PCOM("vdc_clk",	VDC_CLK,	NULL, OFF | CLK_MIN),
-	CLK_PCOM("vfe_camif_clk",	VFE_CAMIF_CLK, 	NULL, 0),
-	CLK_PCOM("vfe_clk",	VFE_CLK,	NULL, 0),
-	CLK_PCOM("vfe_mdc_clk",	VFE_MDC_CLK,	NULL, 0),
-	CLK_PCOM("vfe_pclk",	VFE_P_CLK,	NULL, OFF),
-	CLK_PCOM("vpe_clk",	VPE_CLK,	NULL, 0),
+	CLK_LOOKUP("adm_clk",			adm_clk.c,	"msm_dmov"),
+	CLK_LOOKUP("adsp_clk",			adsp_clk.c,	NULL),
+	CLK_LOOKUP("cam_m_clk",			cam_m_clk.c,	NULL),
+	CLK_LOOKUP("camif_pad_pclk",		camif_pad_p_clk.c,	NULL),
+	CLK_LOOKUP("ce_clk",			ce_clk.c,	NULL),
+	CLK_LOOKUP("codec_ssbi_clk",		codec_ssbi_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",			ebi1_clk.c,	NULL),
+	CLK_LOOKUP("ecodec_clk",		ecodec_clk.c,	NULL),
+	CLK_LOOKUP("emdh_clk",			emdh_clk.c,	NULL),
+	CLK_LOOKUP("emdh_pclk",			emdh_p_clk.c,	NULL),
+	CLK_LOOKUP("gp_clk",			gp_clk.c,	NULL),
+	CLK_LOOKUP("grp_2d_clk",		grp_2d_clk.c,	NULL),
+	CLK_LOOKUP("grp_2d_pclk",		grp_2d_p_clk.c,	NULL),
+	CLK_LOOKUP("grp_clk",			grp_3d_clk.c,	NULL),
+	CLK_LOOKUP("grp_pclk",			grp_3d_p_clk.c,	NULL),
+	CLK_LOOKUP("grp_src_clk",		grp_3d_clk.c,	NULL),
+	CLK_LOOKUP("hdmi_clk",			hdmi_clk.c,	NULL),
+	CLK_LOOKUP("imem_clk",			imem_clk.c,	NULL),
+	CLK_LOOKUP("jpeg_clk",			jpeg_clk.c,	NULL),
+	CLK_LOOKUP("jpeg_pclk",			jpeg_p_clk.c,	NULL),
+	CLK_LOOKUP("lpa_codec_clk",		lpa_codec_clk.c,	NULL),
+	CLK_LOOKUP("lpa_core_clk",		lpa_core_clk.c,	NULL),
+	CLK_LOOKUP("lpa_pclk",			lpa_p_clk.c,	NULL),
+	CLK_LOOKUP("mdc_clk",			mdc_clk.c,	NULL),
+	CLK_LOOKUP("mddi_clk",			pmdh_clk.c,	NULL),
+	CLK_LOOKUP("mddi_pclk",			pmdh_p_clk.c,	NULL),
+	CLK_LOOKUP("mdp_clk",			mdp_clk.c,	NULL),
+	CLK_LOOKUP("mdp_pclk",			mdp_p_clk.c,	NULL),
+	CLK_LOOKUP("mdp_lcdc_pclk_clk",		mdp_lcdc_pclk_clk.c,	NULL),
+	CLK_LOOKUP("mdp_lcdc_pad_pclk_clk",	mdp_lcdc_pad_pclk_clk.c, NULL),
+	CLK_LOOKUP("mdp_vsync_clk",		mdp_vsync_clk.c,	NULL),
+	CLK_LOOKUP("mfc_clk",			mfc_clk.c,		NULL),
+	CLK_LOOKUP("mfc_div2_clk",		mfc_div2_clk.c,		NULL),
+	CLK_LOOKUP("mfc_pclk",			mfc_p_clk.c,		NULL),
+	CLK_LOOKUP("mi2s_m_clk",		mi2s_m_clk.c,		NULL),
+	CLK_LOOKUP("mi2s_s_clk",		mi2s_s_clk.c,		NULL),
+	CLK_LOOKUP("mi2s_codec_rx_m_clk",	mi2s_codec_rx_m_clk.c,	NULL),
+	CLK_LOOKUP("mi2s_codec_rx_s_clk",	mi2s_codec_rx_s_clk.c,	NULL),
+	CLK_LOOKUP("mi2s_codec_tx_m_clk",	mi2s_codec_tx_m_clk.c,	NULL),
+	CLK_LOOKUP("mi2s_codec_tx_s_clk",	mi2s_codec_tx_s_clk.c,	NULL),
+	CLK_LOOKUP("pbus_clk",			pbus_clk.c,		NULL),
+	CLK_LOOKUP("pcm_clk",			pcm_clk.c,		NULL),
+	CLK_LOOKUP("rotator_clk",		axi_rotator_clk.c,	NULL),
+	CLK_LOOKUP("rotator_imem_clk",		rotator_imem_clk.c,	NULL),
+	CLK_LOOKUP("rotator_pclk",		rotator_p_clk.c,	NULL),
+	CLK_LOOKUP("sdac_clk",			sdac_clk.c,	NULL),
+	CLK_LOOKUP("spi_clk",			spi_clk.c,	NULL),
+	CLK_LOOKUP("spi_pclk",			spi_p_clk.c,	NULL),
+	CLK_LOOKUP("tv_src_clk",		tv_enc_clk.c,	NULL),
+	CLK_LOOKUP("tv_dac_clk",		tv_dac_clk.c,	NULL),
+	CLK_LOOKUP("tv_enc_clk",		tv_enc_clk.c,	NULL),
+	CLK_LOOKUP("uart_clk",			uart2_clk.c,	"msm_serial.1"),
+	CLK_LOOKUP("usb_phy_clk",		usb_phy_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs_clk",		usb_hs_clk.c,		NULL),
+	CLK_LOOKUP("usb_hs_pclk",		usb_hs_p_clk.c,		NULL),
+	CLK_LOOKUP("usb_hs_core_clk",		usb_hs_core_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs2_clk",		usb_hs2_clk.c,		NULL),
+	CLK_LOOKUP("usb_hs2_pclk",		usb_hs2_p_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs2_core_clk",		usb_hs2_core_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs3_clk",		usb_hs3_clk.c,		NULL),
+	CLK_LOOKUP("usb_hs3_pclk",		usb_hs3_p_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs3_core_clk",		usb_hs3_core_clk.c,	NULL),
+	CLK_LOOKUP("vdc_clk",			vdc_clk.c,		NULL),
+	CLK_LOOKUP("vfe_camif_clk",		vfe_camif_clk.c,	NULL),
+	CLK_LOOKUP("vfe_clk",			vfe_clk.c,	NULL),
+	CLK_LOOKUP("vfe_mdc_clk",		vfe_mdc_clk.c,	NULL),
+	CLK_LOOKUP("vfe_pclk",			vfe_p_clk.c,	NULL),
+	CLK_LOOKUP("vpe_clk",			vpe_clk.c,	NULL),
 
 	/* 7x30 v2 hardware only. */
-	CLK_PCOM("csi_clk",	CSI0_CLK,	NULL, 0),
-	CLK_PCOM("csi_pclk",	CSI0_P_CLK,	NULL, 0),
-	CLK_PCOM("csi_vfe_clk",	CSI0_VFE_CLK,	NULL, 0),
+	CLK_LOOKUP("csi_clk",			csi0_clk.c,	NULL),
+	CLK_LOOKUP("csi_pclk",			csi0_p_clk.c,	NULL),
+	CLK_LOOKUP("csi_vfe_clk",		csi0_vfe_clk.c,	NULL),
 };
 
 unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 131633b..cc93ce8 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -291,58 +291,110 @@ int __init msm_add_sdcc(unsigned int controller,
 	return platform_device_register(pdev);
 }
 
+static DEFINE_CLK_PCOM(adm_clk,		ADM_CLK,	0);
+static DEFINE_CLK_PCOM(ce_clk,		CE_CLK,		0);
+static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,	CLK_MIN);
+static DEFINE_CLK_PCOM(ebi2_clk,	EBI2_CLK,	0);
+static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,	0);
+static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	OFF | CLK_MINMAX);
+static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,		0);
+static DEFINE_CLK_PCOM(grp_3d_clk,	GRP_3D_CLK,	0);
+static DEFINE_CLK_PCOM(i2c_clk,		I2C_CLK,	0);
+static DEFINE_CLK_PCOM(icodec_rx_clk,	ICODEC_RX_CLK,	0);
+static DEFINE_CLK_PCOM(icodec_tx_clk,	ICODEC_TX_CLK,	0);
+static DEFINE_CLK_PCOM(imem_clk,	IMEM_CLK,	OFF);
+static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,	0);
+static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	OFF | CLK_MINMAX);
+static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,	OFF);
+static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk,	MDP_LCDC_PCLK_CLK, 0);
+static DEFINE_CLK_PCOM(mdp_lcdc_pad_pclk_clk,	MDP_LCDC_PAD_PCLK_CLK, 0);
+static DEFINE_CLK_PCOM(mdp_vsync_clk,	MDP_VSYNC_CLK,	0);
+static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,	CLK_MIN);
+static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,	0);
+static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc1_clk,	SDC1_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc1_p_clk,	SDC1_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc2_clk,	SDC2_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc2_p_clk,	SDC2_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc3_clk,	SDC3_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc3_p_clk,	SDC3_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc4_clk,	SDC4_CLK,	OFF);
+static DEFINE_CLK_PCOM(sdc4_p_clk,	SDC4_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(spi_clk,		SPI_CLK,	0);
+static DEFINE_CLK_PCOM(tsif_clk,	TSIF_CLK,	0);
+static DEFINE_CLK_PCOM(tsif_ref_clk,	TSIF_REF_CLK,	0);
+static DEFINE_CLK_PCOM(tv_dac_clk,	TV_DAC_CLK,	0);
+static DEFINE_CLK_PCOM(tv_enc_clk,	TV_ENC_CLK,	0);
+static DEFINE_CLK_PCOM(uart1_clk,	UART1_CLK,	OFF);
+static DEFINE_CLK_PCOM(uart2_clk,	UART2_CLK,	0);
+static DEFINE_CLK_PCOM(uart3_clk,	UART3_CLK,	OFF);
+static DEFINE_CLK_PCOM(uart1dm_clk,	UART1DM_CLK,	OFF);
+static DEFINE_CLK_PCOM(uart2dm_clk,	UART2DM_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs_clk,	USB_HS_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_otg_clk,	USB_OTG_CLK,	0);
+static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	OFF | CLK_MIN);
+static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,	OFF);
+static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,	OFF);
+static DEFINE_CLK_PCOM(vfe_axi_clk,	VFE_AXI_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_hs2_clk,	USB_HS2_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_hs2_p_clk,	USB_HS2_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_hs3_clk,	USB_HS3_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_hs3_p_clk,	USB_HS3_P_CLK,	OFF);
+static DEFINE_CLK_PCOM(usb_phy_clk,	USB_PHY_CLK,	0);
+
 struct clk_lookup msm_clocks_8x50[] = {
-	CLK_PCOM("adm_clk",	ADM_CLK,	NULL, 0),
-	CLK_PCOM("ce_clk",	CE_CLK,		NULL, 0),
-	CLK_PCOM("ebi1_clk",	EBI1_CLK,	NULL, CLK_MIN),
-	CLK_PCOM("ebi2_clk",	EBI2_CLK,	NULL, 0),
-	CLK_PCOM("ecodec_clk",	ECODEC_CLK,	NULL, 0),
-	CLK_PCOM("emdh_clk",	EMDH_CLK,	NULL, OFF | CLK_MINMAX),
-	CLK_PCOM("gp_clk",	GP_CLK,		NULL, 0),
-	CLK_PCOM("grp_clk",	GRP_3D_CLK,	NULL, 0),
-	CLK_PCOM("i2c_clk",	I2C_CLK,	NULL, 0),
-	CLK_PCOM("icodec_rx_clk",	ICODEC_RX_CLK,	NULL, 0),
-	CLK_PCOM("icodec_tx_clk",	ICODEC_TX_CLK,	NULL, 0),
-	CLK_PCOM("imem_clk",	IMEM_CLK,	NULL, OFF),
-	CLK_PCOM("mdc_clk",	MDC_CLK,	NULL, 0),
-	CLK_PCOM("mddi_clk",	PMDH_CLK,	NULL, OFF | CLK_MINMAX),
-	CLK_PCOM("mdp_clk",	MDP_CLK,	NULL, OFF),
-	CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
-	CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
-	CLK_PCOM("mdp_vsync_clk",	MDP_VSYNC_CLK,	NULL, 0),
-	CLK_PCOM("pbus_clk",	PBUS_CLK,	NULL, CLK_MIN),
-	CLK_PCOM("pcm_clk",	PCM_CLK,	NULL, 0),
-	CLK_PCOM("sdac_clk",	SDAC_CLK,	NULL, OFF),
-	CLK_PCOM("sdc_clk",	SDC1_CLK,	"msm_sdcc.1", OFF),
-	CLK_PCOM("sdc_pclk",	SDC1_P_CLK,	"msm_sdcc.1", OFF),
-	CLK_PCOM("sdc_clk",	SDC2_CLK,	"msm_sdcc.2", OFF),
-	CLK_PCOM("sdc_pclk",	SDC2_P_CLK,	"msm_sdcc.2", OFF),
-	CLK_PCOM("sdc_clk",	SDC3_CLK,	"msm_sdcc.3", OFF),
-	CLK_PCOM("sdc_pclk",	SDC3_P_CLK,	"msm_sdcc.3", OFF),
-	CLK_PCOM("sdc_clk",	SDC4_CLK,	"msm_sdcc.4", OFF),
-	CLK_PCOM("sdc_pclk",	SDC4_P_CLK,	"msm_sdcc.4", OFF),
-	CLK_PCOM("spi_clk",	SPI_CLK,	NULL, 0),
-	CLK_PCOM("tsif_clk",	TSIF_CLK,	NULL, 0),
-	CLK_PCOM("tsif_ref_clk",	TSIF_REF_CLK,	NULL, 0),
-	CLK_PCOM("tv_dac_clk",	TV_DAC_CLK,	NULL, 0),
-	CLK_PCOM("tv_enc_clk",	TV_ENC_CLK,	NULL, 0),
-	CLK_PCOM("uart_clk",	UART1_CLK,	NULL, OFF),
-	CLK_PCOM("uart_clk",	UART2_CLK,	NULL, 0),
-	CLK_PCOM("uart_clk",	UART3_CLK,	"msm_serial.2", OFF),
-	CLK_PCOM("uartdm_clk",	UART1DM_CLK,	NULL, OFF),
-	CLK_PCOM("uartdm_clk",	UART2DM_CLK,	NULL, 0),
-	CLK_PCOM("usb_hs_clk",	USB_HS_CLK,	NULL, OFF),
-	CLK_PCOM("usb_hs_pclk",	USB_HS_P_CLK,	NULL, OFF),
-	CLK_PCOM("usb_otg_clk",	USB_OTG_CLK,	NULL, 0),
-	CLK_PCOM("vdc_clk",	VDC_CLK,	NULL, OFF | CLK_MIN),
-	CLK_PCOM("vfe_clk",	VFE_CLK,	NULL, OFF),
-	CLK_PCOM("vfe_mdc_clk",	VFE_MDC_CLK,	NULL, OFF),
-	CLK_PCOM("vfe_axi_clk",	VFE_AXI_CLK,	NULL, OFF),
-	CLK_PCOM("usb_hs2_clk",	USB_HS2_CLK,	NULL, OFF),
-	CLK_PCOM("usb_hs2_pclk",	USB_HS2_P_CLK,	NULL, OFF),
-	CLK_PCOM("usb_hs3_clk",	USB_HS3_CLK,	NULL, OFF),
-	CLK_PCOM("usb_hs3_pclk",	USB_HS3_P_CLK,	NULL, OFF),
-	CLK_PCOM("usb_phy_clk",	USB_PHY_CLK,	NULL, 0),
+	CLK_LOOKUP("adm_clk",		adm_clk.c,	"msm_dmov"),
+	CLK_LOOKUP("ce_clk",		ce_clk.c,		NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_clk.c,	NULL),
+	CLK_LOOKUP("ebi2_clk",		ebi2_clk.c,	NULL),
+	CLK_LOOKUP("ecodec_clk",	ecodec_clk.c,	NULL),
+	CLK_LOOKUP("emdh_clk",		emdh_clk.c,	NULL),
+	CLK_LOOKUP("gp_clk",		gp_clk.c,		NULL),
+	CLK_LOOKUP("grp_clk",		grp_3d_clk.c,	NULL),
+	CLK_LOOKUP("i2c_clk",		i2c_clk.c,	NULL),
+	CLK_LOOKUP("icodec_rx_clk",	icodec_rx_clk.c,	NULL),
+	CLK_LOOKUP("icodec_tx_clk",	icodec_tx_clk.c,	NULL),
+	CLK_LOOKUP("imem_clk",		imem_clk.c,	NULL),
+	CLK_LOOKUP("mdc_clk",		mdc_clk.c,	NULL),
+	CLK_LOOKUP("mddi_clk",		pmdh_clk.c,	NULL),
+	CLK_LOOKUP("mdp_clk",		mdp_clk.c,	NULL),
+	CLK_LOOKUP("mdp_lcdc_pclk_clk",	mdp_lcdc_pclk_clk.c, NULL),
+	CLK_LOOKUP("mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk.c, NULL),
+	CLK_LOOKUP("mdp_vsync_clk",	mdp_vsync_clk.c,	NULL),
+	CLK_LOOKUP("pbus_clk",		pbus_clk.c,	NULL),
+	CLK_LOOKUP("pcm_clk",		pcm_clk.c,	NULL),
+	CLK_LOOKUP("sdac_clk",		sdac_clk.c,	NULL),
+	CLK_LOOKUP("sdc_clk",		sdc1_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_pclk",		sdc1_p_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_clk",		sdc2_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_pclk",		sdc2_p_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_clk",		sdc3_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_pclk",		sdc3_p_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_clk",		sdc4_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("sdc_pclk",		sdc4_p_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("spi_clk",		spi_clk.c,	NULL),
+	CLK_LOOKUP("tsif_clk",		tsif_clk.c,	NULL),
+	CLK_LOOKUP("tsif_ref_clk",	tsif_ref_clk.c,	NULL),
+	CLK_LOOKUP("tv_dac_clk",	tv_dac_clk.c,	NULL),
+	CLK_LOOKUP("tv_enc_clk",	tv_enc_clk.c,	NULL),
+	CLK_LOOKUP("uart_clk",		uart1_clk.c,	NULL),
+	CLK_LOOKUP("uart_clk",		uart2_clk.c,	NULL),
+	CLK_LOOKUP("uart_clk",		uart3_clk.c,	"msm_serial.2"),
+	CLK_LOOKUP("uartdm_clk",	uart1dm_clk.c,	NULL),
+	CLK_LOOKUP("uartdm_clk",	uart2dm_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs_clk",	usb_hs_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs_pclk",	usb_hs_p_clk.c,	NULL),
+	CLK_LOOKUP("usb_otg_clk",	usb_otg_clk.c,	NULL),
+	CLK_LOOKUP("vdc_clk",		vdc_clk.c,	NULL),
+	CLK_LOOKUP("vfe_clk",		vfe_clk.c,	NULL),
+	CLK_LOOKUP("vfe_mdc_clk",	vfe_mdc_clk.c,	NULL),
+	CLK_LOOKUP("vfe_axi_clk",	vfe_axi_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs2_clk",	usb_hs2_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs2_pclk",	usb_hs2_p_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs3_clk",	usb_hs3_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs3_pclk",	usb_hs3_p_clk.c,	NULL),
+	CLK_LOOKUP("usb_phy_clk",	usb_phy_clk.c,	NULL),
 };
 
 unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 06/34] msm: clock: Support clk_[s|g]et_parent() clk_ops

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Voting clocks are linked to the clock they vote on with a parent
pointer. Add support for these functions so the upcoming clock
voter sub driver can use it to initialize clocks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock.c |    7 ++++++-
 arch/arm/mach-msm/clock.h |    2 ++
 2 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index aa4a450..8508c17 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -106,13 +106,18 @@ EXPORT_SYMBOL(clk_set_max_rate);
 
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
+	if (clk->ops->set_parent)
+		return clk->ops->set_parent(clk, parent);
 	return -ENOSYS;
 }
 EXPORT_SYMBOL(clk_set_parent);
 
 struct clk *clk_get_parent(struct clk *clk)
 {
-	return ERR_PTR(-ENOSYS);
+	if (clk->ops->get_parent)
+		return clk->ops->get_parent(clk);
+
+	return NULL;
 }
 EXPORT_SYMBOL(clk_get_parent);
 
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index ab14f15..6a7cbca 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -44,6 +44,8 @@ struct clk_ops {
 	unsigned (*get_rate)(struct clk *clk);
 	unsigned (*is_enabled)(struct clk *clk);
 	long (*round_rate)(struct clk *clk, unsigned rate);
+	int (*set_parent)(struct clk *clk, struct clk *parent);
+	struct clk *(*get_parent)(struct clk *clk);
 	bool (*is_local)(struct clk *clk);
 };
 
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 07/34] msm: clock-debug: Use clk_enable()/clk_disable() directly

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

The debugfs operations currently sidestep the top level
enable/disable code and directly call the ops->enable/disable
functions. This won't work well when we generically enable parent
clocks in the toplevel clock code. Therefore call enable/disable
directly from the debugfs code to get proper parent enabling.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-debug.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index bddcbc9..a8db06d 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -55,9 +55,9 @@ static int clock_debug_enable_set(void *data, u64 val)
 	int rc = 0;
 
 	if (val)
-		rc = clock->ops->enable(clock);
+		rc = clk_enable(clock);
 	else
-		clock->ops->disable(clock);
+		clk_disable(clock);
 
 	return rc;
 }
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 08/34] msm: clock: Enable/disable parent clocks generically

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Enable the parent clocks whenever a clock is enabled and disable
a parent clock whenever a clock is disabled. This simplifies
sub-driver code by centralizing the parent enabling in the
top-level.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock.c |   33 +++++++++++++++++++++++++++++----
 1 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 8508c17..026bdc0 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -31,24 +31,49 @@
  */
 int clk_enable(struct clk *clk)
 {
+	int ret = 0;
 	unsigned long flags;
+	struct clk *parent;
+
+	if (!clk)
+		return 0;
+
 	spin_lock_irqsave(&clk->lock, flags);
+	if (clk->count == 0) {
+		parent = clk_get_parent(clk);
+		ret = clk_enable(parent);
+		if (ret)
+			goto out;
+
+		ret = clk->ops->enable(clk);
+		if (ret) {
+			clk_disable(parent);
+			goto out;
+		}
+	}
 	clk->count++;
-	if (clk->count == 1)
-		clk->ops->enable(clk);
+out:
 	spin_unlock_irqrestore(&clk->lock, flags);
-	return 0;
+	return ret;
 }
 EXPORT_SYMBOL(clk_enable);
 
 void clk_disable(struct clk *clk)
 {
 	unsigned long flags;
+	struct clk *parent;
+
+	if (!clk)
+		return;
+
 	spin_lock_irqsave(&clk->lock, flags);
 	BUG_ON(clk->count == 0);
 	clk->count--;
-	if (clk->count == 0)
+	if (clk->count == 0) {
 		clk->ops->disable(clk);
+		parent = clk_get_parent(clk);
+		clk_disable(parent);
+	}
 	spin_unlock_irqrestore(&clk->lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 09/34] msm: clock: Implement rate voting

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Some clocks have multiple consumers where each consumer requires
a minimum rate. Implement a sub driver to aggregate
clk_set_rate() calls from each consumer and call clk_set_rate()
on the parent clock when the minimum requested rate of all the
voters changes.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/Makefile      |    1 +
 arch/arm/mach-msm/clock-pcom.h  |    2 +-
 arch/arm/mach-msm/clock-voter.c |  187 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/clock-voter.h |   41 +++++++++
 arch/arm/mach-msm/clock.c       |   18 ++---
 arch/arm/mach-msm/clock.h       |    9 ++
 6 files changed, 245 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mach-msm/clock-voter.c
 create mode 100644 arch/arm/mach-msm/clock-voter.h

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 4285dfd..5318553 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,5 +1,6 @@
 obj-y += io.o idle.o timer.o
 obj-y += clock.o
+obj-y += clock-voter.o
 obj-$(CONFIG_DEBUG_FS) += clock-debug.o
 
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
index 955c917..a5ac74d 100644
--- a/arch/arm/mach-msm/clock-pcom.h
+++ b/arch/arm/mach-msm/clock-pcom.h
@@ -145,7 +145,7 @@ static inline struct pcom_clk *to_pcom_clk(struct clk *clk)
 			.ops = &clk_ops_pcom, \
 			.flags = clk_flags, \
 			.dbg_name = #clk_id, \
-			.lock = __SPIN_LOCK_UNLOCKED(clk_name.c), \
+			CLK_INIT(clk_name.c), \
 		}, \
 	}
 
diff --git a/arch/arm/mach-msm/clock-voter.c b/arch/arm/mach-msm/clock-voter.c
new file mode 100644
index 0000000..6da4384
--- /dev/null
+++ b/arch/arm/mach-msm/clock-voter.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/clk.h>
+
+#include "clock.h"
+#include "clock-voter.h"
+
+static DEFINE_SPINLOCK(voter_clk_lock);
+
+/* Aggregate the rate of clocks that are currently on. */
+static unsigned voter_clk_aggregate_rate(const struct clk *parent)
+{
+	struct clk *clk;
+	unsigned rate = 0;
+
+	list_for_each_entry(clk, &parent->children, siblings) {
+		struct clk_voter *v = to_clk_voter(clk);
+		if (v->enabled)
+			rate = max(v->rate, rate);
+	}
+	return rate;
+}
+
+static int voter_clk_set_rate(struct clk *clk, unsigned rate)
+{
+	int ret = 0;
+	unsigned long flags;
+	struct clk *clkp;
+	struct clk_voter *clkh, *v = to_clk_voter(clk);
+	unsigned cur_rate, new_rate, other_rate = 0;
+
+	spin_lock_irqsave(&voter_clk_lock, flags);
+
+	if (v->enabled) {
+		struct clk *parent = v->parent;
+
+		/*
+		 * Get the aggregate rate without this clock's vote and update
+		 * if the new rate is different than the current rate
+		 */
+		list_for_each_entry(clkp, &parent->children, siblings) {
+			clkh = to_clk_voter(clkp);
+			if (clkh->enabled && clkh != v)
+				other_rate = max(clkh->rate, other_rate);
+		}
+
+		cur_rate = max(other_rate, v->rate);
+		new_rate = max(other_rate, rate);
+
+		if (new_rate != cur_rate) {
+			ret = clk_set_min_rate(parent, new_rate);
+			if (ret)
+				goto unlock;
+		}
+	}
+	v->rate = rate;
+unlock:
+	spin_unlock_irqrestore(&voter_clk_lock, flags);
+
+	return ret;
+}
+
+static int voter_clk_enable(struct clk *clk)
+{
+	int ret;
+	unsigned long flags;
+	unsigned cur_rate;
+	struct clk *parent;
+	struct clk_voter *v = to_clk_voter(clk);
+
+	spin_lock_irqsave(&voter_clk_lock, flags);
+	parent = v->parent;
+
+	/*
+	 * Increase the rate if this clock is voting for a higher rate
+	 * than the current rate.
+	 */
+	cur_rate = voter_clk_aggregate_rate(parent);
+	if (v->rate > cur_rate) {
+		ret = clk_set_min_rate(parent, v->rate);
+		if (ret)
+			goto out;
+	}
+	v->enabled = true;
+out:
+	spin_unlock_irqrestore(&voter_clk_lock, flags);
+
+	return ret;
+}
+
+static void voter_clk_disable(struct clk *clk)
+{
+	unsigned long flags;
+	struct clk *parent;
+	struct clk_voter *v = to_clk_voter(clk);
+	unsigned cur_rate, new_rate;
+
+	spin_lock_irqsave(&voter_clk_lock, flags);
+	parent = v->parent;
+
+	/*
+	 * Decrease the rate if this clock was the only one voting for
+	 * the highest rate.
+	 */
+	v->enabled = false;
+	new_rate = voter_clk_aggregate_rate(parent);
+	cur_rate = max(new_rate, v->rate);
+
+	if (new_rate < cur_rate)
+		clk_set_min_rate(parent, new_rate);
+
+	spin_unlock_irqrestore(&voter_clk_lock, flags);
+}
+
+static unsigned voter_clk_get_rate(struct clk *clk)
+{
+	unsigned rate;
+	unsigned long flags;
+	struct clk_voter *v = to_clk_voter(clk);
+
+	spin_lock_irqsave(&voter_clk_lock, flags);
+	rate = v->rate;
+	spin_unlock_irqrestore(&voter_clk_lock, flags);
+
+	return rate;
+}
+
+static unsigned voter_clk_is_enabled(struct clk *clk)
+{
+	struct clk_voter *v = to_clk_voter(clk);
+	return v->enabled;
+}
+
+static long voter_clk_round_rate(struct clk *clk, unsigned rate)
+{
+	struct clk_voter *v = to_clk_voter(clk);
+	return clk_round_rate(v->parent, rate);
+}
+
+static int voter_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&voter_clk_lock, flags);
+	if (list_empty(&clk->siblings))
+		list_add(&clk->siblings, &parent->children);
+	spin_unlock_irqrestore(&voter_clk_lock, flags);
+
+	return 0;
+}
+
+static struct clk *voter_clk_get_parent(struct clk *clk)
+{
+	struct clk_voter *v = to_clk_voter(clk);
+	return v->parent;
+}
+
+static bool voter_clk_is_local(struct clk *clk)
+{
+	return true;
+}
+
+struct clk_ops clk_ops_voter = {
+	.enable = voter_clk_enable,
+	.disable = voter_clk_disable,
+	.set_rate = voter_clk_set_rate,
+	.set_min_rate = voter_clk_set_rate,
+	.get_rate = voter_clk_get_rate,
+	.is_enabled = voter_clk_is_enabled,
+	.round_rate = voter_clk_round_rate,
+	.set_parent = voter_clk_set_parent,
+	.get_parent = voter_clk_get_parent,
+	.is_local = voter_clk_is_local,
+};
diff --git a/arch/arm/mach-msm/clock-voter.h b/arch/arm/mach-msm/clock-voter.h
new file mode 100644
index 0000000..170ba67
--- /dev/null
+++ b/arch/arm/mach-msm/clock-voter.h
@@ -0,0 +1,41 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_CLOCK_VOTER_H
+#define __ARCH_ARM_MACH_MSM_CLOCK_VOTER_H
+
+struct clk_ops;
+extern struct clk_ops clk_ops_voter;
+
+struct clk_voter {
+	bool enabled;
+	unsigned rate;
+	struct clk *parent;
+	struct clk c;
+};
+
+static inline struct clk_voter *to_clk_voter(struct clk *clk)
+{
+	return container_of(clk, struct clk_voter, c);
+}
+
+#define DEFINE_CLK_VOTER(clk_name, _parent) \
+	struct clk_voter clk_name = { \
+		.parent = _parent, \
+		.c = { \
+			.dbg_name = #clk_name, \
+			.ops = &clk_ops_voter, \
+			CLK_INIT(clk_name.c), \
+		}, \
+	}
+
+#endif
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 026bdc0..ad55eaa 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -154,12 +154,6 @@ int clk_set_flags(struct clk *clk, unsigned long flags)
 }
 EXPORT_SYMBOL(clk_set_flags);
 
-/* EBI1 is the only shared clock that several clients want to vote on as of
- * this commit. If this changes in the future, then it might be better to
- * make clk_min_rate handle the voting or make ebi1_clk_set_min_rate more
- * generic to support different clocks.
- */
-static struct clk *ebi1_clk;
 static struct clk_lookup *msm_clocks;
 static unsigned msm_num_clocks;
 
@@ -167,13 +161,13 @@ void __init msm_clock_init(struct clk_lookup *clock_tbl, size_t num_clocks)
 {
 	unsigned n;
 
-	clkdev_add_table(clock_tbl, num_clocks);
-
-	for (n = 0; n < num_clocks; n++)
-		spin_lock_init(&clock_tbl[n].clk->lock);
+	for (n = 0; n < num_clocks; n++) {
+		struct clk *clk = clock_tbl[n].clk;
+		struct clk *parent = clk_get_parent(clk);
+		clk_set_parent(clk, parent);
+	}
 
-	ebi1_clk = clk_get(NULL, "ebi1_clk");
-	BUG_ON(ebi1_clk == NULL);
+	clkdev_add_table(clock_tbl, num_clocks);
 
 	msm_clocks = clock_tbl;
 	msm_num_clocks = num_clocks;
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 6a7cbca..6aecd95 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -55,9 +55,18 @@ struct clk {
 	uint32_t flags;
 	struct clk_ops *ops;
 	const char *dbg_name;
+
+	struct list_head children;
+	struct list_head siblings;
+
 	spinlock_t lock;
 };
 
+#define CLK_INIT(name) \
+	.lock = __SPIN_LOCK_UNLOCKED((name).lock), \
+	.children = LIST_HEAD_INIT((name).children), \
+	.siblings = LIST_HEAD_INIT((name).siblings)
+
 #define OFF CLKFLAG_AUTO_OFF
 #define CLK_MIN CLKFLAG_MIN
 #define CLK_MAX CLKFLAG_MAX
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 10/34] msm: clock-pcom: Add pbus specific clock ops

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

The pbus clock always runs at half the ebi1 clock frequency.
Since ebi1 clock votes are dropped when the application processor
is power collapsed, the ebi1 clock is reserved for the acpuclock
driver. Other drivers which have ebi1 clock requirements that are
independent of application processor power status use the pbus.
To keep this change transparent across drivers and SoCs, add new
ops that divides the rate by 2 before sending the request to the
modem.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-pcom.c      |   29 +++++++++++++++++++++++++++++
 arch/arm/mach-msm/clock-pcom.h      |    1 +
 arch/arm/mach-msm/devices-msm7x30.c |   11 ++++++++++-
 3 files changed, 40 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index 24ddfd8..e11ef57 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -145,3 +145,32 @@ struct clk_ops clk_ops_pcom = {
 	.round_rate = pc_clk_round_rate,
 	.is_local = pc_clk_is_local,
 };
+
+int pc_clk_set_rate2(struct clk *clk, unsigned rate)
+{
+	return pc_clk_set_rate(clk, rate / 2);
+}
+
+int pc_clk_set_min_rate2(struct clk *clk, unsigned rate)
+{
+	return pc_clk_set_min_rate(clk, rate / 2);
+}
+
+unsigned pc_clk_get_rate2(struct clk *clk)
+{
+	return pc_clk_get_rate(clk) * 2;
+}
+
+struct clk_ops clk_ops_pcom_div2 = {
+	.enable = pc_clk_enable,
+	.disable = pc_clk_disable,
+	.auto_off = pc_clk_disable,
+	.reset = pc_clk_reset,
+	.set_rate = pc_clk_set_rate2,
+	.set_min_rate = pc_clk_set_min_rate2,
+	.set_flags = pc_clk_set_flags,
+	.get_rate = pc_clk_get_rate2,
+	.is_enabled = pc_clk_is_enabled,
+	.round_rate = pc_clk_round_rate,
+	.is_local = pc_clk_is_local,
+};
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
index a5ac74d..23807ff 100644
--- a/arch/arm/mach-msm/clock-pcom.h
+++ b/arch/arm/mach-msm/clock-pcom.h
@@ -122,6 +122,7 @@
 
 struct clk_ops;
 extern struct clk_ops clk_ops_pcom;
+extern struct clk_ops clk_ops_pcom_div2;
 
 /**
  * struct pcom_clk - proc_comm controlled clock
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 1ebb22d..7a548a2 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -169,7 +169,6 @@ static DEFINE_CLK_PCOM(mi2s_codec_rx_m_clk,	MI2S_CODEC_RX_M_CLK,  0);
 static DEFINE_CLK_PCOM(mi2s_codec_rx_s_clk,	MI2S_CODEC_RX_S_CLK,  0);
 static DEFINE_CLK_PCOM(mi2s_codec_tx_m_clk,	MI2S_CODEC_TX_M_CLK,  0);
 static DEFINE_CLK_PCOM(mi2s_codec_tx_s_clk,	MI2S_CODEC_TX_S_CLK,  0);
-static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,		CLK_MIN);
 static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,		0);
 static DEFINE_CLK_PCOM(axi_rotator_clk,	AXI_ROTATOR_CLK,	0);
 static DEFINE_CLK_PCOM(rotator_imem_clk, ROTATOR_IMEM_CLK,	OFF);
@@ -201,6 +200,16 @@ static DEFINE_CLK_PCOM(csi0_clk,	CSI0_CLK,		0);
 static DEFINE_CLK_PCOM(csi0_p_clk,	CSI0_P_CLK,		0);
 static DEFINE_CLK_PCOM(csi0_vfe_clk,	CSI0_VFE_CLK,		0);
 
+static struct pcom_clk pbus_clk = {
+	.id = P_PBUS_CLK,
+	.c = {
+		.dbg_name = "pbus_clk",
+		.ops = &clk_ops_pcom_div2,
+		.flags = CLK_MIN,
+		CLK_INIT(pbus_clk.c),
+	},
+};
+
 struct clk_lookup msm_clocks_7x30[] = {
 	CLK_LOOKUP("adm_clk",			adm_clk.c,	"msm_dmov"),
 	CLK_LOOKUP("adsp_clk",			adsp_clk.c,	NULL),
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 11/34] msm: Migrate to clock rate voting

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Add the appropriate clock voters and integrate clock.c with the
voting driver so that voting works appropriately.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/devices-msm7x30.c |   19 +++++++++++++++++++
 arch/arm/mach-msm/devices-qsd8x50.c |   17 +++++++++++++++++
 2 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 7a548a2..6574b7a 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -24,6 +24,7 @@
 #include <mach/board.h>
 
 #include "devices.h"
+#include "clock-voter.h"
 #include "smd_private.h"
 
 #include <asm/mach/flash.h>
@@ -210,6 +211,15 @@ static struct pcom_clk pbus_clk = {
 	},
 };
 
+static DEFINE_CLK_VOTER(ebi1_dtv_clk,	&pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi1_kgsl_clk,	&pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi1_lcdc_clk,	&pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi1_mddi_clk,	&pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi1_tv_clk,	&pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi1_usb_clk,	&pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi1_vcd_clk,	&pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi1_vfe_clk,	&pbus_clk.c);
+
 struct clk_lookup msm_clocks_7x30[] = {
 	CLK_LOOKUP("adm_clk",			adm_clk.c,	"msm_dmov"),
 	CLK_LOOKUP("adsp_clk",			adsp_clk.c,	NULL),
@@ -284,6 +294,15 @@ struct clk_lookup msm_clocks_7x30[] = {
 	CLK_LOOKUP("csi_clk",			csi0_clk.c,	NULL),
 	CLK_LOOKUP("csi_pclk",			csi0_p_clk.c,	NULL),
 	CLK_LOOKUP("csi_vfe_clk",		csi0_vfe_clk.c,	NULL),
+
+	CLK_LOOKUP("ebi1_clk",	ebi1_dtv_clk.c,		NULL),
+	CLK_LOOKUP("ebi1_clk",	ebi1_kgsl_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",	ebi1_lcdc_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",	ebi1_mddi_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",	ebi1_tv_clk.c,		NULL),
+	CLK_LOOKUP("ebi1_clk",	ebi1_usb_clk.c,		NULL),
+	CLK_LOOKUP("ebi1_clk",	ebi1_vcd_clk.c,		NULL),
+	CLK_LOOKUP("ebi1_clk",	ebi1_vfe_clk.c,		NULL),
 };
 
 unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index cc93ce8..21a1f3a 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -29,6 +29,7 @@
 
 #include <mach/mmc.h>
 #include "clock-pcom.h"
+#include "clock-voter.h"
 
 static struct resource resources_uart3[] = {
 	{
@@ -343,6 +344,14 @@ static DEFINE_CLK_PCOM(usb_hs3_clk,	USB_HS3_CLK,	OFF);
 static DEFINE_CLK_PCOM(usb_hs3_p_clk,	USB_HS3_P_CLK,	OFF);
 static DEFINE_CLK_PCOM(usb_phy_clk,	USB_PHY_CLK,	0);
 
+static DEFINE_CLK_VOTER(ebi1_acpu_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi1_kgsl_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi1_lcdc_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi1_mddi_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi1_tv_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi1_usb_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi1_vfe_clk,	&ebi1_clk.c);
+
 struct clk_lookup msm_clocks_8x50[] = {
 	CLK_LOOKUP("adm_clk",		adm_clk.c,	"msm_dmov"),
 	CLK_LOOKUP("ce_clk",		ce_clk.c,		NULL),
@@ -395,6 +404,14 @@ struct clk_lookup msm_clocks_8x50[] = {
 	CLK_LOOKUP("usb_hs3_clk",	usb_hs3_clk.c,	NULL),
 	CLK_LOOKUP("usb_hs3_pclk",	usb_hs3_p_clk.c,	NULL),
 	CLK_LOOKUP("usb_phy_clk",	usb_phy_clk.c,	NULL),
+
+	CLK_LOOKUP("ebi1_clk",		ebi1_acpu_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_kgsl_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_lcdc_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_mddi_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_tv_clk.c,		NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_usb_clk.c,		NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_vfe_clk.c,		NULL),
 };
 
 unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 12/34] msm: clock: Make most clk_*() operations optional

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Not all clock drivers want to implement support for all the
clk_*() operations. Since only clk_enable(), clk_disable(), and
clk_set_rate() are mandatory, allow the other clk_*() functions
to be optionally implemented by subdrivers. Also make
clk_enable() and clk_disable() optional so that clocks with no
on/off support don't have to define empty clk_enable/disable ops.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock.c |   43 ++++++++++++++++++++++++++++++++++---------
 1 files changed, 34 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index ad55eaa..b571a95 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -1,7 +1,7 @@
 /* arch/arm/mach-msm/clock.c
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -45,7 +45,8 @@ int clk_enable(struct clk *clk)
 		if (ret)
 			goto out;
 
-		ret = clk->ops->enable(clk);
+		if (clk->ops->enable)
+			ret = clk->ops->enable(clk);
 		if (ret) {
 			clk_disable(parent);
 			goto out;
@@ -70,7 +71,8 @@ void clk_disable(struct clk *clk)
 	BUG_ON(clk->count == 0);
 	clk->count--;
 	if (clk->count == 0) {
-		clk->ops->disable(clk);
+		if (clk->ops->disable)
+			clk->ops->disable(clk);
 		parent = clk_get_parent(clk);
 		clk_disable(parent);
 	}
@@ -80,12 +82,18 @@ EXPORT_SYMBOL(clk_disable);
 
 int clk_reset(struct clk *clk, enum clk_reset_action action)
 {
+	if (!clk->ops->reset)
+		return -ENOSYS;
+
 	return clk->ops->reset(clk, action);
 }
 EXPORT_SYMBOL(clk_reset);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
+	if (!clk->ops->get_rate)
+		return 0;
+
 	return clk->ops->get_rate(clk);
 }
 EXPORT_SYMBOL(clk_get_rate);
@@ -93,6 +101,10 @@ EXPORT_SYMBOL(clk_get_rate);
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
 	int ret;
+
+	if (!clk->ops->set_rate)
+		return -ENOSYS;
+
 	if (clk->flags & CLKFLAG_MAX) {
 		ret = clk->ops->set_max_rate(clk, rate);
 		if (ret)
@@ -113,36 +125,46 @@ EXPORT_SYMBOL(clk_set_rate);
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
+	if (!clk->ops->round_rate)
+		return -ENOSYS;
+
 	return clk->ops->round_rate(clk, rate);
 }
 EXPORT_SYMBOL(clk_round_rate);
 
 int clk_set_min_rate(struct clk *clk, unsigned long rate)
 {
+	if (!clk->ops->set_min_rate)
+		return -ENOSYS;
+
 	return clk->ops->set_min_rate(clk, rate);
 }
 EXPORT_SYMBOL(clk_set_min_rate);
 
 int clk_set_max_rate(struct clk *clk, unsigned long rate)
 {
+	if (!clk->ops->set_max_rate)
+		return -ENOSYS;
+
 	return clk->ops->set_max_rate(clk, rate);
 }
 EXPORT_SYMBOL(clk_set_max_rate);
 
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
-	if (clk->ops->set_parent)
-		return clk->ops->set_parent(clk, parent);
-	return -ENOSYS;
+	if (!clk->ops->set_parent)
+		return 0;
+
+	return clk->ops->set_parent(clk, parent);
 }
 EXPORT_SYMBOL(clk_set_parent);
 
 struct clk *clk_get_parent(struct clk *clk)
 {
-	if (clk->ops->get_parent)
-		return clk->ops->get_parent(clk);
+	if (!clk->ops->get_parent)
+		return NULL;
 
-	return NULL;
+	return clk->ops->get_parent(clk);
 }
 EXPORT_SYMBOL(clk_get_parent);
 
@@ -150,6 +172,9 @@ int clk_set_flags(struct clk *clk, unsigned long flags)
 {
 	if (clk == NULL || IS_ERR(clk))
 		return -EINVAL;
+	if (!clk->ops->set_flags)
+		return -ENOSYS;
+
 	return clk->ops->set_flags(clk, flags);
 }
 EXPORT_SYMBOL(clk_set_flags);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 13/34] msm: clock-debug: Implement a default is_enabled()

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Some clocks are simple enough that determining if they are
enabled or disabled can be done by reading the 'count' member of
struct clk. Implement support for such clocks in clock-debug.c so
that these types of clocks don't need to implement the
is_enabled() ops.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-debug.c |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index a8db06d..472a735 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -65,9 +65,14 @@ static int clock_debug_enable_set(void *data, u64 val)
 static int clock_debug_enable_get(void *data, u64 *val)
 {
 	struct clk *clock = data;
+	int enabled;
 
-	*val = clock->ops->is_enabled(clock);
+	if (clock->ops->is_enabled)
+		enabled = clock->ops->is_enabled(clock);
+	else
+		enabled = !!(clock->count);
 
+	*val = enabled;
 	return 0;
 }
 
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 14/34] msm: proc_comm: Add CLKCTL_RPC_SRC_REQUEST

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

This proc_comm command is used to vote for crystal oscillators on
7x30/8x55 variants.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/proc_comm.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/proc_comm.h b/arch/arm/mach-msm/proc_comm.h
index 12da4ca..e2f2d5a 100644
--- a/arch/arm/mach-msm/proc_comm.h
+++ b/arch/arm/mach-msm/proc_comm.h
@@ -137,6 +137,7 @@ enum {
 	PCOM_CLKCTL_RPC_RAIL_DISABLE,
 	PCOM_CLKCTL_RPC_RAIL_CONTROL,
 	PCOM_CLKCTL_RPC_MIN_MSMC1,
+	PCOM_CLKCTL_RPC_SRC_REQUEST,
 	PCOM_NUM_CMDS,
 };
 
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 15/34] msm: clock: Add local clock control framework

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Based on code originally written by Saravana Kannan, rewritten by
Matt Wagantall.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-local.c |  700 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/clock-local.h |  242 ++++++++++++++
 2 files changed, 942 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/clock-local.c
 create mode 100644 arch/arm/mach-msm/clock-local.h

diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
new file mode 100644
index 0000000..7a6dc5d
--- /dev/null
+++ b/arch/arm/mach-msm/clock-local.c
@@ -0,0 +1,700 @@
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/ctype.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+#include <mach/clk.h>
+
+#include "clock.h"
+#include "clock-local.h"
+
+/*
+ * When enabling/disabling a clock, check the halt bit up to this number
+ * number of times (with a 1 us delay in between) before continuing.
+ */
+#define HALT_CHECK_MAX_LOOPS	100
+/* For clock without halt checking, wait this long after enables/disables. */
+#define HALT_CHECK_DELAY_US	10
+
+DEFINE_SPINLOCK(local_clock_reg_lock);
+struct clk_freq_tbl local_dummy_freq = F_END;
+
+unsigned local_sys_vdd_votes[NUM_SYS_VDD_LEVELS];
+static DEFINE_SPINLOCK(sys_vdd_vote_lock);
+
+/*
+ * Common Set-Rate Functions
+ */
+
+/* For clocks with MND dividers. */
+void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf)
+{
+	u32 ns_reg_val, ctl_reg_val;
+
+	/* Assert MND reset. */
+	ns_reg_val = readl_relaxed(clk->ns_reg);
+	ns_reg_val |= BIT(7);
+	writel_relaxed(ns_reg_val, clk->ns_reg);
+
+	/* Program M and D values. */
+	writel_relaxed(nf->md_val, clk->md_reg);
+
+	/* If the clock has a separate CC register, program it. */
+	if (clk->ns_reg != clk->b.ctl_reg) {
+		ctl_reg_val = readl_relaxed(clk->b.ctl_reg);
+		ctl_reg_val &= ~(clk->ctl_mask);
+		ctl_reg_val |= nf->ctl_val;
+		writel_relaxed(ctl_reg_val, clk->b.ctl_reg);
+	}
+
+	/* Deassert MND reset. */
+	ns_reg_val &= ~BIT(7);
+	writel_relaxed(ns_reg_val, clk->ns_reg);
+}
+
+void set_rate_nop(struct rcg_clk *clk, struct clk_freq_tbl *nf)
+{
+	/*
+	 * Nothing to do for fixed-rate or integer-divider clocks. Any settings
+	 * in NS registers are applied in the enable path, since power can be
+	 * saved by leaving an un-clocked or slowly-clocked source selected
+	 * until the clock is enabled.
+	 */
+}
+
+int (*soc_update_sys_vdd)(enum sys_vdd_level level);
+/*
+ * SYS_VDD voting functions
+ */
+
+/* Update system voltage level given the current votes. */
+static int local_update_sys_vdd(void)
+{
+	static int cur_level = NUM_SYS_VDD_LEVELS;
+	int level, rc = 0;
+
+	if (local_sys_vdd_votes[HIGH])
+		level = HIGH;
+	else if (local_sys_vdd_votes[NOMINAL])
+		level = NOMINAL;
+	else if (local_sys_vdd_votes[LOW])
+		level = LOW;
+	else
+		level = NONE;
+
+	if (level == cur_level)
+		return rc;
+
+	rc = soc_update_sys_vdd(level);
+	if (!rc)
+		cur_level = level;
+
+	return rc;
+}
+
+/* Vote for a system voltage level. */
+int local_vote_sys_vdd(unsigned level)
+{
+	int rc = 0;
+	unsigned long flags;
+
+	/* Bounds checking. */
+	if (level >= ARRAY_SIZE(local_sys_vdd_votes))
+		return -EINVAL;
+
+	spin_lock_irqsave(&sys_vdd_vote_lock, flags);
+	local_sys_vdd_votes[level]++;
+	rc = local_update_sys_vdd();
+	if (rc)
+		local_sys_vdd_votes[level]--;
+	spin_unlock_irqrestore(&sys_vdd_vote_lock, flags);
+
+	return rc;
+}
+
+/* Remove vote for a system voltage level. */
+int local_unvote_sys_vdd(unsigned level)
+{
+	int rc = 0;
+	unsigned long flags;
+
+	/* Bounds checking. */
+	if (level >= ARRAY_SIZE(local_sys_vdd_votes))
+		return -EINVAL;
+
+	spin_lock_irqsave(&sys_vdd_vote_lock, flags);
+
+	if (WARN(!local_sys_vdd_votes[level],
+		"Reference counts are incorrect for level %d!\n", level))
+		goto out;
+
+	local_sys_vdd_votes[level]--;
+	rc = local_update_sys_vdd();
+	if (rc)
+		local_sys_vdd_votes[level]++;
+out:
+	spin_unlock_irqrestore(&sys_vdd_vote_lock, flags);
+	return rc;
+}
+/*
+ * Clock enable/disable functions
+ */
+
+/* Return non-zero if a clock status registers shows the clock is halted. */
+static int branch_clk_is_halted(const struct branch *clk)
+{
+	int invert = (clk->halt_check == ENABLE);
+	int status_bit = readl_relaxed(clk->halt_reg) & BIT(clk->halt_bit);
+	return invert ? !status_bit : status_bit;
+}
+
+static void __branch_clk_enable_reg(const struct branch *clk, const char *name)
+{
+	u32 reg_val;
+
+	if (clk->en_mask) {
+		reg_val = readl_relaxed(clk->ctl_reg);
+		reg_val |= clk->en_mask;
+		writel_relaxed(reg_val, clk->ctl_reg);
+	}
+
+	/*
+	 * Use a memory barrier since some halt status registers are
+	 * not within the same 1K segment as the branch/root enable
+	 * registers.  It's also needed in the udelay() case to ensure
+	 * the delay starts after the branch enable.
+	 */
+	mb();
+
+	/* Wait for clock to enable before returning. */
+	if (clk->halt_check == DELAY)
+		udelay(HALT_CHECK_DELAY_US);
+	else if (clk->halt_check == ENABLE || clk->halt_check == HALT
+			|| clk->halt_check == ENABLE_VOTED
+			|| clk->halt_check == HALT_VOTED) {
+		int count;
+
+		/* Wait up to HALT_CHECK_MAX_LOOPS for clock to enable. */
+		for (count = HALT_CHECK_MAX_LOOPS; branch_clk_is_halted(clk)
+					&& count > 0; count--)
+			udelay(1);
+		WARN(count == 0, "%s status stuck at 'off'", name);
+	}
+}
+
+/* Perform any register operations required to enable the clock. */
+static void __rcg_clk_enable_reg(struct rcg_clk *clk)
+{
+	u32 reg_val;
+	void __iomem *const reg = clk->b.ctl_reg;
+
+	WARN(clk->current_freq == &local_dummy_freq,
+		"Attempting to enable %s before setting its rate. "
+		"Set the rate first!\n", clk->c.dbg_name);
+
+	/*
+	 * Program the NS register, if applicable. NS registers are not
+	 * set in the set_rate path because power can be saved by deferring
+	 * the selection of a clocked source until the clock is enabled.
+	 */
+	if (clk->ns_mask) {
+		reg_val = readl_relaxed(clk->ns_reg);
+		reg_val &= ~(clk->ns_mask);
+		reg_val |= (clk->current_freq->ns_val & clk->ns_mask);
+		writel_relaxed(reg_val, clk->ns_reg);
+	}
+
+	/* Enable MN counter, if applicable. */
+	reg_val = readl_relaxed(reg);
+	if (clk->current_freq->mnd_en_mask) {
+		reg_val |= clk->current_freq->mnd_en_mask;
+		writel_relaxed(reg_val, reg);
+	}
+	/* Enable root. */
+	if (clk->root_en_mask) {
+		reg_val |= clk->root_en_mask;
+		writel_relaxed(reg_val, reg);
+	}
+	__branch_clk_enable_reg(&clk->b, clk->c.dbg_name);
+}
+
+/* Perform any register operations required to disable the branch. */
+static u32 __branch_clk_disable_reg(const struct branch *clk, const char *name)
+{
+	u32 reg_val;
+
+	reg_val = readl_relaxed(clk->ctl_reg);
+	if (clk->en_mask) {
+		reg_val &= ~(clk->en_mask);
+		writel_relaxed(reg_val, clk->ctl_reg);
+	}
+
+	/*
+	 * Use a memory barrier since some halt status registers are
+	 * not within the same K segment as the branch/root enable
+	 * registers.  It's also needed in the udelay() case to ensure
+	 * the delay starts after the branch disable.
+	 */
+	mb();
+
+	/* Wait for clock to disable before continuing. */
+	if (clk->halt_check == DELAY || clk->halt_check == ENABLE_VOTED
+				     || clk->halt_check == HALT_VOTED)
+		udelay(HALT_CHECK_DELAY_US);
+	else if (clk->halt_check == ENABLE || clk->halt_check == HALT) {
+		int count;
+
+		/* Wait up to HALT_CHECK_MAX_LOOPS for clock to disable. */
+		for (count = HALT_CHECK_MAX_LOOPS; !branch_clk_is_halted(clk)
+					&& count > 0; count--)
+			udelay(1);
+		WARN(count == 0, "%s status stuck at 'on'", name);
+	}
+
+	return reg_val;
+}
+
+/* Perform any register operations required to disable the generator. */
+static void __rcg_clk_disable_reg(struct rcg_clk *clk)
+{
+	void __iomem *const reg = clk->b.ctl_reg;
+	u32 reg_val;
+
+	reg_val = __branch_clk_disable_reg(&clk->b, clk->c.dbg_name);
+	/* Disable root. */
+	if (clk->root_en_mask) {
+		reg_val &= ~(clk->root_en_mask);
+		writel_relaxed(reg_val, reg);
+	}
+	/* Disable MN counter, if applicable. */
+	if (clk->current_freq->mnd_en_mask) {
+		reg_val &= ~(clk->current_freq->mnd_en_mask);
+		writel_relaxed(reg_val, reg);
+	}
+	/*
+	 * Program NS register to low-power value with an un-clocked or
+	 * slowly-clocked source selected.
+	 */
+	if (clk->ns_mask) {
+		reg_val = readl_relaxed(clk->ns_reg);
+		reg_val &= ~(clk->ns_mask);
+		reg_val |= (clk->freq_tbl->ns_val & clk->ns_mask);
+		writel_relaxed(reg_val, clk->ns_reg);
+	}
+}
+
+static void _rcg_clk_enable(struct rcg_clk *clk)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+	__rcg_clk_enable_reg(clk);
+	clk->enabled = true;
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+}
+
+static void _rcg_clk_disable(struct rcg_clk *clk)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+	__rcg_clk_disable_reg(clk);
+	clk->enabled = false;
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+}
+
+/* Enable a clock and any related power rail. */
+int rcg_clk_enable(struct clk *c)
+{
+	int rc;
+	struct rcg_clk *clk = to_rcg_clk(c);
+
+	rc = local_vote_sys_vdd(clk->current_freq->sys_vdd);
+	if (rc)
+		goto err_vdd;
+	rc = clk_enable(clk->depends);
+	if (rc)
+		goto err_dep;
+	_rcg_clk_enable(clk);
+	return rc;
+
+err_dep:
+	local_unvote_sys_vdd(clk->current_freq->sys_vdd);
+err_vdd:
+	return rc;
+}
+
+/* Disable a clock and any related power rail. */
+void rcg_clk_disable(struct clk *c)
+{
+	struct rcg_clk *clk = to_rcg_clk(c);
+
+	_rcg_clk_disable(clk);
+	clk_disable(clk->depends);
+	local_unvote_sys_vdd(clk->current_freq->sys_vdd);
+}
+
+/* Turn off a clock at boot, without checking refcounts or disabling depends. */
+void rcg_clk_auto_off(struct clk *c)
+{
+	_rcg_clk_disable(to_rcg_clk(c));
+}
+
+/*
+ * Frequency-related functions
+ */
+
+/* Set a clock's frequency. */
+static int _rcg_clk_set_rate(struct rcg_clk *clk, struct clk_freq_tbl *nf)
+{
+	struct clk_freq_tbl *cf;
+	int rc = 0;
+	struct clk *chld;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clk->c.lock, flags);
+
+	/* Check if frequency is actually changed. */
+	cf = clk->current_freq;
+	if (nf == cf)
+		goto unlock;
+
+	if (clk->enabled) {
+		/* Vote for voltage and source for new freq. */
+		rc = local_vote_sys_vdd(nf->sys_vdd);
+		if (rc)
+			goto unlock;
+		rc = clk_enable(nf->src_clk);
+		if (rc) {
+			local_unvote_sys_vdd(nf->sys_vdd);
+			goto unlock;
+		}
+	}
+
+	spin_lock(&local_clock_reg_lock);
+
+	/* Disable all branches to prevent glitches. */
+	list_for_each_entry(chld, &clk->c.children, siblings) {
+		struct branch_clk *x = to_branch_clk(chld);
+		/* Don't bother turning off if it is already off.
+		 * Checking ch->enabled is cheaper (cache) than reading
+		 * and writing to a register (uncached/unbuffered). */
+		if (x->enabled)
+			__branch_clk_disable_reg(&x->b, x->c.dbg_name);
+	}
+	if (clk->enabled)
+		__rcg_clk_disable_reg(clk);
+
+	/* Perform clock-specific frequency switch operations. */
+	BUG_ON(!clk->set_rate);
+	clk->set_rate(clk, nf);
+
+	/*
+	 * Current freq must be updated before __rcg_clk_enable_reg()
+	 * is called to make sure the MNCNTR_EN bit is set correctly.
+	 */
+	clk->current_freq = nf;
+
+	if (clk->enabled)
+		__rcg_clk_enable_reg(clk);
+	/* Enable only branches that were ON before. */
+	list_for_each_entry(chld, &clk->c.children, siblings) {
+		struct branch_clk *x = to_branch_clk(chld);
+		if (x->enabled)
+			__branch_clk_enable_reg(&x->b, x->c.dbg_name);
+	}
+
+	spin_unlock(&local_clock_reg_lock);
+
+	/* Release requirements of the old freq. */
+	if (clk->enabled) {
+		clk_disable(cf->src_clk);
+		local_unvote_sys_vdd(cf->sys_vdd);
+	}
+unlock:
+	spin_unlock_irqrestore(&clk->c.lock, flags);
+
+	return rc;
+}
+
+/* Set a clock to an exact rate. */
+int rcg_clk_set_rate(struct clk *c, unsigned rate)
+{
+	struct rcg_clk *clk = to_rcg_clk(c);
+	struct clk_freq_tbl *nf;
+
+	for (nf = clk->freq_tbl; nf->freq_hz != FREQ_END
+			&& nf->freq_hz != rate; nf++)
+		;
+
+	if (nf->freq_hz == FREQ_END)
+		return -EINVAL;
+
+	return _rcg_clk_set_rate(clk, nf);
+}
+
+/* Set a clock to a rate greater than some minimum. */
+int rcg_clk_set_min_rate(struct clk *c, unsigned rate)
+{
+	struct rcg_clk *clk = to_rcg_clk(c);
+	struct clk_freq_tbl *nf;
+
+	for (nf = clk->freq_tbl; nf->freq_hz != FREQ_END
+			&& nf->freq_hz < rate; nf++)
+		;
+
+	if (nf->freq_hz == FREQ_END)
+		return -EINVAL;
+
+	return _rcg_clk_set_rate(clk, nf);
+}
+
+/* Set a clock to a maximum rate. */
+int rcg_clk_set_max_rate(struct clk *clk, unsigned rate)
+{
+	return -EPERM;
+}
+
+/* Get the currently-set rate of a clock in Hz. */
+unsigned rcg_clk_get_rate(struct clk *c)
+{
+	struct rcg_clk *clk = to_rcg_clk(c);
+	unsigned long flags;
+	unsigned ret = 0;
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+	ret = clk->current_freq->freq_hz;
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+	/*
+	 * Return 0 if the rate has never been set. Might not be correct,
+	 * but it's good enough.
+	 */
+	if (ret == FREQ_END)
+		ret = 0;
+
+	return ret;
+}
+
+/* Check if a clock is currently enabled. */
+unsigned rcg_clk_is_enabled(struct clk *clk)
+{
+	return to_rcg_clk(clk)->enabled;
+}
+
+/* Return a supported rate that's at least the specified rate. */
+long rcg_clk_round_rate(struct clk *c, unsigned rate)
+{
+	struct rcg_clk *clk = to_rcg_clk(c);
+	struct clk_freq_tbl *f;
+
+	for (f = clk->freq_tbl; f->freq_hz != FREQ_END; f++)
+		if (f->freq_hz >= rate)
+			return f->freq_hz;
+
+	return -EPERM;
+}
+
+bool local_clk_is_local(struct clk *clk)
+{
+	return true;
+}
+
+struct clk *rcg_clk_get_parent(struct clk *clk)
+{
+	return to_rcg_clk(clk)->current_freq->src_clk;
+}
+
+static int pll_vote_clk_enable(struct clk *clk)
+{
+	u32 ena;
+	unsigned long flags;
+	struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+	ena = readl_relaxed(pll->en_reg);
+	ena |= pll->en_mask;
+	writel_relaxed(ena, pll->en_reg);
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+	/* Wait until PLL is enabled */
+	while ((readl_relaxed(pll->status_reg) & BIT(16)) == 0)
+		cpu_relax();
+
+	return 0;
+}
+
+static void pll_vote_clk_disable(struct clk *clk)
+{
+	u32 ena;
+	unsigned long flags;
+	struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+	ena = readl_relaxed(pll->en_reg);
+	ena &= ~(pll->en_mask);
+	writel_relaxed(ena, pll->en_reg);
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+}
+
+static unsigned pll_vote_clk_get_rate(struct clk *clk)
+{
+	struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+	return pll->rate;
+}
+
+static struct clk *pll_vote_clk_get_parent(struct clk *clk)
+{
+	struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+	return pll->parent;
+}
+
+static unsigned pll_vote_clk_is_enabled(struct clk *clk)
+{
+	struct pll_vote_clk *pll = to_pll_vote_clk(clk);
+	return !!(readl_relaxed(pll->status_reg) & BIT(16));
+}
+
+struct clk_ops clk_ops_pll_vote = {
+	.enable = pll_vote_clk_enable,
+	.disable = pll_vote_clk_disable,
+	.is_enabled = pll_vote_clk_is_enabled,
+	.get_rate = pll_vote_clk_get_rate,
+	.get_parent = pll_vote_clk_get_parent,
+	.is_local = local_clk_is_local,
+};
+
+struct clk_ops clk_ops_gnd = {
+	.get_rate = fixed_clk_get_rate,
+	.is_local = local_clk_is_local,
+};
+
+struct fixed_clk gnd_clk = {
+	.c = {
+		.dbg_name = "ground_clk",
+		.ops = &clk_ops_gnd,
+		CLK_INIT(gnd_clk.c),
+	},
+};
+
+int branch_clk_enable(struct clk *clk)
+{
+	int rc;
+	unsigned long flags;
+	struct branch_clk *branch = to_branch_clk(clk);
+
+	rc = clk_enable(branch->depends);
+	if (rc)
+		return rc;
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+	__branch_clk_enable_reg(&branch->b, branch->c.dbg_name);
+	branch->enabled = true;
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+	return 0;
+}
+
+void branch_clk_disable(struct clk *clk)
+{
+	unsigned long flags;
+	struct branch_clk *branch = to_branch_clk(clk);
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+	__branch_clk_disable_reg(&branch->b, branch->c.dbg_name);
+	branch->enabled = false;
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+	clk_disable(branch->depends);
+}
+
+struct clk *branch_clk_get_parent(struct clk *clk)
+{
+	struct branch_clk *branch = to_branch_clk(clk);
+	return branch->parent;
+}
+
+int branch_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	/*
+	 * We setup the parent pointer at init time in msm_clock_init().
+	 * This check is to make sure drivers can't change the parent.
+	 */
+	if (parent && list_empty(&clk->siblings)) {
+		list_add(&clk->siblings, &parent->children);
+		return 0;
+	}
+	return -EINVAL;
+}
+
+unsigned branch_clk_is_enabled(struct clk *clk)
+{
+	struct branch_clk *branch = to_branch_clk(clk);
+	return branch->enabled;
+}
+
+void branch_clk_auto_off(struct clk *clk)
+{
+	struct branch_clk *branch = to_branch_clk(clk);
+	unsigned long flags;
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+	__branch_clk_disable_reg(&branch->b, branch->c.dbg_name);
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+}
+
+int branch_reset(struct branch *clk, enum clk_reset_action action)
+{
+	int ret = 0;
+	u32 reg_val;
+	unsigned long flags;
+
+	if (!clk->reset_reg)
+		return -EPERM;
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+
+	reg_val = readl_relaxed(clk->reset_reg);
+	switch (action) {
+	case CLK_RESET_ASSERT:
+		reg_val |= clk->reset_mask;
+		break;
+	case CLK_RESET_DEASSERT:
+		reg_val &= ~(clk->reset_mask);
+		break;
+	default:
+		ret = -EINVAL;
+	}
+	writel_relaxed(reg_val, clk->reset_reg);
+
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+	/* Make sure write is issued before returning. */
+	mb();
+
+	return ret;
+}
+
+int branch_clk_reset(struct clk *clk, enum clk_reset_action action)
+{
+	return branch_reset(&to_branch_clk(clk)->b, action);
+}
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
new file mode 100644
index 0000000..a7c9001
--- /dev/null
+++ b/arch/arm/mach-msm/clock-local.h
@@ -0,0 +1,242 @@
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_CLOCK_LOCAL_H
+#define __ARCH_ARM_MACH_MSM_CLOCK_LOCAL_H
+
+#include <linux/spinlock.h>
+#include "clock.h"
+
+/*
+ * Bit manipulation macros
+ */
+#define BM(msb, lsb)	(((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
+#define BVAL(msb, lsb, val)	(((val) << lsb) & BM(msb, lsb))
+
+/*
+ * Halt/Status Checking Mode Macros
+ */
+#define HALT		0	/* Bit pol: 1 = halted */
+#define NOCHECK		1	/* No bit to check, do nothing */
+#define HALT_VOTED	2	/* Bit pol: 1 = halted; delay on disable */
+#define ENABLE		3	/* Bit pol: 1 = running */
+#define ENABLE_VOTED	4	/* Bit pol: 1 = running; delay on disable */
+#define DELAY		5	/* No bit to check, just delay */
+
+/*
+ * Generic frequency-definition structs and macros
+ */
+struct clk_freq_tbl {
+	const uint32_t	freq_hz;
+	struct clk	*src_clk;
+	const uint32_t	md_val;
+	const uint32_t	ns_val;
+	const uint32_t	ctl_val;
+	uint32_t	mnd_en_mask;
+	const unsigned	sys_vdd;
+	void		*const extra_freq_data;
+};
+
+#define F_RAW(f, sc, m_v, n_v, c_v, m_m, v, e) { \
+	.freq_hz = f, \
+	.src_clk = sc, \
+	.md_val = m_v, \
+	.ns_val = n_v, \
+	.ctl_val = c_v, \
+	.mnd_en_mask = m_m, \
+	.sys_vdd = v, \
+	.extra_freq_data = e, \
+	}
+#define FREQ_END	(UINT_MAX-1)
+#define F_END \
+	{ \
+		.freq_hz = FREQ_END, \
+		.sys_vdd = LOW, \
+	}
+
+/**
+ * struct branch - branch on/off
+ * @ctl_reg: clock control register
+ * @en_mask: ORed with @ctl_reg to enable the clock
+ * @halt_reg: halt register
+ * @halt_check: type of halt check to perform
+ * @halt_bit: ANDed with @halt_reg to test for clock halted
+ * @reset_reg: reset register
+ * @reset_mask: ORed with @reset_reg to reset the clock domain
+ */
+struct branch {
+	void __iomem *const ctl_reg;
+	const u32 en_mask;
+
+	void __iomem *const halt_reg;
+	const u16 halt_check;
+	const u16 halt_bit;
+
+	void __iomem *const reset_reg;
+	const u32 reset_mask;
+};
+
+int branch_reset(struct branch *clk, enum clk_reset_action action);
+
+/*
+ * Generic clock-definition struct and macros
+ */
+struct rcg_clk {
+	bool		enabled;
+	struct branch	b;
+	void		*const ns_reg;
+	void		*const md_reg;
+	const uint32_t	root_en_mask;
+	uint32_t	ns_mask;
+	const uint32_t	ctl_mask;
+	struct clk *depends;
+	void		(*set_rate)(struct clk_local *, struct clk_freq_tbl *);
+	struct clk_freq_tbl *const freq_tbl;
+	struct clk_freq_tbl *current_freq;
+
+	struct clk	c;
+};
+
+static inline struct rcg_clk *to_rcg_clk(struct clk *clk)
+{
+	return container_of(clk, struct rcg_clk, c);
+}
+
+int rcg_clk_enable(struct clk *clk);
+void rcg_clk_disable(struct clk *clk);
+void rcg_clk_auto_off(struct clk *clk);
+int rcg_clk_set_rate(struct clk *clk, unsigned rate);
+int rcg_clk_set_min_rate(struct clk *clk, unsigned rate);
+int rcg_clk_set_max_rate(struct clk *clk, unsigned rate);
+unsigned rcg_clk_get_rate(struct clk *clk);
+unsigned rcg_clk_is_enabled(struct clk *clk);
+long rcg_clk_round_rate(struct clk *clk, unsigned rate);
+struct clk *rcg_clk_get_parent(struct clk *c);
+
+/*
+ * SYS_VDD voltage levels
+ */
+enum sys_vdd_level {
+	NONE,
+	LOW,
+	NOMINAL,
+	HIGH,
+	NUM_SYS_VDD_LEVELS
+};
+
+/**
+ * struct fixed_clk - fixed rate clock (used for crystal oscillators)
+ * @rate: output rate
+ * @c: clk
+ */
+struct fixed_clk {
+	unsigned long rate;
+	struct clk c;
+};
+
+static inline struct fixed_clk *to_fixed_clk(struct clk *clk)
+{
+	return container_of(clk, struct fixed_clk, c);
+}
+
+static inline unsigned fixed_clk_get_rate(struct clk *clk)
+{
+	struct fixed_clk *f = to_fixed_clk(clk);
+	return f->rate;
+}
+
+
+/**
+ * struct pll_vote_clk - phase locked loop (HW voteable)
+ * @rate: output rate
+ * @en_reg: enable register
+ * @en_mask: ORed with @en_reg to enable the clock
+ * @status_reg: status register
+ * @parent: clock source
+ * @c: clk
+ */
+struct pll_vote_clk {
+	unsigned long rate;
+
+	void __iomem *const en_reg;
+	const u32 en_mask;
+
+	void __iomem *const status_reg;
+
+	struct clk *parent;
+	struct clk c;
+};
+
+extern struct clk_ops clk_ops_pll_vote;
+
+static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *clk)
+{
+	return container_of(clk, struct pll_vote_clk, c);
+}
+
+/**
+ * struct branch_clk - branch
+ * @enabled: true if clock is on, false otherwise
+ * @b: branch
+ * @parent: clock source
+ * @c: clk
+ *
+ * An on/off switch with a rate derived from the parent.
+ */
+struct branch_clk {
+	bool enabled;
+	struct branch b;
+	struct clk *parent;
+	struct clk *depends;
+	struct clk c;
+};
+
+static inline struct branch_clk *to_branch_clk(struct clk *clk)
+{
+	return container_of(clk, struct branch_clk, c);
+}
+
+int branch_clk_enable(struct clk *clk);
+void branch_clk_disable(struct clk *clk);
+struct clk *branch_clk_get_parent(struct clk *clk);
+int branch_clk_set_parent(struct clk *clk, struct clk *parent);
+unsigned branch_clk_is_enabled(struct clk *clk);
+void branch_clk_auto_off(struct clk *clk);
+int branch_clk_reset(struct clk *c, enum clk_reset_action action);
+
+/*
+ * Variables from clock-local driver
+ */
+extern spinlock_t		local_clock_reg_lock;
+extern struct clk_freq_tbl	local_dummy_freq;
+extern struct fixed_clk		gnd_clk;
+
+/*
+ * Local-clock APIs
+ */
+int local_vote_sys_vdd(enum sys_vdd_level level);
+int local_unvote_sys_vdd(enum sys_vdd_level level);
+bool local_clk_is_local(struct clk *clk);
+
+/*
+ * Required SoC-specific functions, implemented for every supported SoC
+ */
+extern int (*soc_update_sys_vdd)(enum sys_vdd_level level);
+
+/*
+ * Generic set-rate implementations
+ */
+void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);
+void set_rate_nop(struct rcg_clk *clk, struct clk_freq_tbl *nf);
+
+#endif /* __ARCH_ARM_MACH_MSM_CLOCK_LOCAL_H */
+
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 16/34] msm: clock-pcom: Expose pc_clk_reset

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

The 7x30 clock driver needs to perform clock resets and the only
way that is possible is through proc_comm. Expose the reset
functionality as a new function callable from the 7x30 clock
driver.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-pcom.c |   13 +++++++++----
 arch/arm/mach-msm/clock-pcom.h |    2 ++
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index e11ef57..f441247 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -41,10 +41,9 @@ static void pc_clk_disable(struct clk *clk)
 	msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
 }
 
-int pc_clk_reset(struct clk *clk, enum clk_reset_action action)
+int pc_clk_reset(unsigned id, enum clk_reset_action action)
 {
 	int rc;
-	unsigned id = to_pcom_clk(clk)->id;
 
 	if (action == CLK_RESET_ASSERT)
 		rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
@@ -57,6 +56,12 @@ int pc_clk_reset(struct clk *clk, enum clk_reset_action action)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
+static int pc_reset(struct clk *clk, enum clk_reset_action action)
+{
+	unsigned id = to_pcom_clk(clk)->id;
+	return pc_clk_reset(id, action);
+}
+
 static int pc_clk_set_rate(struct clk *clk, unsigned rate)
 {
 	/* The rate _might_ be rounded off to the nearest KHz value by the
@@ -135,7 +140,7 @@ struct clk_ops clk_ops_pcom = {
 	.enable = pc_clk_enable,
 	.disable = pc_clk_disable,
 	.auto_off = pc_clk_disable,
-	.reset = pc_clk_reset,
+	.reset = pc_reset,
 	.set_rate = pc_clk_set_rate,
 	.set_min_rate = pc_clk_set_min_rate,
 	.set_max_rate = pc_clk_set_max_rate,
@@ -165,7 +170,7 @@ struct clk_ops clk_ops_pcom_div2 = {
 	.enable = pc_clk_enable,
 	.disable = pc_clk_disable,
 	.auto_off = pc_clk_disable,
-	.reset = pc_clk_reset,
+	.reset = pc_reset,
 	.set_rate = pc_clk_set_rate2,
 	.set_min_rate = pc_clk_set_min_rate2,
 	.set_flags = pc_clk_set_flags,
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
index 23807ff..c3beb47 100644
--- a/arch/arm/mach-msm/clock-pcom.h
+++ b/arch/arm/mach-msm/clock-pcom.h
@@ -120,6 +120,8 @@
 
 #define P_NR_CLKS		102
 
+extern int pc_clk_reset(unsigned id, enum clk_reset_action action);
+
 struct clk_ops;
 extern struct clk_ops clk_ops_pcom;
 extern struct clk_ops clk_ops_pcom_div2;
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 17/34] msm: clock: Add 7x30 local clock support

[David Brown]

From: Saravana Kannan <skannan@codeaurora.org>

Support locally controllable clocks on 7x30.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/Makefile          |    1 +
 arch/arm/mach-msm/clock-7x30.c      | 2784 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/clock-7x30.h      |  143 --
 arch/arm/mach-msm/clock.c           |    3 +
 arch/arm/mach-msm/clock.h           |    6 +
 arch/arm/mach-msm/devices-msm7x30.c |  181 ---
 6 files changed, 2794 insertions(+), 324 deletions(-)
 create mode 100644 arch/arm/mach-msm/clock-7x30.c
 delete mode 100644 arch/arm/mach-msm/clock-7x30.h

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 5318553..c0e8e8e 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -2,6 +2,7 @@ obj-y += io.o idle.o timer.o
 obj-y += clock.o
 obj-y += clock-voter.o
 obj-$(CONFIG_DEBUG_FS) += clock-debug.o
+obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o
 
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
 obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
new file mode 100644
index 0000000..306a64f
--- /dev/null
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -0,0 +1,2784 @@
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/ctype.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/string.h>
+
+#include <mach/msm_iomap.h>
+#include <mach/clk.h>
+
+#include "clock.h"
+#include "clock-local.h"
+#include "clock-pcom.h"
+#include "clock-voter.h"
+#include "proc_comm.h"
+
+#define REG_BASE(off) (MSM_CLK_CTL_BASE + (off))
+#define REG(off) (MSM_CLK_CTL_SH2_BASE + (off))
+
+/* Shadow-region 2 (SH2) registers. */
+#define	QUP_I2C_NS_REG		REG(0x04F0)
+#define CAM_NS_REG		REG(0x0374)
+#define CAM_VFE_NS_REG		REG(0x0044)
+#define CLK_HALT_STATEA_REG	REG(0x0108)
+#define CLK_HALT_STATEB_REG	REG(0x010C)
+#define CLK_HALT_STATEC_REG	REG(0x02D4)
+#define CSI_NS_REG		REG(0x0174)
+#define EMDH_NS_REG		REG(0x0050)
+#define GLBL_CLK_ENA_2_SC_REG	REG(0x03C0)
+#define GLBL_CLK_ENA_SC_REG	REG(0x03BC)
+#define GLBL_CLK_STATE_2_REG	REG(0x037C)
+#define GLBL_CLK_STATE_REG	REG(0x0004)
+#define GRP_2D_NS_REG		REG(0x0034)
+#define GRP_NS_REG		REG(0x0084)
+#define HDMI_NS_REG		REG(0x0484)
+#define I2C_2_NS_REG		REG(0x02D8)
+#define I2C_NS_REG		REG(0x0068)
+#define JPEG_NS_REG		REG(0x0164)
+#define LPA_CORE_CLK_MA0_REG	REG(0x04F4)
+#define LPA_CORE_CLK_MA2_REG	REG(0x04FC)
+#define LPA_NS_REG		REG(0x02E8)
+#define MDC_NS_REG		REG(0x007C)
+#define MDP_LCDC_NS_REG		REG(0x0390)
+#define MDP_NS_REG		REG(0x014C)
+#define MDP_VSYNC_REG		REG(0x0460)
+#define MFC_NS_REG		REG(0x0154)
+#define MI2S_CODEC_RX_DIV_REG	REG(0x02EC)
+#define MI2S_CODEC_TX_DIV_REG	REG(0x02F0)
+#define MI2S_DIV_REG		REG(0x02E4)
+#define MI2S_NS_REG		REG(0x02E0)
+#define MI2S_RX_NS_REG		REG(0x0070)
+#define MI2S_TX_NS_REG		REG(0x0078)
+#define MIDI_NS_REG		REG(0x02D0)
+#define PLL_ENA_REG		REG(0x0264)
+#define PMDH_NS_REG		REG(0x008C)
+#define SDAC_NS_REG		REG(0x009C)
+#define SDCn_NS_REG(n)		REG(0x00A4+(0x8*((n)-1)))
+#define SPI_NS_REG		REG(0x02C8)
+#define TSIF_NS_REG		REG(0x00C4)
+#define TV_NS_REG		REG(0x00CC)
+#define UART1DM_NS_REG		REG(0x00D4)
+#define UART2DM_NS_REG		REG(0x00DC)
+#define UART2_NS_REG		REG(0x0464)
+#define UART_NS_REG		REG(0x00E0)
+#define USBH2_NS_REG		REG(0x046C)
+#define USBH3_NS_REG		REG(0x0470)
+#define USBH_MD_REG		REG(0x02BC)
+#define USBH_NS_REG		REG(0x02C0)
+#define VPE_NS_REG		REG(0x015C)
+
+/* Registers in the base (non-shadow) region. */
+#define CLK_TEST_BASE_REG	REG_BASE(0x011C)
+#define CLK_TEST_2_BASE_REG	REG_BASE(0x0384)
+#define MISC_CLK_CTL_BASE_REG	REG_BASE(0x0110)
+#define PRPH_WEB_NS_BASE_REG	REG_BASE(0x0080)
+#define PLL0_STATUS_BASE_REG	REG_BASE(0x0318)
+#define PLL1_STATUS_BASE_REG	REG_BASE(0x0334)
+#define PLL2_STATUS_BASE_REG	REG_BASE(0x0350)
+#define PLL3_STATUS_BASE_REG	REG_BASE(0x036C)
+#define PLL4_STATUS_BASE_REG	REG_BASE(0x0254)
+#define PLL5_STATUS_BASE_REG	REG_BASE(0x0258)
+#define PLL6_STATUS_BASE_REG	REG_BASE(0x04EC)
+#define RINGOSC_CNT_BASE_REG	REG_BASE(0x00FC)
+#define SH2_OWN_APPS1_BASE_REG	REG_BASE(0x040C)
+#define SH2_OWN_APPS2_BASE_REG	REG_BASE(0x0414)
+#define SH2_OWN_APPS3_BASE_REG	REG_BASE(0x0444)
+#define SH2_OWN_GLBL_BASE_REG	REG_BASE(0x0404)
+#define SH2_OWN_ROW1_BASE_REG	REG_BASE(0x041C)
+#define SH2_OWN_ROW2_BASE_REG	REG_BASE(0x0424)
+#define TCXO_CNT_BASE_REG	REG_BASE(0x00F8)
+#define TCXO_CNT_DONE_BASE_REG	REG_BASE(0x00F8)
+
+
+/* MUX source input identifiers. */
+#define SRC_SEL_pll0		4 /* Modem PLL */
+#define SRC_SEL_pll1		1 /* Global PLL */
+#define SRC_SEL_pll3		3 /* Multimedia/Peripheral PLL or Backup PLL1 */
+#define SRC_SEL_pll4		2 /* Display PLL */
+#define SRC_SEL_SDAC_lpxo	5 /* Low-power XO for SDAC */
+#define SRC_SEL_lpxo		6 /* Low-power XO */
+#define SRC_SEL_tcxo		0 /* Used for rates from TCXO */
+#define SRC_SEL_axi		0 /* Used for rates that sync to AXI */
+#define SRC_SEL_gnd		7 /* No clock */
+
+/* Clock declaration macros. */
+#define MN_MODE_DUAL_EDGE	0x2
+#define MD8(m, n)		(BVAL(15, 8, m) | BVAL(7, 0, ~(n)))
+#define N8(msb, lsb, m, n)	(BVAL(msb, lsb, ~(n-m)) | BVAL(6, 5, \
+					(MN_MODE_DUAL_EDGE * !!(n))))
+#define MD16(m, n)		(BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
+#define N16(m, n)		(BVAL(31, 16, ~(n-m)) | BVAL(6, 5, \
+					(MN_MODE_DUAL_EDGE * !!(n))))
+#define SPDIV(s, d)		(BVAL(4, 3, d-1) | BVAL(2, 0, s))
+#define SDIV(s, d)		(BVAL(6, 3, d-1) | BVAL(2, 0, s))
+#define F_MASK_BASIC		(BM(6, 3)|BM(2, 0))
+#define F_MASK_MND16		(BM(31, 16)|BM(6, 5)|BM(4, 3)|BM(2, 0))
+#define F_MASK_MND8(m, l)	(BM(m, l)|BM(6, 5)|BM(4, 3)|BM(2, 0))
+
+/*
+ * Clock frequency definitions and macros
+ */
+#define F_BASIC(f, s, div, v) \
+	{ \
+		.freq_hz = f, \
+		.src_clk = &s##_clk.c, \
+		.ns_val = SDIV(SRC_SEL_##s, div), \
+		.sys_vdd = v, \
+	}
+
+#define F_MND16(f, s, div, m, n, v) \
+	{ \
+		.freq_hz = f, \
+		.src_clk = &s##_clk.c, \
+		.md_val = MD16(m, n), \
+		.ns_val = N16(m, n) | SPDIV(SRC_SEL_##s, div), \
+		.mnd_en_mask = BIT(8) * !!(n), \
+		.sys_vdd = v, \
+	}
+
+#define F_MND8(f, nmsb, nlsb, s, div, m, n, v) \
+	{ \
+		.freq_hz = f, \
+		.src_clk = &s##_clk.c, \
+		.md_val = MD8(m, n), \
+		.ns_val = N8(nmsb, nlsb, m, n) | SPDIV(SRC_SEL_##s, div), \
+		.mnd_en_mask = BIT(8) * !!(n), \
+		.sys_vdd = v, \
+	}
+
+static struct clk_ops soc_clk_ops_7x30;
+
+#define PCOM_XO_DISABLE	0
+#define PCOM_XO_ENABLE	1
+#define PCOM_XO_TCXO	0
+#define PCOM_XO_LPXO	1
+
+static bool pcom_is_local(struct clk *clk)
+{
+	return false;
+}
+
+static int pcom_xo_enable(unsigned pcom_id, unsigned enable)
+{
+	/* TODO: Check return code in pcom_id */
+	return msm_proc_comm(PCOM_CLKCTL_RPC_SRC_REQUEST, &pcom_id, &enable);
+}
+
+static int tcxo_clk_enable(struct clk *clk)
+{
+	return pcom_xo_enable(PCOM_XO_TCXO, PCOM_XO_ENABLE);
+}
+
+static void tcxo_clk_disable(struct clk *clk)
+{
+	pcom_xo_enable(PCOM_XO_TCXO, PCOM_XO_DISABLE);
+}
+
+static struct clk_ops clk_ops_tcxo = {
+	.enable = tcxo_clk_enable,
+	.disable = tcxo_clk_disable,
+	.get_rate = fixed_clk_get_rate,
+	.is_local = pcom_is_local,
+};
+
+static struct fixed_clk tcxo_clk = {
+	.rate = 19200000,
+	.c = {
+		.dbg_name = "tcxo_clk",
+		.ops = &clk_ops_tcxo,
+		CLK_INIT(tcxo_clk.c),
+	},
+};
+
+static int lpxo_clk_enable(struct clk *clk)
+{
+	return pcom_xo_enable(PCOM_XO_LPXO, PCOM_XO_ENABLE);
+}
+
+static void lpxo_clk_disable(struct clk *clk)
+{
+	pcom_xo_enable(PCOM_XO_LPXO, PCOM_XO_DISABLE);
+}
+
+static struct clk_ops clk_ops_lpxo = {
+	.enable = lpxo_clk_enable,
+	.disable = lpxo_clk_disable,
+	.get_rate = fixed_clk_get_rate,
+	.is_local = pcom_is_local,
+};
+
+static struct fixed_clk lpxo_clk = {
+	.rate = 24576000,
+	.c = {
+		.dbg_name = "lpxo_clk",
+		.ops = &clk_ops_lpxo,
+		CLK_INIT(lpxo_clk.c),
+	},
+};
+
+static struct pll_vote_clk pll1_clk = {
+	.rate = 768000000,
+	.en_reg = PLL_ENA_REG,
+	.en_mask = BIT(1),
+	.status_reg = PLL1_STATUS_BASE_REG,
+	.parent = &tcxo_clk.c,
+	.c = {
+		.dbg_name = "pll1_clk",
+		.ops = &clk_ops_pll_vote,
+		CLK_INIT(pll1_clk.c),
+	},
+};
+
+static struct pll_vote_clk pll2_clk = {
+	.rate = 806400000, /* TODO: Support scaling */
+	.en_reg = PLL_ENA_REG,
+	.en_mask = BIT(2),
+	.status_reg = PLL2_STATUS_BASE_REG,
+	.parent = &tcxo_clk.c,
+	.c = {
+		.dbg_name = "pll2_clk",
+		.ops = &clk_ops_pll_vote,
+		CLK_INIT(pll2_clk.c),
+	},
+};
+
+static struct pll_vote_clk pll3_clk = {
+	.rate = 737280000,
+	.en_reg = PLL_ENA_REG,
+	.en_mask = BIT(3),
+	.status_reg = PLL3_STATUS_BASE_REG,
+	.parent = &lpxo_clk.c,
+	.c = {
+		.dbg_name = "pll3_clk",
+		.ops = &clk_ops_pll_vote,
+		CLK_INIT(pll3_clk.c),
+	},
+};
+
+static struct pll_vote_clk pll4_clk = {
+	.rate = 891000000,
+	.en_reg = PLL_ENA_REG,
+	.en_mask = BIT(4),
+	.status_reg = PLL4_STATUS_BASE_REG,
+	.parent = &lpxo_clk.c,
+	.c = {
+		.dbg_name = "pll4_clk",
+		.ops = &clk_ops_pll_vote,
+		CLK_INIT(pll4_clk.c),
+	},
+};
+
+static struct clk_ops clk_ops_branch;
+
+static struct clk_freq_tbl clk_tbl_axi[] = {
+	F_RAW(1, &lpxo_clk.c, 0, 0, 0, 0, NOMINAL, NULL),
+	F_END,
+};
+
+/* For global clocks to be on we must have GLBL_ROOT_ENA set */
+static struct rcg_clk glbl_root_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(29),
+		.halt_check = NOCHECK,
+	},
+	.freq_tbl = clk_tbl_axi,
+	.set_rate = set_rate_nop,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_nop,
+	.c = {
+		.dbg_name = "glbl_root_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(glbl_root_clk.c),
+	},
+};
+
+/* AXI bridge clocks. */
+static struct branch_clk axi_li_apps_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(2),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 2,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "axi_li_apps_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_li_apps_clk.c),
+	},
+};
+
+static struct branch_clk axi_li_adsp_a_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(14),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 14,
+	},
+	.parent = &axi_li_apps_clk.c,
+	.c = {
+		.dbg_name = "axi_li_adsp_a_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_li_adsp_a_clk.c),
+	},
+};
+
+static struct branch_clk axi_li_jpeg_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(19),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 19,
+	},
+	.parent = &axi_li_apps_clk.c,
+	.c = {
+		.dbg_name = "axi_li_jpeg_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_li_jpeg_clk.c),
+	},
+};
+
+static struct branch_clk axi_li_vfe_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(23),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 23,
+	},
+	.parent = &axi_li_apps_clk.c,
+	.c = {
+		.dbg_name = "axi_li_vfe_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_li_vfe_clk.c),
+	},
+};
+
+static struct branch_clk axi_mdp_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(29),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 29,
+	},
+	.parent = &axi_li_apps_clk.c,
+	.c = {
+		.dbg_name = "axi_mdp_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_mdp_clk.c),
+	},
+};
+
+static struct branch_clk axi_li_vg_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(3),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 3,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "axi_li_vg_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_li_vg_clk.c),
+	},
+};
+
+static struct branch_clk axi_grp_2d_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(21),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 21,
+	},
+	.parent = &axi_li_vg_clk.c,
+	.c = {
+		.dbg_name = "axi_grp_2d_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_grp_2d_clk.c),
+	},
+};
+
+static struct branch_clk axi_li_grp_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(22),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 22,
+	},
+	.parent = &axi_li_vg_clk.c,
+	.c = {
+		.dbg_name = "axi_li_grp_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_li_grp_clk.c),
+	},
+};
+
+static struct branch_clk axi_mfc_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(20),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 20,
+	},
+	.parent = &axi_li_vg_clk.c,
+	.c = {
+		.dbg_name = "axi_mfc_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_mfc_clk.c),
+	},
+};
+
+static struct branch_clk axi_rotator_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(22),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 22,
+		.reset_mask = P_AXI_ROTATOR_CLK,
+	},
+	.parent = &axi_li_vg_clk.c,
+	.c = {
+		.dbg_name = "axi_rotator_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_rotator_clk.c),
+	},
+};
+
+static struct branch_clk axi_vpe_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(21),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 21,
+	},
+	.parent = &axi_li_vg_clk.c,
+	.c = {
+		.dbg_name = "axi_vpe_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(axi_vpe_clk.c),
+	},
+};
+
+/* Peripheral bus clocks. */
+static struct branch_clk adm_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(5),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 5,
+		.reset_mask = P_ADM_CLK,
+	},
+	.parent = &axi_li_apps_clk.c,
+	.c = {
+		.dbg_name = "adm_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(adm_clk.c),
+	},
+};
+
+static struct branch_clk adm_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(15),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 15,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "adm_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(adm_p_clk.c),
+	},
+};
+
+static struct branch_clk ce_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(6),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 6,
+		.reset_mask = P_CE_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "ce_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(ce_clk.c),
+	},
+};
+
+static struct branch_clk camif_pad_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(9),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 9,
+		.reset_mask = P_CAMIF_PAD_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "camif_pad_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(camif_pad_p_clk.c),
+	},
+};
+
+static struct branch_clk csi0_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(30),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 30,
+		.reset_mask = P_CSI0_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "csi0_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(csi0_p_clk.c),
+	},
+};
+
+static struct branch_clk emdh_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(3),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 3,
+		.reset_mask = P_EMDH_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "emdh_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(emdh_p_clk.c),
+	},
+};
+
+static struct branch_clk grp_2d_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(24),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 24,
+		.reset_mask = P_GRP_2D_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "grp_2d_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(grp_2d_p_clk.c),
+	},
+};
+
+static struct branch_clk grp_3d_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(17),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 17,
+		.reset_mask = P_GRP_3D_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "grp_3d_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(grp_3d_p_clk.c),
+	},
+};
+
+static struct branch_clk jpeg_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(24),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 24,
+		.reset_mask = P_JPEG_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "jpeg_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(jpeg_p_clk.c),
+	},
+};
+
+static struct branch_clk lpa_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(7),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 7,
+		.reset_mask = P_LPA_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "lpa_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(lpa_p_clk.c),
+	},
+};
+
+static struct branch_clk mdp_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(6),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 6,
+		.reset_mask = P_MDP_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "mdp_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(mdp_p_clk.c),
+	},
+};
+
+static struct branch_clk mfc_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(26),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 26,
+		.reset_mask = P_MFC_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "mfc_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(mfc_p_clk.c),
+	},
+};
+
+static struct branch_clk pmdh_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(4),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 4,
+		.reset_mask = P_PMDH_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "pmdh_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(pmdh_p_clk.c),
+	},
+};
+
+static struct branch_clk rotator_imem_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(23),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 23,
+		.reset_mask = P_ROTATOR_IMEM_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "rotator_imem_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(rotator_imem_clk.c),
+	},
+};
+
+static struct branch_clk rotator_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(25),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 25,
+		.reset_mask = P_ROTATOR_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "rotator_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(rotator_p_clk.c),
+	},
+};
+
+static struct branch_clk sdc1_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(7),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 7,
+		.reset_mask = P_SDC1_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "sdc1_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(sdc1_p_clk.c),
+	},
+};
+
+static struct branch_clk sdc2_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(8),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 8,
+		.reset_mask = P_SDC2_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "sdc2_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(sdc2_p_clk.c),
+	},
+};
+
+static struct branch_clk sdc3_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(27),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 27,
+		.reset_mask = P_SDC3_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "sdc3_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(sdc3_p_clk.c),
+	},
+};
+
+static struct branch_clk sdc4_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(28),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 28,
+		.reset_mask = P_SDC4_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "sdc4_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(sdc4_p_clk.c),
+	},
+};
+
+static struct branch_clk spi_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(10),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 10,
+		.reset_mask = P_SPI_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "spi_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(spi_p_clk.c),
+	},
+};
+
+static struct branch_clk tsif_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(18),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 18,
+		.reset_mask = P_TSIF_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "tsif_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(tsif_p_clk.c),
+	},
+};
+
+static struct branch_clk uart1dm_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(17),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 17,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "uart1dm_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(uart1dm_p_clk.c),
+	},
+};
+
+static struct branch_clk uart2dm_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(26),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 26,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "uart2dm_p_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(uart2dm_p_clk.c),
+	},
+};
+
+static struct branch_clk usb_hs2_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(8),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 8,
+		.reset_mask = P_USB_HS2_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "usb_hs2_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(usb_hs2_p_clk.c),
+	},
+};
+
+static struct branch_clk usb_hs3_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(9),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 9,
+		.reset_mask = P_USB_HS3_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "usb_hs3_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(usb_hs3_p_clk.c),
+	},
+};
+
+static struct branch_clk usb_hs_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_SC_REG,
+		.en_mask = BIT(25),
+		.halt_reg = GLBL_CLK_STATE_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 25,
+		.reset_mask = P_USB_HS_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "usb_hs_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(usb_hs_p_clk.c),
+	},
+};
+
+static struct branch_clk vfe_p_clk = {
+	.b = {
+		.ctl_reg = GLBL_CLK_ENA_2_SC_REG,
+		.en_mask = BIT(27),
+		.halt_reg = GLBL_CLK_STATE_2_REG,
+		.halt_check = HALT_VOTED,
+		.halt_bit = 27,
+		.reset_mask = P_VFE_P_CLK,
+	},
+	.parent = &glbl_root_clk.c,
+	.c = {
+		.dbg_name = "vfe_p_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(vfe_p_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_csi[] = {
+	F_MND8(        0,  0,  0, gnd,  1, 0, 0, NONE),
+	F_MND8(153600000, 24, 17, pll1, 2, 2, 5, NOMINAL),
+	F_MND8(192000000, 24, 17, pll1, 4, 0, 0, NOMINAL),
+	F_MND8(384000000, 24, 17, pll1, 2, 0, 0, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk csi0_clk = {
+	.b = {
+		.ctl_reg = CSI_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 17,
+		.reset_mask = P_CSI0_CLK,
+	},
+	.ns_reg = CSI_NS_REG,
+	.md_reg = CSI_NS_REG - 4,
+	.ns_mask = F_MASK_MND8(24, 17),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_csi,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "csi0_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(csi0_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_tcxo[] = {
+	F_RAW(19200000, &tcxo_clk.c, 0, 0, 0, 0, NOMINAL, NULL),
+	F_END,
+};
+
+static struct rcg_clk i2c_clk = {
+	.b = {
+		.ctl_reg = I2C_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 15,
+		.reset_mask = P_I2C_CLK,
+	},
+	.set_rate = set_rate_nop,
+	.freq_tbl = clk_tbl_tcxo,
+	.root_en_mask = BIT(11),
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "i2c_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(i2c_clk.c),
+	},
+};
+
+static struct rcg_clk i2c_2_clk = {
+	.b = {
+		.ctl_reg = I2C_2_NS_REG,
+		.en_mask = BIT(0),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 2,
+		.reset_mask = P_I2C_2_CLK,
+	},
+	.root_en_mask = BIT(2),
+	.freq_tbl = clk_tbl_tcxo,
+	.set_rate = set_rate_nop,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "i2c_2_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(i2c_2_clk.c),
+	},
+};
+
+static struct rcg_clk qup_i2c_clk = {
+	.b = {
+		.ctl_reg = QUP_I2C_NS_REG,
+		.en_mask = BIT(0),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 31,
+		.reset_mask = P_QUP_I2C_CLK,
+	},
+	.root_en_mask = BIT(2),
+	.freq_tbl = clk_tbl_tcxo,
+	.set_rate = set_rate_nop,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "qup_i2c_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(qup_i2c_clk.c),
+	},
+};
+
+static struct rcg_clk uart1_clk = {
+	.b = {
+		.ctl_reg = UART_NS_REG,
+		.en_mask = BIT(5),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 7,
+		.reset_mask = P_UART1_CLK,
+	},
+	.root_en_mask = BIT(4),
+	.freq_tbl = clk_tbl_tcxo,
+	.set_rate = set_rate_nop,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "uart1_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(uart1_clk.c),
+	},
+};
+
+static struct rcg_clk uart2_clk = {
+	.b = {
+		.ctl_reg = UART2_NS_REG,
+		.en_mask = BIT(5),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 5,
+		.reset_mask = P_UART2_CLK,
+	},
+	.root_en_mask = BIT(4),
+	.freq_tbl = clk_tbl_tcxo,
+	.set_rate = set_rate_nop,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "uart2_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(uart2_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_uartdm[] = {
+	F_MND16(       0, gnd,  1,   0,   0, NONE),
+	F_MND16( 3686400, pll3, 3,   3, 200, NOMINAL),
+	F_MND16( 7372800, pll3, 3,   3, 100, NOMINAL),
+	F_MND16(14745600, pll3, 3,   3,  50, NOMINAL),
+	F_MND16(32000000, pll3, 3,  25, 192, NOMINAL),
+	F_MND16(40000000, pll3, 3, 125, 768, NOMINAL),
+	F_MND16(46400000, pll3, 3, 145, 768, NOMINAL),
+	F_MND16(48000000, pll3, 3,  25, 128, NOMINAL),
+	F_MND16(51200000, pll3, 3,   5,  24, NOMINAL),
+	F_MND16(56000000, pll3, 3, 175, 768, NOMINAL),
+	F_MND16(58982400, pll3, 3,   6,  25, NOMINAL),
+	F_MND16(64000000, pll1, 4,   1,   3, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk uart1dm_clk = {
+	.b = {
+		.ctl_reg = UART1DM_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 6,
+		.reset_mask = P_UART1DM_CLK,
+	},
+	.ns_reg = UART1DM_NS_REG,
+	.md_reg = UART1DM_NS_REG - 4,
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_uartdm,
+	.ns_mask = F_MASK_MND16,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "uart1dm_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(uart1dm_clk.c),
+	},
+};
+
+static struct rcg_clk uart2dm_clk = {
+	.b = {
+		.ctl_reg = UART2DM_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 23,
+		.reset_mask = P_UART2DM_CLK,
+	},
+	.ns_reg = UART2DM_NS_REG,
+	.md_reg = UART2DM_NS_REG - 4,
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_uartdm,
+	.ns_mask = F_MASK_MND16,
+	.set_rate = set_rate_mnd,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "uart2dm_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(uart2dm_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_mdh[] = {
+	F_BASIC(        0, gnd,   1, NONE),
+	F_BASIC( 49150000, pll3, 15, NOMINAL),
+	F_BASIC( 92160000, pll3,  8, NOMINAL),
+	F_BASIC(122880000, pll3,  6, NOMINAL),
+	F_BASIC(184320000, pll3,  4, NOMINAL),
+	F_BASIC(245760000, pll3,  3, NOMINAL),
+	F_BASIC(368640000, pll3,  2, NOMINAL),
+	F_BASIC(384000000, pll1,  2, NOMINAL),
+	F_BASIC(445500000, pll4,  2, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk emdh_clk = {
+	.b = {
+		.ctl_reg = EMDH_NS_REG,
+		.halt_check = DELAY,
+		.reset_mask = P_EMDH_CLK,
+	},
+	.root_en_mask = BIT(11),
+	.ns_reg = EMDH_NS_REG,
+	.ns_mask = F_MASK_BASIC,
+	.depends = &axi_li_adsp_a_clk.c,
+	.set_rate = set_rate_nop,
+	.freq_tbl = clk_tbl_mdh,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "emdh_clk",
+		.flags = CLKFLAG_AUTO_OFF | CLKFLAG_MIN | CLKFLAG_MAX,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(emdh_clk.c),
+	},
+};
+
+static struct rcg_clk pmdh_clk = {
+	.b = {
+		.ctl_reg = PMDH_NS_REG,
+		.halt_check = DELAY,
+		.reset_mask = P_PMDH_CLK,
+	},
+	.root_en_mask = BIT(11),
+	.ns_reg = PMDH_NS_REG,
+	.ns_mask = F_MASK_BASIC,
+	.depends = &axi_li_adsp_a_clk.c,
+	.set_rate = set_rate_nop,
+	.freq_tbl = clk_tbl_mdh,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "pmdh_clk",
+		.flags = CLKFLAG_AUTO_OFF | CLKFLAG_MIN | CLKFLAG_MAX,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(pmdh_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_grp[] = {
+	F_BASIC( 24576000, lpxo,  1, NOMINAL),
+	F_BASIC( 46080000, pll3, 16, NOMINAL),
+	F_BASIC( 49152000, pll3, 15, NOMINAL),
+	F_BASIC( 52662875, pll3, 14, NOMINAL),
+	F_BASIC( 56713846, pll3, 13, NOMINAL),
+	F_BASIC( 61440000, pll3, 12, NOMINAL),
+	F_BASIC( 67025454, pll3, 11, NOMINAL),
+	F_BASIC( 73728000, pll3, 10, NOMINAL),
+	F_BASIC( 81920000, pll3,  9, NOMINAL),
+	F_BASIC( 92160000, pll3,  8, NOMINAL),
+	F_BASIC(105325714, pll3,  7, NOMINAL),
+	F_BASIC(122880000, pll3,  6, NOMINAL),
+	F_BASIC(147456000, pll3,  5, NOMINAL),
+	F_BASIC(184320000, pll3,  4, NOMINAL),
+	F_BASIC(192000000, pll1,  4, NOMINAL),
+	F_BASIC(245760000, pll3,  3, HIGH),
+	/* Sync to AXI. Hence this "rate" is not fixed. */
+	F_RAW(1, &lpxo_clk.c, 0, BIT(14), 0, 0, NOMINAL, NULL),
+	F_END,
+};
+
+static struct rcg_clk grp_2d_clk = {
+	.b = {
+		.ctl_reg = GRP_2D_NS_REG,
+		.en_mask = BIT(7),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 31,
+		.reset_mask = P_GRP_2D_CLK,
+	},
+	.ns_reg = GRP_2D_NS_REG,
+	.root_en_mask = BIT(11),
+	.ns_mask = F_MASK_BASIC | (7 << 12),
+	.set_rate = set_rate_nop,
+	.freq_tbl = clk_tbl_grp,
+	.depends = &axi_grp_2d_clk.c,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "grp_2d_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(grp_2d_clk.c),
+	},
+};
+
+static struct rcg_clk grp_3d_src_clk = {
+	.ns_reg = GRP_NS_REG,
+	.b = {
+		.ctl_reg = GRP_NS_REG,
+		.halt_check = NOCHECK,
+	},
+	.root_en_mask = BIT(11),
+	.ns_mask = F_MASK_BASIC | (7 << 12),
+	.set_rate = set_rate_nop,
+	.freq_tbl = clk_tbl_grp,
+	.depends = &axi_li_grp_clk.c,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "grp_3d_src_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(grp_3d_src_clk.c),
+	},
+};
+
+static struct branch_clk grp_3d_clk = {
+	.b = {
+		.ctl_reg = GRP_NS_REG,
+		.en_mask = BIT(7),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 18,
+		.reset_mask = P_GRP_3D_CLK,
+	},
+	.parent = &grp_3d_src_clk.c,
+	.c = {
+		.dbg_name = "grp_3d_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(grp_3d_clk.c),
+	},
+};
+
+static struct branch_clk imem_clk = {
+	.b = {
+		.ctl_reg = GRP_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 19,
+		.reset_mask = P_IMEM_CLK,
+	},
+	.parent = &grp_3d_src_clk.c,
+	.c = {
+		.dbg_name = "imem_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(imem_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_sdc1_3[] = {
+	F_MND8(       0,  0,  0, gnd,  1,   0,  0,   NONE),
+	F_MND8(  144000, 19, 12, lpxo, 1,   1,  171, NOMINAL),
+	F_MND8(  400000, 19, 12, lpxo, 1,   2,  123, NOMINAL),
+	F_MND8(16027000, 19, 12, pll3, 3,  14,  215, NOMINAL),
+	F_MND8(17000000, 19, 12, pll3, 4,  19,  206, NOMINAL),
+	F_MND8(20480000, 19, 12, pll3, 4,  23,  212, NOMINAL),
+	F_MND8(24576000, 19, 12, lpxo, 1,   0,    0, NOMINAL),
+	F_MND8(49152000, 19, 12, pll3, 3,   1,    5, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk sdc1_clk = {
+	.b = {
+		.ctl_reg = SDCn_NS_REG(1),
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 1,
+		.reset_mask = P_SDC1_CLK,
+	},
+	.ns_reg = SDCn_NS_REG(1),
+	.md_reg = SDCn_NS_REG(1) - 4,
+	.ns_mask = F_MASK_MND8(19, 12),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_sdc1_3,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "sdc1_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(sdc1_clk.c),
+	},
+};
+
+static struct rcg_clk sdc3_clk = {
+	.b = {
+		.ctl_reg = SDCn_NS_REG(3),
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 24,
+		.reset_mask = P_SDC3_CLK,
+	},
+	.ns_reg = SDCn_NS_REG(3),
+	.md_reg = SDCn_NS_REG(3) - 4,
+	.ns_mask = F_MASK_MND8(19, 12),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_sdc1_3,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "sdc3_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(sdc3_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_sdc2_4[] = {
+	F_MND8(       0,  0,  0, gnd,  1,   0,  0,   NONE),
+	F_MND8(  144000, 20, 13, lpxo, 1,   1,  171, NOMINAL),
+	F_MND8(  400000, 20, 13, lpxo, 1,   2,  123, NOMINAL),
+	F_MND8(16027000, 20, 13, pll3, 3,  14,  215, NOMINAL),
+	F_MND8(17000000, 20, 13, pll3, 4,  19,  206, NOMINAL),
+	F_MND8(20480000, 20, 13, pll3, 4,  23,  212, NOMINAL),
+	F_MND8(24576000, 20, 13, lpxo, 1,   0,    0, NOMINAL),
+	F_MND8(49152000, 20, 13, pll3, 3,   1,    5, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk sdc2_clk = {
+	.b = {
+		.ctl_reg = SDCn_NS_REG(2),
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 0,
+		.reset_mask = P_SDC2_CLK,
+	},
+	.ns_reg = SDCn_NS_REG(2),
+	.md_reg = SDCn_NS_REG(2) - 4,
+	.ns_mask = F_MASK_MND8(20, 13),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_sdc2_4,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "sdc2_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(sdc2_clk.c),
+	},
+};
+
+static struct rcg_clk sdc4_clk = {
+	.b = {
+		.ctl_reg = SDCn_NS_REG(4),
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 25,
+		.reset_mask = P_SDC4_CLK,
+	},
+	.ns_reg = SDCn_NS_REG(4),
+	.md_reg = SDCn_NS_REG(4) - 4,
+	.ns_mask = F_MASK_MND8(20, 13),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_sdc2_4,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "sdc4_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(sdc4_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_mdp_core[] = {
+	F_BASIC( 24576000, lpxo,  1, NOMINAL),
+	F_BASIC( 46080000, pll3, 16, NOMINAL),
+	F_BASIC( 49152000, pll3, 15, NOMINAL),
+	F_BASIC( 52663000, pll3, 14, NOMINAL),
+	F_BASIC( 92160000, pll3,  8, NOMINAL),
+	F_BASIC(122880000, pll3,  6, NOMINAL),
+	F_BASIC(147456000, pll3,  5, NOMINAL),
+	F_BASIC(153600000, pll1,  5, NOMINAL),
+	F_BASIC(192000000, pll1,  4, HIGH),
+	F_END,
+};
+
+static struct rcg_clk mdp_clk = {
+	.b = {
+		.ctl_reg = MDP_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 16,
+		.reset_mask = P_MDP_CLK,
+	},
+	.ns_reg = MDP_NS_REG,
+	.root_en_mask = BIT(11),
+	.ns_mask = F_MASK_BASIC,
+	.depends = &axi_mdp_clk.c,
+	.set_rate = set_rate_nop,
+	.freq_tbl = clk_tbl_mdp_core,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "mdp_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(mdp_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_mdp_lcdc[] = {
+	F_MND16(       0, gnd,  1,   0,   0, NONE),
+	F_MND16(24576000, lpxo, 1,   0,   0, NOMINAL),
+	F_MND16(30720000, pll3, 4,   1,   6, NOMINAL),
+	F_MND16(32768000, pll3, 3,   2,  15, NOMINAL),
+	F_MND16(40960000, pll3, 2,   1,   9, NOMINAL),
+	F_MND16(73728000, pll3, 2,   1,   5, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk mdp_lcdc_pclk_clk = {
+	.b = {
+		.ctl_reg = MDP_LCDC_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 28,
+		.reset_mask = P_MDP_LCDC_PCLK_CLK,
+	},
+	.ns_reg = MDP_LCDC_NS_REG,
+	.md_reg = MDP_LCDC_NS_REG - 4,
+	.root_en_mask = BIT(11),
+	.ns_mask = F_MASK_MND16,
+	.set_rate = set_rate_mnd,
+	.freq_tbl = clk_tbl_mdp_lcdc,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "mdp_lcdc_pclk_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(mdp_lcdc_pclk_clk.c),
+	},
+};
+
+static struct branch_clk mdp_lcdc_pad_pclk_clk = {
+	.b = {
+		.ctl_reg = MDP_LCDC_NS_REG,
+		.en_mask = BIT(12),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 29,
+		.reset_mask = P_MDP_LCDC_PAD_PCLK_CLK,
+	},
+	.parent = &mdp_lcdc_pclk_clk.c,
+	.c = {
+		.dbg_name = "mdp_lcdc_pad_pclk_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(mdp_lcdc_pad_pclk_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
+	F_RAW(       0, &gnd_clk.c,  0, (0x3<<2), 0, 0, NONE,    NULL),
+	F_RAW(24576000, &lpxo_clk.c, 0, (0x1<<2), 0, 0, NOMINAL, NULL),
+	F_END,
+};
+
+static struct rcg_clk mdp_vsync_clk = {
+	.b = {
+		.ctl_reg = MDP_VSYNC_REG,
+		.en_mask = BIT(0),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 30,
+		.reset_mask = P_MDP_VSYNC_CLK,
+	},
+	.ns_reg = MDP_VSYNC_REG,
+	.ns_mask = BM(3, 2),
+	.freq_tbl = clk_tbl_mdp_vsync,
+	.set_rate = set_rate_nop,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "mdp_vsync_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(mdp_vsync_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_mi2s_codec[] = {
+	F_MND16(       0, gnd,  1,   0,   0, NONE),
+	F_MND16( 2048000, lpxo, 4,   1,   3, NOMINAL),
+	F_MND16(12288000, lpxo, 2,   0,   0, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk mi2s_codec_rx_m_clk = {
+	.b = {
+		.ctl_reg = MI2S_RX_NS_REG,
+		.en_mask = BIT(12),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 12,
+		.reset_mask = P_MI2S_CODEC_RX_M_CLK,
+	},
+	.ns_reg = MI2S_RX_NS_REG,
+	.md_reg = MI2S_RX_NS_REG - 4,
+	.root_en_mask = BIT(11),
+	.ns_mask = F_MASK_MND16,
+	.set_rate = set_rate_mnd,
+	.freq_tbl = clk_tbl_mi2s_codec,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "mi2s_codec_rx_m_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(mi2s_codec_rx_m_clk.c),
+	},
+};
+
+static struct branch_clk mi2s_codec_rx_s_clk = {
+	.b = {
+		.ctl_reg = MI2S_RX_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 13,
+		.reset_mask = P_MI2S_CODEC_RX_S_CLK,
+	},
+	.parent = &mi2s_codec_rx_m_clk.c,
+	.c = {
+		.dbg_name = "mi2s_codec_rx_s_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(mi2s_codec_rx_s_clk.c),
+	},
+};
+
+static struct rcg_clk mi2s_codec_tx_m_clk = {
+	.b = {
+		.ctl_reg = MI2S_TX_NS_REG,
+		.en_mask = BIT(12),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 8,
+		.reset_mask = P_MI2S_CODEC_TX_M_CLK,
+	},
+	.ns_reg = MI2S_TX_NS_REG,
+	.md_reg = MI2S_TX_NS_REG - 4,
+	.root_en_mask = BIT(11),
+	.ns_mask = F_MASK_MND16,
+	.set_rate = set_rate_mnd,
+	.freq_tbl = clk_tbl_mi2s_codec,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "mi2s_codec_tx_m_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(mi2s_codec_tx_m_clk.c),
+	},
+};
+
+static struct branch_clk mi2s_codec_tx_s_clk = {
+	.b = {
+		.ctl_reg = MI2S_TX_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 11,
+		.reset_mask = P_MI2S_CODEC_TX_S_CLK,
+	},
+	.parent = &mi2s_codec_tx_m_clk.c,
+	.c = {
+		.dbg_name = "mi2s_codec_tx_s_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(mi2s_codec_tx_s_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_mi2s[] = {
+	F_MND16(       0, gnd,  1,   0,   0, NONE),
+	F_MND16(12288000, lpxo, 2,   0,   0, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk mi2s_m_clk = {
+	.b = {
+		.ctl_reg = MI2S_NS_REG,
+		.en_mask = BIT(12),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 4,
+		.reset_mask = P_MI2S_M_CLK,
+	},
+	.ns_reg = MI2S_NS_REG,
+	.md_reg = MI2S_NS_REG - 4,
+	.root_en_mask = BIT(11),
+	.ns_mask = F_MASK_MND16,
+	.set_rate = set_rate_mnd,
+	.freq_tbl = clk_tbl_mi2s,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "mi2s_m_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(mi2s_m_clk.c),
+	},
+};
+
+static struct branch_clk mi2s_s_clk = {
+	.b = {
+		.ctl_reg = MI2S_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 3,
+		.reset_mask = P_MI2S_S_CLK,
+	},
+	.parent = &mi2s_m_clk.c,
+	.c = {
+		.dbg_name = "mi2s_s_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(mi2s_s_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_midi[] = {
+	F_MND8(       0,  0,  0, gnd,  1,  0,  0, NONE),
+	F_MND8(98304000, 19, 12, pll3, 3,  2,  5, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk midi_clk = {
+	.b = {
+		.ctl_reg = MIDI_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 1,
+	},
+	.ns_reg = MIDI_NS_REG,
+	.md_reg = MIDI_NS_REG - 4,
+	.ns_mask = F_MASK_MND8(19, 12),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_midi,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "midi_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(midi_clk.c),
+	},
+};
+
+#define F_SDAC(f, s, div, m, n, v) \
+	{ \
+		.freq_hz = f, \
+		.md_val = MD16(m, n), \
+		.ns_val = N16(m, n) | SPDIV(SRC_SEL_SDAC_##s, div), \
+		.mnd_en_mask = BIT(8) * !!(n), \
+		.sys_vdd = v, \
+		.src_clk = &s##_clk.c, \
+	}
+
+static struct clk_freq_tbl clk_tbl_sdac[] = {
+	F_SDAC( 256000, lpxo, 4,   1,    24, NOMINAL),
+	F_SDAC( 352800, lpxo, 1, 147, 10240, NOMINAL),
+	F_SDAC( 384000, lpxo, 4,   1,    16, NOMINAL),
+	F_SDAC( 512000, lpxo, 4,   1,    12, NOMINAL),
+	F_SDAC( 705600, lpxo, 1, 147,  5120, NOMINAL),
+	F_SDAC( 768000, lpxo, 4,   1,     8, NOMINAL),
+	F_SDAC(1024000, lpxo, 4,   1,     6, NOMINAL),
+	F_SDAC(1411200, lpxo, 1, 147,  2560, NOMINAL),
+	F_SDAC(1536000, lpxo, 4,   1,     4, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk sdac_clk = {
+	.b = {
+		.ctl_reg = SDAC_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 2,
+		.reset_mask = P_SDAC_CLK,
+	},
+	.ns_reg = SDAC_NS_REG,
+	.md_reg = SDAC_NS_REG - 4,
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_sdac,
+	.ns_mask = F_MASK_MND16,
+	.set_rate = set_rate_mnd,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "sdac_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(sdac_clk.c),
+	},
+};
+
+static struct branch_clk sdac_m_clk = {
+	.b = {
+		.ctl_reg = SDAC_NS_REG,
+		.en_mask = BIT(12),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 17,
+		.reset_mask = P_SDAC_M_CLK,
+	},
+	.parent = &sdac_clk.c,
+	.c = {
+		.dbg_name = "sdac_m_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(sdac_m_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_tv[] = {
+	F_MND8(       0,  0,  0, gnd,  1,  0,   0, NONE),
+	F_MND8(27000000, 23, 16, pll4, 2,  2,  33, NOMINAL),
+	F_MND8(74250000, 23, 16, pll4, 2,  1,   6, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk tv_clk = {
+	.ns_reg = TV_NS_REG,
+	.b = {
+		.ctl_reg = TV_NS_REG,
+		.halt_check = NOCHECK,
+	},
+	.md_reg = TV_NS_REG - 4,
+	.ns_mask = F_MASK_MND8(23, 16),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_tv,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "tv_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(tv_clk.c),
+	},
+};
+
+static struct branch_clk hdmi_clk = {
+	.b = {
+		.ctl_reg = HDMI_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 7,
+		.reset_mask = P_HDMI_CLK,
+	},
+	.parent = &tv_clk.c,
+	.c = {
+		.dbg_name = "hdmi_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(hdmi_clk.c),
+	},
+};
+
+static struct branch_clk tv_dac_clk = {
+	.b = {
+		.ctl_reg = TV_NS_REG,
+		.en_mask = BIT(12),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 27,
+		.reset_mask = P_TV_DAC_CLK,
+	},
+	.parent = &tv_clk.c,
+	.c = {
+		.dbg_name = "tv_dac_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(tv_dac_clk.c),
+	},
+};
+
+static struct branch_clk tv_enc_clk = {
+	.b = {
+		.ctl_reg = TV_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 10,
+		.reset_mask = P_TV_ENC_CLK,
+	},
+	.parent = &tv_clk.c,
+	.c = {
+		.dbg_name = "tv_enc_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(tv_enc_clk.c),
+	},
+};
+
+/* Hacking root & branch into one param. */
+static struct branch_clk tsif_ref_clk = {
+	.b = {
+		.ctl_reg = TSIF_NS_REG,
+		.en_mask = BIT(9)|BIT(11),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 11,
+		.reset_mask = P_TSIF_REF_CLK,
+	},
+	.parent = &tv_clk.c,
+	.c = {
+		.dbg_name = "tsif_ref_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(tsif_ref_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_usb[] = {
+	F_MND8(       0,  0,  0, gnd,  1,  0,  0,  NONE),
+	F_MND8(60000000, 23, 16, pll1, 2,  5,  32, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk usb_hs_src_clk = {
+	.ns_reg = USBH_NS_REG,
+	.b = {
+		.ctl_reg = USBH_NS_REG,
+		.halt_check = NOCHECK,
+	},
+	.md_reg = USBH_NS_REG - 4,
+	.ns_mask = F_MASK_MND8(23, 16),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_usb,
+	.current_freq = &local_dummy_freq,
+	.depends = &axi_li_adsp_a_clk.c,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "usb_hs_src_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(usb_hs_src_clk.c),
+	},
+};
+
+static struct branch_clk usb_hs_clk = {
+	.b = {
+		.ctl_reg = USBH_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 26,
+		.reset_mask = P_USB_HS_CLK,
+	},
+	.c = {
+		.dbg_name = "usb_hs_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(usb_hs_clk.c),
+	},
+};
+
+static struct branch_clk usb_hs_core_clk = {
+	.b = {
+		.ctl_reg = USBH_NS_REG,
+		.en_mask = BIT(13),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 27,
+		.reset_mask = P_USB_HS_CORE_CLK,
+	},
+	.parent = &usb_hs_src_clk.c,
+	.c = {
+		.dbg_name = "usb_hs_core_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(usb_hs_core_clk.c),
+	},
+};
+
+static struct branch_clk usb_hs2_clk = {
+	.b = {
+		.ctl_reg = USBH2_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 3,
+		.reset_mask = P_USB_HS2_CLK,
+	},
+	.parent = &usb_hs_src_clk.c,
+	.c = {
+		.dbg_name = "usb_hs2_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(usb_hs2_clk.c),
+	},
+};
+
+static struct branch_clk usb_hs2_core_clk = {
+	.b = {
+		.ctl_reg = USBH2_NS_REG,
+		.en_mask = BIT(4),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 28,
+		.reset_mask = P_USB_HS2_CORE_CLK,
+	},
+	.parent = &usb_hs_src_clk.c,
+	.c = {
+		.dbg_name = "usb_hs2_core_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(usb_hs2_core_clk.c),
+	},
+};
+
+static struct branch_clk usb_hs3_clk = {
+	.b = {
+		.ctl_reg = USBH3_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 2,
+		.reset_mask = P_USB_HS3_CLK,
+	},
+	.parent = &usb_hs_src_clk.c,
+	.c = {
+		.dbg_name = "usb_hs3_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(usb_hs3_clk.c),
+	},
+};
+
+static struct branch_clk usb_hs3_core_clk = {
+	.b = {
+		.ctl_reg = USBH3_NS_REG,
+		.en_mask = BIT(4),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 29,
+		.reset_mask = P_USB_HS3_CORE_CLK,
+	},
+	.parent = &usb_hs_src_clk.c,
+	.c = {
+		.dbg_name = "usb_hs3_core_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &clk_ops_branch,
+		CLK_INIT(usb_hs3_core_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_vfe_jpeg[] = {
+	F_MND16( 24576000, lpxo, 1,   0,   0, NOMINAL),
+	F_MND16( 36864000, pll3, 4,   1,   5, NOMINAL),
+	F_MND16( 46080000, pll3, 4,   1,   4, NOMINAL),
+	F_MND16( 61440000, pll3, 4,   1,   3, NOMINAL),
+	F_MND16( 73728000, pll3, 2,   1,   5, NOMINAL),
+	F_MND16( 81920000, pll3, 3,   1,   3, NOMINAL),
+	F_MND16( 92160000, pll3, 4,   1,   2, NOMINAL),
+	F_MND16( 98304000, pll3, 3,   2,   5, NOMINAL),
+	F_MND16(105326000, pll3, 2,   2,   7, NOMINAL),
+	F_MND16(122880000, pll3, 2,   1,   3, NOMINAL),
+	F_MND16(147456000, pll3, 2,   2,   5, NOMINAL),
+	F_MND16(153600000, pll1, 2,   2,   5, NOMINAL),
+	F_MND16(192000000, pll1, 4,   0,   0, HIGH),
+	F_END,
+};
+
+static struct rcg_clk jpeg_clk = {
+	.b = {
+		.ctl_reg = JPEG_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 1,
+		.reset_mask = P_JPEG_CLK,
+	},
+	.ns_reg = JPEG_NS_REG,
+	.md_reg = JPEG_NS_REG - 4,
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_vfe_jpeg,
+	.ns_mask = F_MASK_MND16,
+	.set_rate = set_rate_mnd,
+	.depends = &axi_li_jpeg_clk.c,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "jpeg_clk",
+		.flags = CLKFLAG_AUTO_OFF,
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(jpeg_clk.c),
+	},
+};
+
+static struct rcg_clk vfe_clk = {
+	.b = {
+		.ctl_reg = CAM_VFE_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEB_REG,
+		.halt_bit = 0,
+		.reset_mask = P_VFE_CLK,
+	},
+	.ns_reg = CAM_VFE_NS_REG,
+	.md_reg = CAM_VFE_NS_REG - 4,
+	.root_en_mask = BIT(13),
+	.freq_tbl = clk_tbl_vfe_jpeg,
+	.ns_mask = F_MASK_MND16,
+	.set_rate = set_rate_mnd,
+	.depends = &axi_li_vfe_clk.c,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "vfe_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(vfe_clk.c),
+	},
+};
+
+static struct branch_clk vfe_mdc_clk = {
+	.b = {
+		.ctl_reg = CAM_VFE_NS_REG,
+		.en_mask = BIT(11),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 9,
+		.reset_mask = P_VFE_MDC_CLK,
+	},
+	.parent = &vfe_clk.c,
+	.c = {
+		.dbg_name = "vfe_mdc_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(vfe_mdc_clk.c),
+	},
+};
+
+static struct branch_clk vfe_camif_clk = {
+	.b = {
+		.ctl_reg = CAM_VFE_NS_REG,
+		.en_mask = BIT(15),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 13,
+		.reset_mask = P_VFE_CAMIF_CLK,
+	},
+	.parent = &vfe_clk.c,
+	.c = {
+		.dbg_name = "vfe_camif_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(vfe_camif_clk.c),
+	},
+};
+
+static struct branch_clk csi0_vfe_clk = {
+	.b = {
+		.ctl_reg = CSI_NS_REG,
+		.en_mask = BIT(15),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 16,
+		.reset_mask = P_CSI0_VFE_CLK,
+	},
+	.parent = &vfe_clk.c,
+	.c = {
+		.dbg_name = "csi0_vfe_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(csi0_vfe_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_cam[] = {
+	F_MND16(       0, gnd,  1,   0,   0, NONE),
+	F_MND16( 6000000, pll1, 4,   1,  32, NOMINAL),
+	F_MND16( 8000000, pll1, 4,   1,  24, NOMINAL),
+	F_MND16(12000000, pll1, 4,   1,  16, NOMINAL),
+	F_MND16(16000000, pll1, 4,   1,  12, NOMINAL),
+	F_MND16(19200000, pll1, 4,   1,  10, NOMINAL),
+	F_MND16(24000000, pll1, 4,   1,   8, NOMINAL),
+	F_MND16(32000000, pll1, 4,   1,   6, NOMINAL),
+	F_MND16(48000000, pll1, 4,   1,   4, NOMINAL),
+	F_MND16(64000000, pll1, 4,   1,   3, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk cam_m_clk = {
+	.b = {
+		.ctl_reg = CAM_NS_REG,
+		.halt_check = DELAY,
+		.reset_mask = P_CAM_M_CLK,
+	},
+	.ns_reg = CAM_NS_REG,
+	.md_reg = CAM_NS_REG - 4,
+	.root_en_mask = BIT(9),
+	.freq_tbl = clk_tbl_cam,
+	.ns_mask = F_MASK_MND16,
+	.set_rate = set_rate_mnd,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "cam_m_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(cam_m_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_vpe[] = {
+	F_MND8( 24576000, 22, 15, lpxo, 1,   0,   0, NOMINAL),
+	F_MND8( 30720000, 22, 15, pll3, 4,   1,   6, NOMINAL),
+	F_MND8( 61440000, 22, 15, pll3, 4,   1,   3, NOMINAL),
+	F_MND8( 81920000, 22, 15, pll3, 3,   1,   3, NOMINAL),
+	F_MND8(122880000, 22, 15, pll3, 3,   1,   2, NOMINAL),
+	F_MND8(147456000, 22, 15, pll3, 1,   1,   5, NOMINAL),
+	F_MND8(153600000, 22, 15, pll1, 1,   1,   5, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk vpe_clk = {
+	.b = {
+		.ctl_reg = VPE_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 10,
+		.reset_mask = P_VPE_CLK,
+	},
+	.ns_reg = VPE_NS_REG,
+	.md_reg = VPE_NS_REG - 4,
+	.ns_mask = F_MASK_MND8(22, 15),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_vpe,
+	.current_freq = &local_dummy_freq,
+	.depends = &axi_vpe_clk.c,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "vpe_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(vpe_clk.c),
+	},
+};
+
+
+static struct clk_freq_tbl clk_tbl_mfc[] = {
+	F_MND8( 24576000, 24, 17, lpxo, 1,   0,   0, NOMINAL),
+	F_MND8( 30720000, 24, 17, pll3, 4,   1,   6, NOMINAL),
+	F_MND8( 61440000, 24, 17, pll3, 4,   1,   3, NOMINAL),
+	F_MND8( 81920000, 24, 17, pll3, 3,   1,   3, NOMINAL),
+	F_MND8(122880000, 24, 17, pll3, 3,   1,   2, NOMINAL),
+	F_MND8(147456000, 24, 17, pll3, 1,   1,   5, NOMINAL),
+	F_MND8(153600000, 24, 17, pll1, 1,   1,   5, NOMINAL),
+	F_MND8(170667000, 24, 17, pll1, 1,   2,   9, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk mfc_clk = {
+	.b = {
+		.ctl_reg = MFC_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 12,
+		.reset_mask = P_MFC_CLK,
+	},
+	.ns_reg = MFC_NS_REG,
+	.md_reg = MFC_NS_REG - 4,
+	.ns_mask = F_MASK_MND8(24, 17),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_mfc,
+	.current_freq = &local_dummy_freq,
+	.depends = &axi_mfc_clk.c,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "mfc_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(mfc_clk.c),
+	},
+};
+
+static struct branch_clk mfc_div2_clk = {
+	.b = {
+		.ctl_reg = MFC_NS_REG,
+		.en_mask = BIT(15),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 11,
+		.reset_mask = P_MFC_DIV2_CLK,
+	},
+	.parent = &mfc_clk.c,
+	.c = {
+		.dbg_name = "mfc_div2_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(mfc_div2_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_spi[] = {
+	F_MND8(       0,  0,  0, gnd,  1,   0,     0, NONE),
+	F_MND8( 9963243, 19, 12, pll3, 4,   2,    37, NOMINAL),
+	F_MND8(26331429, 19, 12, pll3, 4,   1,     7, NOMINAL),
+	F_END,
+};
+
+static struct rcg_clk spi_clk = {
+	.b = {
+		.ctl_reg = SPI_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 0,
+		.reset_mask = P_SPI_CLK,
+	},
+	.ns_reg = SPI_NS_REG,
+	.md_reg = SPI_NS_REG - 4,
+	.ns_mask = F_MASK_MND8(19, 12),
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_spi,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_mnd,
+	.c = {
+		.dbg_name = "spi_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(spi_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_lpa_codec[] = {
+	F_RAW(1, NULL, 0, 0, 0, 0, LOW, NULL), /* src MI2S_CODEC_RX */
+	F_RAW(2, NULL, 0, 1, 0, 0, LOW, NULL), /* src ECODEC_CIF */
+	F_RAW(3, NULL, 0, 2, 0, 0, LOW, NULL), /* src MI2S */
+	F_RAW(4, NULL, 0, 3, 0, 0, LOW, NULL), /* src SDAC */
+	F_END,
+};
+
+static struct rcg_clk lpa_codec_clk = {
+	.b = {
+		.ctl_reg = LPA_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 6,
+		.reset_mask = P_LPA_CODEC_CLK,
+	},
+	.ns_reg = LPA_NS_REG,
+	.ns_mask = BM(1, 0),
+	.set_rate = set_rate_nop,
+	.freq_tbl = clk_tbl_lpa_codec,
+	.current_freq = &local_dummy_freq,
+	.c = {
+		.dbg_name = "lpa_codec_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(lpa_codec_clk.c),
+	},
+};
+
+static struct clk_freq_tbl clk_tbl_mdc[] = {
+	F_RAW(1, NULL, 0, 0, 0, 0, LOW, NULL),
+	F_END
+};
+
+static struct rcg_clk mdc_clk = {
+	.b = {
+		.ctl_reg = MDC_NS_REG,
+		.en_mask = BIT(9),
+		.halt_reg = CLK_HALT_STATEA_REG,
+		.halt_bit = 10,
+		.reset_mask = P_MDC_CLK,
+	},
+	.ns_reg = MDC_NS_REG,
+	.root_en_mask = BIT(11),
+	.freq_tbl = clk_tbl_mdc,
+	.current_freq = &local_dummy_freq,
+	.set_rate = set_rate_nop,
+	.c = {
+		.dbg_name = "mdc_clk",
+		.ops = &soc_clk_ops_7x30,
+		CLK_INIT(mdc_clk.c),
+	},
+};
+
+static struct branch_clk lpa_core_clk = {
+	.b = {
+		.ctl_reg = LPA_NS_REG,
+		.en_mask = BIT(5),
+		.halt_reg = CLK_HALT_STATEC_REG,
+		.halt_bit = 5,
+		.reset_mask = P_LPA_CORE_CLK,
+	},
+	.c = {
+		.dbg_name = "lpa_core_clk",
+		.ops = &clk_ops_branch,
+		CLK_INIT(lpa_core_clk.c),
+	},
+};
+
+static DEFINE_CLK_PCOM(adsp_clk, ADSP_CLK, 0);
+static DEFINE_CLK_PCOM(codec_ssbi_clk,	CODEC_SSBI_CLK, 0);
+static DEFINE_CLK_PCOM(ebi1_clk, EBI1_CLK, CLK_MIN);
+static DEFINE_CLK_PCOM(ecodec_clk, ECODEC_CLK, 0);
+static DEFINE_CLK_PCOM(gp_clk, GP_CLK, 0);
+static DEFINE_CLK_PCOM(uart3_clk, UART3_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(usb_phy_clk, USB_PHY_CLK, CLKFLAG_AUTO_OFF | CLK_MIN);
+
+static DEFINE_CLK_PCOM(p_grp_2d_clk, GRP_2D_CLK, 0);
+static DEFINE_CLK_PCOM(p_grp_2d_p_clk, GRP_2D_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_hdmi_clk, HDMI_CLK, 0);
+static DEFINE_CLK_PCOM(p_jpeg_clk, JPEG_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_jpeg_p_clk, JPEG_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_lpa_codec_clk, LPA_CODEC_CLK, 0);
+static DEFINE_CLK_PCOM(p_lpa_core_clk, LPA_CORE_CLK, 0);
+static DEFINE_CLK_PCOM(p_lpa_p_clk, LPA_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_mi2s_m_clk, MI2S_M_CLK, 0);
+static DEFINE_CLK_PCOM(p_mi2s_s_clk, MI2S_S_CLK, 0);
+static DEFINE_CLK_PCOM(p_mi2s_codec_rx_m_clk, MI2S_CODEC_RX_M_CLK, 0);
+static DEFINE_CLK_PCOM(p_mi2s_codec_rx_s_clk, MI2S_CODEC_RX_S_CLK, 0);
+static DEFINE_CLK_PCOM(p_mi2s_codec_tx_m_clk, MI2S_CODEC_TX_M_CLK, 0);
+static DEFINE_CLK_PCOM(p_mi2s_codec_tx_s_clk, MI2S_CODEC_TX_S_CLK, 0);
+static DEFINE_CLK_PCOM(p_sdac_clk, SDAC_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_sdac_m_clk, SDAC_M_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_vfe_clk, VFE_CLK, 0);
+static DEFINE_CLK_PCOM(p_vfe_camif_clk, VFE_CAMIF_CLK, 0);
+static DEFINE_CLK_PCOM(p_vfe_mdc_clk, VFE_MDC_CLK, 0);
+static DEFINE_CLK_PCOM(p_vfe_p_clk, VFE_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_grp_3d_clk, GRP_3D_CLK, 0);
+static DEFINE_CLK_PCOM(p_grp_3d_p_clk, GRP_3D_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_imem_clk, IMEM_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mdp_lcdc_pad_pclk_clk, MDP_LCDC_PAD_PCLK_CLK, 0);
+static DEFINE_CLK_PCOM(p_mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK, 0);
+static DEFINE_CLK_PCOM(p_mdp_p_clk, MDP_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_mdp_vsync_clk, MDP_VSYNC_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_tsif_ref_clk, TSIF_REF_CLK, 0);
+static DEFINE_CLK_PCOM(p_tsif_p_clk, TSIF_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_tv_dac_clk, TV_DAC_CLK, 0);
+static DEFINE_CLK_PCOM(p_tv_enc_clk, TV_ENC_CLK, 0);
+static DEFINE_CLK_PCOM(p_emdh_clk, EMDH_CLK,
+		CLKFLAG_AUTO_OFF | CLKFLAG_MIN | CLKFLAG_MAX);
+static DEFINE_CLK_PCOM(p_emdh_p_clk, EMDH_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_i2c_clk, I2C_CLK, 0);
+static DEFINE_CLK_PCOM(p_i2c_2_clk, I2C_2_CLK, 0);
+static DEFINE_CLK_PCOM(p_mdc_clk, MDC_CLK, 0);
+static DEFINE_CLK_PCOM(p_pmdh_clk, PMDH_CLK,
+		CLKFLAG_AUTO_OFF | CLKFLAG_MIN | CLKFLAG_MAX);
+static DEFINE_CLK_PCOM(p_pmdh_p_clk, PMDH_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_sdc1_clk, SDC1_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_sdc1_p_clk, SDC1_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_sdc2_clk, SDC2_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_sdc2_p_clk, SDC2_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_sdc3_clk, SDC3_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_sdc3_p_clk, SDC3_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_sdc4_clk, SDC4_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_sdc4_p_clk, SDC4_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_uart2_clk, UART2_CLK, 0);
+static DEFINE_CLK_PCOM(p_usb_hs2_clk, USB_HS2_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_usb_hs2_core_clk, USB_HS2_CORE_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_usb_hs2_p_clk, USB_HS2_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_usb_hs3_clk, USB_HS3_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_usb_hs3_core_clk, USB_HS3_CORE_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_usb_hs3_p_clk, USB_HS3_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_qup_i2c_clk, QUP_I2C_CLK, 0);
+static DEFINE_CLK_PCOM(p_spi_clk, SPI_CLK, 0);
+static DEFINE_CLK_PCOM(p_spi_p_clk, SPI_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_uart1_clk, UART1_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_uart1dm_clk, UART1DM_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_uart2dm_clk, UART2DM_CLK, 0);
+static DEFINE_CLK_PCOM(p_usb_hs_clk, USB_HS_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_usb_hs_core_clk, USB_HS_CORE_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_usb_hs_p_clk, USB_HS_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_cam_m_clk, CAM_M_CLK, 0);
+static DEFINE_CLK_PCOM(p_camif_pad_p_clk, CAMIF_PAD_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_csi0_clk, CSI0_CLK, 0);
+static DEFINE_CLK_PCOM(p_csi0_vfe_clk, CSI0_VFE_CLK, 0);
+static DEFINE_CLK_PCOM(p_csi0_p_clk, CSI0_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_mdp_clk, MDP_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mfc_clk, MFC_CLK, 0);
+static DEFINE_CLK_PCOM(p_mfc_div2_clk, MFC_DIV2_CLK, 0);
+static DEFINE_CLK_PCOM(p_mfc_p_clk, MFC_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_vpe_clk, VPE_CLK, 0);
+static DEFINE_CLK_PCOM(p_adm_clk, ADM_CLK, 0);
+static DEFINE_CLK_PCOM(p_ce_clk, CE_CLK, 0);
+static DEFINE_CLK_PCOM(p_axi_rotator_clk, AXI_ROTATOR_CLK, 0);
+static DEFINE_CLK_PCOM(p_rotator_imem_clk, ROTATOR_IMEM_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_rotator_p_clk, ROTATOR_P_CLK, CLKFLAG_AUTO_OFF);
+
+static struct pcom_clk pbus_clk = {
+	.id = P_PBUS_CLK,
+	.c = {
+		.ops = &clk_ops_pcom_div2,
+		.flags = CLKFLAG_MIN,
+		.dbg_name = "pbus_clk",
+		CLK_INIT(pbus_clk.c),
+	},
+};
+
+static DEFINE_CLK_VOTER(ebi_dtv_clk, &pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi_kgsl_clk, &pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi_lcdc_clk, &pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi_mddi_clk, &pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi_tv_clk, &pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi_vcd_clk, &pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi_vfe_clk, &pbus_clk.c);
+
+/*
+ * SoC-specific functions required by clock-local driver
+ */
+
+/* Update the sys_vdd voltage given a level. */
+static int msm7x30_update_sys_vdd(enum sys_vdd_level level)
+{
+	int rc, target_mv;
+	static const int mv[NUM_SYS_VDD_LEVELS] = {
+		[NONE...LOW] = 1000,
+		[NOMINAL] = 1100,
+		[HIGH]    = 1200,
+	};
+
+	target_mv = mv[level];
+	rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_MSMC1, &target_mv, NULL);
+	if (rc)
+		goto out;
+	if (target_mv) {
+		rc = -EINVAL;
+		goto out;
+	}
+out:
+	return rc;
+}
+
+/* Implementation for clk_set_flags(). */
+int soc_clk_set_flags(struct clk *clk, unsigned clk_flags)
+{
+	u32 regval, ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+
+	if (clk == &vfe_clk.c) {
+		regval = readl_relaxed(CAM_VFE_NS_REG);
+		/* Flag values chosen for backward compatibility
+		 * with proc_comm remote clock control. */
+		if (clk_flags == 0x00000100) {
+			/* Select external source. */
+			regval |= BIT(14);
+		} else if (clk_flags == 0x00000200) {
+			/* Select internal source. */
+			regval &= ~BIT(14);
+		} else
+			ret = -EINVAL;
+
+		writel_relaxed(regval, CAM_VFE_NS_REG);
+		/* Make sure write is issued before returning. */
+		mb();
+	} else
+		ret = -EPERM;
+
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+	return ret;
+}
+
+static int msm7x30_clk_reset(struct clk *clk, enum clk_reset_action action)
+{
+	/* reset_mask is actually a proc_comm id */
+	unsigned id = to_rcg_clk(clk)->b.reset_mask;
+	return pc_clk_reset(id, action);
+}
+
+static int soc_branch_clk_reset(struct clk *clk, enum clk_reset_action action)
+{
+	unsigned id = to_branch_clk(clk)->b.reset_mask;
+	return pc_clk_reset(id, action);
+}
+
+/*
+ * Clock ownership detection code
+ */
+
+enum {
+	SH2_OWN_GLBL,
+	SH2_OWN_APPS1,
+	SH2_OWN_APPS2,
+	SH2_OWN_ROW1,
+	SH2_OWN_ROW2,
+	SH2_OWN_APPS3,
+	NUM_OWNERSHIP
+};
+static __initdata u32 ownership_regs[NUM_OWNERSHIP];
+
+static void __init cache_ownership(void)
+{
+	ownership_regs[SH2_OWN_GLBL]  = readl_relaxed(SH2_OWN_GLBL_BASE_REG);
+	ownership_regs[SH2_OWN_APPS1] = readl_relaxed(SH2_OWN_APPS1_BASE_REG);
+	ownership_regs[SH2_OWN_APPS2] = readl_relaxed(SH2_OWN_APPS2_BASE_REG);
+	ownership_regs[SH2_OWN_ROW1]  = readl_relaxed(SH2_OWN_ROW1_BASE_REG);
+	ownership_regs[SH2_OWN_ROW2]  = readl_relaxed(SH2_OWN_ROW2_BASE_REG);
+	ownership_regs[SH2_OWN_APPS3] = readl_relaxed(SH2_OWN_APPS3_BASE_REG);
+}
+
+static void __init print_ownership(void)
+{
+	pr_info("Clock ownership\n");
+	pr_info("  GLBL  : %08x\n", ownership_regs[SH2_OWN_GLBL]);
+	pr_info("  APPS  : %08x %08x %08x\n", ownership_regs[SH2_OWN_APPS1],
+		ownership_regs[SH2_OWN_APPS2], ownership_regs[SH2_OWN_APPS3]);
+	pr_info("  ROW   : %08x %08x\n", ownership_regs[SH2_OWN_ROW1],
+		ownership_regs[SH2_OWN_ROW2]);
+}
+
+#define O(x) (&ownership_regs[(SH2_OWN_##x)])
+#define OWN(r, b, name, clk, dev) \
+	{ \
+		.lk = CLK_LOOKUP(name, clk.c, dev), \
+		.remote = &p_##clk.c, \
+		.reg = O(r), \
+		.bit = BIT(b), \
+	}
+
+static struct clk_local_ownership {
+	struct clk_lookup lk;
+	const u32 *reg;
+	const u32 bit;
+	struct clk *remote;
+} ownership_map[] __initdata = {
+	/* Sources */
+	{ CLK_LOOKUP("pll1_clk",	pll1_clk.c,	"acpu") },
+	{ CLK_LOOKUP("pll2_clk",	pll2_clk.c,	"acpu") },
+	{ CLK_LOOKUP("pll3_clk",	pll3_clk.c,	"acpu") },
+
+	/* PCOM */
+	{ CLK_LOOKUP("adsp_clk",	adsp_clk.c,	NULL) },
+	{ CLK_LOOKUP("codec_ssbi_clk",	codec_ssbi_clk.c,	NULL) },
+	{ CLK_LOOKUP("ebi1_clk",	ebi1_clk.c,	NULL) },
+	{ CLK_LOOKUP("ecodec_clk",	ecodec_clk.c,	NULL) },
+	{ CLK_LOOKUP("gp_clk",		gp_clk.c,	NULL) },
+	{ CLK_LOOKUP("uart_clk",	uart3_clk.c,	"msm_serial.2") },
+	{ CLK_LOOKUP("usb_phy_clk",	usb_phy_clk.c,	NULL) },
+	{ CLK_LOOKUP("pbus_clk",	pbus_clk.c,	NULL) },
+
+	/* Voters */
+	{ CLK_LOOKUP("ebi1_dtv_clk",	ebi_dtv_clk.c,	NULL) },
+	{ CLK_LOOKUP("ebi1_kgsl_clk",	ebi_kgsl_clk.c,	NULL) },
+	{ CLK_LOOKUP("ebi1_lcdc_clk",	ebi_lcdc_clk.c,	NULL) },
+	{ CLK_LOOKUP("ebi1_mddi_clk",	ebi_mddi_clk.c,	NULL) },
+	{ CLK_LOOKUP("ebi1_tv_clk",	ebi_tv_clk.c,	NULL) },
+	{ CLK_LOOKUP("ebi1_vcd_clk",	ebi_vcd_clk.c,	NULL) },
+	{ CLK_LOOKUP("ebi1_vfe_clk",	ebi_vfe_clk.c,	NULL) },
+
+	/*
+	 * This is a many-to-one mapping because we don't know how the remote
+	 * clock code has decided to handle the dependencies between clocks for
+	 * a particular hardware block. We determine the ownership for all the
+	 * clocks going into a block by checking the ownership bit of one
+	 * register (usually the ns register).
+	 */
+	OWN(APPS1,  6, "grp_2d_clk",	grp_2d_clk,	NULL),
+	OWN(APPS1,  6, "grp_2d_pclk",	grp_2d_p_clk,	NULL),
+	OWN(APPS1, 31, "hdmi_clk",	hdmi_clk,	NULL),
+	OWN(APPS1,  0, "jpeg_clk",	jpeg_clk,	NULL),
+	OWN(APPS1,  0, "jpeg_pclk",	jpeg_p_clk,	NULL),
+	OWN(APPS1, 23, "lpa_codec_clk", lpa_codec_clk,	NULL),
+	OWN(APPS1, 23, "lpa_core_clk",	lpa_core_clk,	NULL),
+	OWN(APPS1, 23, "lpa_pclk",	lpa_p_clk,	NULL),
+	OWN(APPS1, 28, "mi2s_m_clk",	mi2s_m_clk,	NULL),
+	OWN(APPS1, 28, "mi2s_s_clk",	mi2s_s_clk,	NULL),
+	OWN(APPS1, 12, "mi2s_codec_rx_m_clk", mi2s_codec_rx_m_clk, NULL),
+	OWN(APPS1, 12, "mi2s_codec_rx_s_clk", mi2s_codec_rx_s_clk, NULL),
+	OWN(APPS1, 14, "mi2s_codec_tx_m_clk", mi2s_codec_tx_m_clk, NULL),
+	OWN(APPS1, 14, "mi2s_codec_tx_s_clk", mi2s_codec_tx_s_clk, NULL),
+	{ CLK_LOOKUP("midi_clk",        midi_clk.c,     NULL),
+		O(APPS1), BIT(22) },
+	OWN(APPS1, 26, "sdac_clk",	sdac_clk,	NULL),
+	OWN(APPS1, 26, "sdac_m_clk",	sdac_m_clk,	NULL),
+	OWN(APPS1,  8, "vfe_clk",	vfe_clk,	NULL),
+	OWN(APPS1,  8, "vfe_camif_clk", vfe_camif_clk,	NULL),
+	OWN(APPS1,  8, "vfe_mdc_clk",	vfe_mdc_clk,	NULL),
+	OWN(APPS1,  8, "vfe_pclk",	vfe_p_clk,	NULL),
+
+	OWN(APPS2,  0, "grp_clk",	grp_3d_clk,	NULL),
+	OWN(APPS2,  0, "grp_pclk",	grp_3d_p_clk,	NULL),
+	{ CLK_LOOKUP("grp_src_clk",     grp_3d_src_clk.c, NULL),
+		O(APPS2), BIT(0), &p_grp_3d_clk.c },
+	OWN(APPS2,  0, "imem_clk",	imem_clk,	NULL),
+	OWN(APPS2,  4, "mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk, NULL),
+	OWN(APPS2,  4, "mdp_lcdc_pclk_clk", mdp_lcdc_pclk_clk, NULL),
+	OWN(APPS2,  4, "mdp_pclk",	mdp_p_clk,	NULL),
+	OWN(APPS2, 28, "mdp_vsync_clk", mdp_vsync_clk,	NULL),
+	OWN(APPS2,  5, "tsif_ref_clk",	tsif_ref_clk,	NULL),
+	OWN(APPS2,  5, "tsif_pclk",	tsif_p_clk,	NULL),
+	{ CLK_LOOKUP("tv_src_clk",      tv_clk.c,       NULL),
+		O(APPS2), BIT(2), &p_tv_enc_clk.c },
+	OWN(APPS2,  2, "tv_dac_clk",	tv_dac_clk,	NULL),
+	OWN(APPS2,  2, "tv_enc_clk",	tv_enc_clk,	NULL),
+
+	OWN(ROW1,  7, "emdh_clk",	emdh_clk,	"msm_mddi.1"),
+	OWN(ROW1,  7, "emdh_pclk",	emdh_p_clk,	"msm_mddi.1"),
+	OWN(ROW1, 11, "i2c_clk",	i2c_clk,	"msm_i2c.0"),
+	OWN(ROW1, 12, "i2c_clk",	i2c_2_clk,	"msm_i2c.2"),
+	OWN(ROW1, 17, "mdc_clk",	mdc_clk,	NULL),
+	OWN(ROW1, 19, "mddi_clk",	pmdh_clk,	NULL),
+	OWN(ROW1, 19, "mddi_pclk",	pmdh_p_clk,	NULL),
+	OWN(ROW1, 23, "sdc_clk",	sdc1_clk,	"msm_sdcc.1"),
+	OWN(ROW1, 23, "sdc_pclk",	sdc1_p_clk,	"msm_sdcc.1"),
+	OWN(ROW1, 25, "sdc_clk",	sdc2_clk,	"msm_sdcc.2"),
+	OWN(ROW1, 25, "sdc_pclk",	sdc2_p_clk,	"msm_sdcc.2"),
+	OWN(ROW1, 27, "sdc_clk",	sdc3_clk,	"msm_sdcc.3"),
+	OWN(ROW1, 27, "sdc_pclk",	sdc3_p_clk,	"msm_sdcc.3"),
+	OWN(ROW1, 29, "sdc_clk",	sdc4_clk,	"msm_sdcc.4"),
+	OWN(ROW1, 29, "sdc_pclk",	sdc4_p_clk,	"msm_sdcc.4"),
+	OWN(ROW1,  0, "uart_clk",	uart2_clk,	"msm_serial.1"),
+	OWN(ROW1,  2, "usb_hs2_clk",	usb_hs2_clk,	NULL),
+	OWN(ROW1,  2, "usb_hs2_core_clk", usb_hs2_core_clk, NULL),
+	OWN(ROW1,  2, "usb_hs2_pclk",	usb_hs2_p_clk,	NULL),
+	OWN(ROW1,  4, "usb_hs3_clk",	usb_hs3_clk,	NULL),
+	OWN(ROW1,  4, "usb_hs3_core_clk", usb_hs3_core_clk, NULL),
+	OWN(ROW1,  4, "usb_hs3_pclk",	usb_hs3_p_clk,	NULL),
+
+	OWN(ROW2,  3, "qup_clk",	qup_i2c_clk,	"qup_i2c.4"),
+	OWN(ROW2,  1, "spi_clk",	spi_clk,	NULL),
+	OWN(ROW2,  1, "spi_pclk",	spi_p_clk,	NULL),
+	OWN(ROW2,  9, "uart_clk",	uart1_clk,	"msm_serial.0"),
+	OWN(ROW2,  6, "uartdm_clk",	uart1dm_clk,	"msm_serial_hs.0"),
+	OWN(ROW2,  8, "uartdm_clk",	uart2dm_clk,	"msm_serial_hs.1"),
+	OWN(ROW2, 11, "usb_hs_clk",	usb_hs_clk,	NULL),
+	OWN(ROW2, 11, "usb_hs_core_clk", usb_hs_core_clk, NULL),
+	OWN(ROW2, 11, "usb_hs_pclk",	usb_hs_p_clk,	NULL),
+
+	OWN(APPS3,  6, "cam_m_clk",	cam_m_clk,	NULL),
+	OWN(APPS3,  6, "camif_pad_pclk", camif_pad_p_clk, NULL),
+	OWN(APPS3, 11, "csi_clk",	csi0_clk,	NULL),
+	OWN(APPS3, 11, "csi_vfe_clk",	csi0_vfe_clk,	NULL),
+	OWN(APPS3, 11, "csi_pclk",	csi0_p_clk,	NULL),
+	OWN(APPS3,  0, "mdp_clk",	mdp_clk,	NULL),
+	OWN(APPS3,  2, "mfc_clk",	mfc_clk,	NULL),
+	OWN(APPS3,  2, "mfc_div2_clk",	mfc_div2_clk,	NULL),
+	OWN(APPS3,  2, "mfc_pclk",	mfc_p_clk,	NULL),
+	OWN(APPS3,  4, "vpe_clk",	vpe_clk,	NULL),
+
+	OWN(GLBL,  8, "adm_clk",	adm_clk,	NULL),
+	{ CLK_LOOKUP("adm_pclk", adm_p_clk.c,	NULL), O(GLBL), BIT(13) },
+	OWN(GLBL,  8, "ce_clk",	ce_clk,		NULL),
+	OWN(GLBL, 13, "rotator_clk",	axi_rotator_clk, NULL),
+	OWN(GLBL, 13, "rotator_imem_clk", rotator_imem_clk, NULL),
+	OWN(GLBL, 13, "rotator_pclk",	rotator_p_clk,	NULL),
+	{ CLK_LOOKUP("uartdm_pclk",     uart1dm_p_clk.c, "msm_serial_hs.0"),
+		O(GLBL), BIT(8) },
+	{ CLK_LOOKUP("uartdm_pclk",     uart2dm_p_clk.c, "msm_serial_hs.1"),
+		O(GLBL), BIT(8) },
+};
+
+struct clk_lookup msm_clocks_7x30[ARRAY_SIZE(ownership_map)];
+unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);
+
+static void __init set_clock_ownership(void)
+{
+	unsigned i;
+	struct clk_lookup *lk;
+
+	for (i = 0; i < ARRAY_SIZE(ownership_map); i++) {
+		const u32 *reg = ownership_map[i].reg;
+		u32 bit = ownership_map[i].bit;
+		struct clk *remote = ownership_map[i].remote;
+
+		lk = &ownership_map[i].lk;
+		memcpy(&msm_clocks_7x30[i], lk, sizeof(*lk));
+
+		if (reg && !(*reg & bit))
+			msm_clocks_7x30[i].clk = remote;
+	}
+}
+
+/*
+ * Miscellaneous clock register initializations
+ */
+static const struct reg_init {
+	const void __iomem *reg;
+	u32 mask;
+	u32 val;
+} ri_list[] __initconst = {
+	/* Enable UMDX_P clock. Known to causes issues, so never turn off. */
+	{GLBL_CLK_ENA_2_SC_REG, BIT(2), BIT(2)},
+
+	/* Disable all the child clocks of USB_HS_SRC. */
+	{ USBH_NS_REG, BIT(13) | BIT(9), 0 },
+	{ USBH2_NS_REG, BIT(9) | BIT(4), 0 },
+	{ USBH3_NS_REG, BIT(9) | BIT(4), 0 },
+
+	{EMDH_NS_REG, BM(18, 17) , BVAL(18, 17, 0x3)}, /* RX div = div-4. */
+	{PMDH_NS_REG, BM(18, 17), BVAL(18, 17, 0x3)}, /* RX div = div-4. */
+	/* MI2S_CODEC_RX_S src = MI2S_CODEC_RX_M. */
+	{MI2S_RX_NS_REG, BIT(14), 0x0},
+	/* MI2S_CODEC_TX_S src = MI2S_CODEC_TX_M. */
+	{MI2S_TX_NS_REG, BIT(14), 0x0},
+	{MI2S_NS_REG, BIT(14), 0x0}, /* MI2S_S src = MI2S_M. */
+	/* Allow DSP to decide the LPA CORE src. */
+	{LPA_CORE_CLK_MA0_REG, BIT(0), BIT(0)},
+	{LPA_CORE_CLK_MA2_REG, BIT(0), BIT(0)},
+	{MI2S_CODEC_RX_DIV_REG, 0xF, 0xD}, /* MI2S_CODEC_RX_S div = div-8. */
+	{MI2S_CODEC_TX_DIV_REG, 0xF, 0xD}, /* MI2S_CODEC_TX_S div = div-8. */
+	{MI2S_DIV_REG, 0xF, 0x7}, /* MI2S_S div = div-8. */
+	{MDC_NS_REG, 0x3, 0x3}, /* MDC src = external MDH src. */
+	{SDAC_NS_REG, BM(15, 14), 0x0}, /* SDAC div = div-1. */
+	/* Disable sources TCXO/5 & TCXO/6. UART1 src = TCXO*/
+	{UART_NS_REG, BM(26, 25) | BM(2, 0), 0x0},
+	/* HDMI div = div-1, non-inverted. tv_enc_src = tv_clk_src */
+	{HDMI_NS_REG, 0x7, 0x0},
+	{TV_NS_REG, BM(15, 14), 0x0}, /* tv_clk_src_div2 = div-1 */
+
+	/* USBH core clocks src = USB_HS_SRC. */
+	{USBH_NS_REG, BIT(15), BIT(15)},
+	{USBH2_NS_REG, BIT(6), BIT(6)},
+	{USBH3_NS_REG, BIT(6), BIT(6)},
+};
+
+/* Local clock driver initialization. */
+void __init msm_clk_soc_init(void)
+{
+	int i;
+	u32 val;
+
+	cache_ownership();
+	print_ownership();
+	set_clock_ownership();
+
+	soc_update_sys_vdd = msm7x30_update_sys_vdd;
+
+	/* When we have no local clock control, the rest of the code in this
+	 * function is a NOP since writes to shadow regions that we don't own
+	 * are ignored. */
+
+	clk_set_rate(&usb_hs_src_clk.c, clk_tbl_usb[1].freq_hz);
+
+	for (i = 0; i < ARRAY_SIZE(ri_list); i++) {
+		val = readl_relaxed(ri_list[i].reg);
+		val &= ~ri_list[i].mask;
+		val |= ri_list[i].val;
+		writel_relaxed(val, ri_list[i].reg);
+	}
+
+	clk_set_rate(&i2c_clk.c, 19200000);
+	clk_set_rate(&i2c_2_clk.c, 19200000);
+	clk_set_rate(&qup_i2c_clk.c, 19200000);
+	clk_set_rate(&uart1_clk.c, 19200000);
+	clk_set_rate(&uart2_clk.c, 19200000);
+	clk_set_rate(&mi2s_m_clk.c, 12288000);
+	clk_set_rate(&midi_clk.c, 98304000);
+	clk_set_rate(&mdp_vsync_clk.c, 24576000);
+	clk_set_rate(&glbl_root_clk.c, 1);
+	clk_set_rate(&mdc_clk.c, 1);
+	/* Sync the LPA_CODEC clock to MI2S_CODEC_RX */
+	clk_set_rate(&lpa_codec_clk.c, 1);
+	/* Sync the GRP2D clock to AXI */
+	clk_set_rate(&grp_2d_clk.c, 1);
+}
+
+/*
+ * Clock operation handler registration
+ */
+static struct clk_ops soc_clk_ops_7x30 = {
+	.enable = rcg_clk_enable,
+	.disable = rcg_clk_disable,
+	.auto_off = rcg_clk_auto_off,
+	.set_rate = rcg_clk_set_rate,
+	.set_min_rate = rcg_clk_set_min_rate,
+	.set_max_rate = rcg_clk_set_max_rate,
+	.get_rate = rcg_clk_get_rate,
+	.is_enabled = rcg_clk_is_enabled,
+	.round_rate = rcg_clk_round_rate,
+	.reset = msm7x30_clk_reset,
+	.set_flags = soc_clk_set_flags,
+	.is_local = local_clk_is_local,
+	.get_parent = rcg_clk_get_parent,
+};
+
+static struct clk_ops clk_ops_branch = {
+	.enable = branch_clk_enable,
+	.disable = branch_clk_disable,
+	.auto_off = branch_clk_auto_off,
+	.is_enabled = branch_clk_is_enabled,
+	.reset = soc_branch_clk_reset,
+	.set_flags = soc_clk_set_flags,
+	.is_local = local_clk_is_local,
+	.get_parent = branch_clk_get_parent,
+	.set_parent = branch_clk_set_parent,
+};
diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h
deleted file mode 100644
index 3eaaee1..0000000
--- a/arch/arm/mach-msm/clock-7x30.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
-#define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
-
-enum {
-	L_7X30_NONE_CLK = -1,
-	L_7X30_ADM_CLK,
-	L_7X30_I2C_CLK,
-	L_7X30_I2C_2_CLK,
-	L_7X30_QUP_I2C_CLK,
-	L_7X30_UART1DM_CLK,
-	L_7X30_UART1DM_P_CLK,
-	L_7X30_UART2DM_CLK,
-	L_7X30_UART2DM_P_CLK,
-	L_7X30_EMDH_CLK,
-	L_7X30_EMDH_P_CLK,
-	L_7X30_PMDH_CLK,
-	L_7X30_PMDH_P_CLK,
-	L_7X30_GRP_2D_CLK,
-	L_7X30_GRP_2D_P_CLK,
-	L_7X30_GRP_3D_SRC_CLK,
-	L_7X30_GRP_3D_CLK,
-	L_7X30_GRP_3D_P_CLK,
-	L_7X30_IMEM_CLK,
-	L_7X30_SDC1_CLK,
-	L_7X30_SDC1_P_CLK,
-	L_7X30_SDC2_CLK,
-	L_7X30_SDC2_P_CLK,
-	L_7X30_SDC3_CLK,
-	L_7X30_SDC3_P_CLK,
-	L_7X30_SDC4_CLK,
-	L_7X30_SDC4_P_CLK,
-	L_7X30_MDP_CLK,
-	L_7X30_MDP_P_CLK,
-	L_7X30_MDP_LCDC_PCLK_CLK,
-	L_7X30_MDP_LCDC_PAD_PCLK_CLK,
-	L_7X30_MDP_VSYNC_CLK,
-	L_7X30_MI2S_CODEC_RX_M_CLK,
-	L_7X30_MI2S_CODEC_RX_S_CLK,
-	L_7X30_MI2S_CODEC_TX_M_CLK,
-	L_7X30_MI2S_CODEC_TX_S_CLK,
-	L_7X30_MI2S_M_CLK,
-	L_7X30_MI2S_S_CLK,
-	L_7X30_LPA_CODEC_CLK,
-	L_7X30_LPA_CORE_CLK,
-	L_7X30_LPA_P_CLK,
-	L_7X30_MIDI_CLK,
-	L_7X30_MDC_CLK,
-	L_7X30_ROTATOR_IMEM_CLK,
-	L_7X30_ROTATOR_P_CLK,
-	L_7X30_SDAC_M_CLK,
-	L_7X30_SDAC_CLK,
-	L_7X30_UART1_CLK,
-	L_7X30_UART2_CLK,
-	L_7X30_UART3_CLK,
-	L_7X30_TV_CLK,
-	L_7X30_TV_DAC_CLK,
-	L_7X30_TV_ENC_CLK,
-	L_7X30_HDMI_CLK,
-	L_7X30_TSIF_REF_CLK,
-	L_7X30_TSIF_P_CLK,
-	L_7X30_USB_HS_SRC_CLK,
-	L_7X30_USB_HS_CLK,
-	L_7X30_USB_HS_CORE_CLK,
-	L_7X30_USB_HS_P_CLK,
-	L_7X30_USB_HS2_CLK,
-	L_7X30_USB_HS2_CORE_CLK,
-	L_7X30_USB_HS2_P_CLK,
-	L_7X30_USB_HS3_CLK,
-	L_7X30_USB_HS3_CORE_CLK,
-	L_7X30_USB_HS3_P_CLK,
-	L_7X30_VFE_CLK,
-	L_7X30_VFE_P_CLK,
-	L_7X30_VFE_MDC_CLK,
-	L_7X30_VFE_CAMIF_CLK,
-	L_7X30_CAMIF_PAD_P_CLK,
-	L_7X30_CAM_M_CLK,
-	L_7X30_JPEG_CLK,
-	L_7X30_JPEG_P_CLK,
-	L_7X30_VPE_CLK,
-	L_7X30_MFC_CLK,
-	L_7X30_MFC_DIV2_CLK,
-	L_7X30_MFC_P_CLK,
-	L_7X30_SPI_CLK,
-	L_7X30_SPI_P_CLK,
-	L_7X30_CSI0_CLK,
-	L_7X30_CSI0_VFE_CLK,
-	L_7X30_CSI0_P_CLK,
-	L_7X30_CSI1_CLK,
-	L_7X30_CSI1_VFE_CLK,
-	L_7X30_CSI1_P_CLK,
-	L_7X30_GLBL_ROOT_CLK,
-
-	L_7X30_AXI_LI_VG_CLK,
-	L_7X30_AXI_LI_GRP_CLK,
-	L_7X30_AXI_LI_JPEG_CLK,
-	L_7X30_AXI_GRP_2D_CLK,
-	L_7X30_AXI_MFC_CLK,
-	L_7X30_AXI_VPE_CLK,
-	L_7X30_AXI_LI_VFE_CLK,
-	L_7X30_AXI_LI_APPS_CLK,
-	L_7X30_AXI_MDP_CLK,
-	L_7X30_AXI_IMEM_CLK,
-	L_7X30_AXI_LI_ADSP_A_CLK,
-	L_7X30_AXI_ROTATOR_CLK,
-
-	L_7X30_NR_CLKS
-};
-
-struct clk_ops;
-extern struct clk_ops clk_ops_7x30;
-
-struct clk_ops *clk_7x30_is_local(uint32_t id);
-int clk_7x30_init(void);
-
-void pll_enable(uint32_t pll);
-void pll_disable(uint32_t pll);
-
-extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
-
-#define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) {	\
-	.con_id = clk_name, \
-	.dev_id = clk_dev, \
-	.clk = &(struct clk){ \
-		.id = L_7X30_##clk_id, \
-		.remote_id = P_##clk_id, \
-		.flags = clk_flags, \
-		.dbg_name = #clk_id, \
-	}, \
-	}
-
-#endif
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index b571a95..2781ccf 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -186,6 +186,9 @@ void __init msm_clock_init(struct clk_lookup *clock_tbl, size_t num_clocks)
 {
 	unsigned n;
 
+	/* Do SoC-speficic clock init operations. */
+	msm_clk_soc_init();
+
 	for (n = 0; n < num_clocks; n++) {
 		struct clk *clk = clock_tbl[n].clk;
 		struct clk *parent = clk_get_parent(clk);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 6aecd95..82aa133 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -72,6 +72,12 @@ struct clk {
 #define CLK_MAX CLKFLAG_MAX
 #define CLK_MINMAX (CLK_MIN | CLK_MAX)
 
+#if defined(CONFIG_ARCH_MSM7X30)
+void __init msm_clk_soc_init(void);
+#else
+static inline void __init msm_clk_soc_init(void) { }
+#endif
+
 #ifdef CONFIG_DEBUG_FS
 int __init clock_debug_init(void);
 int __init clock_debug_add(struct clk *clock);
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 6574b7a..92600e6 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -24,14 +24,10 @@
 #include <mach/board.h>
 
 #include "devices.h"
-#include "clock-voter.h"
 #include "smd_private.h"
 
 #include <asm/mach/flash.h>
 
-#include "clock-pcom.h"
-#include "clock-7x30.h"
-
 #include <mach/mmc.h>
 
 static struct resource resources_uart2[] = {
@@ -130,180 +126,3 @@ struct platform_device msm_device_hsusb_host = {
 		.coherent_dma_mask      = 0xffffffffULL,
 	},
 };
-
-static DEFINE_CLK_PCOM(adm_clk,		ADM_CLK,		0);
-static DEFINE_CLK_PCOM(adsp_clk,	ADSP_CLK,		0);
-static DEFINE_CLK_PCOM(cam_m_clk,	CAM_M_CLK,		0);
-static DEFINE_CLK_PCOM(camif_pad_p_clk,	CAMIF_PAD_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(ce_clk,		CE_CLK,			0);
-static DEFINE_CLK_PCOM(codec_ssbi_clk,	CODEC_SSBI_CLK,		0);
-static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,		CLK_MIN);
-static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,		0);
-static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	OFF | CLK_MINMAX);
-static DEFINE_CLK_PCOM(emdh_p_clk,	EMDH_P_CLK,		OFF);
-static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,			0);
-static DEFINE_CLK_PCOM(grp_2d_clk,	GRP_2D_CLK,		0);
-static DEFINE_CLK_PCOM(grp_2d_p_clk,	GRP_2D_P_CLK,		0);
-static DEFINE_CLK_PCOM(grp_3d_clk,	GRP_3D_CLK,		0);
-static DEFINE_CLK_PCOM(grp_3d_p_clk,	GRP_3D_P_CLK,		0);
-static DEFINE_CLK_PCOM(hdmi_clk,	HDMI_CLK,		0);
-static DEFINE_CLK_PCOM(imem_clk,	IMEM_CLK,		OFF);
-static DEFINE_CLK_PCOM(jpeg_clk,	JPEG_CLK,		OFF);
-static DEFINE_CLK_PCOM(jpeg_p_clk,	JPEG_P_CLK,		OFF);
-static DEFINE_CLK_PCOM(lpa_codec_clk,	LPA_CODEC_CLK,		0);
-static DEFINE_CLK_PCOM(lpa_core_clk,	LPA_CORE_CLK,		0);
-static DEFINE_CLK_PCOM(lpa_p_clk,	LPA_P_CLK,		0);
-static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,		0);
-static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	OFF | CLK_MINMAX);
-static DEFINE_CLK_PCOM(pmdh_p_clk,	PMDH_P_CLK,		0);
-static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,		OFF);
-static DEFINE_CLK_PCOM(mdp_p_clk,	MDP_P_CLK,		0);
-static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK,	0);
-static DEFINE_CLK_PCOM(mdp_lcdc_pad_pclk_clk, MDP_LCDC_PAD_PCLK_CLK, 0);
-static DEFINE_CLK_PCOM(mdp_vsync_clk,	MDP_VSYNC_CLK,		0);
-static DEFINE_CLK_PCOM(mfc_clk,		MFC_CLK,		0);
-static DEFINE_CLK_PCOM(mfc_div2_clk,	MFC_DIV2_CLK,		0);
-static DEFINE_CLK_PCOM(mfc_p_clk,	MFC_P_CLK,		0);
-static DEFINE_CLK_PCOM(mi2s_m_clk,	MI2S_M_CLK,  		0);
-static DEFINE_CLK_PCOM(mi2s_s_clk,	MI2S_S_CLK,  		0);
-static DEFINE_CLK_PCOM(mi2s_codec_rx_m_clk,	MI2S_CODEC_RX_M_CLK,  0);
-static DEFINE_CLK_PCOM(mi2s_codec_rx_s_clk,	MI2S_CODEC_RX_S_CLK,  0);
-static DEFINE_CLK_PCOM(mi2s_codec_tx_m_clk,	MI2S_CODEC_TX_M_CLK,  0);
-static DEFINE_CLK_PCOM(mi2s_codec_tx_s_clk,	MI2S_CODEC_TX_S_CLK,  0);
-static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,		0);
-static DEFINE_CLK_PCOM(axi_rotator_clk,	AXI_ROTATOR_CLK,	0);
-static DEFINE_CLK_PCOM(rotator_imem_clk, ROTATOR_IMEM_CLK,	OFF);
-static DEFINE_CLK_PCOM(rotator_p_clk,	ROTATOR_P_CLK,		OFF);
-static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,		OFF);
-static DEFINE_CLK_PCOM(spi_clk,		SPI_CLK,		0);
-static DEFINE_CLK_PCOM(spi_p_clk,	SPI_P_CLK,		0);
-static DEFINE_CLK_PCOM(tv_dac_clk,	TV_DAC_CLK,		0);
-static DEFINE_CLK_PCOM(tv_enc_clk,	TV_ENC_CLK,		0);
-static DEFINE_CLK_PCOM(uart2_clk,	UART2_CLK,		0);
-static DEFINE_CLK_PCOM(usb_phy_clk,	USB_PHY_CLK,		0);
-static DEFINE_CLK_PCOM(usb_hs_clk,	USB_HS_CLK,		OFF);
-static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,		OFF);
-static DEFINE_CLK_PCOM(usb_hs_core_clk,	USB_HS_CORE_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_hs2_clk,	USB_HS2_CLK,		OFF);
-static DEFINE_CLK_PCOM(usb_hs2_p_clk,	USB_HS2_P_CLK,		OFF);
-static DEFINE_CLK_PCOM(usb_hs2_core_clk,USB_HS2_CORE_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_hs3_clk,	USB_HS3_CLK,		OFF);
-static DEFINE_CLK_PCOM(usb_hs3_p_clk,	USB_HS3_P_CLK,		OFF);
-static DEFINE_CLK_PCOM(usb_hs3_core_clk,USB_HS3_CORE_CLK,	OFF);
-static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,		OFF | CLK_MIN);
-static DEFINE_CLK_PCOM(vfe_camif_clk,	VFE_CAMIF_CLK, 		0);
-static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,		0);
-static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,		0);
-static DEFINE_CLK_PCOM(vfe_p_clk,	VFE_P_CLK,		OFF);
-static DEFINE_CLK_PCOM(vpe_clk,		VPE_CLK,		0);
-
-static DEFINE_CLK_PCOM(csi0_clk,	CSI0_CLK,		0);
-static DEFINE_CLK_PCOM(csi0_p_clk,	CSI0_P_CLK,		0);
-static DEFINE_CLK_PCOM(csi0_vfe_clk,	CSI0_VFE_CLK,		0);
-
-static struct pcom_clk pbus_clk = {
-	.id = P_PBUS_CLK,
-	.c = {
-		.dbg_name = "pbus_clk",
-		.ops = &clk_ops_pcom_div2,
-		.flags = CLK_MIN,
-		CLK_INIT(pbus_clk.c),
-	},
-};
-
-static DEFINE_CLK_VOTER(ebi1_dtv_clk,	&pbus_clk.c);
-static DEFINE_CLK_VOTER(ebi1_kgsl_clk,	&pbus_clk.c);
-static DEFINE_CLK_VOTER(ebi1_lcdc_clk,	&pbus_clk.c);
-static DEFINE_CLK_VOTER(ebi1_mddi_clk,	&pbus_clk.c);
-static DEFINE_CLK_VOTER(ebi1_tv_clk,	&pbus_clk.c);
-static DEFINE_CLK_VOTER(ebi1_usb_clk,	&pbus_clk.c);
-static DEFINE_CLK_VOTER(ebi1_vcd_clk,	&pbus_clk.c);
-static DEFINE_CLK_VOTER(ebi1_vfe_clk,	&pbus_clk.c);
-
-struct clk_lookup msm_clocks_7x30[] = {
-	CLK_LOOKUP("adm_clk",			adm_clk.c,	"msm_dmov"),
-	CLK_LOOKUP("adsp_clk",			adsp_clk.c,	NULL),
-	CLK_LOOKUP("cam_m_clk",			cam_m_clk.c,	NULL),
-	CLK_LOOKUP("camif_pad_pclk",		camif_pad_p_clk.c,	NULL),
-	CLK_LOOKUP("ce_clk",			ce_clk.c,	NULL),
-	CLK_LOOKUP("codec_ssbi_clk",		codec_ssbi_clk.c,	NULL),
-	CLK_LOOKUP("ebi1_clk",			ebi1_clk.c,	NULL),
-	CLK_LOOKUP("ecodec_clk",		ecodec_clk.c,	NULL),
-	CLK_LOOKUP("emdh_clk",			emdh_clk.c,	NULL),
-	CLK_LOOKUP("emdh_pclk",			emdh_p_clk.c,	NULL),
-	CLK_LOOKUP("gp_clk",			gp_clk.c,	NULL),
-	CLK_LOOKUP("grp_2d_clk",		grp_2d_clk.c,	NULL),
-	CLK_LOOKUP("grp_2d_pclk",		grp_2d_p_clk.c,	NULL),
-	CLK_LOOKUP("grp_clk",			grp_3d_clk.c,	NULL),
-	CLK_LOOKUP("grp_pclk",			grp_3d_p_clk.c,	NULL),
-	CLK_LOOKUP("grp_src_clk",		grp_3d_clk.c,	NULL),
-	CLK_LOOKUP("hdmi_clk",			hdmi_clk.c,	NULL),
-	CLK_LOOKUP("imem_clk",			imem_clk.c,	NULL),
-	CLK_LOOKUP("jpeg_clk",			jpeg_clk.c,	NULL),
-	CLK_LOOKUP("jpeg_pclk",			jpeg_p_clk.c,	NULL),
-	CLK_LOOKUP("lpa_codec_clk",		lpa_codec_clk.c,	NULL),
-	CLK_LOOKUP("lpa_core_clk",		lpa_core_clk.c,	NULL),
-	CLK_LOOKUP("lpa_pclk",			lpa_p_clk.c,	NULL),
-	CLK_LOOKUP("mdc_clk",			mdc_clk.c,	NULL),
-	CLK_LOOKUP("mddi_clk",			pmdh_clk.c,	NULL),
-	CLK_LOOKUP("mddi_pclk",			pmdh_p_clk.c,	NULL),
-	CLK_LOOKUP("mdp_clk",			mdp_clk.c,	NULL),
-	CLK_LOOKUP("mdp_pclk",			mdp_p_clk.c,	NULL),
-	CLK_LOOKUP("mdp_lcdc_pclk_clk",		mdp_lcdc_pclk_clk.c,	NULL),
-	CLK_LOOKUP("mdp_lcdc_pad_pclk_clk",	mdp_lcdc_pad_pclk_clk.c, NULL),
-	CLK_LOOKUP("mdp_vsync_clk",		mdp_vsync_clk.c,	NULL),
-	CLK_LOOKUP("mfc_clk",			mfc_clk.c,		NULL),
-	CLK_LOOKUP("mfc_div2_clk",		mfc_div2_clk.c,		NULL),
-	CLK_LOOKUP("mfc_pclk",			mfc_p_clk.c,		NULL),
-	CLK_LOOKUP("mi2s_m_clk",		mi2s_m_clk.c,		NULL),
-	CLK_LOOKUP("mi2s_s_clk",		mi2s_s_clk.c,		NULL),
-	CLK_LOOKUP("mi2s_codec_rx_m_clk",	mi2s_codec_rx_m_clk.c,	NULL),
-	CLK_LOOKUP("mi2s_codec_rx_s_clk",	mi2s_codec_rx_s_clk.c,	NULL),
-	CLK_LOOKUP("mi2s_codec_tx_m_clk",	mi2s_codec_tx_m_clk.c,	NULL),
-	CLK_LOOKUP("mi2s_codec_tx_s_clk",	mi2s_codec_tx_s_clk.c,	NULL),
-	CLK_LOOKUP("pbus_clk",			pbus_clk.c,		NULL),
-	CLK_LOOKUP("pcm_clk",			pcm_clk.c,		NULL),
-	CLK_LOOKUP("rotator_clk",		axi_rotator_clk.c,	NULL),
-	CLK_LOOKUP("rotator_imem_clk",		rotator_imem_clk.c,	NULL),
-	CLK_LOOKUP("rotator_pclk",		rotator_p_clk.c,	NULL),
-	CLK_LOOKUP("sdac_clk",			sdac_clk.c,	NULL),
-	CLK_LOOKUP("spi_clk",			spi_clk.c,	NULL),
-	CLK_LOOKUP("spi_pclk",			spi_p_clk.c,	NULL),
-	CLK_LOOKUP("tv_src_clk",		tv_enc_clk.c,	NULL),
-	CLK_LOOKUP("tv_dac_clk",		tv_dac_clk.c,	NULL),
-	CLK_LOOKUP("tv_enc_clk",		tv_enc_clk.c,	NULL),
-	CLK_LOOKUP("uart_clk",			uart2_clk.c,	"msm_serial.1"),
-	CLK_LOOKUP("usb_phy_clk",		usb_phy_clk.c,	NULL),
-	CLK_LOOKUP("usb_hs_clk",		usb_hs_clk.c,		NULL),
-	CLK_LOOKUP("usb_hs_pclk",		usb_hs_p_clk.c,		NULL),
-	CLK_LOOKUP("usb_hs_core_clk",		usb_hs_core_clk.c,	NULL),
-	CLK_LOOKUP("usb_hs2_clk",		usb_hs2_clk.c,		NULL),
-	CLK_LOOKUP("usb_hs2_pclk",		usb_hs2_p_clk.c,	NULL),
-	CLK_LOOKUP("usb_hs2_core_clk",		usb_hs2_core_clk.c,	NULL),
-	CLK_LOOKUP("usb_hs3_clk",		usb_hs3_clk.c,		NULL),
-	CLK_LOOKUP("usb_hs3_pclk",		usb_hs3_p_clk.c,	NULL),
-	CLK_LOOKUP("usb_hs3_core_clk",		usb_hs3_core_clk.c,	NULL),
-	CLK_LOOKUP("vdc_clk",			vdc_clk.c,		NULL),
-	CLK_LOOKUP("vfe_camif_clk",		vfe_camif_clk.c,	NULL),
-	CLK_LOOKUP("vfe_clk",			vfe_clk.c,	NULL),
-	CLK_LOOKUP("vfe_mdc_clk",		vfe_mdc_clk.c,	NULL),
-	CLK_LOOKUP("vfe_pclk",			vfe_p_clk.c,	NULL),
-	CLK_LOOKUP("vpe_clk",			vpe_clk.c,	NULL),
-
-	/* 7x30 v2 hardware only. */
-	CLK_LOOKUP("csi_clk",			csi0_clk.c,	NULL),
-	CLK_LOOKUP("csi_pclk",			csi0_p_clk.c,	NULL),
-	CLK_LOOKUP("csi_vfe_clk",		csi0_vfe_clk.c,	NULL),
-
-	CLK_LOOKUP("ebi1_clk",	ebi1_dtv_clk.c,		NULL),
-	CLK_LOOKUP("ebi1_clk",	ebi1_kgsl_clk.c,	NULL),
-	CLK_LOOKUP("ebi1_clk",	ebi1_lcdc_clk.c,	NULL),
-	CLK_LOOKUP("ebi1_clk",	ebi1_mddi_clk.c,	NULL),
-	CLK_LOOKUP("ebi1_clk",	ebi1_tv_clk.c,		NULL),
-	CLK_LOOKUP("ebi1_clk",	ebi1_usb_clk.c,		NULL),
-	CLK_LOOKUP("ebi1_clk",	ebi1_vcd_clk.c,		NULL),
-	CLK_LOOKUP("ebi1_clk",	ebi1_vfe_clk.c,		NULL),
-};
-
-unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);
-
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 18/34] msm: clock-local: Add support for 8x60 clock types

[David Brown]

From: Matt Wagantall <mattw@codeaurora.org>

Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-local.c |  290 ++++++++++++++++++++++++++++++++++++---
 arch/arm/mach-msm/clock-local.h |   47 ++++++-
 2 files changed, 318 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index 7a6dc5d..3ee318d 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -81,11 +81,185 @@ void set_rate_nop(struct rcg_clk *clk, struct clk_freq_tbl *nf)
 	 */
 }
 
-int (*soc_update_sys_vdd)(enum sys_vdd_level level);
+void set_rate_mnd_8(struct rcg_clk *clk, struct clk_freq_tbl *nf)
+{
+	u32 ctl_reg_val;
+
+	/* Assert MND reset. */
+	ctl_reg_val = readl_relaxed(clk->b.ctl_reg);
+	ctl_reg_val |= BIT(8);
+	writel_relaxed(ctl_reg_val, clk->b.ctl_reg);
+
+	/* Program M and D values. */
+	writel_relaxed(nf->md_val, clk->md_reg);
+
+	/* Program MN counter Enable and Mode. */
+	ctl_reg_val &= ~(clk->ctl_mask);
+	ctl_reg_val |= nf->ctl_val;
+	writel_relaxed(ctl_reg_val, clk->b.ctl_reg);
+
+	/* Deassert MND reset. */
+	ctl_reg_val &= ~BIT(8);
+	writel_relaxed(ctl_reg_val, clk->b.ctl_reg);
+}
+
+void set_rate_mnd_banked(struct rcg_clk *clk, struct clk_freq_tbl *nf)
+{
+	struct bank_masks *banks = clk->bank_masks;
+	const struct bank_mask_info *new_bank_masks;
+	const struct bank_mask_info *old_bank_masks;
+	u32 ns_reg_val, ctl_reg_val;
+	u32 bank_sel;
+
+	/*
+	 * Determine active bank and program the other one. If the clock is
+	 * off, program the active bank since bank switching won't work if
+	 * both banks aren't running.
+	 */
+	ctl_reg_val = readl_relaxed(clk->b.ctl_reg);
+	bank_sel = !!(ctl_reg_val & banks->bank_sel_mask);
+	 /* If clock isn't running, don't switch banks. */
+	bank_sel ^= (!clk->enabled || clk->current_freq->freq_hz == 0);
+	if (bank_sel == 0) {
+		new_bank_masks = &banks->bank1_mask;
+		old_bank_masks = &banks->bank0_mask;
+	} else {
+		new_bank_masks = &banks->bank0_mask;
+		old_bank_masks = &banks->bank1_mask;
+	}
+
+	ns_reg_val = readl_relaxed(clk->ns_reg);
+
+	/* Assert bank MND reset. */
+	ns_reg_val |= new_bank_masks->rst_mask;
+	writel_relaxed(ns_reg_val, clk->ns_reg);
+
+	/*
+	 * Program NS only if the clock is enabled, since the NS will be set
+	 * as part of the enable procedure and should remain with a low-power
+	 * MUX input selected until then.
+	 */
+	if (clk->enabled) {
+		ns_reg_val &= ~(new_bank_masks->ns_mask);
+		ns_reg_val |= (nf->ns_val & new_bank_masks->ns_mask);
+		writel_relaxed(ns_reg_val, clk->ns_reg);
+	}
+
+	writel_relaxed(nf->md_val, new_bank_masks->md_reg);
+
+	/* Enable counter only if clock is enabled. */
+	if (clk->enabled)
+		ctl_reg_val |= new_bank_masks->mnd_en_mask;
+	else
+		ctl_reg_val &= ~(new_bank_masks->mnd_en_mask);
+
+	ctl_reg_val &= ~(new_bank_masks->mode_mask);
+	ctl_reg_val |= (nf->ctl_val & new_bank_masks->mode_mask);
+	writel_relaxed(ctl_reg_val, clk->b.ctl_reg);
+
+	/* Deassert bank MND reset. */
+	ns_reg_val &= ~(new_bank_masks->rst_mask);
+	writel_relaxed(ns_reg_val, clk->ns_reg);
+
+	/*
+	 * Switch to the new bank if clock is running.  If it isn't, then
+	 * no switch is necessary since we programmed the active bank.
+	 */
+	if (clk->enabled && clk->current_freq->freq_hz) {
+		ctl_reg_val ^= banks->bank_sel_mask;
+		writel_relaxed(ctl_reg_val, clk->b.ctl_reg);
+		/*
+		 * Wait at least 6 cycles of slowest bank's clock
+		 * for the glitch-free MUX to fully switch sources.
+		 */
+		mb();
+		udelay(1);
+
+		/* Disable old bank's MN counter. */
+		ctl_reg_val &= ~(old_bank_masks->mnd_en_mask);
+		writel_relaxed(ctl_reg_val, clk->b.ctl_reg);
+
+		/* Program old bank to a low-power source and divider. */
+		ns_reg_val &= ~(old_bank_masks->ns_mask);
+		ns_reg_val |= (clk->freq_tbl->ns_val & old_bank_masks->ns_mask);
+		writel_relaxed(ns_reg_val, clk->ns_reg);
+	}
+
+	/*
+	 * If this freq requires the MN counter to be enabled,
+	 * update the enable mask to match the current bank.
+	 */
+	if (nf->mnd_en_mask)
+		nf->mnd_en_mask = new_bank_masks->mnd_en_mask;
+	/* Update the NS mask to match the current bank. */
+	clk->ns_mask = new_bank_masks->ns_mask;
+}
+
+void set_rate_div_banked(struct rcg_clk *clk, struct clk_freq_tbl *nf)
+{
+	struct bank_masks *banks = clk->bank_masks;
+	const struct bank_mask_info *new_bank_masks;
+	const struct bank_mask_info *old_bank_masks;
+	u32 ns_reg_val, bank_sel;
+
+	/*
+	 * Determine active bank and program the other one. If the clock is
+	 * off, program the active bank since bank switching won't work if
+	 * both banks aren't running.
+	 */
+	ns_reg_val = readl_relaxed(clk->ns_reg);
+	bank_sel = !!(ns_reg_val & banks->bank_sel_mask);
+	 /* If clock isn't running, don't switch banks. */
+	bank_sel ^= (!clk->enabled || clk->current_freq->freq_hz == 0);
+	if (bank_sel == 0) {
+		new_bank_masks = &banks->bank1_mask;
+		old_bank_masks = &banks->bank0_mask;
+	} else {
+		new_bank_masks = &banks->bank0_mask;
+		old_bank_masks = &banks->bank1_mask;
+	}
+
+	/*
+	 * Program NS only if the clock is enabled, since the NS will be set
+	 * as part of the enable procedure and should remain with a low-power
+	 * MUX input selected until then.
+	 */
+	if (clk->enabled) {
+		ns_reg_val &= ~(new_bank_masks->ns_mask);
+		ns_reg_val |= (nf->ns_val & new_bank_masks->ns_mask);
+		writel_relaxed(ns_reg_val, clk->ns_reg);
+	}
+
+	/*
+	 * Switch to the new bank if clock is running.  If it isn't, then
+	 * no switch is necessary since we programmed the active bank.
+	 */
+	if (clk->enabled && clk->current_freq->freq_hz) {
+		ns_reg_val ^= banks->bank_sel_mask;
+		writel_relaxed(ns_reg_val, clk->ns_reg);
+		/*
+		 * Wait at least 6 cycles of slowest bank's clock
+		 * for the glitch-free MUX to fully switch sources.
+		 */
+		mb();
+		udelay(1);
+
+		/* Program old bank to a low-power source and divider. */
+		ns_reg_val &= ~(old_bank_masks->ns_mask);
+		ns_reg_val |= (clk->freq_tbl->ns_val & old_bank_masks->ns_mask);
+		writel_relaxed(ns_reg_val, clk->ns_reg);
+	}
+
+	/* Update the NS mask to match the current bank. */
+	clk->ns_mask = new_bank_masks->ns_mask;
+}
+
 /*
  * SYS_VDD voting functions
  */
 
+int (*soc_update_sys_vdd)(enum sys_vdd_level level);
+
 /* Update system voltage level given the current votes. */
 static int local_update_sys_vdd(void)
 {
@@ -392,17 +566,22 @@ static int _rcg_clk_set_rate(struct rcg_clk *clk, struct clk_freq_tbl *nf)
 
 	spin_lock(&local_clock_reg_lock);
 
-	/* Disable all branches to prevent glitches. */
-	list_for_each_entry(chld, &clk->c.children, siblings) {
-		struct branch_clk *x = to_branch_clk(chld);
-		/* Don't bother turning off if it is already off.
-		 * Checking ch->enabled is cheaper (cache) than reading
-		 * and writing to a register (uncached/unbuffered). */
-		if (x->enabled)
-			__branch_clk_disable_reg(&x->b, x->c.dbg_name);
+	/* Disable branch if clock isn't dual-banked with a glitch-free MUX. */
+	if (clk->bank_masks == NULL) {
+		/* Disable all branches to prevent glitches. */
+		list_for_each_entry(chld, &clk->c.children, siblings) {
+			struct branch_clk *x = to_branch_clk(chld);
+			/*
+			 * We don't need to grab the child's lock because
+			 * we hold the local_clock_reg_lock and 'enabled' is
+			 * only modified within lock.
+			 */
+			if (x->enabled)
+				__branch_clk_disable_reg(&x->b, x->c.dbg_name);
+		}
+		if (clk->enabled)
+			__rcg_clk_disable_reg(clk);
 	}
-	if (clk->enabled)
-		__rcg_clk_disable_reg(clk);
 
 	/* Perform clock-specific frequency switch operations. */
 	BUG_ON(!clk->set_rate);
@@ -414,13 +593,16 @@ static int _rcg_clk_set_rate(struct rcg_clk *clk, struct clk_freq_tbl *nf)
 	 */
 	clk->current_freq = nf;
 
-	if (clk->enabled)
-		__rcg_clk_enable_reg(clk);
-	/* Enable only branches that were ON before. */
-	list_for_each_entry(chld, &clk->c.children, siblings) {
-		struct branch_clk *x = to_branch_clk(chld);
-		if (x->enabled)
-			__branch_clk_enable_reg(&x->b, x->c.dbg_name);
+	/* Enable any clocks that were disabled. */
+	if (clk->bank_masks == NULL) {
+		if (clk->enabled)
+			__rcg_clk_enable_reg(clk);
+		/* Enable only branches that were ON before. */
+		list_for_each_entry(chld, &clk->c.children, siblings) {
+			struct branch_clk *x = to_branch_clk(chld);
+			if (x->enabled)
+				__branch_clk_enable_reg(&x->b, x->c.dbg_name);
+		}
 	}
 
 	spin_unlock(&local_clock_reg_lock);
@@ -583,6 +765,78 @@ struct clk_ops clk_ops_pll_vote = {
 	.is_local = local_clk_is_local,
 };
 
+static int pll_clk_enable(struct clk *clk)
+{
+	u32 mode;
+	unsigned long flags;
+	struct pll_clk *pll = to_pll_clk(clk);
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+	mode = readl_relaxed(pll->mode_reg);
+	/* Disable PLL bypass mode. */
+	mode |= BIT(1);
+	writel_relaxed(mode, pll->mode_reg);
+
+	/*
+	 * H/W requires a 5us delay between disabling the bypass and
+	 * de-asserting the reset. Delay 10us just to be safe.
+	 */
+	mb();
+	udelay(10);
+
+	/* De-assert active-low PLL reset. */
+	mode |= BIT(2);
+	writel_relaxed(mode, pll->mode_reg);
+
+	/* Wait until PLL is locked. */
+	mb();
+	udelay(50);
+
+	/* Enable PLL output. */
+	mode |= BIT(0);
+	writel_relaxed(mode, pll->mode_reg);
+
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+	return 0;
+}
+
+static void pll_clk_disable(struct clk *clk)
+{
+	u32 mode;
+	unsigned long flags;
+	struct pll_clk *pll = to_pll_clk(clk);
+
+	/*
+	 * Disable the PLL output, disable test mode, enable
+	 * the bypass mode, and assert the reset.
+	 */
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+	mode = readl_relaxed(pll->mode_reg);
+	mode &= ~BM(3, 0);
+	writel_relaxed(mode, pll->mode_reg);
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+}
+
+static unsigned pll_clk_get_rate(struct clk *clk)
+{
+	struct pll_clk *pll = to_pll_clk(clk);
+	return pll->rate;
+}
+
+static struct clk *pll_clk_get_parent(struct clk *clk)
+{
+	struct pll_clk *pll = to_pll_clk(clk);
+	return pll->parent;
+}
+
+struct clk_ops clk_ops_pll = {
+	.enable = pll_clk_enable,
+	.disable = pll_clk_disable,
+	.get_rate = pll_clk_get_rate,
+	.get_parent = pll_clk_get_parent,
+	.is_local = local_clk_is_local,
+};
+
 struct clk_ops clk_ops_gnd = {
 	.get_rate = fixed_clk_get_rate,
 	.is_local = local_clk_is_local,
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index a7c9001..e004490 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -46,6 +46,23 @@ struct clk_freq_tbl {
 	void		*const extra_freq_data;
 };
 
+/* Some clocks have two banks to avoid glitches when switching frequencies.
+ * The unused bank is programmed while running on the other bank, and
+ * switched to afterwards. The following two structs describe the banks. */
+struct bank_mask_info {
+	void *const md_reg;
+	const uint32_t	ns_mask;
+	const uint32_t	rst_mask;
+	const uint32_t	mnd_en_mask;
+	const uint32_t	mode_mask;
+};
+
+struct bank_masks {
+	const uint32_t			bank_sel_mask;
+	const struct bank_mask_info	bank0_mask;
+	const struct bank_mask_info	bank1_mask;
+};
+
 #define F_RAW(f, sc, m_v, n_v, c_v, m_m, v, e) { \
 	.freq_hz = f, \
 	.src_clk = sc, \
@@ -98,8 +115,9 @@ struct rcg_clk {
 	const uint32_t	root_en_mask;
 	uint32_t	ns_mask;
 	const uint32_t	ctl_mask;
+	struct bank_masks *const bank_masks;
 	struct clk *depends;
-	void		(*set_rate)(struct clk_local *, struct clk_freq_tbl *);
+	void   (*set_rate)(struct rcg_clk *, struct clk_freq_tbl *);
 	struct clk_freq_tbl *const freq_tbl;
 	struct clk_freq_tbl *current_freq;
 
@@ -118,6 +136,7 @@ int rcg_clk_set_rate(struct clk *clk, unsigned rate);
 int rcg_clk_set_min_rate(struct clk *clk, unsigned rate);
 int rcg_clk_set_max_rate(struct clk *clk, unsigned rate);
 unsigned rcg_clk_get_rate(struct clk *clk);
+int rcg_clk_list_rate(struct clk *clk, unsigned n);
 unsigned rcg_clk_is_enabled(struct clk *clk);
 long rcg_clk_round_rate(struct clk *clk, unsigned rate);
 struct clk *rcg_clk_get_parent(struct clk *c);
@@ -184,6 +203,29 @@ static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *clk)
 }
 
 /**
+ * struct pll_clk - phase locked loop
+ * @rate: output rate
+ * @mode_reg: enable register
+ * @parent: clock source
+ * @c: clk
+ */
+struct pll_clk {
+	unsigned long rate;
+
+	void __iomem *const mode_reg;
+
+	struct clk *parent;
+	struct clk c;
+};
+
+extern struct clk_ops clk_ops_pll;
+
+static inline struct pll_clk *to_pll_clk(struct clk *clk)
+{
+	return container_of(clk, struct pll_clk, c);
+}
+
+/**
  * struct branch_clk - branch
  * @enabled: true if clock is on, false otherwise
  * @b: branch
@@ -237,6 +279,9 @@ extern int (*soc_update_sys_vdd)(enum sys_vdd_level level);
  */
 void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);
 void set_rate_nop(struct rcg_clk *clk, struct clk_freq_tbl *nf);
+void set_rate_mnd_8(struct rcg_clk *clk, struct clk_freq_tbl *nf);
+void set_rate_mnd_banked(struct rcg_clk *clk, struct clk_freq_tbl *nf);
+void set_rate_div_banked(struct rcg_clk *clk, struct clk_freq_tbl *nf);
 
 #endif /* __ARCH_ARM_MACH_MSM_CLOCK_LOCAL_H */
 
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 20/34] msm: clock: Add list_rate debugfs nodes for locally-controlled clocks

[David Brown]

From: Matt Wagantall <mattw@codeaurora.org>

Add debugfs nodes to list all of the supported rates for rate-settable
locally-controlled clocks. This allows a clock's supported rates to
be queried from userspace, and allows more comprehensive userspace
clock tests to be developed.

Reviewed-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-7x30.c  |    1 +
 arch/arm/mach-msm/clock-8x60.c  |    1 +
 arch/arm/mach-msm/clock-debug.c |   30 ++++++++++++++++++++++++++++++
 arch/arm/mach-msm/clock-local.c |   11 +++++++++++
 arch/arm/mach-msm/clock.h       |    1 +
 5 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index 306a64f..5b796e8 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -2763,6 +2763,7 @@ static struct clk_ops soc_clk_ops_7x30 = {
 	.set_min_rate = rcg_clk_set_min_rate,
 	.set_max_rate = rcg_clk_set_max_rate,
 	.get_rate = rcg_clk_get_rate,
+	.list_rate = rcg_clk_list_rate,
 	.is_enabled = rcg_clk_is_enabled,
 	.round_rate = rcg_clk_round_rate,
 	.reset = msm7x30_clk_reset,
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 6fdf4de..170797a 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -462,6 +462,7 @@ static struct clk_ops soc_clk_ops_8x60 = {
 	.set_min_rate = rcg_clk_set_min_rate,
 	.set_max_rate = rcg_clk_set_max_rate,
 	.get_rate = rcg_clk_get_rate,
+	.list_rate = rcg_clk_list_rate,
 	.is_enabled = rcg_clk_is_enabled,
 	.round_rate = rcg_clk_round_rate,
 	.reset = soc_clk_reset,
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index 472a735..78b7b6c 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -17,6 +17,7 @@
 #include <linux/module.h>
 #include <linux/ctype.h>
 #include <linux/debugfs.h>
+#include <linux/seq_file.h>
 #include <linux/clk.h>
 #include "clock.h"
 
@@ -101,6 +102,29 @@ int __init clock_debug_init(void)
 	return 0;
 }
 
+static int list_rates_show(struct seq_file *m, void *unused)
+{
+	struct clk *clock = m->private;
+	int rate, i = 0;
+
+	while ((rate = clock->ops->list_rate(clock, i++)) >= 0)
+		seq_printf(m, "%d\n", rate);
+
+	return 0;
+}
+
+static int list_rates_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, list_rates_show, inode->i_private);
+}
+
+static const struct file_operations list_rates_fops = {
+	.open		= list_rates_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= seq_release,
+};
+
 int __init clock_debug_add(struct clk *clock)
 {
 	char temp[50], *ptr;
@@ -128,6 +152,12 @@ int __init clock_debug_add(struct clk *clock)
 	if (!debugfs_create_file("is_local", S_IRUGO, clk_dir, clock,
 				&clock_local_fops))
 		goto error;
+
+	if (clock->ops->list_rate)
+		if (!debugfs_create_file("list_rates",
+				S_IRUGO, clk_dir, clock, &list_rates_fops))
+			goto error;
+
 	return 0;
 error:
 	debugfs_remove_recursive(clk_dir);
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index 3ee318d..c79895c 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -701,6 +701,17 @@ bool local_clk_is_local(struct clk *clk)
 	return true;
 }
 
+/* Return the nth supported frequency for a given clock. */
+int rcg_clk_list_rate(struct clk *c, unsigned n)
+{
+	struct rcg_clk *clk = to_rcg_clk(c);
+
+	if (!clk->freq_tbl || clk->freq_tbl->freq_hz == FREQ_END)
+		return -ENXIO;
+
+	return (clk->freq_tbl + n)->freq_hz;
+}
+
 struct clk *rcg_clk_get_parent(struct clk *clk)
 {
 	return to_rcg_clk(clk)->current_freq->src_clk;
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 8ae86ce..26b52f2 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -42,6 +42,7 @@ struct clk_ops {
 	int (*set_max_rate)(struct clk *clk, unsigned rate);
 	int (*set_flags)(struct clk *clk, unsigned flags);
 	unsigned (*get_rate)(struct clk *clk);
+	int (*list_rate)(struct clk *clk, unsigned n);
 	unsigned (*is_enabled)(struct clk *clk);
 	long (*round_rate)(struct clk *clk, unsigned rate);
 	int (*set_parent)(struct clk *clk, struct clk *parent);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 21/34] msm: clock: Add debugfs interface to measure clock rates

[David Brown]

From: Matt Wagantall <mattw@codeaurora.org>

Use the SoC's ring oscillator hardware to measure the clock rate
of locally-controlled clocks. This allows for the development of
more comprehensive end-to-end clock tests.

A 'measure' debugfs node is created for each clock to perform the
measurement and retrieve the result. soc_clk_measure_rate() should
*only* be used for debug purposes since it busy-loops while the
measurement takes place (~15 ms).

Clock rates are in units of Hz. Clocks that don't support rate
measurement will return -1.

Reviewed-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-7x30.c  |  239 ++++++++++++++++++++++++++++
 arch/arm/mach-msm/clock-8x60.c  |  333 ++++++++++++++++++++++++++++++++++++--
 arch/arm/mach-msm/clock-debug.c |   36 ++++-
 arch/arm/mach-msm/clock.h       |    2 +-
 4 files changed, 589 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index 5b796e8..f73e76f 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -2426,6 +2426,244 @@ out:
 	return rc;
 }
 
+#ifdef CONFIG_DEBUG_FS
+
+#define CLK_TEST_2(s) (s)
+#define CLK_TEST_HS(s) (0x4000 | ((s) << 8))
+#define CLK_TEST_LS(s) (0x4D40 | (s))
+
+struct measure_sel {
+	u32 test_vector;
+	struct clk *clk;
+};
+
+static struct measure_sel measure_mux[] = {
+	{ CLK_TEST_2(0x03), &emdh_p_clk.c },
+	{ CLK_TEST_2(0x04), &pmdh_p_clk.c },
+	{ CLK_TEST_2(0x06), &mdp_p_clk.c },
+	{ CLK_TEST_2(0x07), &lpa_p_clk.c },
+	{ CLK_TEST_2(0x08), &usb_hs2_p_clk.c },
+	{ CLK_TEST_2(0x09), &spi_clk.c },
+	{ CLK_TEST_2(0x0A), &midi_clk.c },
+	{ CLK_TEST_2(0x0B), &i2c_2_clk.c },
+	{ CLK_TEST_2(0x0D), &mi2s_m_clk.c },
+	{ CLK_TEST_2(0x0E), &lpa_core_clk.c },
+	{ CLK_TEST_2(0x0F), &lpa_codec_clk.c },
+	{ CLK_TEST_2(0x10), &usb_hs3_p_clk.c },
+	{ CLK_TEST_2(0x11), &adm_p_clk.c },
+	{ CLK_TEST_2(0x13), &hdmi_clk.c },
+	{ CLK_TEST_2(0x14), &usb_hs_core_clk.c },
+	{ CLK_TEST_2(0x15), &usb_hs2_core_clk.c },
+	{ CLK_TEST_2(0x16), &usb_hs3_core_clk.c },
+	{ CLK_TEST_2(0x17), &mi2s_codec_tx_s_clk.c },
+	{ CLK_TEST_2(0x18), &spi_p_clk.c },
+	{ CLK_TEST_2(0x1A), &camif_pad_p_clk.c },
+	{ CLK_TEST_2(0x1C), &qup_i2c_clk.c },
+	{ CLK_TEST_2(0x1F), &mfc_div2_clk.c },
+	{ CLK_TEST_2(0x38), &mfc_clk.c },
+
+	{ CLK_TEST_HS(0x00), &adm_clk.c },
+	{ CLK_TEST_HS(0x01), &mdp_lcdc_pad_pclk_clk.c },
+	{ CLK_TEST_HS(0x02), &mdp_lcdc_pclk_clk.c },
+	{ CLK_TEST_HS(0x03), &axi_rotator_clk.c },
+	{ CLK_TEST_HS(0x07), &axi_li_vg_clk.c },
+	{ CLK_TEST_HS(0x09), &axi_li_apps_clk.c },
+	{ CLK_TEST_HS(0x0E), &axi_li_jpeg_clk.c },
+	{ CLK_TEST_HS(0x0F), &emdh_clk.c },
+	{ CLK_TEST_HS(0x14), &mdp_clk.c },
+	{ CLK_TEST_HS(0x15), &pmdh_clk.c },
+	{ CLK_TEST_HS(0x19), &axi_grp_2d_clk.c },
+	{ CLK_TEST_HS(0x1A), &axi_li_grp_clk.c },
+	{ CLK_TEST_HS(0x1B), &axi_li_vfe_clk.c },
+	{ CLK_TEST_HS(0x1C), &grp_2d_clk.c },
+	{ CLK_TEST_HS(0x1E), &grp_3d_clk.c },
+	{ CLK_TEST_HS(0x1F), &imem_clk.c },
+	{ CLK_TEST_HS(0x20), &jpeg_clk.c },
+	{ CLK_TEST_HS(0x24), &axi_li_adsp_a_clk.c },
+	{ CLK_TEST_HS(0x26), &rotator_imem_clk.c },
+	{ CLK_TEST_HS(0x27), &axi_vpe_clk.c },
+	{ CLK_TEST_HS(0x2A), &axi_mfc_clk.c },
+	{ CLK_TEST_HS(0x2B), &axi_mdp_clk.c },
+	{ CLK_TEST_HS(0x2C), &vpe_clk.c },
+	{ CLK_TEST_HS(0x30), &vfe_camif_clk.c },
+	{ CLK_TEST_HS(0x31), &csi0_clk.c },
+	{ CLK_TEST_HS(0x32), &csi0_vfe_clk.c },
+	{ CLK_TEST_HS(0x33), &csi0_p_clk.c },
+
+	{ CLK_TEST_LS(0x03), &ce_clk.c },
+	{ CLK_TEST_LS(0x04), &cam_m_clk.c },
+	{ CLK_TEST_LS(0x0C), &grp_2d_p_clk.c },
+	{ CLK_TEST_LS(0x0D), &i2c_clk.c },
+	{ CLK_TEST_LS(0x0E), &mi2s_codec_rx_m_clk.c },
+	{ CLK_TEST_LS(0x0F), &mi2s_codec_rx_s_clk.c },
+	{ CLK_TEST_LS(0x10), &mi2s_codec_tx_m_clk.c },
+	{ CLK_TEST_LS(0x13), &mdp_vsync_clk.c },
+	{ CLK_TEST_LS(0x15), &vfe_p_clk.c },
+	{ CLK_TEST_LS(0x16), &mdc_clk.c },
+	{ CLK_TEST_LS(0x17), &vfe_mdc_clk.c },
+	{ CLK_TEST_LS(0x18), &usb_hs_p_clk.c },
+	{ CLK_TEST_LS(0x1C), &uart1dm_p_clk.c },
+	{ CLK_TEST_LS(0x1E), &jpeg_p_clk.c },
+	{ CLK_TEST_LS(0x20), &sdac_clk.c },
+	{ CLK_TEST_LS(0x21), &sdc1_p_clk.c },
+	{ CLK_TEST_LS(0x22), &sdc1_clk.c },
+	{ CLK_TEST_LS(0x23), &sdc2_p_clk.c },
+	{ CLK_TEST_LS(0x24), &sdc2_clk.c },
+	{ CLK_TEST_LS(0x25), &tsif_p_clk.c },
+	{ CLK_TEST_LS(0x26), &sdac_m_clk.c },
+	{ CLK_TEST_LS(0x27), &grp_3d_p_clk.c },
+	{ CLK_TEST_LS(0x2A), &tsif_ref_clk.c },
+	{ CLK_TEST_LS(0x2B), &tv_enc_clk.c },
+	{ CLK_TEST_LS(0x2C), &tv_dac_clk.c },
+	{ CLK_TEST_LS(0x2D), &rotator_p_clk.c },
+	{ CLK_TEST_LS(0x2F), &uart1_clk.c },
+	{ CLK_TEST_LS(0x30), &uart1dm_clk.c },
+	{ CLK_TEST_LS(0x31), &uart2_clk.c },
+	{ CLK_TEST_LS(0x33), &usb_hs2_clk.c },
+	{ CLK_TEST_LS(0x34), &usb_hs3_clk.c },
+	{ CLK_TEST_LS(0x35), &mfc_p_clk.c },
+	{ CLK_TEST_LS(0x36), &vfe_clk.c },
+	{ CLK_TEST_LS(0x39), &sdc3_p_clk.c },
+	{ CLK_TEST_LS(0x3A), &sdc3_clk.c },
+	{ CLK_TEST_LS(0x3B), &sdc4_p_clk.c },
+	{ CLK_TEST_LS(0x3C), &sdc4_clk.c },
+	{ CLK_TEST_LS(0x3D), &uart2dm_clk.c },
+	{ CLK_TEST_LS(0x3E), &uart2dm_p_clk.c },
+	{ CLK_TEST_LS(0x3F), &usb_hs_clk.c },
+};
+
+static struct measure_sel *find_measure_sel(struct clk *clk)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
+		if (measure_mux[i].clk == clk)
+			return &measure_mux[i];
+	return NULL;
+}
+
+static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct measure_sel *p;
+	unsigned long flags;
+
+	if (!parent)
+		return -EINVAL;
+
+	p = find_measure_sel(parent);
+	if (!p)
+		return -EINVAL;
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+
+	/* Program test vector. */
+	if (p->test_vector <= 0xFF) {
+		/* Select CLK_TEST_2 */
+		writel_relaxed(0x4D40, CLK_TEST_BASE_REG);
+		writel_relaxed(p->test_vector, CLK_TEST_2_BASE_REG);
+	} else
+		writel_relaxed(p->test_vector, CLK_TEST_BASE_REG);
+
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+	return 0;
+}
+
+/* Sample clock for 'tcxo4_ticks' reference clock ticks. */
+static u32 run_measurement(unsigned tcxo4_ticks)
+{
+	/* TCXO4_CNT_EN and RINGOSC_CNT_EN register values. */
+	u32 reg_val_enable = readl_relaxed(MISC_CLK_CTL_BASE_REG) | 0x3;
+	u32 reg_val_disable = reg_val_enable & ~0x3;
+
+	/* Stop counters and set the TCXO4 counter start value. */
+	writel_relaxed(reg_val_disable, MISC_CLK_CTL_BASE_REG);
+	writel_relaxed(tcxo4_ticks, TCXO_CNT_BASE_REG);
+
+	/* Run measurement and wait for completion. */
+	writel_relaxed(reg_val_enable, MISC_CLK_CTL_BASE_REG);
+	while (readl_relaxed(TCXO_CNT_DONE_BASE_REG) == 0)
+		cpu_relax();
+
+	/* Stop counters. */
+	writel_relaxed(reg_val_disable, MISC_CLK_CTL_BASE_REG);
+
+	return readl_relaxed(RINGOSC_CNT_BASE_REG);
+}
+
+/* Perform a hardware rate measurement for a given clock.
+   FOR DEBUG USE ONLY: Measurements take ~15 ms! */
+static unsigned measure_clk_get_rate(struct clk *clk)
+{
+	unsigned long flags;
+	u32 regval, prph_web_reg_old;
+	u64 raw_count_short, raw_count_full;
+	unsigned ret;
+
+	clk_enable(&tcxo_clk.c);
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+
+	/* Enable TCXO4 clock branch and root. */
+	prph_web_reg_old = readl_relaxed(PRPH_WEB_NS_BASE_REG);
+	regval = prph_web_reg_old | BIT(9) | BIT(11);
+	writel_relaxed(regval, PRPH_WEB_NS_BASE_REG);
+
+	/*
+	 * The ring oscillator counter will not reset if the measured clock
+	 * is not running.  To detect this, run a short measurement before
+	 * the full measurement.  If the raw results of the two are the same
+	 * then the clock must be off.
+	 */
+
+	/* Run a short measurement. (~1 ms) */
+	raw_count_short = run_measurement(0x1000);
+	/* Run a full measurement. (~14 ms) */
+	raw_count_full = run_measurement(0x10000);
+
+	/* Disable TCXO4 clock branch and root. */
+	writel_relaxed(prph_web_reg_old, PRPH_WEB_NS_BASE_REG);
+
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+	/* Return 0 if the clock is off. */
+	if (raw_count_full == raw_count_short)
+		ret = 0;
+	else {
+		/* Compute rate in Hz. */
+		raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
+		do_div(raw_count_full, ((0x10000 * 10) + 35));
+		ret = raw_count_full;
+	}
+
+	clk_disable(&tcxo_clk.c);
+
+	return ret;
+}
+#else /* !CONFIG_DEBUG_FS */
+static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	return -EINVAL;
+}
+
+static unsigned measure_clk_get_rate(struct clk *clk)
+{
+	return 0;
+}
+#endif /* CONFIG_DEBUG_FS */
+
+static struct clk_ops measure_clk_ops = {
+	.set_parent = measure_clk_set_parent,
+	.get_rate = measure_clk_get_rate,
+	.is_local = local_clk_is_local,
+};
+
+static struct clk measure_clk = {
+	.dbg_name = "measure_clk",
+	.ops = &measure_clk_ops,
+	CLK_INIT(measure_clk),
+};
+
 /* Implementation for clk_set_flags(). */
 int soc_clk_set_flags(struct clk *clk, unsigned clk_flags)
 {
@@ -2525,6 +2763,7 @@ static struct clk_local_ownership {
 	{ CLK_LOOKUP("pll1_clk",	pll1_clk.c,	"acpu") },
 	{ CLK_LOOKUP("pll2_clk",	pll2_clk.c,	"acpu") },
 	{ CLK_LOOKUP("pll3_clk",	pll3_clk.c,	"acpu") },
+	{ CLK_LOOKUP("measure",		measure_clk,	"debug") },
 
 	/* PCOM */
 	{ CLK_LOOKUP("adsp_clk",	adsp_clk.c,	NULL) },
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 170797a..7dac975 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -809,7 +809,7 @@ static struct branch_clk ijpeg_p_clk = {
 		.halt_bit = 9,
 	},
 	.c = {
-		.dbg_name = "ijepg_p_clk",
+		.dbg_name = "ijpeg_p_clk",
 		.ops = &clk_ops_branch,
 		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ijpeg_p_clk.c),
@@ -2991,7 +2991,7 @@ static struct clk_freq_tbl clk_tbl_aif_osr[] = {
 	F_END
 };
 
-#define CLK_AIF_OSR(i, ns, md, h_r, tv) \
+#define CLK_AIF_OSR(i, ns, md, h_r) \
 	struct rcg_clk i##_clk = { \
 		.b = { \
 			.ctl_reg = ns, \
@@ -3031,7 +3031,7 @@ static struct clk_freq_tbl clk_tbl_aif_bit[] = {
 	F_END
 };
 
-#define CLK_AIF_BIT(i, ns, h_r, tv) \
+#define CLK_AIF_BIT(i, ns, h_r) \
 	struct rcg_clk i##_clk = { \
 		.b = { \
 			.ctl_reg = ns, \
@@ -3053,33 +3053,28 @@ static struct clk_freq_tbl clk_tbl_aif_bit[] = {
 	}
 
 static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
-		LCC_MI2S_STATUS_REG, TEST_LPA(0x0A));
-static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG,
-		TEST_LPA(0x0B));
+		LCC_MI2S_STATUS_REG);
+static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
 
 static CLK_AIF_OSR(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
-		LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG,
-		TEST_LPA(0x0C));
+		LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
 static CLK_AIF_BIT(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
-		LCC_CODEC_I2S_MIC_STATUS_REG, TEST_LPA(0x0D));
+		LCC_CODEC_I2S_MIC_STATUS_REG);
 
 static CLK_AIF_OSR(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
-		LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG,
-		TEST_LPA(0x10));
+		LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
 static CLK_AIF_BIT(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
-		LCC_SPARE_I2S_MIC_STATUS_REG, TEST_LPA(0x11));
+		LCC_SPARE_I2S_MIC_STATUS_REG);
 
 static CLK_AIF_OSR(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
-		LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG,
-		TEST_LPA(0x0E));
+		LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
 static CLK_AIF_BIT(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
-		LCC_CODEC_I2S_SPKR_STATUS_REG, TEST_LPA(0x0F));
+		LCC_CODEC_I2S_SPKR_STATUS_REG);
 
 static CLK_AIF_OSR(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
-		LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG,
-		TEST_LPA(0x12));
+		LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
 static CLK_AIF_BIT(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
-		LCC_SPARE_I2S_SPKR_STATUS_REG, TEST_LPA(0x13));
+		LCC_SPARE_I2S_SPKR_STATUS_REG);
 
 #define F_PCM(f, s, d, m, n, v) \
 	{ \
@@ -3131,10 +3126,312 @@ static struct rcg_clk pcm_clk = {
 	},
 };
 
+#ifdef CONFIG_DEBUG_FS
+struct measure_sel {
+	u32 test_vector;
+	struct clk *clk;
+};
+
+static struct measure_sel measure_mux[] = {
+	{ TEST_PER_LS(0x08), &modem_ahb1_p_clk.c },
+	{ TEST_PER_LS(0x09), &modem_ahb2_p_clk.c },
+	{ TEST_PER_LS(0x12), &sdc1_p_clk.c },
+	{ TEST_PER_LS(0x13), &sdc1_clk.c },
+	{ TEST_PER_LS(0x14), &sdc2_p_clk.c },
+	{ TEST_PER_LS(0x15), &sdc2_clk.c },
+	{ TEST_PER_LS(0x16), &sdc3_p_clk.c },
+	{ TEST_PER_LS(0x17), &sdc3_clk.c },
+	{ TEST_PER_LS(0x18), &sdc4_p_clk.c },
+	{ TEST_PER_LS(0x19), &sdc4_clk.c },
+	{ TEST_PER_LS(0x1A), &sdc5_p_clk.c },
+	{ TEST_PER_LS(0x1B), &sdc5_clk.c },
+	{ TEST_PER_LS(0x26), &pmem_clk.c },
+	{ TEST_PER_LS(0x2B), &ppss_p_clk.c },
+	{ TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
+	{ TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
+	{ TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
+	{ TEST_PER_LS(0x41), &gsbi2_p_clk.c },
+	{ TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
+	{ TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
+	{ TEST_PER_LS(0x45), &gsbi3_p_clk.c },
+	{ TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
+	{ TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
+	{ TEST_PER_LS(0x49), &gsbi4_p_clk.c },
+	{ TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
+	{ TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
+	{ TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
+	{ TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
+	{ TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
+	{ TEST_PER_LS(0x51), &gsbi6_p_clk.c },
+	{ TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
+	{ TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
+	{ TEST_PER_LS(0x55), &gsbi7_p_clk.c },
+	{ TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
+	{ TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
+	{ TEST_PER_LS(0x59), &gsbi8_p_clk.c },
+	{ TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
+	{ TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
+	{ TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
+	{ TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
+	{ TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
+	{ TEST_PER_LS(0x61), &gsbi10_p_clk.c },
+	{ TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
+	{ TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
+	{ TEST_PER_LS(0x65), &gsbi11_p_clk.c },
+	{ TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
+	{ TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
+	{ TEST_PER_LS(0x69), &gsbi12_p_clk.c },
+	{ TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
+	{ TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
+	{ TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
+	{ TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
+	{ TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
+	{ TEST_PER_LS(0x7D), &prng_clk.c },
+	{ TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
+	{ TEST_PER_LS(0x80), &adm0_p_clk.c },
+	{ TEST_PER_LS(0x81), &adm1_p_clk.c },
+	{ TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
+	{ TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
+	{ TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
+	{ TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
+	{ TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
+	{ TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
+	{ TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
+	{ TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
+	{ TEST_PER_LS(0x8F), &tsif_p_clk.c },
+	{ TEST_PER_LS(0x91), &tsif_ref_clk.c },
+	{ TEST_PER_LS(0x93), &ce2_p_clk.c },
+	{ TEST_PER_LS(0x94), &tssc_clk.c },
+
+	{ TEST_PER_HS(0x2A), &adm0_clk.c },
+	{ TEST_PER_HS(0x2B), &adm1_clk.c },
+
+	{ TEST_MM_LS(0x00), &dsi_byte_clk.c },
+	{ TEST_MM_LS(0x01), &pixel_lcdc_clk.c },
+	{ TEST_MM_LS(0x04), &pixel_mdp_clk.c },
+	{ TEST_MM_LS(0x06), &amp_p_clk.c },
+	{ TEST_MM_LS(0x07), &csi0_p_clk.c },
+	{ TEST_MM_LS(0x08), &csi1_p_clk.c },
+	{ TEST_MM_LS(0x09), &dsi_m_p_clk.c },
+	{ TEST_MM_LS(0x0A), &dsi_s_p_clk.c },
+	{ TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
+	{ TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
+	{ TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
+	{ TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
+	{ TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
+	{ TEST_MM_LS(0x11), &ijpeg_p_clk.c },
+	{ TEST_MM_LS(0x12), &imem_p_clk.c },
+	{ TEST_MM_LS(0x13), &jpegd_p_clk.c },
+	{ TEST_MM_LS(0x14), &mdp_p_clk.c },
+	{ TEST_MM_LS(0x16), &rot_p_clk.c },
+	{ TEST_MM_LS(0x18), &smmu_p_clk.c },
+	{ TEST_MM_LS(0x19), &tv_enc_p_clk.c },
+	{ TEST_MM_LS(0x1A), &vcodec_p_clk.c },
+	{ TEST_MM_LS(0x1B), &vfe_p_clk.c },
+	{ TEST_MM_LS(0x1C), &vpe_p_clk.c },
+	{ TEST_MM_LS(0x1D), &cam_clk.c },
+	{ TEST_MM_LS(0x1F), &hdmi_app_clk.c },
+	{ TEST_MM_LS(0x20), &mdp_vsync_clk.c },
+	{ TEST_MM_LS(0x21), &tv_dac_clk.c },
+	{ TEST_MM_LS(0x22), &tv_enc_clk.c },
+	{ TEST_MM_LS(0x23), &dsi_esc_clk.c },
+
+	{ TEST_MM_HS(0x00), &csi0_clk.c },
+	{ TEST_MM_HS(0x01), &csi1_clk.c },
+	{ TEST_MM_HS(0x03), &csi0_vfe_clk.c },
+	{ TEST_MM_HS(0x04), &csi1_vfe_clk.c },
+	{ TEST_MM_HS(0x05), &ijpeg_clk.c },
+	{ TEST_MM_HS(0x06), &vfe_clk.c },
+	{ TEST_MM_HS(0x07), &gfx2d0_clk.c },
+	{ TEST_MM_HS(0x08), &gfx2d1_clk.c },
+	{ TEST_MM_HS(0x09), &gfx3d_clk.c },
+	{ TEST_MM_HS(0x0A), &jpegd_clk.c },
+	{ TEST_MM_HS(0x0B), &vcodec_clk.c },
+	{ TEST_MM_HS(0x11), &gmem_axi_clk.c },
+	{ TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
+	{ TEST_MM_HS(0x13), &imem_axi_clk.c },
+	{ TEST_MM_HS(0x14), &jpegd_axi_clk.c },
+	{ TEST_MM_HS(0x15), &mdp_axi_clk.c },
+	{ TEST_MM_HS(0x17), &vcodec_axi_clk.c },
+	{ TEST_MM_HS(0x18), &vfe_axi_clk.c },
+	{ TEST_MM_HS(0x1A), &mdp_clk.c },
+	{ TEST_MM_HS(0x1B), &rot_clk.c },
+	{ TEST_MM_HS(0x1C), &vpe_clk.c },
+	{ TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
+	{ TEST_MM_HS(0x1F), &mdp_tv_clk.c },
+
+	{ TEST_LPA(0x0A), &mi2s_osr_clk.c },
+	{ TEST_LPA(0x0B), &mi2s_bit_clk.c },
+	{ TEST_LPA(0x0C), &codec_i2s_mic_osr_clk.c },
+	{ TEST_LPA(0x0D), &codec_i2s_mic_bit_clk.c },
+	{ TEST_LPA(0x0E), &codec_i2s_spkr_osr_clk.c },
+	{ TEST_LPA(0x0F), &codec_i2s_spkr_bit_clk.c },
+	{ TEST_LPA(0x10), &spare_i2s_mic_osr_clk.c },
+	{ TEST_LPA(0x11), &spare_i2s_mic_bit_clk.c },
+	{ TEST_LPA(0x12), &spare_i2s_spkr_osr_clk.c },
+	{ TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
+	{ TEST_LPA(0x14), &pcm_clk.c },
+};
+
+static struct measure_sel *find_measure_sel(struct clk *clk)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
+		if (measure_mux[i].clk == clk)
+			return &measure_mux[i];
+	return NULL;
+}
+
+static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	int ret = 0;
+	u32 clk_sel;
+	struct measure_sel *p;
+	unsigned long flags;
+
+	if (!parent)
+		return -EINVAL;
+
+	p = find_measure_sel(parent);
+	if (!p)
+		return -EINVAL;
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+
+	/* Program the test vector. */
+	clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
+	switch (p->test_vector >> TEST_TYPE_SHIFT) {
+	case TEST_TYPE_PER_LS:
+		writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
+		break;
+	case TEST_TYPE_PER_HS:
+		writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
+		break;
+	case TEST_TYPE_MM_LS:
+		writel_relaxed(0x4030D97, CLK_TEST_REG);
+		writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
+		break;
+	case TEST_TYPE_MM_HS:
+		writel_relaxed(0x402B800, CLK_TEST_REG);
+		writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
+		break;
+	case TEST_TYPE_LPA:
+		writel_relaxed(0x4030D98, CLK_TEST_REG);
+		writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
+				LCC_CLK_LS_DEBUG_CFG_REG);
+		break;
+	default:
+		ret = -EPERM;
+	}
+	/* Make sure test vector is set before starting measurements. */
+	mb();
+
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+	return ret;
+}
+
+/* Sample clock for 'ticks' reference clock ticks. */
+static u32 run_measurement(unsigned ticks)
+{
+	/* Stop counters and set the XO4 counter start value. */
+	writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
+	writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
+
+	/* Wait for timer to become ready. */
+	while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
+		cpu_relax();
+
+	/* Run measurement and wait for completion. */
+	writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
+	while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
+		cpu_relax();
+
+	/* Stop counters. */
+	writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
+
+	/* Return measured ticks. */
+	return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
+}
+
+/* Perform a hardware rate measurement for a given clock.
+   FOR DEBUG USE ONLY: Measurements take ~15 ms! */
+static unsigned measure_clk_get_rate(struct clk *clk)
+{
+	unsigned long flags;
+	u32 pdm_reg_backup, ringosc_reg_backup;
+	u64 raw_count_short, raw_count_full;
+	unsigned ret;
+
+	spin_lock_irqsave(&local_clock_reg_lock, flags);
+
+	/* Enable CXO/4 and RINGOSC branch and root. */
+	pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
+	ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
+	writel_relaxed(0x2898, PDM_CLK_NS_REG);
+	writel_relaxed(0xA00, RINGOSC_NS_REG);
+
+	/*
+	 * The ring oscillator counter will not reset if the measured clock
+	 * is not running.  To detect this, run a short measurement before
+	 * the full measurement.  If the raw results of the two are the same
+	 * then the clock must be off.
+	 */
+
+	/* Run a short measurement. (~1 ms) */
+	raw_count_short = run_measurement(0x1000);
+	/* Run a full measurement. (~14 ms) */
+	raw_count_full = run_measurement(0x10000);
+
+	writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
+	writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
+
+	/* Return 0 if the clock is off. */
+	if (raw_count_full == raw_count_short)
+		ret = 0;
+	else {
+		/* Compute rate in Hz. */
+		raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
+		do_div(raw_count_full, ((0x10000 * 10) + 35));
+		ret = raw_count_full;
+	}
+
+	/* Route dbg_hs_clk to PLLTEST.  300mV single-ended amplitude. */
+	writel_relaxed(0x3CF8, PLLTEST_PAD_CFG_REG);
+	spin_unlock_irqrestore(&local_clock_reg_lock, flags);
+
+	return ret;
+}
+#else /* !CONFIG_DEBUG_FS */
+static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	return -EINVAL;
+}
+
+static unsigned measure_clk_get_rate(struct clk *clk)
+{
+	return 0;
+}
+#endif /* CONFIG_DEBUG_FS */
+
+static struct clk_ops measure_clk_ops = {
+	.set_parent = measure_clk_set_parent,
+	.get_rate = measure_clk_get_rate,
+	.is_local = local_clk_is_local,
+};
+
+static struct clk measure_clk = {
+	.dbg_name = "measure_clk",
+	.ops = &measure_clk_ops,
+	CLK_INIT(measure_clk),
+};
+
 struct clk_lookup msm_clocks_8x60[] = {
 	CLK_LOOKUP("cxo",		cxo_clk.c,	NULL),
 	CLK_LOOKUP("pll4",		pll4_clk.c,	NULL),
 	CLK_LOOKUP("pll4",		pll4_clk.c,	"peripheral-reset"),
+	CLK_LOOKUP("measure",		measure_clk,	"debug"),
 
 	CLK_LOOKUP("gsbi_uart_clk",	gsbi1_uart_clk.c,		NULL),
 	CLK_LOOKUP("gsbi_uart_clk",	gsbi2_uart_clk.c,		NULL),
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index 78b7b6c..1a08a9a 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -50,6 +50,23 @@ static int clock_debug_rate_get(void *data, u64 *val)
 DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get,
 			clock_debug_rate_set, "%llu\n");
 
+static struct clk *measure;
+
+static int clock_debug_measure_get(void *data, u64 *val)
+{
+	int ret;
+	struct clk *clock = data;
+
+	ret = clk_set_parent(measure, clock);
+	if (!ret)
+		*val = clk_get_rate(measure);
+
+	return ret;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(clock_measure_fops, clock_debug_measure_get,
+			NULL, "%lld\n");
+
 static int clock_debug_enable_set(void *data, u64 val)
 {
 	struct clk *clock = data;
@@ -96,10 +113,19 @@ static struct dentry *debugfs_base;
 
 int __init clock_debug_init(void)
 {
+	int ret = 0;
+
 	debugfs_base = debugfs_create_dir("clk", NULL);
 	if (!debugfs_base)
 		return -ENOMEM;
-	return 0;
+
+	measure = clk_get_sys("debug", "measure");
+	if (IS_ERR(measure)) {
+		ret = PTR_ERR(measure);
+		measure = NULL;
+	}
+
+	return ret;
 }
 
 static int list_rates_show(struct seq_file *m, void *unused)
@@ -153,6 +179,12 @@ int __init clock_debug_add(struct clk *clock)
 				&clock_local_fops))
 		goto error;
 
+	if (measure &&
+	    !clk_set_parent(measure, clock) &&
+	    !debugfs_create_file("measure", S_IRUGO, clk_dir, clock,
+				&clock_measure_fops))
+		goto error;
+
 	if (clock->ops->list_rate)
 		if (!debugfs_create_file("list_rates",
 				S_IRUGO, clk_dir, clock, &list_rates_fops))
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 26b52f2..32b164c 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-msm/clock.h
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 22/34] msm: clock-8x60: Support measurement of CPU and L2 clocks

[David Brown]

From: Matt Wagantall <mattw@codeaurora.org>

Users of these debug facilities should keep in mind that these
clocks can gate automatically when the CPU or L2 is idle,
resulting in a lower-than-expected or 0 Hz measurement in those
cases.

Also, because the test points used to measure these clocks are
after a hard-wired divide-by-two, the rates of these clocks
are multiplied again by two in software to get the actual CPU
and L2 rates. When observing these clocks on an oscilloscope,
however, the half-rate clocks are what is seen.

CRs-Fixed: 273908
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-8x60.c  |   51 ++++++++++++++++++++++++++++++--------
 arch/arm/mach-msm/clock-local.c |    4 +++
 arch/arm/mach-msm/clock-local.h |   29 ++++++++++++++++++++++
 3 files changed, 73 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 7dac975..71e014d 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -219,6 +219,7 @@
 #define TEST_TYPE_MM_LS		3
 #define TEST_TYPE_MM_HS		4
 #define TEST_TYPE_LPA		5
+#define TEST_TYPE_SC		6
 #define TEST_TYPE_SHIFT		24
 #define TEST_CLK_SEL_MASK	BM(23, 0)
 #define TEST_VECTOR(s, t)	(((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
@@ -227,6 +228,7 @@
 #define TEST_MM_LS(s)		TEST_VECTOR((s), TEST_TYPE_MM_LS)
 #define TEST_MM_HS(s)		TEST_VECTOR((s), TEST_TYPE_MM_HS)
 #define TEST_LPA(s)		TEST_VECTOR((s), TEST_TYPE_LPA)
+#define TEST_SC(s)		TEST_VECTOR((s), TEST_TYPE_SC)
 
 struct pll_rate {
 	const uint32_t	l_val;
@@ -3126,6 +3128,10 @@ static struct rcg_clk pcm_clk = {
 	},
 };
 
+static DEFINE_CLK_MEASURE(sc0_m_clk);
+static DEFINE_CLK_MEASURE(sc1_m_clk);
+static DEFINE_CLK_MEASURE(l2_m_clk);
+
 #ifdef CONFIG_DEBUG_FS
 struct measure_sel {
 	u32 test_vector;
@@ -3271,6 +3277,10 @@ static struct measure_sel measure_mux[] = {
 	{ TEST_LPA(0x12), &spare_i2s_spkr_osr_clk.c },
 	{ TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
 	{ TEST_LPA(0x14), &pcm_clk.c },
+
+	{ TEST_SC(0x40), &sc0_m_clk },
+	{ TEST_SC(0x41), &sc1_m_clk },
+	{ TEST_SC(0x42), &l2_m_clk },
 };
 
 static struct measure_sel *find_measure_sel(struct clk *clk)
@@ -3283,11 +3293,12 @@ static struct measure_sel *find_measure_sel(struct clk *clk)
 	return NULL;
 }
 
-static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
+static int measure_clk_set_parent(struct clk *c, struct clk *parent)
 {
 	int ret = 0;
 	u32 clk_sel;
 	struct measure_sel *p;
+	struct measure_clk *clk = to_measure_clk(c);
 	unsigned long flags;
 
 	if (!parent)
@@ -3299,8 +3310,13 @@ static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
 
 	spin_lock_irqsave(&local_clock_reg_lock, flags);
 
-	/* Program the test vector. */
+	/*
+	 * Program the test vector, measurement period (sample_ticks)
+	 * and scaling factor (multiplier).
+	 */
 	clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
+	clk->sample_ticks = 0x10000;
+	clk->multiplier = 1;
 	switch (p->test_vector >> TEST_TYPE_SHIFT) {
 	case TEST_TYPE_PER_LS:
 		writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
@@ -3321,6 +3337,11 @@ static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
 		writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
 				LCC_CLK_LS_DEBUG_CFG_REG);
 		break;
+	case TEST_TYPE_SC:
+		writel_relaxed(0x5020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
+		clk->sample_ticks = 0x4000;
+		clk->multiplier = 2;
+		break;
 	default:
 		ret = -EPERM;
 	}
@@ -3357,11 +3378,12 @@ static u32 run_measurement(unsigned ticks)
 
 /* Perform a hardware rate measurement for a given clock.
    FOR DEBUG USE ONLY: Measurements take ~15 ms! */
-static unsigned measure_clk_get_rate(struct clk *clk)
+static unsigned measure_clk_get_rate(struct clk *c)
 {
 	unsigned long flags;
 	u32 pdm_reg_backup, ringosc_reg_backup;
 	u64 raw_count_short, raw_count_full;
+	struct measure_clk *clk = to_measure_clk(c);
 	unsigned ret;
 
 	spin_lock_irqsave(&local_clock_reg_lock, flags);
@@ -3382,7 +3404,7 @@ static unsigned measure_clk_get_rate(struct clk *clk)
 	/* Run a short measurement. (~1 ms) */
 	raw_count_short = run_measurement(0x1000);
 	/* Run a full measurement. (~14 ms) */
-	raw_count_full = run_measurement(0x10000);
+	raw_count_full = run_measurement(clk->sample_ticks);
 
 	writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
 	writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
@@ -3393,8 +3415,8 @@ static unsigned measure_clk_get_rate(struct clk *clk)
 	else {
 		/* Compute rate in Hz. */
 		raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
-		do_div(raw_count_full, ((0x10000 * 10) + 35));
-		ret = raw_count_full;
+		do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
+		ret = (raw_count_full * clk->multiplier);
 	}
 
 	/* Route dbg_hs_clk to PLLTEST.  300mV single-ended amplitude. */
@@ -3421,17 +3443,20 @@ static struct clk_ops measure_clk_ops = {
 	.is_local = local_clk_is_local,
 };
 
-static struct clk measure_clk = {
-	.dbg_name = "measure_clk",
-	.ops = &measure_clk_ops,
-	CLK_INIT(measure_clk),
+static struct measure_clk measure_clk = {
+	.c = {
+		.dbg_name = "measure_clk",
+		.ops = &measure_clk_ops,
+		CLK_INIT(measure_clk.c),
+	},
+	.multiplier = 1,
 };
 
 struct clk_lookup msm_clocks_8x60[] = {
 	CLK_LOOKUP("cxo",		cxo_clk.c,	NULL),
 	CLK_LOOKUP("pll4",		pll4_clk.c,	NULL),
 	CLK_LOOKUP("pll4",		pll4_clk.c,	"peripheral-reset"),
-	CLK_LOOKUP("measure",		measure_clk,	"debug"),
+	CLK_LOOKUP("measure",		measure_clk.c,	"debug"),
 
 	CLK_LOOKUP("gsbi_uart_clk",	gsbi1_uart_clk.c,		NULL),
 	CLK_LOOKUP("gsbi_uart_clk",	gsbi2_uart_clk.c,		NULL),
@@ -3592,6 +3617,10 @@ struct clk_lookup msm_clocks_8x60[] = {
 	CLK_LOOKUP("iommu_clk",		gfx3d_clk.c, "msm_iommu.9"),
 	CLK_LOOKUP("iommu_clk",		gfx2d0_clk.c, "msm_iommu.10"),
 	CLK_LOOKUP("iommu_clk",		gfx2d1_clk.c, "msm_iommu.11"),
+
+	CLK_LOOKUP("sc0_mclk",		sc0_m_clk, NULL),
+	CLK_LOOKUP("sc1_mclk",		sc1_m_clk, NULL),
+	CLK_LOOKUP("l2_mclk",		l2_m_clk,  NULL),
 };
 unsigned msm_num_clocks_8x60 = ARRAY_SIZE(msm_clocks_8x60);
 
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index c79895c..e2dab7a 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -861,6 +861,10 @@ struct fixed_clk gnd_clk = {
 	},
 };
 
+struct clk_ops clk_ops_measure = {
+	.is_local = local_clk_is_local,
+};
+
 int branch_clk_enable(struct clk *clk)
 {
 	int rc;
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index e004490..6d48e61 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -33,6 +33,16 @@
 #define DELAY		5	/* No bit to check, just delay */
 
 /*
+ * Clock Definition Macros
+ */
+#define DEFINE_CLK_MEASURE(name) \
+	struct clk name = { \
+		.ops = &clk_ops_measure, \
+		.dbg_name = #name, \
+		CLK_INIT(name), \
+	}; \
+
+/*
  * Generic frequency-definition structs and macros
  */
 struct clk_freq_tbl {
@@ -255,6 +265,25 @@ unsigned branch_clk_is_enabled(struct clk *clk);
 void branch_clk_auto_off(struct clk *clk);
 int branch_clk_reset(struct clk *c, enum clk_reset_action action);
 
+/**
+ * struct measure_clk - for rate measurement debug use
+ * @sample_ticks: sample period in reference clock ticks
+ * @multiplier: measurement scale-up factor
+ * @c: clk
+*/
+struct measure_clk {
+	u64 sample_ticks;
+	u32 multiplier;
+	struct clk c;
+};
+
+extern struct clk_ops clk_ops_measure;
+
+static inline struct measure_clk *to_measure_clk(struct clk *clk)
+{
+	return container_of(clk, struct measure_clk, c);
+}
+
 /*
  * Variables from clock-local driver
  */
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 23/34] msm: Unify iomap for clock regions

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

8960 requires the iomap to be unified across all versions of the
MSM. Unify the io regions to avoid build errors.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    5 ++---
 arch/arm/mach-msm/include/mach/msm_iomap-7x30.h |    5 ++---
 arch/arm/mach-msm/include/mach/msm_iomap-8x50.h |    5 ++---
 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h |   15 ++++++---------
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    3 +++
 arch/arm/mach-msm/io.c                          |   12 ++++++------
 6 files changed, 21 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 94fe9fe..70dde27 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -61,9 +61,8 @@
 #define MSM7X00_GPIO2_PHYS        0xA9300000
 #define MSM7X00_GPIO2_SIZE        SZ_4K
 
-#define MSM_CLK_CTL_BASE      IOMEM(0xE0005000)
-#define MSM_CLK_CTL_PHYS      0xA8600000
-#define MSM_CLK_CTL_SIZE      SZ_4K
+#define MSM7X00_CLK_CTL_PHYS      0xA8600000
+#define MSM7X00_CLK_CTL_SIZE      SZ_4K
 
 #define MSM_SHARED_RAM_BASE   IOMEM(0xE0100000)
 #define MSM_SHARED_RAM_PHYS   0x01F00000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 3769444..e89264b 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -52,9 +52,8 @@
 #define MSM7X30_GPIO2_PHYS        0xAC101000
 #define MSM7X30_GPIO2_SIZE        SZ_4K
 
-#define MSM_CLK_CTL_BASE      IOMEM(0xE0005000)
-#define MSM_CLK_CTL_PHYS      0xAB800000
-#define MSM_CLK_CTL_SIZE      SZ_4K
+#define MSM7X30_CLK_CTL_PHYS      0xAB800000
+#define MSM7X30_CLK_CTL_SIZE      SZ_4K
 
 #define MSM_CLK_CTL_SH2_BASE  IOMEM(0xE0006000)
 #define MSM_CLK_CTL_SH2_PHYS  0xABA01000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index d67cd73..e8a209c 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -52,9 +52,8 @@
 #define QSD8X50_GPIO2_PHYS        0xA9100000
 #define QSD8X50_GPIO2_SIZE        SZ_4K
 
-#define MSM_CLK_CTL_BASE      IOMEM(0xE0005000)
-#define MSM_CLK_CTL_PHYS      0xA8600000
-#define MSM_CLK_CTL_SIZE      SZ_4K
+#define QSD8X50_CLK_CTL_PHYS      0xA8600000
+#define QSD8X50_CLK_CTL_SIZE      SZ_4K
 
 #define MSM_SIRC_BASE         IOMEM(0xE1006000)
 #define MSM_SIRC_PHYS         0xAC200000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 5b9718f..25b044e 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -53,17 +53,14 @@
 #define MSM_TLMM_PHYS		0x00800000
 #define MSM_TLMM_SIZE		SZ_16K
 
-#define MSM_CLK_CTL_BASE	IOMEM(0xFA010000)
-#define MSM_CLK_CTL_PHYS	0x00900000
-#define MSM_CLK_CTL_SIZE	SZ_16K
+#define MSM8X60_CLK_CTL_PHYS	0x00900000
+#define MSM8X60_CLK_CTL_SIZE	SZ_16K
 
-#define MSM_MMSS_CLK_CTL_BASE	IOMEM(0xFA014000)
-#define MSM_MMSS_CLK_CTL_PHYS	0x04000000
-#define MSM_MMSS_CLK_CTL_SIZE	SZ_4K
+#define MSM8X60_MMSS_CLK_CTL_PHYS	0x04000000
+#define MSM8X60_MMSS_CLK_CTL_SIZE	SZ_4K
 
-#define MSM_LPASS_CLK_CTL_BASE	IOMEM(0xFA015000)
-#define MSM_LPASS_CLK_CTL_PHYS	0x28000000
-#define MSM_LPASS_CLK_CTL_SIZE	SZ_4K
+#define MSM8X60_LPASS_CLK_CTL_PHYS	0x28000000
+#define MSM8X60_LPASS_CLK_CTL_SIZE	SZ_4K
 
 #define MSM_SHARED_RAM_BASE	IOMEM(0xF0100000)
 #define MSM_SHARED_RAM_SIZE	SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 4ded152..20fcb41 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -63,5 +63,8 @@
 #define MSM_TMR0_BASE		IOMEM(0xF0201000)
 #define MSM_GPIO1_BASE		IOMEM(0xE0003000)
 #define MSM_GPIO2_BASE		IOMEM(0xE0004000)
+#define MSM_CLK_CTL_BASE	IOMEM(0xF0202000)
+#define MSM_MMSS_CLK_CTL_BASE	IOMEM(0xF0206000)
+#define MSM_LPASS_CLK_CTL_BASE	IOMEM(0xF0207000)
 
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index ff41964..8a6600c 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -45,7 +45,7 @@ static struct map_desc msm_io_desc[] __initdata = {
 	MSM_DEVICE(DMOV),
 	MSM_CHIP_DEVICE(GPIO1, MSM7X00),
 	MSM_CHIP_DEVICE(GPIO2, MSM7X00),
-	MSM_DEVICE(CLK_CTL),
+	MSM_CHIP_DEVICE(CLK_CTL, MSM7X00),
 #ifdef CONFIG_MSM_DEBUG_UART
 	MSM_DEVICE(DEBUG_UART),
 #endif
@@ -78,7 +78,7 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
 	MSM_DEVICE(DMOV),
 	MSM_CHIP_DEVICE(GPIO1, QSD8X50),
 	MSM_CHIP_DEVICE(GPIO2, QSD8X50),
-	MSM_DEVICE(CLK_CTL),
+	MSM_CHIP_DEVICE(CLK_CTL, QSD8X50),
 	MSM_DEVICE(SIRC),
 	MSM_DEVICE(SCPLL),
 	MSM_DEVICE(AD5),
@@ -108,9 +108,9 @@ static struct map_desc msm8x60_io_desc[] __initdata = {
 	MSM_CHIP_DEVICE(TMR0, MSM8X60),
 	MSM_DEVICE(ACC),
 	MSM_DEVICE(GCC),
-	MSM_DEVICE(CLK_CTL),
-	MSM_DEVICE(MMSS_CLK_CTL),
-	MSM_DEVICE(LPASS_CLK_CTL),
+	MSM_CHIP_DEVICE(CLK_CTL, MSM8X60),
+	MSM_CHIP_DEVICE(MMSS_CLK_CTL, MSM8X60),
+	MSM_CHIP_DEVICE(LPASS_CLK_CTL, MSM8X60),
 };
 
 void __init msm_map_msm8x60_io(void)
@@ -140,7 +140,7 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
 	MSM_DEVICE(DMOV),
 	MSM_CHIP_DEVICE(GPIO1, MSM7X30),
 	MSM_CHIP_DEVICE(GPIO2, MSM7X30),
-	MSM_DEVICE(CLK_CTL),
+	MSM_CHIP_DEVICE(CLK_CTL, MSM7X30),
 	MSM_DEVICE(CLK_CTL_SH2),
 	MSM_DEVICE(AD5),
 	MSM_DEVICE(MDC),
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 24/34] msm: clock: Support dummy clocks

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Implement a dummy clock driver and macro in the spirit of
CLK_PCOM(). This is useful on targets where a pclk doesn't exist
and we want to keep drivers sane by providing such clocks.

Reviewed-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/Makefile      |    1 +
 arch/arm/mach-msm/clock-dummy.c |   69 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/clock.h       |    9 +++++
 3 files changed, 79 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/clock-dummy.c

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index f1152ed..fd7f757 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,6 +1,7 @@
 obj-y += io.o idle.o timer.o
 obj-y += clock.o
 obj-y += clock-voter.o
+obj-y += clock-dummy.o
 obj-$(CONFIG_DEBUG_FS) += clock-debug.o
 obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o
 obj-$(CONFIG_ARCH_MSM8X60) += clock-local.o clock-8x60.o
diff --git a/arch/arm/mach-msm/clock-dummy.c b/arch/arm/mach-msm/clock-dummy.c
new file mode 100644
index 0000000..47a94e3
--- /dev/null
+++ b/arch/arm/mach-msm/clock-dummy.c
@@ -0,0 +1,69 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "clock.h"
+
+static int dummy_clk_reset(struct clk *clk, enum clk_reset_action action)
+{
+	return 0;
+}
+
+static int dummy_clk_set_rate(struct clk *clk, unsigned rate)
+{
+	return 0;
+}
+
+static int dummy_clk_set_min_rate(struct clk *clk, unsigned rate)
+{
+	return 0;
+}
+
+static int dummy_clk_set_max_rate(struct clk *clk, unsigned rate)
+{
+	return 0;
+}
+
+static int dummy_clk_set_flags(struct clk *clk, unsigned flags)
+{
+	return 0;
+}
+
+static unsigned dummy_clk_get_rate(struct clk *clk)
+{
+	return 0;
+}
+
+static long dummy_clk_round_rate(struct clk *clk, unsigned rate)
+{
+	return rate;
+}
+
+static bool dummy_clk_is_local(struct clk *clk)
+{
+	return true;
+}
+
+static struct clk_ops clk_ops_dummy = {
+	.reset = dummy_clk_reset,
+	.set_rate = dummy_clk_set_rate,
+	.set_min_rate = dummy_clk_set_min_rate,
+	.set_max_rate = dummy_clk_set_max_rate,
+	.set_flags = dummy_clk_set_flags,
+	.get_rate = dummy_clk_get_rate,
+	.round_rate = dummy_clk_round_rate,
+	.is_local = dummy_clk_is_local,
+};
+
+struct clk dummy_clk = {
+	.ops = &clk_ops_dummy,
+	.dbg_name = "dummy_clk",
+};
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 32b164c..11cfac8 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -87,5 +87,14 @@ static inline int __init clock_debug_init(void) { return 0; }
 static inline int __init clock_debug_add(struct clk *clock) { return 0; }
 #endif
 
+extern struct clk dummy_clk;
+
+#define CLK_DUMMY(clk_name, clk_id, clk_dev) {	\
+	.con_id = clk_name, \
+	.dev_id = clk_dev, \
+	.clk = &dummy_clk, \
+	}
+
 #define CLK_LOOKUP(con, c, dev) { .con_id = con, .clk = &c, .dev_id = dev }
+
 #endif
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 26/34] msm: 8660: Add FLUID support

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

The machine descriptor for FLUID was missing. Adding it allows us
to boot FLUID devices since the basic support for 8660 is the
same.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/Kconfig         |    6 ++++++
 arch/arm/mach-msm/board-msm8x60.c |    8 ++++++++
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index ebde97f..57c0ae2 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -138,6 +138,12 @@ config MACH_MSM8X60_FFA
 	help
 	  Support for the Qualcomm MSM8x60 FFA eval board.
 
+config MACH_MSM8X60_FLUID
+	depends on ARCH_MSM8X60
+	bool "MSM8x60 FLUID"
+	help
+	  Support for the Qualcomm MSM8x60 FLUID board.
+
 config MACH_MSM8960_SIM
 	depends on ARCH_MSM8960
 	bool "MSM8960 Simulator"
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index a6bfc91..7b8016f 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -116,3 +116,11 @@ MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END
+
+MACHINE_START(MSM8X60_FLUID, "QCT MSM8X60 FLUID")
+	.map_io = msm8x60_map_io,
+	.init_early = msm8x60_init_early,
+	.init_irq = msm8x60_init_irq,
+	.init_machine = msm8x60_init,
+	.timer = &msm_timer,
+MACHINE_END
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 27/34] msm-8x60: Add serial support

[David Brown]

From: Stepan Moskovchenko <stepanm@codeaurora.org>

Add the platform data to the board file.

Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/board-msm8x60.c |   50 +++++++++++++++++++++++++++++++++++++
 1 files changed, 50 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 7b8016f..f034bf5 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -73,8 +73,58 @@ static void __init msm8x60_init_irq(void)
 		writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
 }
 
+static struct resource msm_uart12_dm_resources[] = {
+	{
+		.start = 0x19C40000,
+		.end   = 0x19C40000 + PAGE_SIZE - 1,
+		.name  = "uart_resource",
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = INT_UART12DM_IRQ,
+		.end   = INT_UART12DM_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+	{
+		/* GSBI 12 is UARTDM2 */
+		.start = 0x19C00000,
+		.end   = 0x19C00000 + PAGE_SIZE - 1,
+		.name  = "gsbi_resource",
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device msm_device_uart_dm12 = {
+	.name = "msm_serial",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(msm_uart12_dm_resources),
+	.resource = msm_uart12_dm_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+	&msm_device_uart_dm12,
+};
+
+static void __init msm8x60_init_uart12dm(void)
+{
+	/* 0x1D000000 now belongs to EBI2:CS3 i.e. USB ISP Controller */
+	void *fpga_mem = ioremap_nocache(0x1D000000, SZ_4K);
+	/* Advanced mode */
+	writew(0xFFFF, fpga_mem + 0x15C);
+	/* FPGA_UART_SEL */
+	writew(0, fpga_mem + 0x172);
+	/* FPGA_GPIO_CONFIG_117 */
+	writew(1, fpga_mem + 0xEA);
+	/* FPGA_GPIO_CONFIG_118 */
+	writew(1, fpga_mem + 0xEC);
+	dmb();
+	iounmap(fpga_mem);
+}
+
 static void __init msm8x60_init(void)
 {
+	msm8x60_init_uart12dm();
+	platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
 MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 28/34] msm: clock: Invert CLKFLAG_AUTO_OFF

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

All locally controlled clocks can participate in the auto off
operations. Make the auto off flag default (and 0) to save lines
in struct clk definitions. We make the auto_off ops optional to
avoid marking PLLs and XOs explicitly.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-7x30.c        |  210 ++++++++----------
 arch/arm/mach-msm/clock-8960.c        |  116 ----------
 arch/arm/mach-msm/clock-8x60.c        |  104 ---------
 arch/arm/mach-msm/clock-pcom-lookup.c |  381 +++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/clock-voter.h       |    1 +
 arch/arm/mach-msm/clock.c             |   11 +-
 arch/arm/mach-msm/clock.h             |    3 +-
 arch/arm/mach-msm/devices-msm7x00.c   |   82 ++++----
 arch/arm/mach-msm/devices-qsd8x50.c   |  100 +++++-----
 9 files changed, 573 insertions(+), 435 deletions(-)
 create mode 100644 arch/arm/mach-msm/clock-pcom-lookup.c

diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index f73e76f..ce0e73c 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -553,7 +553,6 @@ static struct branch_clk camif_pad_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "camif_pad_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(camif_pad_p_clk.c),
 	},
@@ -588,7 +587,6 @@ static struct branch_clk emdh_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "emdh_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(emdh_p_clk.c),
 	},
@@ -640,7 +638,6 @@ static struct branch_clk jpeg_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "jpeg_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(jpeg_p_clk.c),
 	},
@@ -726,7 +723,6 @@ static struct branch_clk rotator_imem_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "rotator_imem_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(rotator_imem_clk.c),
 	},
@@ -744,7 +740,6 @@ static struct branch_clk rotator_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "rotator_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(rotator_p_clk.c),
 	},
@@ -762,7 +757,6 @@ static struct branch_clk sdc1_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "sdc1_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(sdc1_p_clk.c),
 	},
@@ -780,7 +774,6 @@ static struct branch_clk sdc2_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "sdc2_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(sdc2_p_clk.c),
 	},
@@ -798,7 +791,6 @@ static struct branch_clk sdc3_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "sdc3_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(sdc3_p_clk.c),
 	},
@@ -816,7 +808,6 @@ static struct branch_clk sdc4_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "sdc4_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(sdc4_p_clk.c),
 	},
@@ -900,7 +891,6 @@ static struct branch_clk usb_hs2_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "usb_hs2_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(usb_hs2_p_clk.c),
 	},
@@ -918,7 +908,6 @@ static struct branch_clk usb_hs3_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "usb_hs3_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(usb_hs3_p_clk.c),
 	},
@@ -936,7 +925,6 @@ static struct branch_clk usb_hs_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "usb_hs_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(usb_hs_p_clk.c),
 	},
@@ -954,7 +942,6 @@ static struct branch_clk vfe_p_clk = {
 	.parent = &glbl_root_clk.c,
 	.c = {
 		.dbg_name = "vfe_p_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(vfe_p_clk.c),
 	},
@@ -1066,7 +1053,6 @@ static struct rcg_clk uart1_clk = {
 	.current_freq = &local_dummy_freq,
 	.c = {
 		.dbg_name = "uart1_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(uart1_clk.c),
 	},
@@ -1124,7 +1110,6 @@ static struct rcg_clk uart1dm_clk = {
 	.set_rate = set_rate_mnd,
 	.c = {
 		.dbg_name = "uart1dm_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(uart1dm_clk.c),
 	},
@@ -1180,7 +1165,7 @@ static struct rcg_clk emdh_clk = {
 	.current_freq = &local_dummy_freq,
 	.c = {
 		.dbg_name = "emdh_clk",
-		.flags = CLKFLAG_AUTO_OFF | CLKFLAG_MIN | CLKFLAG_MAX,
+		.flags = CLKFLAG_MIN | CLKFLAG_MAX,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(emdh_clk.c),
 	},
@@ -1201,7 +1186,7 @@ static struct rcg_clk pmdh_clk = {
 	.current_freq = &local_dummy_freq,
 	.c = {
 		.dbg_name = "pmdh_clk",
-		.flags = CLKFLAG_AUTO_OFF | CLKFLAG_MIN | CLKFLAG_MAX,
+		.flags = CLKFLAG_MIN | CLKFLAG_MAX,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(pmdh_clk.c),
 	},
@@ -1297,7 +1282,6 @@ static struct branch_clk imem_clk = {
 	.parent = &grp_3d_src_clk.c,
 	.c = {
 		.dbg_name = "imem_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(imem_clk.c),
 	},
@@ -1332,7 +1316,6 @@ static struct rcg_clk sdc1_clk = {
 	.set_rate = set_rate_mnd,
 	.c = {
 		.dbg_name = "sdc1_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(sdc1_clk.c),
 	},
@@ -1355,7 +1338,6 @@ static struct rcg_clk sdc3_clk = {
 	.set_rate = set_rate_mnd,
 	.c = {
 		.dbg_name = "sdc3_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(sdc3_clk.c),
 	},
@@ -1390,7 +1372,6 @@ static struct rcg_clk sdc2_clk = {
 	.set_rate = set_rate_mnd,
 	.c = {
 		.dbg_name = "sdc2_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(sdc2_clk.c),
 	},
@@ -1413,7 +1394,6 @@ static struct rcg_clk sdc4_clk = {
 	.set_rate = set_rate_mnd,
 	.c = {
 		.dbg_name = "sdc4_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(sdc4_clk.c),
 	},
@@ -1449,7 +1429,6 @@ static struct rcg_clk mdp_clk = {
 	.current_freq = &local_dummy_freq,
 	.c = {
 		.dbg_name = "mdp_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(mdp_clk.c),
 	},
@@ -1524,7 +1503,6 @@ static struct rcg_clk mdp_vsync_clk = {
 	.current_freq = &local_dummy_freq,
 	.c = {
 		.dbg_name = "mdp_vsync_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(mdp_vsync_clk.c),
 	},
@@ -1724,7 +1702,6 @@ static struct rcg_clk sdac_clk = {
 	.current_freq = &local_dummy_freq,
 	.c = {
 		.dbg_name = "sdac_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(sdac_clk.c),
 	},
@@ -1741,7 +1718,6 @@ static struct branch_clk sdac_m_clk = {
 	.parent = &sdac_clk.c,
 	.c = {
 		.dbg_name = "sdac_m_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(sdac_m_clk.c),
 	},
@@ -1874,7 +1850,6 @@ static struct branch_clk usb_hs_clk = {
 	},
 	.c = {
 		.dbg_name = "usb_hs_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(usb_hs_clk.c),
 	},
@@ -1891,7 +1866,6 @@ static struct branch_clk usb_hs_core_clk = {
 	.parent = &usb_hs_src_clk.c,
 	.c = {
 		.dbg_name = "usb_hs_core_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(usb_hs_core_clk.c),
 	},
@@ -1908,7 +1882,6 @@ static struct branch_clk usb_hs2_clk = {
 	.parent = &usb_hs_src_clk.c,
 	.c = {
 		.dbg_name = "usb_hs2_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(usb_hs2_clk.c),
 	},
@@ -1925,7 +1898,6 @@ static struct branch_clk usb_hs2_core_clk = {
 	.parent = &usb_hs_src_clk.c,
 	.c = {
 		.dbg_name = "usb_hs2_core_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(usb_hs2_core_clk.c),
 	},
@@ -1942,7 +1914,6 @@ static struct branch_clk usb_hs3_clk = {
 	.parent = &usb_hs_src_clk.c,
 	.c = {
 		.dbg_name = "usb_hs3_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(usb_hs3_clk.c),
 	},
@@ -1959,7 +1930,6 @@ static struct branch_clk usb_hs3_core_clk = {
 	.parent = &usb_hs_src_clk.c,
 	.c = {
 		.dbg_name = "usb_hs3_core_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &clk_ops_branch,
 		CLK_INIT(usb_hs3_core_clk.c),
 	},
@@ -2000,7 +1970,6 @@ static struct rcg_clk jpeg_clk = {
 	.current_freq = &local_dummy_freq,
 	.c = {
 		.dbg_name = "jpeg_clk",
-		.flags = CLKFLAG_AUTO_OFF,
 		.ops = &soc_clk_ops_7x30,
 		CLK_INIT(jpeg_clk.c),
 	},
@@ -2294,93 +2263,98 @@ static struct branch_clk lpa_core_clk = {
 	},
 };
 
-static DEFINE_CLK_PCOM(adsp_clk, ADSP_CLK, 0);
-static DEFINE_CLK_PCOM(codec_ssbi_clk,	CODEC_SSBI_CLK, 0);
+static DEFINE_CLK_PCOM(adsp_clk, ADSP_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(codec_ssbi_clk,	CODEC_SSBI_CLK, CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(ebi1_clk, EBI1_CLK, CLK_MIN);
-static DEFINE_CLK_PCOM(ecodec_clk, ECODEC_CLK, 0);
-static DEFINE_CLK_PCOM(gp_clk, GP_CLK, 0);
-static DEFINE_CLK_PCOM(uart3_clk, UART3_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(usb_phy_clk, USB_PHY_CLK, CLKFLAG_AUTO_OFF | CLK_MIN);
+static DEFINE_CLK_PCOM(ecodec_clk, ECODEC_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(gp_clk, GP_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(uart3_clk, UART3_CLK, 0);
+static DEFINE_CLK_PCOM(usb_phy_clk, USB_PHY_CLK, CLK_MIN);
 
-static DEFINE_CLK_PCOM(p_grp_2d_clk, GRP_2D_CLK, 0);
-static DEFINE_CLK_PCOM(p_grp_2d_p_clk, GRP_2D_P_CLK, 0);
-static DEFINE_CLK_PCOM(p_hdmi_clk, HDMI_CLK, 0);
-static DEFINE_CLK_PCOM(p_jpeg_clk, JPEG_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_jpeg_p_clk, JPEG_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_lpa_codec_clk, LPA_CODEC_CLK, 0);
-static DEFINE_CLK_PCOM(p_lpa_core_clk, LPA_CORE_CLK, 0);
-static DEFINE_CLK_PCOM(p_lpa_p_clk, LPA_P_CLK, 0);
-static DEFINE_CLK_PCOM(p_mi2s_m_clk, MI2S_M_CLK, 0);
-static DEFINE_CLK_PCOM(p_mi2s_s_clk, MI2S_S_CLK, 0);
-static DEFINE_CLK_PCOM(p_mi2s_codec_rx_m_clk, MI2S_CODEC_RX_M_CLK, 0);
-static DEFINE_CLK_PCOM(p_mi2s_codec_rx_s_clk, MI2S_CODEC_RX_S_CLK, 0);
-static DEFINE_CLK_PCOM(p_mi2s_codec_tx_m_clk, MI2S_CODEC_TX_M_CLK, 0);
-static DEFINE_CLK_PCOM(p_mi2s_codec_tx_s_clk, MI2S_CODEC_TX_S_CLK, 0);
-static DEFINE_CLK_PCOM(p_sdac_clk, SDAC_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_sdac_m_clk, SDAC_M_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_vfe_clk, VFE_CLK, 0);
-static DEFINE_CLK_PCOM(p_vfe_camif_clk, VFE_CAMIF_CLK, 0);
-static DEFINE_CLK_PCOM(p_vfe_mdc_clk, VFE_MDC_CLK, 0);
-static DEFINE_CLK_PCOM(p_vfe_p_clk, VFE_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_grp_3d_clk, GRP_3D_CLK, 0);
-static DEFINE_CLK_PCOM(p_grp_3d_p_clk, GRP_3D_P_CLK, 0);
-static DEFINE_CLK_PCOM(p_imem_clk, IMEM_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_mdp_lcdc_pad_pclk_clk, MDP_LCDC_PAD_PCLK_CLK, 0);
-static DEFINE_CLK_PCOM(p_mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK, 0);
-static DEFINE_CLK_PCOM(p_mdp_p_clk, MDP_P_CLK, 0);
-static DEFINE_CLK_PCOM(p_mdp_vsync_clk, MDP_VSYNC_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_tsif_ref_clk, TSIF_REF_CLK, 0);
-static DEFINE_CLK_PCOM(p_tsif_p_clk, TSIF_P_CLK, 0);
-static DEFINE_CLK_PCOM(p_tv_dac_clk, TV_DAC_CLK, 0);
-static DEFINE_CLK_PCOM(p_tv_enc_clk, TV_ENC_CLK, 0);
-static DEFINE_CLK_PCOM(p_emdh_clk, EMDH_CLK,
-		CLKFLAG_AUTO_OFF | CLKFLAG_MIN | CLKFLAG_MAX);
-static DEFINE_CLK_PCOM(p_emdh_p_clk, EMDH_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_i2c_clk, I2C_CLK, 0);
-static DEFINE_CLK_PCOM(p_i2c_2_clk, I2C_2_CLK, 0);
-static DEFINE_CLK_PCOM(p_mdc_clk, MDC_CLK, 0);
-static DEFINE_CLK_PCOM(p_pmdh_clk, PMDH_CLK,
-		CLKFLAG_AUTO_OFF | CLKFLAG_MIN | CLKFLAG_MAX);
-static DEFINE_CLK_PCOM(p_pmdh_p_clk, PMDH_P_CLK, 0);
-static DEFINE_CLK_PCOM(p_sdc1_clk, SDC1_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_sdc1_p_clk, SDC1_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_sdc2_clk, SDC2_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_sdc2_p_clk, SDC2_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_sdc3_clk, SDC3_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_sdc3_p_clk, SDC3_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_sdc4_clk, SDC4_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_sdc4_p_clk, SDC4_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_uart2_clk, UART2_CLK, 0);
-static DEFINE_CLK_PCOM(p_usb_hs2_clk, USB_HS2_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_usb_hs2_core_clk, USB_HS2_CORE_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_usb_hs2_p_clk, USB_HS2_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_usb_hs3_clk, USB_HS3_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_usb_hs3_core_clk, USB_HS3_CORE_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_usb_hs3_p_clk, USB_HS3_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_qup_i2c_clk, QUP_I2C_CLK, 0);
-static DEFINE_CLK_PCOM(p_spi_clk, SPI_CLK, 0);
-static DEFINE_CLK_PCOM(p_spi_p_clk, SPI_P_CLK, 0);
-static DEFINE_CLK_PCOM(p_uart1_clk, UART1_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_uart1dm_clk, UART1DM_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_uart2dm_clk, UART2DM_CLK, 0);
-static DEFINE_CLK_PCOM(p_usb_hs_clk, USB_HS_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_usb_hs_core_clk, USB_HS_CORE_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_usb_hs_p_clk, USB_HS_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_cam_m_clk, CAM_M_CLK, 0);
-static DEFINE_CLK_PCOM(p_camif_pad_p_clk, CAMIF_PAD_P_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_csi0_clk, CSI0_CLK, 0);
-static DEFINE_CLK_PCOM(p_csi0_vfe_clk, CSI0_VFE_CLK, 0);
-static DEFINE_CLK_PCOM(p_csi0_p_clk, CSI0_P_CLK, 0);
-static DEFINE_CLK_PCOM(p_mdp_clk, MDP_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_mfc_clk, MFC_CLK, 0);
-static DEFINE_CLK_PCOM(p_mfc_div2_clk, MFC_DIV2_CLK, 0);
-static DEFINE_CLK_PCOM(p_mfc_p_clk, MFC_P_CLK, 0);
-static DEFINE_CLK_PCOM(p_vpe_clk, VPE_CLK, 0);
-static DEFINE_CLK_PCOM(p_adm_clk, ADM_CLK, 0);
-static DEFINE_CLK_PCOM(p_ce_clk, CE_CLK, 0);
-static DEFINE_CLK_PCOM(p_axi_rotator_clk, AXI_ROTATOR_CLK, 0);
-static DEFINE_CLK_PCOM(p_rotator_imem_clk, ROTATOR_IMEM_CLK, CLKFLAG_AUTO_OFF);
-static DEFINE_CLK_PCOM(p_rotator_p_clk, ROTATOR_P_CLK, CLKFLAG_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_grp_2d_clk, GRP_2D_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_grp_2d_p_clk, GRP_2D_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_hdmi_clk, HDMI_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_jpeg_clk, JPEG_CLK, 0);
+static DEFINE_CLK_PCOM(p_jpeg_p_clk, JPEG_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_lpa_codec_clk, LPA_CODEC_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_lpa_core_clk, LPA_CORE_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_lpa_p_clk, LPA_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mi2s_m_clk, MI2S_M_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mi2s_s_clk, MI2S_S_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mi2s_codec_rx_m_clk, MI2S_CODEC_RX_M_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mi2s_codec_rx_s_clk, MI2S_CODEC_RX_S_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mi2s_codec_tx_m_clk, MI2S_CODEC_TX_M_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mi2s_codec_tx_s_clk, MI2S_CODEC_TX_S_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_sdac_clk, SDAC_CLK, 0);
+static DEFINE_CLK_PCOM(p_sdac_m_clk, SDAC_M_CLK, 0);
+static DEFINE_CLK_PCOM(p_vfe_clk, VFE_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_vfe_camif_clk, VFE_CAMIF_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_vfe_mdc_clk, VFE_MDC_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_vfe_p_clk, VFE_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_grp_3d_clk, GRP_3D_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_grp_3d_p_clk, GRP_3D_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_imem_clk, IMEM_CLK, 0);
+static DEFINE_CLK_PCOM(p_mdp_lcdc_pad_pclk_clk, MDP_LCDC_PAD_PCLK_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mdp_p_clk, MDP_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mdp_vsync_clk, MDP_VSYNC_CLK, 0);
+static DEFINE_CLK_PCOM(p_tsif_ref_clk, TSIF_REF_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_tsif_p_clk, TSIF_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_tv_dac_clk, TV_DAC_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_tv_enc_clk, TV_ENC_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_emdh_clk, EMDH_CLK, CLKFLAG_MIN | CLKFLAG_MAX);
+static DEFINE_CLK_PCOM(p_emdh_p_clk, EMDH_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_i2c_clk, I2C_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_i2c_2_clk, I2C_2_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mdc_clk, MDC_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_pmdh_clk, PMDH_CLK, CLKFLAG_MIN | CLKFLAG_MAX);
+static DEFINE_CLK_PCOM(p_pmdh_p_clk, PMDH_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_sdc1_clk, SDC1_CLK, 0);
+static DEFINE_CLK_PCOM(p_sdc1_p_clk, SDC1_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_sdc2_clk, SDC2_CLK, 0);
+static DEFINE_CLK_PCOM(p_sdc2_p_clk, SDC2_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_sdc3_clk, SDC3_CLK, 0);
+static DEFINE_CLK_PCOM(p_sdc3_p_clk, SDC3_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_sdc4_clk, SDC4_CLK, 0);
+static DEFINE_CLK_PCOM(p_sdc4_p_clk, SDC4_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_uart2_clk, UART2_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_usb_hs2_clk, USB_HS2_CLK, 0);
+static DEFINE_CLK_PCOM(p_usb_hs2_core_clk, USB_HS2_CORE_CLK, 0);
+static DEFINE_CLK_PCOM(p_usb_hs2_p_clk, USB_HS2_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_usb_hs3_clk, USB_HS3_CLK, 0);
+static DEFINE_CLK_PCOM(p_usb_hs3_core_clk, USB_HS3_CORE_CLK, 0);
+static DEFINE_CLK_PCOM(p_usb_hs3_p_clk, USB_HS3_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_qup_i2c_clk, QUP_I2C_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_spi_clk, SPI_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_spi_p_clk, SPI_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_uart1_clk, UART1_CLK, 0);
+static DEFINE_CLK_PCOM(p_uart1dm_clk, UART1DM_CLK, 0);
+static DEFINE_CLK_PCOM(p_uart2dm_clk, UART2DM_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_usb_hs_clk, USB_HS_CLK, 0);
+static DEFINE_CLK_PCOM(p_usb_hs_core_clk, USB_HS_CORE_CLK, 0);
+static DEFINE_CLK_PCOM(p_usb_hs_p_clk, USB_HS_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_cam_m_clk, CAM_M_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_camif_pad_p_clk, CAMIF_PAD_P_CLK, 0);
+static DEFINE_CLK_PCOM(p_csi0_clk, CSI0_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_csi0_vfe_clk, CSI0_VFE_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_csi0_p_clk, CSI0_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mdp_clk, MDP_CLK, 0);
+static DEFINE_CLK_PCOM(p_mfc_clk, MFC_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mfc_div2_clk, MFC_DIV2_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_mfc_p_clk, MFC_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_vpe_clk, VPE_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_adm_clk, ADM_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_ce_clk, CE_CLK, CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_axi_rotator_clk, AXI_ROTATOR_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(p_rotator_imem_clk, ROTATOR_IMEM_CLK, 0);
+static DEFINE_CLK_PCOM(p_rotator_p_clk, ROTATOR_P_CLK, 0);
 
 static struct pcom_clk pbus_clk = {
 	.id = P_PBUS_CLK,
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 6ecc5d5..d885644 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -438,7 +438,6 @@ static struct branch_clk gmem_axi_clk = {
 	.c = {
 		.dbg_name = "gmem_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gmem_axi_clk.c),
 	},
 };
@@ -455,7 +454,6 @@ static struct branch_clk ijpeg_axi_clk = {
 	.c = {
 		.dbg_name = "ijpeg_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ijpeg_axi_clk.c),
 	},
 };
@@ -472,7 +470,6 @@ static struct branch_clk imem_axi_clk = {
 	.c = {
 		.dbg_name = "imem_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(imem_axi_clk.c),
 	},
 };
@@ -487,7 +484,6 @@ static struct branch_clk jpegd_axi_clk = {
 	.c = {
 		.dbg_name = "jpegd_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(jpegd_axi_clk.c),
 	},
 };
@@ -502,7 +498,6 @@ static struct branch_clk vcodec_axi_b_clk = {
 	.c = {
 		.dbg_name = "vcodec_axi_b_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vcodec_axi_b_clk.c),
 	},
 };
@@ -518,7 +513,6 @@ static struct branch_clk vcodec_axi_a_clk = {
 	.c = {
 		.dbg_name = "vcodec_axi_a_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vcodec_axi_a_clk.c),
 	},
 };
@@ -536,7 +530,6 @@ static struct branch_clk vcodec_axi_clk = {
 	.c = {
 		.dbg_name = "vcodec_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vcodec_axi_clk.c),
 	},
 };
@@ -553,7 +546,6 @@ static struct branch_clk vfe_axi_clk = {
 	.c = {
 		.dbg_name = "vfe_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vfe_axi_clk.c),
 	},
 };
@@ -620,7 +612,6 @@ static struct branch_clk amp_p_clk = {
 	.c = {
 		.dbg_name = "amp_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(amp_p_clk.c),
 	},
 };
@@ -637,7 +628,6 @@ static struct branch_clk csi0_p_clk = {
 	.c = {
 		.dbg_name = "csi0_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi0_p_clk.c),
 	},
 };
@@ -654,7 +644,6 @@ static struct branch_clk dsi1_m_p_clk = {
 	.c = {
 		.dbg_name = "dsi1_m_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi1_m_p_clk.c),
 	},
 };
@@ -671,7 +660,6 @@ static struct branch_clk dsi1_s_p_clk = {
 	.c = {
 		.dbg_name = "dsi1_s_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi1_s_p_clk.c),
 	},
 };
@@ -688,7 +676,6 @@ static struct branch_clk dsi2_m_p_clk = {
 	.c = {
 		.dbg_name = "dsi2_m_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi2_m_p_clk.c),
 	},
 };
@@ -705,7 +692,6 @@ static struct branch_clk dsi2_s_p_clk = {
 	.c = {
 		.dbg_name = "dsi2_s_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi2_s_p_clk.c),
 	},
 };
@@ -722,7 +708,6 @@ static struct branch_clk gfx2d0_p_clk = {
 	.c = {
 		.dbg_name = "gfx2d0_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx2d0_p_clk.c),
 	},
 };
@@ -739,7 +724,6 @@ static struct branch_clk gfx2d1_p_clk = {
 	.c = {
 		.dbg_name = "gfx2d1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx2d1_p_clk.c),
 	},
 };
@@ -756,7 +740,6 @@ static struct branch_clk gfx3d_p_clk = {
 	.c = {
 		.dbg_name = "gfx3d_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx3d_p_clk.c),
 	},
 };
@@ -773,7 +756,6 @@ static struct branch_clk hdmi_m_p_clk = {
 	.c = {
 		.dbg_name = "hdmi_m_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(hdmi_m_p_clk.c),
 	},
 };
@@ -790,7 +772,6 @@ static struct branch_clk hdmi_s_p_clk = {
 	.c = {
 		.dbg_name = "hdmi_s_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(hdmi_s_p_clk.c),
 	},
 };
@@ -807,7 +788,6 @@ static struct branch_clk ijpeg_p_clk = {
 	.c = {
 		.dbg_name = "ijpeg_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ijpeg_p_clk.c),
 	},
 };
@@ -824,7 +804,6 @@ static struct branch_clk imem_p_clk = {
 	.c = {
 		.dbg_name = "imem_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(imem_p_clk.c),
 	},
 };
@@ -841,7 +820,6 @@ static struct branch_clk jpegd_p_clk = {
 	.c = {
 		.dbg_name = "jpegd_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(jpegd_p_clk.c),
 	},
 };
@@ -858,7 +836,6 @@ static struct branch_clk mdp_p_clk = {
 	.c = {
 		.dbg_name = "mdp_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(mdp_p_clk.c),
 	},
 };
@@ -875,7 +852,6 @@ static struct branch_clk rot_p_clk = {
 	.c = {
 		.dbg_name = "rot_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(rot_p_clk.c),
 	},
 };
@@ -890,7 +866,6 @@ static struct branch_clk smmu_p_clk = {
 	.c = {
 		.dbg_name = "smmu_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(smmu_p_clk.c),
 	},
 };
@@ -907,7 +882,6 @@ static struct branch_clk tv_enc_p_clk = {
 	.c = {
 		.dbg_name = "tv_enc_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tv_enc_p_clk.c),
 	},
 };
@@ -924,7 +898,6 @@ static struct branch_clk vcodec_p_clk = {
 	.c = {
 		.dbg_name = "vcodec_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vcodec_p_clk.c),
 	},
 };
@@ -941,7 +914,6 @@ static struct branch_clk vfe_p_clk = {
 	.c = {
 		.dbg_name = "vfe_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vfe_p_clk.c),
 	},
 };
@@ -958,7 +930,6 @@ static struct branch_clk vpe_p_clk = {
 	.c = {
 		.dbg_name = "vpe_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vpe_p_clk.c),
 	},
 };
@@ -986,7 +957,6 @@ static struct branch_clk vpe_p_clk = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8960, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -1051,7 +1021,6 @@ static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8960, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -1122,7 +1091,6 @@ static struct rcg_clk pdm_clk = {
 	.c = {
 		.dbg_name = "pdm_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pdm_clk.c),
 	},
 };
@@ -1137,7 +1105,6 @@ static struct branch_clk pmem_clk = {
 	.c = {
 		.dbg_name = "pmem_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pmem_clk.c),
 	},
 };
@@ -1167,7 +1134,6 @@ static struct rcg_clk prng_clk = {
 	.c = {
 		.dbg_name = "prng_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(prng_clk.c),
 	},
 };
@@ -1193,7 +1159,6 @@ static struct rcg_clk prng_clk = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8960, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -1259,7 +1224,6 @@ static struct rcg_clk tsif_ref_clk = {
 	.c = {
 		.dbg_name = "tsif_ref_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tsif_ref_clk.c),
 	},
 };
@@ -1292,7 +1256,6 @@ static struct rcg_clk tssc_clk = {
 	.c = {
 		.dbg_name = "tssc_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tssc_clk.c),
 	},
 };
@@ -1331,7 +1294,6 @@ static struct rcg_clk usb_hs1_xcvr_clk = {
 	.c = {
 		.dbg_name = "usb_hs1_xcvr_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_hs1_xcvr_clk.c),
 	},
 };
@@ -1364,7 +1326,6 @@ static struct branch_clk usb_phy0_clk = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8960, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -1383,7 +1344,6 @@ static struct branch_clk usb_fs1_xcvr_clk = {
 	.c = {
 		.dbg_name = "usb_fs1_xcvr_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs1_xcvr_clk.c),
 	},
 };
@@ -1401,7 +1361,6 @@ static struct branch_clk usb_fs1_sys_clk = {
 	.c = {
 		.dbg_name = "usb_fs1_sys_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs1_sys_clk.c),
 	},
 };
@@ -1420,7 +1379,6 @@ static struct branch_clk usb_fs2_xcvr_clk = {
 	.c = {
 		.dbg_name = "usb_fs2_xcvr_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs2_xcvr_clk.c),
 	},
 };
@@ -1438,7 +1396,6 @@ static struct branch_clk usb_fs2_sys_clk = {
 	.c = {
 		.dbg_name = "usb_fs2_sys_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs2_sys_clk.c),
 	},
 };
@@ -1454,7 +1411,6 @@ static struct branch_clk ce1_core_clk = {
 	.c = {
 		.dbg_name = "ce1_core_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ce1_core_clk.c),
 	},
 };
@@ -1468,7 +1424,6 @@ static struct branch_clk ce1_p_clk = {
 	.c = {
 		.dbg_name = "ce1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ce1_p_clk.c),
 	},
 };
@@ -1483,7 +1438,6 @@ static struct branch_clk dma_bam_p_clk = {
 	.c = {
 		.dbg_name = "dma_bam_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dma_bam_p_clk.c),
 	},
 };
@@ -1498,7 +1452,6 @@ static struct branch_clk gsbi1_p_clk = {
 	.c = {
 		.dbg_name = "gsbi1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi1_p_clk.c),
 	},
 };
@@ -1513,7 +1466,6 @@ static struct branch_clk gsbi2_p_clk = {
 	.c = {
 		.dbg_name = "gsbi2_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi2_p_clk.c),
 	},
 };
@@ -1528,7 +1480,6 @@ static struct branch_clk gsbi3_p_clk = {
 	.c = {
 		.dbg_name = "gsbi3_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi3_p_clk.c),
 	},
 };
@@ -1543,7 +1494,6 @@ static struct branch_clk gsbi4_p_clk = {
 	.c = {
 		.dbg_name = "gsbi4_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi4_p_clk.c),
 	},
 };
@@ -1558,7 +1508,6 @@ static struct branch_clk gsbi5_p_clk = {
 	.c = {
 		.dbg_name = "gsbi5_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi5_p_clk.c),
 	},
 };
@@ -1573,7 +1522,6 @@ static struct branch_clk gsbi6_p_clk = {
 	.c = {
 		.dbg_name = "gsbi6_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi6_p_clk.c),
 	},
 };
@@ -1588,7 +1536,6 @@ static struct branch_clk gsbi7_p_clk = {
 	.c = {
 		.dbg_name = "gsbi7_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi7_p_clk.c),
 	},
 };
@@ -1603,7 +1550,6 @@ static struct branch_clk gsbi8_p_clk = {
 	.c = {
 		.dbg_name = "gsbi8_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi8_p_clk.c),
 	},
 };
@@ -1618,7 +1564,6 @@ static struct branch_clk gsbi9_p_clk = {
 	.c = {
 		.dbg_name = "gsbi9_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi9_p_clk.c),
 	},
 };
@@ -1633,7 +1578,6 @@ static struct branch_clk gsbi10_p_clk = {
 	.c = {
 		.dbg_name = "gsbi10_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi10_p_clk.c),
 	},
 };
@@ -1648,7 +1592,6 @@ static struct branch_clk gsbi11_p_clk = {
 	.c = {
 		.dbg_name = "gsbi11_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi11_p_clk.c),
 	},
 };
@@ -1663,7 +1606,6 @@ static struct branch_clk gsbi12_p_clk = {
 	.c = {
 		.dbg_name = "gsbi12_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi12_p_clk.c),
 	},
 };
@@ -1678,7 +1620,6 @@ static struct branch_clk tsif_p_clk = {
 	.c = {
 		.dbg_name = "tsif_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tsif_p_clk.c),
 	},
 };
@@ -1693,7 +1634,6 @@ static struct branch_clk usb_fs1_p_clk = {
 	.c = {
 		.dbg_name = "usb_fs1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs1_p_clk.c),
 	},
 };
@@ -1708,7 +1648,6 @@ static struct branch_clk usb_fs2_p_clk = {
 	.c = {
 		.dbg_name = "usb_fs2_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs2_p_clk.c),
 	},
 };
@@ -1723,7 +1662,6 @@ static struct branch_clk usb_hs1_p_clk = {
 	.c = {
 		.dbg_name = "usb_hs1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_hs1_p_clk.c),
 	},
 };
@@ -1738,7 +1676,6 @@ static struct branch_clk sdc1_p_clk = {
 	.c = {
 		.dbg_name = "sdc1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sdc1_p_clk.c),
 	},
 };
@@ -1753,7 +1690,6 @@ static struct branch_clk sdc2_p_clk = {
 	.c = {
 		.dbg_name = "sdc2_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sdc2_p_clk.c),
 	},
 };
@@ -1768,7 +1704,6 @@ static struct branch_clk sdc3_p_clk = {
 	.c = {
 		.dbg_name = "sdc3_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sdc3_p_clk.c),
 	},
 };
@@ -1783,7 +1718,6 @@ static struct branch_clk sdc4_p_clk = {
 	.c = {
 		.dbg_name = "sdc4_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sdc4_p_clk.c),
 	},
 };
@@ -1798,7 +1732,6 @@ static struct branch_clk sdc5_p_clk = {
 	.c = {
 		.dbg_name = "sdc5_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sdc5_p_clk.c),
 	},
 };
@@ -1815,7 +1748,6 @@ static struct branch_clk adm0_clk = {
 	.c = {
 		.dbg_name = "adm0_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(adm0_clk.c),
 	},
 };
@@ -1831,7 +1763,6 @@ static struct branch_clk adm0_p_clk = {
 	.c = {
 		.dbg_name = "adm0_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(adm0_p_clk.c),
 	},
 };
@@ -1847,7 +1778,6 @@ static struct branch_clk pmic_arb0_p_clk = {
 	.c = {
 		.dbg_name = "pmic_arb0_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pmic_arb0_p_clk.c),
 	},
 };
@@ -1863,7 +1793,6 @@ static struct branch_clk pmic_arb1_p_clk = {
 	.c = {
 		.dbg_name = "pmic_arb1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pmic_arb1_p_clk.c),
 	},
 };
@@ -1879,7 +1808,6 @@ static struct branch_clk pmic_ssbi2_clk = {
 	.c = {
 		.dbg_name = "pmic_ssbi2_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pmic_ssbi2_clk.c),
 	},
 };
@@ -1895,7 +1823,6 @@ static struct branch_clk rpm_msg_ram_p_clk = {
 	.c = {
 		.dbg_name = "rpm_msg_ram_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(rpm_msg_ram_p_clk.c),
 	},
 };
@@ -1935,7 +1862,6 @@ static struct branch_clk amp_clk = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8960, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -2001,7 +1927,6 @@ static struct rcg_clk csi0_src_clk = {
 	.c = {
 		.dbg_name = "csi0_src_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi0_src_clk.c),
 	},
 };
@@ -2019,7 +1944,6 @@ static struct branch_clk csi0_clk = {
 	.c = {
 		.dbg_name = "csi0_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi0_clk.c),
 	},
 };
@@ -2037,7 +1961,6 @@ static struct branch_clk csi0_phy_clk = {
 	.c = {
 		.dbg_name = "csi0_phy_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi0_phy_clk.c),
 	},
 };
@@ -2058,7 +1981,6 @@ static struct rcg_clk csi1_src_clk = {
 	.c = {
 		.dbg_name = "csi1_src_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi1_src_clk.c),
 	},
 };
@@ -2076,7 +1998,6 @@ static struct branch_clk csi1_clk = {
 	.c = {
 		.dbg_name = "csi1_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi1_clk.c),
 	},
 };
@@ -2094,7 +2015,6 @@ static struct branch_clk csi1_phy_clk = {
 	.c = {
 		.dbg_name = "csi1_phy_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi1_phy_clk.c),
 	},
 };
@@ -2139,7 +2059,6 @@ static struct rcg_clk csi_pix_clk = {
 	.c = {
 		.dbg_name = "csi_pix_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi_pix_clk.c),
 	},
 };
@@ -2160,7 +2079,6 @@ static struct rcg_clk csi_rdi_clk = {
 	.c = {
 		.dbg_name = "csi_rdi_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi_rdi_clk.c),
 	},
 };
@@ -2198,7 +2116,6 @@ static struct rcg_clk csiphy_timer_src_clk = {
 	.c = {
 		.dbg_name = "csiphy_timer_src_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csiphy_timer_src_clk.c),
 	},
 };
@@ -2214,7 +2131,6 @@ static struct branch_clk csi0phy_timer_clk = {
 	.c = {
 		.dbg_name = "csi0phy_timer_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi0phy_timer_clk.c),
 	},
 };
@@ -2230,7 +2146,6 @@ static struct branch_clk csi1phy_timer_clk = {
 	.c = {
 		.dbg_name = "csi1phy_timer_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi1phy_timer_clk.c),
 	},
 };
@@ -2271,7 +2186,6 @@ static struct rcg_clk dsi1_byte_clk = {
 	.c = {
 		.dbg_name = "dsi1_byte_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi1_byte_clk.c),
 	},
 };
@@ -2294,7 +2208,6 @@ static struct rcg_clk dsi2_byte_clk = {
 	.c = {
 		.dbg_name = "dsi2_byte_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi2_byte_clk.c),
 	},
 };
@@ -2316,7 +2229,6 @@ static struct rcg_clk dsi1_esc_clk = {
 	.c = {
 		.dbg_name = "dsi1_esc_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi1_esc_clk.c),
 	},
 };
@@ -2337,7 +2249,6 @@ static struct rcg_clk dsi2_esc_clk = {
 	.c = {
 		.dbg_name = "dsi2_esc_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi2_esc_clk.c),
 	},
 };
@@ -2405,7 +2316,6 @@ static struct rcg_clk gfx2d0_clk = {
 	.c = {
 		.dbg_name = "gfx2d0_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx2d0_clk.c),
 	},
 };
@@ -2446,7 +2356,6 @@ static struct rcg_clk gfx2d1_clk = {
 	.c = {
 		.dbg_name = "gfx2d1_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx2d1_clk.c),
 	},
 };
@@ -2517,7 +2426,6 @@ static struct rcg_clk gfx3d_clk = {
 	.c = {
 		.dbg_name = "gfx3d_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx3d_clk.c),
 	},
 };
@@ -2567,7 +2475,6 @@ static struct rcg_clk ijpeg_clk = {
 	.c = {
 		.dbg_name = "ijpeg_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ijpeg_clk.c),
 	},
 };
@@ -2608,7 +2515,6 @@ static struct rcg_clk jpegd_clk = {
 	.c = {
 		.dbg_name = "jpegd_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(jpegd_clk.c),
 	},
 };
@@ -2679,7 +2585,6 @@ static struct rcg_clk mdp_clk = {
 	.c = {
 		.dbg_name = "mdp_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(mdp_clk.c),
 	},
 };
@@ -2695,7 +2600,6 @@ static struct branch_clk lut_mdp_clk = {
 	.c = {
 		.dbg_name = "lut_mdp_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(lut_mdp_clk.c),
 	},
 };
@@ -2729,7 +2633,6 @@ static struct rcg_clk mdp_vsync_clk = {
 	.c = {
 		.dbg_name = "mdp_vsync_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(mdp_vsync_clk.c),
 	},
 };
@@ -2789,7 +2692,6 @@ static struct rcg_clk rot_clk = {
 	.c = {
 		.dbg_name = "rot_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(rot_clk.c),
 	},
 };
@@ -2827,7 +2729,6 @@ static struct rcg_clk tv_src_clk = {
 	.c = {
 		.dbg_name = "tv_src_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tv_src_clk.c),
 	},
 };
@@ -2845,7 +2746,6 @@ static struct branch_clk tv_enc_clk = {
 	.c = {
 		.dbg_name = "tv_enc_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tv_enc_clk.c),
 	},
 };
@@ -2861,7 +2761,6 @@ static struct branch_clk tv_dac_clk = {
 	.c = {
 		.dbg_name = "tv_dac_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tv_dac_clk.c),
 	},
 };
@@ -2879,7 +2778,6 @@ static struct branch_clk mdp_tv_clk = {
 	.c = {
 		.dbg_name = "mdp_tv_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(mdp_tv_clk.c),
 	},
 };
@@ -2897,7 +2795,6 @@ static struct branch_clk hdmi_tv_clk = {
 	.c = {
 		.dbg_name = "hdmi_tv_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(hdmi_tv_clk.c),
 	},
 };
@@ -2914,7 +2811,6 @@ static struct branch_clk hdmi_app_clk = {
 	.c = {
 		.dbg_name = "hdmi_app_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(hdmi_app_clk.c),
 	},
 };
@@ -2978,7 +2874,6 @@ static struct rcg_clk vcodec_clk = {
 	.c = {
 		.dbg_name = "vcodec_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vcodec_clk.c),
 	},
 };
@@ -3022,7 +2917,6 @@ static struct rcg_clk vpe_clk = {
 	.c = {
 		.dbg_name = "vpe_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vpe_clk.c),
 	},
 };
@@ -3080,7 +2974,6 @@ static struct rcg_clk vfe_clk = {
 	.c = {
 		.dbg_name = "vfe_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vfe_clk.c),
 	},
 };
@@ -3098,7 +2991,6 @@ static struct branch_clk csi0_vfe_clk = {
 	.c = {
 		.dbg_name = "csi0_vfe_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi0_vfe_clk.c),
 	},
 };
@@ -3151,7 +3043,6 @@ static struct clk_freq_tbl clk_tbl_aif_osr[] = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8960, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -3176,7 +3067,6 @@ static struct clk_freq_tbl clk_tbl_aif_osr[] = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8960, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -3211,7 +3101,6 @@ static struct clk_freq_tbl clk_tbl_aif_bit[] = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8960, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -3248,7 +3137,6 @@ static struct clk_freq_tbl clk_tbl_aif_bit_div[] = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8960, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -3322,7 +3210,6 @@ static struct rcg_clk pcm_clk = {
 	.c = {
 		.dbg_name = "pcm_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pcm_clk.c),
 	},
 };
@@ -3347,7 +3234,6 @@ static struct rcg_clk audio_slimbus_clk = {
 	.c = {
 		.dbg_name = "audio_slimbus_clk",
 		.ops = &soc_clk_ops_8960,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(audio_slimbus_clk.c),
 	},
 };
@@ -3364,7 +3250,6 @@ static struct branch_clk sps_slimbus_clk = {
 	.c = {
 		.dbg_name = "sps_slimbus_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sps_slimbus_clk.c),
 	},
 };
@@ -3381,7 +3266,6 @@ static struct branch_clk slimbus_xo_src_clk = {
 	.c = {
 		.dbg_name = "slimbus_xo_src_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(slimbus_xo_src_clk.c),
 	},
 };
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 71e014d..4f999d2 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -503,7 +503,6 @@ static struct branch_clk gmem_axi_clk = {
 	.c = {
 		.dbg_name = "gmem_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gmem_axi_clk.c),
 	},
 };
@@ -520,7 +519,6 @@ static struct branch_clk ijpeg_axi_clk = {
 	.c = {
 		.dbg_name = "ijpeg_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ijpeg_axi_clk.c),
 	},
 };
@@ -537,7 +535,6 @@ static struct branch_clk imem_axi_clk = {
 	.c = {
 		.dbg_name = "imem_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(imem_axi_clk.c),
 	},
 };
@@ -552,7 +549,6 @@ static struct branch_clk jpegd_axi_clk = {
 	.c = {
 		.dbg_name = "jpegd_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(jpegd_axi_clk.c),
 	},
 };
@@ -569,7 +565,6 @@ static struct branch_clk mdp_axi_clk = {
 	.c = {
 		.dbg_name = "mdp_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(mdp_axi_clk.c),
 	},
 };
@@ -586,7 +581,6 @@ static struct branch_clk vcodec_axi_clk = {
 	.c = {
 		.dbg_name = "vcodec_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vcodec_axi_clk.c),
 	},
 };
@@ -603,7 +597,6 @@ static struct branch_clk vfe_axi_clk = {
 	.c = {
 		.dbg_name = "vfe_axi_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vfe_axi_clk.c),
 	},
 };
@@ -643,7 +636,6 @@ static struct branch_clk amp_p_clk = {
 	.c = {
 		.dbg_name = "amp_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(amp_p_clk.c),
 	},
 };
@@ -660,7 +652,6 @@ static struct branch_clk csi0_p_clk = {
 	.c = {
 		.dbg_name = "csi0_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi0_p_clk.c),
 	},
 };
@@ -677,7 +668,6 @@ static struct branch_clk csi1_p_clk = {
 	.c = {
 		.dbg_name = "csi1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi1_p_clk.c),
 	},
 };
@@ -694,7 +684,6 @@ static struct branch_clk dsi_m_p_clk = {
 	.c = {
 		.dbg_name = "dsi_m_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi_m_p_clk.c),
 	},
 };
@@ -711,7 +700,6 @@ static struct branch_clk dsi_s_p_clk = {
 	.c = {
 		.dbg_name = "dsi_s_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi_s_p_clk.c),
 	},
 };
@@ -728,7 +716,6 @@ static struct branch_clk gfx2d0_p_clk = {
 	.c = {
 		.dbg_name = "gfx2d0_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx2d0_p_clk.c),
 	},
 };
@@ -745,7 +732,6 @@ static struct branch_clk gfx2d1_p_clk = {
 	.c = {
 		.dbg_name = "gfx2d1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx2d1_p_clk.c),
 	},
 };
@@ -762,7 +748,6 @@ static struct branch_clk gfx3d_p_clk = {
 	.c = {
 		.dbg_name = "gfx3d_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx3d_p_clk.c),
 	},
 };
@@ -779,7 +764,6 @@ static struct branch_clk hdmi_m_p_clk = {
 	.c = {
 		.dbg_name = "hdmi_m_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(hdmi_m_p_clk.c),
 	},
 };
@@ -796,7 +780,6 @@ static struct branch_clk hdmi_s_p_clk = {
 	.c = {
 		.dbg_name = "hdmi_s_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(hdmi_s_p_clk.c),
 	},
 };
@@ -813,7 +796,6 @@ static struct branch_clk ijpeg_p_clk = {
 	.c = {
 		.dbg_name = "ijpeg_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ijpeg_p_clk.c),
 	},
 };
@@ -830,7 +812,6 @@ static struct branch_clk imem_p_clk = {
 	.c = {
 		.dbg_name = "imem_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(imem_p_clk.c),
 	},
 };
@@ -847,7 +828,6 @@ static struct branch_clk jpegd_p_clk = {
 	.c = {
 		.dbg_name = "jpegd_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(jpegd_p_clk.c),
 	},
 };
@@ -864,7 +844,6 @@ static struct branch_clk mdp_p_clk = {
 	.c = {
 		.dbg_name = "mdp_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(mdp_p_clk.c),
 	},
 };
@@ -881,7 +860,6 @@ static struct branch_clk rot_p_clk = {
 	.c = {
 		.dbg_name = "rot_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(rot_p_clk.c),
 	},
 };
@@ -896,7 +874,6 @@ static struct branch_clk smmu_p_clk = {
 	.c = {
 		.dbg_name = "smmu_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(smmu_p_clk.c),
 	},
 };
@@ -913,7 +890,6 @@ static struct branch_clk tv_enc_p_clk = {
 	.c = {
 		.dbg_name = "tv_enc_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tv_enc_p_clk.c),
 	},
 };
@@ -930,7 +906,6 @@ static struct branch_clk vcodec_p_clk = {
 	.c = {
 		.dbg_name = "vcodec_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vcodec_p_clk.c),
 	},
 };
@@ -947,7 +922,6 @@ static struct branch_clk vfe_p_clk = {
 	.c = {
 		.dbg_name = "vfe_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vfe_p_clk.c),
 	},
 };
@@ -964,7 +938,6 @@ static struct branch_clk vpe_p_clk = {
 	.c = {
 		.dbg_name = "vpe_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vpe_p_clk.c),
 	},
 };
@@ -992,7 +965,6 @@ static struct branch_clk vpe_p_clk = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8x60, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -1057,7 +1029,6 @@ static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8x60, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -1128,7 +1099,6 @@ static struct rcg_clk pdm_clk = {
 	.c = {
 		.dbg_name = "pdm_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pdm_clk.c),
 	},
 };
@@ -1143,7 +1113,6 @@ static struct branch_clk pmem_clk = {
 	.c = {
 		.dbg_name = "pmem_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pmem_clk.c),
 	},
 };
@@ -1173,7 +1142,6 @@ static struct rcg_clk prng_clk = {
 	.c = {
 		.dbg_name = "prng_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(prng_clk.c),
 	},
 };
@@ -1198,7 +1166,6 @@ static struct rcg_clk prng_clk = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8x60, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -1261,7 +1228,6 @@ static struct rcg_clk tsif_ref_clk = {
 	.c = {
 		.dbg_name = "tsif_ref_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tsif_ref_clk.c),
 	},
 };
@@ -1294,7 +1260,6 @@ static struct rcg_clk tssc_clk = {
 	.c = {
 		.dbg_name = "tssc_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tssc_clk.c),
 	},
 };
@@ -1333,7 +1298,6 @@ static struct rcg_clk usb_hs1_xcvr_clk = {
 	.c = {
 		.dbg_name = "usb_hs1_xcvr_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_hs1_xcvr_clk.c),
 	},
 };
@@ -1366,7 +1330,6 @@ static struct branch_clk usb_phy0_clk = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8x60, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -1385,7 +1348,6 @@ static struct branch_clk usb_fs1_xcvr_clk = {
 	.c = {
 		.dbg_name = "usb_fs1_xcvr_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs1_xcvr_clk.c),
 	},
 };
@@ -1403,7 +1365,6 @@ static struct branch_clk usb_fs1_sys_clk = {
 	.c = {
 		.dbg_name = "usb_fs1_sys_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs1_sys_clk.c),
 	},
 };
@@ -1422,7 +1383,6 @@ static struct branch_clk usb_fs2_xcvr_clk = {
 	.c = {
 		.dbg_name = "usb_fs2_xcvr_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs2_xcvr_clk.c),
 	},
 };
@@ -1440,7 +1400,6 @@ static struct branch_clk usb_fs2_sys_clk = {
 	.c = {
 		.dbg_name = "usb_fs2_sys_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs2_sys_clk.c),
 	},
 };
@@ -1457,7 +1416,6 @@ static struct branch_clk ce2_p_clk = {
 	.c = {
 		.dbg_name = "ce2_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ce2_p_clk.c),
 	},
 };
@@ -1472,7 +1430,6 @@ static struct branch_clk gsbi1_p_clk = {
 	.c = {
 		.dbg_name = "gsbi1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi1_p_clk.c),
 	},
 };
@@ -1487,7 +1444,6 @@ static struct branch_clk gsbi2_p_clk = {
 	.c = {
 		.dbg_name = "gsbi2_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi2_p_clk.c),
 	},
 };
@@ -1502,7 +1458,6 @@ static struct branch_clk gsbi3_p_clk = {
 	.c = {
 		.dbg_name = "gsbi3_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi3_p_clk.c),
 	},
 };
@@ -1517,7 +1472,6 @@ static struct branch_clk gsbi4_p_clk = {
 	.c = {
 		.dbg_name = "gsbi4_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi4_p_clk.c),
 	},
 };
@@ -1532,7 +1486,6 @@ static struct branch_clk gsbi5_p_clk = {
 	.c = {
 		.dbg_name = "gsbi5_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi5_p_clk.c),
 	},
 };
@@ -1547,7 +1500,6 @@ static struct branch_clk gsbi6_p_clk = {
 	.c = {
 		.dbg_name = "gsbi6_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi6_p_clk.c),
 	},
 };
@@ -1562,7 +1514,6 @@ static struct branch_clk gsbi7_p_clk = {
 	.c = {
 		.dbg_name = "gsbi7_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi7_p_clk.c),
 	},
 };
@@ -1577,7 +1528,6 @@ static struct branch_clk gsbi8_p_clk = {
 	.c = {
 		.dbg_name = "gsbi8_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi8_p_clk.c),
 	},
 };
@@ -1592,7 +1542,6 @@ static struct branch_clk gsbi9_p_clk = {
 	.c = {
 		.dbg_name = "gsbi9_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi9_p_clk.c),
 	},
 };
@@ -1607,7 +1556,6 @@ static struct branch_clk gsbi10_p_clk = {
 	.c = {
 		.dbg_name = "gsbi10_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi10_p_clk.c),
 	},
 };
@@ -1622,7 +1570,6 @@ static struct branch_clk gsbi11_p_clk = {
 	.c = {
 		.dbg_name = "gsbi11_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi11_p_clk.c),
 	},
 };
@@ -1637,7 +1584,6 @@ static struct branch_clk gsbi12_p_clk = {
 	.c = {
 		.dbg_name = "gsbi12_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gsbi12_p_clk.c),
 	},
 };
@@ -1652,7 +1598,6 @@ static struct branch_clk ppss_p_clk = {
 	.c = {
 		.dbg_name = "ppss_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ppss_p_clk.c),
 	},
 };
@@ -1667,7 +1612,6 @@ static struct branch_clk tsif_p_clk = {
 	.c = {
 		.dbg_name = "tsif_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tsif_p_clk.c),
 	},
 };
@@ -1682,7 +1626,6 @@ static struct branch_clk usb_fs1_p_clk = {
 	.c = {
 		.dbg_name = "usb_fs1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs1_p_clk.c),
 	},
 };
@@ -1697,7 +1640,6 @@ static struct branch_clk usb_fs2_p_clk = {
 	.c = {
 		.dbg_name = "usb_fs2_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_fs2_p_clk.c),
 	},
 };
@@ -1712,7 +1654,6 @@ static struct branch_clk usb_hs1_p_clk = {
 	.c = {
 		.dbg_name = "usb_hs1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(usb_hs1_p_clk.c),
 	},
 };
@@ -1727,7 +1668,6 @@ static struct branch_clk sdc1_p_clk = {
 	.c = {
 		.dbg_name = "sdc1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sdc1_p_clk.c),
 	},
 };
@@ -1742,7 +1682,6 @@ static struct branch_clk sdc2_p_clk = {
 	.c = {
 		.dbg_name = "sdc2_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sdc2_p_clk.c),
 	},
 };
@@ -1757,7 +1696,6 @@ static struct branch_clk sdc3_p_clk = {
 	.c = {
 		.dbg_name = "sdc3_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sdc3_p_clk.c),
 	},
 };
@@ -1772,7 +1710,6 @@ static struct branch_clk sdc4_p_clk = {
 	.c = {
 		.dbg_name = "sdc4_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sdc4_p_clk.c),
 	},
 };
@@ -1787,7 +1724,6 @@ static struct branch_clk sdc5_p_clk = {
 	.c = {
 		.dbg_name = "sdc5_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(sdc5_p_clk.c),
 	},
 };
@@ -1805,7 +1741,6 @@ static struct branch_clk adm0_clk = {
 	.c = {
 		.dbg_name = "adm0_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(adm0_clk.c),
 	},
 };
@@ -1821,7 +1756,6 @@ static struct branch_clk adm0_p_clk = {
 	.c = {
 		.dbg_name = "adm0_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(adm0_p_clk.c),
 	},
 };
@@ -1838,7 +1772,6 @@ static struct branch_clk adm1_clk = {
 	.c = {
 		.dbg_name = "adm1_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(adm1_clk.c),
 	},
 };
@@ -1854,7 +1787,6 @@ static struct branch_clk adm1_p_clk = {
 	.c = {
 		.dbg_name = "adm1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(adm1_p_clk.c),
 	},
 };
@@ -1870,7 +1802,6 @@ static struct branch_clk modem_ahb1_p_clk = {
 	.c = {
 		.dbg_name = "modem_ahb1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(modem_ahb1_p_clk.c),
 	},
 };
@@ -1886,7 +1817,6 @@ static struct branch_clk modem_ahb2_p_clk = {
 	.c = {
 		.dbg_name = "modem_ahb2_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(modem_ahb2_p_clk.c),
 	},
 };
@@ -1902,7 +1832,6 @@ static struct branch_clk pmic_arb0_p_clk = {
 	.c = {
 		.dbg_name = "pmic_arb0_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pmic_arb0_p_clk.c),
 	},
 };
@@ -1918,7 +1847,6 @@ static struct branch_clk pmic_arb1_p_clk = {
 	.c = {
 		.dbg_name = "pmic_arb1_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pmic_arb1_p_clk.c),
 	},
 };
@@ -1934,7 +1862,6 @@ static struct branch_clk pmic_ssbi2_clk = {
 	.c = {
 		.dbg_name = "pmic_ssbi2_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pmic_ssbi2_clk.c),
 	},
 };
@@ -1950,7 +1877,6 @@ static struct branch_clk rpm_msg_ram_p_clk = {
 	.c = {
 		.dbg_name = "rpm_msg_ram_p_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(rpm_msg_ram_p_clk.c),
 	},
 };
@@ -2014,7 +1940,6 @@ static struct rcg_clk cam_clk = {
 	.c = {
 		.dbg_name = "cam_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(cam_clk.c),
 	},
 };
@@ -2047,7 +1972,6 @@ static struct rcg_clk csi_src_clk = {
 	.c = {
 		.dbg_name = "csi_src_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi_src_clk.c),
 	},
 };
@@ -2065,7 +1989,6 @@ static struct branch_clk csi0_clk = {
 	.c = {
 		.dbg_name = "csi0_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi0_clk.c),
 	},
 };
@@ -2083,7 +2006,6 @@ static struct branch_clk csi1_clk = {
 	.c = {
 		.dbg_name = "csi1_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi1_clk.c),
 	},
 };
@@ -2121,7 +2043,6 @@ static struct rcg_clk dsi_byte_clk = {
 	.c = {
 		.dbg_name = "dsi_byte_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi_byte_clk.c),
 	},
 };
@@ -2136,7 +2057,6 @@ static struct branch_clk dsi_esc_clk = {
 	.c = {
 		.dbg_name = "dsi_esc_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(dsi_esc_clk.c),
 	},
 };
@@ -2204,7 +2124,6 @@ static struct rcg_clk gfx2d0_clk = {
 	.c = {
 		.dbg_name = "gfx2d0_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx2d0_clk.c),
 	},
 };
@@ -2245,7 +2164,6 @@ static struct rcg_clk gfx2d1_clk = {
 	.c = {
 		.dbg_name = "gfx2d1_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx2d1_clk.c),
 	},
 };
@@ -2316,7 +2234,6 @@ static struct rcg_clk gfx3d_clk = {
 	.c = {
 		.dbg_name = "gfx3d_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(gfx3d_clk.c),
 	},
 };
@@ -2366,7 +2283,6 @@ static struct rcg_clk ijpeg_clk = {
 	.c = {
 		.dbg_name = "ijpeg_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(ijpeg_clk.c),
 	},
 };
@@ -2407,7 +2323,6 @@ static struct rcg_clk jpegd_clk = {
 	.c = {
 		.dbg_name = "jpegd_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(jpegd_clk.c),
 	},
 };
@@ -2478,7 +2393,6 @@ static struct rcg_clk mdp_clk = {
 	.c = {
 		.dbg_name = "mdp_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(mdp_clk.c),
 	},
 };
@@ -2512,7 +2426,6 @@ static struct rcg_clk mdp_vsync_clk = {
 	.c = {
 		.dbg_name = "mdp_vsync_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(mdp_vsync_clk.c),
 	},
 };
@@ -2563,7 +2476,6 @@ static struct rcg_clk pixel_mdp_clk = {
 	.c = {
 		.dbg_name = "pixel_mdp_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pixel_mdp_clk.c),
 	},
 };
@@ -2579,7 +2491,6 @@ static struct branch_clk pixel_lcdc_clk = {
 	.c = {
 		.dbg_name = "pixel_lcdc_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pixel_lcdc_clk.c),
 	},
 };
@@ -2638,7 +2549,6 @@ static struct rcg_clk rot_clk = {
 	.c = {
 		.dbg_name = "rot_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(rot_clk.c),
 	},
 };
@@ -2688,7 +2598,6 @@ static struct rcg_clk tv_src_clk = {
 	.c = {
 		.dbg_name = "tv_src_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tv_src_clk.c),
 	},
 };
@@ -2706,7 +2615,6 @@ static struct branch_clk tv_enc_clk = {
 	.c = {
 		.dbg_name = "tv_enc_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tv_enc_clk.c),
 	},
 };
@@ -2722,7 +2630,6 @@ static struct branch_clk tv_dac_clk = {
 	.c = {
 		.dbg_name = "tv_dac_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(tv_dac_clk.c),
 	},
 };
@@ -2740,7 +2647,6 @@ static struct branch_clk mdp_tv_clk = {
 	.c = {
 		.dbg_name = "mdp_tv_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(mdp_tv_clk.c),
 	},
 };
@@ -2758,7 +2664,6 @@ static struct branch_clk hdmi_tv_clk = {
 	.c = {
 		.dbg_name = "hdmi_tv_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(hdmi_tv_clk.c),
 	},
 };
@@ -2775,7 +2680,6 @@ static struct branch_clk hdmi_app_clk = {
 	.c = {
 		.dbg_name = "hdmi_app_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(hdmi_app_clk.c),
 	},
 };
@@ -2824,7 +2728,6 @@ static struct rcg_clk vcodec_clk = {
 	.c = {
 		.dbg_name = "vcodec_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vcodec_clk.c),
 	},
 };
@@ -2868,7 +2771,6 @@ static struct rcg_clk vpe_clk = {
 	.c = {
 		.dbg_name = "vpe_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vpe_clk.c),
 	},
 };
@@ -2925,7 +2827,6 @@ static struct rcg_clk vfe_clk = {
 	.c = {
 		.dbg_name = "vfe_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(vfe_clk.c),
 	},
 };
@@ -2943,7 +2844,6 @@ static struct branch_clk csi0_vfe_clk = {
 	.c = {
 		.dbg_name = "csi0_vfe_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi0_vfe_clk.c),
 	},
 };
@@ -2961,7 +2861,6 @@ static struct branch_clk csi1_vfe_clk = {
 	.c = {
 		.dbg_name = "csi1_vfe_clk",
 		.ops = &clk_ops_branch,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(csi1_vfe_clk.c),
 	},
 };
@@ -3014,7 +2913,6 @@ static struct clk_freq_tbl clk_tbl_aif_osr[] = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8x60, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -3049,7 +2947,6 @@ static struct clk_freq_tbl clk_tbl_aif_bit[] = {
 		.c = { \
 			.dbg_name = #i "_clk", \
 			.ops = &soc_clk_ops_8x60, \
-			.flags = CLKFLAG_AUTO_OFF, \
 			CLK_INIT(i##_clk.c), \
 		}, \
 	}
@@ -3123,7 +3020,6 @@ static struct rcg_clk pcm_clk = {
 	.c = {
 		.dbg_name = "pcm_clk",
 		.ops = &soc_clk_ops_8x60,
-		.flags = CLKFLAG_AUTO_OFF,
 		CLK_INIT(pcm_clk.c),
 	},
 };
diff --git a/arch/arm/mach-msm/clock-pcom-lookup.c b/arch/arm/mach-msm/clock-pcom-lookup.c
new file mode 100644
index 0000000..22f8145
--- /dev/null
+++ b/arch/arm/mach-msm/clock-pcom-lookup.c
@@ -0,0 +1,381 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "clock.h"
+#include "clock-pcom.h"
+#include "clock-voter.h"
+
+static DEFINE_CLK_PCOM(adm_clk,		ADM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(adsp_clk,	ADSP_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(ahb_m_clk,	AHB_M_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(ahb_s_clk,	AHB_S_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(cam_m_clk,	CAM_M_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(axi_rotator_clk,	AXI_ROTATOR_CLK, 0);
+static DEFINE_CLK_PCOM(ce_clk,		CE_CLK,		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(csi0_clk,	CSI0_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(csi0_p_clk,	CSI0_P_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(csi0_vfe_clk,	CSI0_VFE_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(csi1_clk,	CSI1_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(csi1_p_clk,	CSI1_P_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(csi1_vfe_clk,	CSI1_VFE_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+
+static struct pcom_clk dsi_byte_clk = {
+	.id = P_DSI_BYTE_CLK,
+	.c = {
+		.ops = &clk_ops_pcom_ext_config,
+		.dbg_name = "dsi_byte_clk",
+		CLK_INIT(dsi_byte_clk.c),
+	},
+};
+
+static struct pcom_clk dsi_clk = {
+	.id = P_DSI_CLK,
+	.c = {
+		.ops = &clk_ops_pcom_ext_config,
+		.dbg_name = "dsi_clk",
+		CLK_INIT(dsi_clk.c),
+	},
+};
+
+static struct pcom_clk dsi_esc_clk = {
+	.id = P_DSI_ESC_CLK,
+	.c = {
+		.ops = &clk_ops_pcom_ext_config,
+		.dbg_name = "dsi_esc_clk",
+		CLK_INIT(dsi_esc_clk.c),
+	},
+};
+
+static struct pcom_clk dsi_pixel_clk = {
+	.id = P_DSI_PIXEL_CLK,
+	.c = {
+		.ops = &clk_ops_pcom_ext_config,
+		.dbg_name = "dsi_pixel_clk",
+		CLK_INIT(dsi_pixel_clk.c),
+	},
+};
+
+static DEFINE_CLK_PCOM(dsi_ref_clk,	DSI_REF_CLK,	0);
+static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,
+		CLKFLAG_SKIP_AUTO_OFF | CLK_MIN);
+static DEFINE_CLK_PCOM(ebi2_clk,	EBI2_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	CLK_MINMAX);
+static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(grp_2d_clk,	GRP_2D_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(grp_2d_p_clk,	GRP_2D_P_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(grp_3d_clk,	GRP_3D_CLK,	0);
+static DEFINE_CLK_PCOM(grp_3d_p_clk,	GRP_3D_P_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(gsbi1_qup_clk,	GSBI1_QUP_CLK,	0);
+static DEFINE_CLK_PCOM(gsbi1_qup_p_clk,	GSBI1_QUP_P_CLK, 0);
+static DEFINE_CLK_PCOM(gsbi2_qup_clk,	GSBI2_QUP_CLK,	0);
+static DEFINE_CLK_PCOM(gsbi2_qup_p_clk,	GSBI2_QUP_P_CLK, 0);
+static DEFINE_CLK_PCOM(gsbi_clk,	GSBI_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(gsbi_p_clk,	GSBI_P_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(hdmi_clk,	HDMI_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(i2c_clk,		I2C_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(icodec_rx_clk,	ICODEC_RX_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(icodec_tx_clk,	ICODEC_TX_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(imem_clk,	IMEM_CLK,	0);
+static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,	0);
+static DEFINE_CLK_PCOM(mdp_lcdc_pad_pclk_clk, MDP_LCDC_PAD_PCLK_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(mdp_vsync_clk,	MDP_VSYNC_CLK,	0);
+static DEFINE_CLK_PCOM(mdp_dsi_p_clk,	MDP_DSI_P_CLK,	0);
+static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,
+		CLKFLAG_SKIP_AUTO_OFF | CLK_MIN);
+static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	CLK_MINMAX);
+static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,	0);
+static DEFINE_CLK_PCOM(sdc1_clk,	SDC1_CLK,	0);
+static DEFINE_CLK_PCOM(sdc1_p_clk,	SDC1_P_CLK,	0);
+static DEFINE_CLK_PCOM(sdc2_clk,	SDC2_CLK,	0);
+static DEFINE_CLK_PCOM(sdc2_p_clk,	SDC2_P_CLK,	0);
+static DEFINE_CLK_PCOM(sdc3_clk,	SDC3_CLK,	0);
+static DEFINE_CLK_PCOM(sdc3_p_clk,	SDC3_P_CLK,	0);
+static DEFINE_CLK_PCOM(sdc4_clk,	SDC4_CLK,	0);
+static DEFINE_CLK_PCOM(sdc4_p_clk,	SDC4_P_CLK,	0);
+static DEFINE_CLK_PCOM(spi_clk,		SPI_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tsif_clk,	TSIF_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tsif_p_clk,	TSIF_P_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tsif_ref_clk,	TSIF_REF_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tv_dac_clk,	TV_DAC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tv_enc_clk,	TV_ENC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(uart1_clk,	UART1_CLK,	0);
+static DEFINE_CLK_PCOM(uart1dm_clk,	UART1DM_CLK,	0);
+static DEFINE_CLK_PCOM(uart2_clk,	UART2_CLK,	0);
+static DEFINE_CLK_PCOM(uart2dm_clk,	UART2DM_CLK,	0);
+static DEFINE_CLK_PCOM(uart3_clk,	UART3_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs2_clk,	USB_HS2_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs2_p_clk,	USB_HS2_P_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs3_clk,	USB_HS3_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs3_p_clk,	USB_HS3_P_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs_clk,	USB_HS_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs_core_clk,	USB_HS_CORE_CLK, 0);
+static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,	0);
+static DEFINE_CLK_PCOM(usb_otg_clk,	USB_OTG_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(usb_phy_clk,	USB_PHY_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	CLK_MIN);
+static DEFINE_CLK_PCOM(vfe_axi_clk,	VFE_AXI_CLK,	0);
+static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,	0);
+static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,	0);
+
+static DEFINE_CLK_VOTER(ebi_acpu_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi_kgsl_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi_lcdc_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi_mddi_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi_tv_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi_usb_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi_vfe_clk,	&ebi1_clk.c);
+
+struct clk_lookup msm_clocks_7x01a[] = {
+	CLK_LOOKUP("adm_clk",		adm_clk.c,	NULL),
+	CLK_LOOKUP("adsp_clk",		adsp_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_clk.c,	NULL),
+	CLK_LOOKUP("ebi2_clk",		ebi2_clk.c,	NULL),
+	CLK_LOOKUP("ecodec_clk",	ecodec_clk.c,	NULL),
+	CLK_LOOKUP("emdh_clk",		emdh_clk.c,	NULL),
+	CLK_LOOKUP("gp_clk",		gp_clk.c,		NULL),
+	CLK_LOOKUP("grp_clk",		grp_3d_clk.c,	NULL),
+	CLK_LOOKUP("i2c_clk",		i2c_clk.c,	"msm_i2c.0"),
+	CLK_LOOKUP("icodec_rx_clk",	icodec_rx_clk.c,	NULL),
+	CLK_LOOKUP("icodec_tx_clk",	icodec_tx_clk.c,	NULL),
+	CLK_LOOKUP("imem_clk",		imem_clk.c,	NULL),
+	CLK_LOOKUP("mdc_clk",		mdc_clk.c,	NULL),
+	CLK_LOOKUP("mddi_clk",		pmdh_clk.c,	NULL),
+	CLK_LOOKUP("mdp_clk",		mdp_clk.c,	NULL),
+	CLK_LOOKUP("pbus_clk",		pbus_clk.c,	NULL),
+	CLK_LOOKUP("pcm_clk",		pcm_clk.c,	NULL),
+	CLK_LOOKUP("sdac_clk",		sdac_clk.c,	NULL),
+	CLK_LOOKUP("sdc_clk",		sdc1_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_pclk",		sdc1_p_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_clk",		sdc2_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_pclk",		sdc2_p_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_clk",		sdc3_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_pclk",		sdc3_p_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_clk",		sdc4_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("sdc_pclk",		sdc4_p_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("tsif_clk",		tsif_clk.c,	NULL),
+	CLK_LOOKUP("tsif_ref_clk",	tsif_ref_clk.c,	NULL),
+	CLK_LOOKUP("tv_dac_clk",	tv_dac_clk.c,	NULL),
+	CLK_LOOKUP("tv_enc_clk",	tv_enc_clk.c,	NULL),
+	CLK_LOOKUP("uart_clk",		uart1_clk.c,	"msm_serial.0"),
+	CLK_LOOKUP("uart_clk",		uart2_clk.c,	"msm_serial.1"),
+	CLK_LOOKUP("uart_clk",		uart3_clk.c,	"msm_serial.2"),
+	CLK_LOOKUP("uartdm_clk",	uart1dm_clk.c,	"msm_serial_hs.0"),
+	CLK_LOOKUP("uartdm_clk",	uart2dm_clk.c,	"msm_serial_hs.1"),
+	CLK_LOOKUP("usb_hs_clk",	usb_hs_clk.c,	"msm_otg"),
+	CLK_LOOKUP("usb_hs_pclk",	usb_hs_p_clk.c,	"msm_otg"),
+	CLK_LOOKUP("usb_otg_clk",	usb_otg_clk.c,	NULL),
+	CLK_LOOKUP("vdc_clk",		vdc_clk.c,	NULL),
+	CLK_LOOKUP("vfe_clk",		vfe_clk.c,	NULL),
+	CLK_LOOKUP("vfe_mdc_clk",	vfe_mdc_clk.c,	NULL),
+};
+unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a);
+
+struct clk_lookup msm_clocks_7x27[] = {
+	CLK_LOOKUP("adm_clk",		adm_clk.c,	NULL),
+	CLK_LOOKUP("adsp_clk",		adsp_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_clk.c,	NULL),
+	CLK_LOOKUP("ebi2_clk",		ebi2_clk.c,	NULL),
+	CLK_LOOKUP("ecodec_clk",	ecodec_clk.c,	NULL),
+	CLK_LOOKUP("gp_clk",		gp_clk.c,		NULL),
+	CLK_LOOKUP("grp_clk",		grp_3d_clk.c,	NULL),
+	CLK_LOOKUP("grp_pclk",		grp_3d_p_clk.c,	NULL),
+	CLK_LOOKUP("i2c_clk",		i2c_clk.c,	"msm_i2c.0"),
+	CLK_LOOKUP("icodec_rx_clk",	icodec_rx_clk.c,	NULL),
+	CLK_LOOKUP("icodec_tx_clk",	icodec_tx_clk.c,	NULL),
+	CLK_LOOKUP("imem_clk",		imem_clk.c,	NULL),
+	CLK_LOOKUP("mdc_clk",		mdc_clk.c,	NULL),
+	CLK_LOOKUP("mddi_clk",		pmdh_clk.c,	NULL),
+	CLK_LOOKUP("mdp_clk",		mdp_clk.c,	NULL),
+	CLK_LOOKUP("mdp_lcdc_pclk_clk", mdp_lcdc_pclk_clk.c, NULL),
+	CLK_LOOKUP("mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk.c, NULL),
+	CLK_LOOKUP("mdp_vsync_clk",	mdp_vsync_clk.c,  NULL),
+	CLK_LOOKUP("pbus_clk",		pbus_clk.c,	NULL),
+	CLK_LOOKUP("pcm_clk",		pcm_clk.c,	NULL),
+	CLK_LOOKUP("sdac_clk",		sdac_clk.c,	NULL),
+	CLK_LOOKUP("sdc_clk",		sdc1_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_pclk",		sdc1_p_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_clk",		sdc2_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_pclk",		sdc2_p_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_clk",		sdc3_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_pclk",		sdc3_p_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_clk",		sdc4_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("sdc_pclk",		sdc4_p_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("tsif_clk",		tsif_clk.c,	NULL),
+	CLK_LOOKUP("tsif_ref_clk",	tsif_ref_clk.c,	NULL),
+	CLK_LOOKUP("tsif_pclk",		tsif_p_clk.c,	NULL),
+	CLK_LOOKUP("uart_clk",		uart1_clk.c,	"msm_serial.0"),
+	CLK_LOOKUP("uart_clk",		uart2_clk.c,	"msm_serial.1"),
+	CLK_LOOKUP("uartdm_clk",	uart1dm_clk.c,	"msm_serial_hs.0"),
+	CLK_LOOKUP("uartdm_clk",	uart2dm_clk.c,	"msm_serial_hs.1"),
+	CLK_LOOKUP("usb_hs_clk",	usb_hs_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs_pclk",	usb_hs_p_clk.c,	NULL),
+	CLK_LOOKUP("usb_otg_clk",	usb_otg_clk.c,	NULL),
+	CLK_LOOKUP("usb_phy_clk",	usb_phy_clk.c,	NULL),
+	CLK_LOOKUP("vdc_clk",		vdc_clk.c,	NULL),
+	CLK_LOOKUP("vfe_clk",		vfe_clk.c,	NULL),
+	CLK_LOOKUP("vfe_mdc_clk",	vfe_mdc_clk.c,	NULL),
+
+	CLK_LOOKUP("ebi1_acpu_clk",	ebi_acpu_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_kgsl_clk",	ebi_kgsl_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_lcdc_clk",	ebi_lcdc_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_mddi_clk",	ebi_mddi_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_usb_clk",	ebi_usb_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_vfe_clk",	ebi_vfe_clk.c,	NULL),
+};
+unsigned msm_num_clocks_7x27 = ARRAY_SIZE(msm_clocks_7x27);
+
+struct clk_lookup msm_clocks_7x27a[] = {
+	CLK_LOOKUP("adm_clk",		adm_clk.c,	NULL),
+	CLK_LOOKUP("adsp_clk",		adsp_clk.c,	NULL),
+	CLK_LOOKUP("ahb_m_clk",		ahb_m_clk.c,	NULL),
+	CLK_LOOKUP("ahb_s_clk",		ahb_s_clk.c,	NULL),
+	CLK_LOOKUP("cam_m_clk",		cam_m_clk.c,	NULL),
+	CLK_LOOKUP("csi_clk",		csi0_clk.c,	NULL),
+	CLK_LOOKUP("csi_pclk",		csi0_p_clk.c,	NULL),
+	CLK_LOOKUP("csi_vfe_clk",	csi0_vfe_clk.c,	NULL),
+	CLK_LOOKUP("csi_clk",		csi1_clk.c,	NULL),
+	CLK_LOOKUP("csi_pclk",		csi1_p_clk.c,	NULL),
+	CLK_LOOKUP("csi_vfe_clk",	csi1_vfe_clk.c,	NULL),
+	CLK_LOOKUP("dsi_byte_clk",	dsi_byte_clk.c,	NULL),
+	CLK_LOOKUP("dsi_clk",		dsi_clk.c,	NULL),
+	CLK_LOOKUP("dsi_esc_clk",	dsi_esc_clk.c,	NULL),
+	CLK_LOOKUP("dsi_pixel_clk",	dsi_pixel_clk.c, NULL),
+	CLK_LOOKUP("dsi_ref_clk",	dsi_ref_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_clk.c,	NULL),
+	CLK_LOOKUP("ebi2_clk",		ebi2_clk.c,	NULL),
+	CLK_LOOKUP("ecodec_clk",	ecodec_clk.c,	NULL),
+	CLK_LOOKUP("gp_clk",		gp_clk.c,	NULL),
+	CLK_LOOKUP("grp_clk",		grp_3d_clk.c,	NULL),
+	CLK_LOOKUP("grp_pclk",		grp_3d_p_clk.c,	NULL),
+	CLK_LOOKUP("gsbi_qup_clk",	gsbi1_qup_clk.c, "qup_i2c.0"),
+	CLK_LOOKUP("gsbi_qup_clk",	gsbi2_qup_clk.c, "qup_i2c.1"),
+	CLK_LOOKUP("gsbi_qup_pclk",	gsbi1_qup_p_clk.c, "qup_i2c.0"),
+	CLK_LOOKUP("gsbi_qup_pclk",	gsbi2_qup_p_clk.c, "qup_i2c.1"),
+	CLK_LOOKUP("icodec_rx_clk",	icodec_rx_clk.c, NULL),
+	CLK_LOOKUP("icodec_tx_clk",	icodec_tx_clk.c, NULL),
+	CLK_LOOKUP("imem_clk",		imem_clk.c,	NULL),
+	CLK_LOOKUP("mddi_clk",		pmdh_clk.c,	NULL),
+	CLK_LOOKUP("mdp_clk",		mdp_clk.c,	NULL),
+	CLK_LOOKUP("mdp_lcdc_pclk_clk",	mdp_lcdc_pclk_clk.c, NULL),
+	CLK_LOOKUP("mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk.c, NULL),
+	CLK_LOOKUP("mdp_vsync_clk",	mdp_vsync_clk.c,	NULL),
+	CLK_LOOKUP("mdp_dsi_pclk",	mdp_dsi_p_clk.c,	NULL),
+	CLK_LOOKUP("pbus_clk",		pbus_clk.c,	NULL),
+	CLK_LOOKUP("pcm_clk",		pcm_clk.c,	NULL),
+	CLK_LOOKUP("sdac_clk",		sdac_clk.c,	NULL),
+	CLK_LOOKUP("sdc_clk",		sdc1_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_pclk",		sdc1_p_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_clk",		sdc2_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_pclk",		sdc2_p_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_clk",		sdc3_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_pclk",		sdc3_p_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_clk",		sdc4_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("sdc_pclk",		sdc4_p_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("tsif_ref_clk",	tsif_ref_clk.c,	NULL),
+	CLK_LOOKUP("tsif_pclk",		tsif_p_clk.c,	NULL),
+	CLK_LOOKUP("uart_clk",		uart1_clk.c,	"msm_serial.0"),
+	CLK_LOOKUP("uart_clk",		uart2_clk.c,	"msm_serial.1"),
+	CLK_LOOKUP("uartdm_clk",	uart1dm_clk.c,	"msm_serial_hs.0"),
+	CLK_LOOKUP("uartdm_clk",	uart2dm_clk.c,	"msm_serial_hsl.0"),
+	CLK_LOOKUP("usb_hs_core_clk",	usb_hs_core_clk.c, NULL),
+	CLK_LOOKUP("usb_hs2_clk",	usb_hs2_clk.c, NULL),
+	CLK_LOOKUP("usb_hs_clk",	usb_hs_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs_pclk",	usb_hs_p_clk.c,	NULL),
+	CLK_LOOKUP("usb_phy_clk",	usb_phy_clk.c,	NULL),
+	CLK_LOOKUP("vdc_clk",		vdc_clk.c,	NULL),
+	CLK_LOOKUP("vfe_clk",		vfe_clk.c,	NULL),
+	CLK_LOOKUP("vfe_mdc_clk",	vfe_mdc_clk.c,	NULL),
+
+	CLK_LOOKUP("ebi1_acpu_clk",	ebi_acpu_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_kgsl_clk",	ebi_kgsl_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_lcdc_clk",	ebi_lcdc_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_mddi_clk",	ebi_mddi_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_usb_clk",	ebi_usb_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_vfe_clk",	ebi_vfe_clk.c,	NULL),
+};
+unsigned msm_num_clocks_7x27a = ARRAY_SIZE(msm_clocks_7x27a);
+
+struct clk_lookup msm_clocks_8x50[] = {
+	CLK_LOOKUP("adm_clk",		adm_clk.c,	NULL),
+	CLK_LOOKUP("ce_clk",		ce_clk.c,		NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi1_clk.c,	NULL),
+	CLK_LOOKUP("ebi2_clk",		ebi2_clk.c,	NULL),
+	CLK_LOOKUP("ecodec_clk",	ecodec_clk.c,	NULL),
+	CLK_LOOKUP("emdh_clk",		emdh_clk.c,	NULL),
+	CLK_LOOKUP("gp_clk",		gp_clk.c,		NULL),
+	CLK_LOOKUP("grp_clk",		grp_3d_clk.c,	NULL),
+	CLK_LOOKUP("i2c_clk",		i2c_clk.c,	"msm_i2c.0"),
+	CLK_LOOKUP("icodec_rx_clk",	icodec_rx_clk.c,	NULL),
+	CLK_LOOKUP("icodec_tx_clk",	icodec_tx_clk.c,	NULL),
+	CLK_LOOKUP("imem_clk",		imem_clk.c,	NULL),
+	CLK_LOOKUP("mdc_clk",		mdc_clk.c,	NULL),
+	CLK_LOOKUP("mddi_clk",		pmdh_clk.c,	NULL),
+	CLK_LOOKUP("mdp_clk",		mdp_clk.c,	NULL),
+	CLK_LOOKUP("mdp_lcdc_pclk_clk", mdp_lcdc_pclk_clk.c, NULL),
+	CLK_LOOKUP("mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk.c, NULL),
+	CLK_LOOKUP("mdp_vsync_clk",	mdp_vsync_clk.c,	NULL),
+	CLK_LOOKUP("pbus_clk",		pbus_clk.c,	NULL),
+	CLK_LOOKUP("pcm_clk",		pcm_clk.c,	NULL),
+	CLK_LOOKUP("sdac_clk",		sdac_clk.c,	NULL),
+	CLK_LOOKUP("sdc_clk",		sdc1_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_pclk",		sdc1_p_clk.c,	"msm_sdcc.1"),
+	CLK_LOOKUP("sdc_clk",		sdc2_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_pclk",		sdc2_p_clk.c,	"msm_sdcc.2"),
+	CLK_LOOKUP("sdc_clk",		sdc3_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_pclk",		sdc3_p_clk.c,	"msm_sdcc.3"),
+	CLK_LOOKUP("sdc_clk",		sdc4_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("sdc_pclk",		sdc4_p_clk.c,	"msm_sdcc.4"),
+	CLK_LOOKUP("spi_clk",		spi_clk.c,	NULL),
+	CLK_DUMMY("spi_pclk",		SPI_P_CLK,	"spi_qsd.0", 0),
+	CLK_LOOKUP("tsif_clk",		tsif_clk.c,	NULL),
+	CLK_LOOKUP("tsif_ref_clk",	tsif_ref_clk.c,	NULL),
+	CLK_LOOKUP("tv_dac_clk",	tv_dac_clk.c,	NULL),
+	CLK_LOOKUP("tv_enc_clk",	tv_enc_clk.c,	NULL),
+	CLK_LOOKUP("uart_clk",		uart1_clk.c,	"msm_serial.0"),
+	CLK_LOOKUP("uart_clk",		uart2_clk.c,	"msm_serial.1"),
+	CLK_LOOKUP("uart_clk",		uart3_clk.c,	"msm_serial.2"),
+	CLK_LOOKUP("uartdm_clk",	uart1dm_clk.c,	"msm_serial_hs.0"),
+	CLK_LOOKUP("uartdm_clk",	uart2dm_clk.c,	"msm_serial_hs.1"),
+	CLK_LOOKUP("usb_hs_clk",	usb_hs_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs_pclk",	usb_hs_p_clk.c,	NULL),
+	CLK_LOOKUP("usb_otg_clk",	usb_otg_clk.c,	NULL),
+	CLK_LOOKUP("vdc_clk",		vdc_clk.c,	NULL),
+	CLK_LOOKUP("vfe_clk",		vfe_clk.c,	NULL),
+	CLK_LOOKUP("vfe_mdc_clk",	vfe_mdc_clk.c,	NULL),
+	CLK_LOOKUP("vfe_axi_clk",	vfe_axi_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs2_clk",	usb_hs2_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs2_pclk",	usb_hs2_p_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs3_clk",	usb_hs3_clk.c,	NULL),
+	CLK_LOOKUP("usb_hs3_pclk",	usb_hs3_p_clk.c,	NULL),
+	CLK_LOOKUP("usb_phy_clk",	usb_phy_clk.c,	NULL),
+
+	CLK_LOOKUP("ebi1_acpu_clk",	ebi_acpu_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_kgsl_clk",	ebi_kgsl_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_lcdc_clk",	ebi_lcdc_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_mddi_clk",	ebi_mddi_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_tv_clk",	ebi_tv_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_usb_clk",	ebi_usb_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_vfe_clk",	ebi_vfe_clk.c,	NULL),
+
+	CLK_LOOKUP("grp_pclk",		grp_3d_p_clk.c,	NULL),
+	CLK_LOOKUP("grp_2d_clk",	grp_2d_clk.c,	NULL),
+	CLK_LOOKUP("grp_2d_pclk",	grp_2d_p_clk.c,	NULL),
+	CLK_LOOKUP("qup_clk",		gsbi_clk.c,	"qup_i2c.4"),
+	CLK_LOOKUP("qup_pclk",		gsbi_p_clk.c,	"qup_i2c.4"),
+};
+unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
diff --git a/arch/arm/mach-msm/clock-voter.h b/arch/arm/mach-msm/clock-voter.h
index 170ba67..8370c11 100644
--- a/arch/arm/mach-msm/clock-voter.h
+++ b/arch/arm/mach-msm/clock-voter.h
@@ -34,6 +34,7 @@ static inline struct clk_voter *to_clk_voter(struct clk *clk)
 		.c = { \
 			.dbg_name = #clk_name, \
 			.ops = &clk_ops_voter, \
+			.flags = CLKFLAG_SKIP_AUTO_OFF, \
 			CLK_INIT(clk_name.c), \
 		}, \
 	}
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 2781ccf..7daadb1 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -201,9 +201,10 @@ void __init msm_clock_init(struct clk_lookup *clock_tbl, size_t num_clocks)
 	msm_num_clocks = num_clocks;
 }
 
-/* The bootloader and/or AMSS may have left various clocks enabled.
- * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have
- * not been explicitly enabled by a clk_enable() call.
+/*
+ * The bootloader and/or AMSS may have left various clocks enabled.
+ * Disable any clocks that have not been explicitly enabled by a
+ * clk_enable() call and don't have the CLKFLAG_SKIP_AUTO_OFF flag.
  */
 static int __init clock_late_init(void)
 {
@@ -215,9 +216,9 @@ static int __init clock_late_init(void)
 		struct clk *clk = msm_clocks[i].clk;
 
 		clock_debug_add(clk);
-		if (clk->flags & CLKFLAG_AUTO_OFF) {
+		if (!(clk->flags & CLKFLAG_SKIP_AUTO_OFF)) {
 			spin_lock_irqsave(&clk->lock, flags);
-			if (!clk->count) {
+			if (!clk->count && clk->ops->auto_off) {
 				count++;
 				clk->ops->auto_off(clk);
 			}
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 1d0c94b..09afadd 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -28,7 +28,7 @@
 #define CLKFLAG_NORESET			0x00000008
 
 #define CLK_FIRST_AVAILABLE_FLAG	0x00000100
-#define CLKFLAG_AUTO_OFF		0x00000200
+#define CLKFLAG_SKIP_AUTO_OFF			0x00000200
 #define CLKFLAG_MIN			0x00000400
 #define CLKFLAG_MAX			0x00000800
 
@@ -68,7 +68,6 @@ struct clk {
 	.children = LIST_HEAD_INIT((name).children), \
 	.siblings = LIST_HEAD_INIT((name).siblings)
 
-#define OFF CLKFLAG_AUTO_OFF
 #define CLK_MIN CLKFLAG_MIN
 #define CLK_MAX CLKFLAG_MAX
 #define CLK_MINMAX (CLK_MIN | CLK_MAX)
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 1cef1e2..a7764bd 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -394,47 +394,47 @@ struct platform_device msm_device_mdp = {
 	.resource = resources_mdp,
 };
 
-static DEFINE_CLK_PCOM(adm_clk,		ADM_CLK,	0);
-static DEFINE_CLK_PCOM(adsp_clk,	ADSP_CLK,	0);
-static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,	0);
-static DEFINE_CLK_PCOM(ebi2_clk,	EBI2_CLK,	0);
-static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,	0);
-static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	OFF);
-static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,		0);
-static DEFINE_CLK_PCOM(grp_3d_clk,	GRP_3D_CLK,	OFF);
-static DEFINE_CLK_PCOM(i2c_clk,		I2C_CLK,	0);
-static DEFINE_CLK_PCOM(icodec_rx_clk,	ICODEC_RX_CLK,	0);
-static DEFINE_CLK_PCOM(icodec_tx_clk,	ICODEC_TX_CLK,	0);
-static DEFINE_CLK_PCOM(imem_clk,	IMEM_CLK,	OFF);
-static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,	0);
-static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,	OFF);
-static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,	0);
-static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,	0);
-static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	OFF | CLK_MINMAX);
-static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc1_clk,	SDC1_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc1_p_clk,	SDC1_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc2_clk,	SDC2_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc2_p_clk,	SDC2_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc3_clk,	SDC3_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc3_p_clk,	SDC3_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc4_clk,	SDC4_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc4_p_clk,	SDC4_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(tsif_clk,	TSIF_CLK,	0);
-static DEFINE_CLK_PCOM(tsif_ref_clk,	TSIF_REF_CLK,	0);
-static DEFINE_CLK_PCOM(tv_dac_clk,	TV_DAC_CLK,	0);
-static DEFINE_CLK_PCOM(tv_enc_clk,	TV_ENC_CLK,	0);
-static DEFINE_CLK_PCOM(uart1_clk,	UART1_CLK,	OFF);
-static DEFINE_CLK_PCOM(uart2_clk,	UART2_CLK,	0);
-static DEFINE_CLK_PCOM(uart3_clk,	UART3_CLK,	OFF);
-static DEFINE_CLK_PCOM(uart1dm_clk,	UART1DM_CLK,	OFF);
-static DEFINE_CLK_PCOM(uart2dm_clk,	UART2DM_CLK,	0);
-static DEFINE_CLK_PCOM(usb_hs_clk,	USB_HS_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_otg_clk,	USB_OTG_CLK,	0);
-static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	OFF);
-static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,	OFF);
-static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,	OFF);
+static DEFINE_CLK_PCOM(adm_clk,		ADM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(adsp_clk,	ADSP_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(ebi2_clk,	EBI2_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	0);
+static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(grp_3d_clk,	GRP_3D_CLK,	0);
+static DEFINE_CLK_PCOM(i2c_clk,		I2C_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(icodec_rx_clk,	ICODEC_RX_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(icodec_tx_clk,	ICODEC_TX_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(imem_clk,	IMEM_CLK,	0);
+static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,	0);
+static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	CLK_MINMAX);
+static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,	0);
+static DEFINE_CLK_PCOM(sdc1_clk,	SDC1_CLK,	0);
+static DEFINE_CLK_PCOM(sdc1_p_clk,	SDC1_P_CLK,	0);
+static DEFINE_CLK_PCOM(sdc2_clk,	SDC2_CLK,	0);
+static DEFINE_CLK_PCOM(sdc2_p_clk,	SDC2_P_CLK,	0);
+static DEFINE_CLK_PCOM(sdc3_clk,	SDC3_CLK,	0);
+static DEFINE_CLK_PCOM(sdc3_p_clk,	SDC3_P_CLK,	0);
+static DEFINE_CLK_PCOM(sdc4_clk,	SDC4_CLK,	0);
+static DEFINE_CLK_PCOM(sdc4_p_clk,	SDC4_P_CLK,	0);
+static DEFINE_CLK_PCOM(tsif_clk,	TSIF_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tsif_ref_clk,	TSIF_REF_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tv_dac_clk,	TV_DAC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tv_enc_clk,	TV_ENC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(uart1_clk,	UART1_CLK,	0);
+static DEFINE_CLK_PCOM(uart2_clk,	UART2_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(uart3_clk,	UART3_CLK,	0);
+static DEFINE_CLK_PCOM(uart1dm_clk,	UART1DM_CLK,	0);
+static DEFINE_CLK_PCOM(uart2dm_clk,	UART2DM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(usb_hs_clk,	USB_HS_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,	0);
+static DEFINE_CLK_PCOM(usb_otg_clk,	USB_OTG_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	0);
+static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,	0);
+static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,	0);
 
 struct clk_lookup msm_clocks_7x01a[] = {
 	CLK_LOOKUP("adm_clk",		adm_clk.c,	"msm_dmov"),
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 21a1f3a..f4e65f0 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -292,57 +292,59 @@ int __init msm_add_sdcc(unsigned int controller,
 	return platform_device_register(pdev);
 }
 
-static DEFINE_CLK_PCOM(adm_clk,		ADM_CLK,	0);
-static DEFINE_CLK_PCOM(ce_clk,		CE_CLK,		0);
+static DEFINE_CLK_PCOM(adm_clk,		ADM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(ce_clk,		CE_CLK,		CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,	CLK_MIN);
-static DEFINE_CLK_PCOM(ebi2_clk,	EBI2_CLK,	0);
-static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,	0);
-static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	OFF | CLK_MINMAX);
-static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,		0);
-static DEFINE_CLK_PCOM(grp_3d_clk,	GRP_3D_CLK,	0);
-static DEFINE_CLK_PCOM(i2c_clk,		I2C_CLK,	0);
-static DEFINE_CLK_PCOM(icodec_rx_clk,	ICODEC_RX_CLK,	0);
-static DEFINE_CLK_PCOM(icodec_tx_clk,	ICODEC_TX_CLK,	0);
-static DEFINE_CLK_PCOM(imem_clk,	IMEM_CLK,	OFF);
-static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,	0);
-static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	OFF | CLK_MINMAX);
-static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,	OFF);
-static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk,	MDP_LCDC_PCLK_CLK, 0);
-static DEFINE_CLK_PCOM(mdp_lcdc_pad_pclk_clk,	MDP_LCDC_PAD_PCLK_CLK, 0);
-static DEFINE_CLK_PCOM(mdp_vsync_clk,	MDP_VSYNC_CLK,	0);
+static DEFINE_CLK_PCOM(ebi2_clk,	EBI2_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	CLK_MINMAX);
+static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(grp_3d_clk,	GRP_3D_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(i2c_clk,		I2C_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(icodec_rx_clk,	ICODEC_RX_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(icodec_tx_clk,	ICODEC_TX_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(imem_clk,	IMEM_CLK,	0);
+static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	CLK_MINMAX);
+static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,	0);
+static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk,	MDP_LCDC_PCLK_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(mdp_lcdc_pad_pclk_clk,	MDP_LCDC_PAD_PCLK_CLK,
+		CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(mdp_vsync_clk,	MDP_VSYNC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,	CLK_MIN);
-static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,	0);
-static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc1_clk,	SDC1_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc1_p_clk,	SDC1_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc2_clk,	SDC2_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc2_p_clk,	SDC2_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc3_clk,	SDC3_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc3_p_clk,	SDC3_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc4_clk,	SDC4_CLK,	OFF);
-static DEFINE_CLK_PCOM(sdc4_p_clk,	SDC4_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(spi_clk,		SPI_CLK,	0);
-static DEFINE_CLK_PCOM(tsif_clk,	TSIF_CLK,	0);
-static DEFINE_CLK_PCOM(tsif_ref_clk,	TSIF_REF_CLK,	0);
-static DEFINE_CLK_PCOM(tv_dac_clk,	TV_DAC_CLK,	0);
-static DEFINE_CLK_PCOM(tv_enc_clk,	TV_ENC_CLK,	0);
-static DEFINE_CLK_PCOM(uart1_clk,	UART1_CLK,	OFF);
-static DEFINE_CLK_PCOM(uart2_clk,	UART2_CLK,	0);
-static DEFINE_CLK_PCOM(uart3_clk,	UART3_CLK,	OFF);
-static DEFINE_CLK_PCOM(uart1dm_clk,	UART1DM_CLK,	OFF);
-static DEFINE_CLK_PCOM(uart2dm_clk,	UART2DM_CLK,	0);
-static DEFINE_CLK_PCOM(usb_hs_clk,	USB_HS_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_otg_clk,	USB_OTG_CLK,	0);
-static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	OFF | CLK_MIN);
-static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,	OFF);
-static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,	OFF);
-static DEFINE_CLK_PCOM(vfe_axi_clk,	VFE_AXI_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_hs2_clk,	USB_HS2_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_hs2_p_clk,	USB_HS2_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_hs3_clk,	USB_HS3_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_hs3_p_clk,	USB_HS3_P_CLK,	OFF);
-static DEFINE_CLK_PCOM(usb_phy_clk,	USB_PHY_CLK,	0);
+static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,	0);
+static DEFINE_CLK_PCOM(sdc1_clk,	SDC1_CLK,	0);
+static DEFINE_CLK_PCOM(sdc1_p_clk,	SDC1_P_CLK,	0);
+static DEFINE_CLK_PCOM(sdc2_clk,	SDC2_CLK,	0);
+static DEFINE_CLK_PCOM(sdc2_p_clk,	SDC2_P_CLK,	0);
+static DEFINE_CLK_PCOM(sdc3_clk,	SDC3_CLK,	0);
+static DEFINE_CLK_PCOM(sdc3_p_clk,	SDC3_P_CLK,	0);
+static DEFINE_CLK_PCOM(sdc4_clk,	SDC4_CLK,	0);
+static DEFINE_CLK_PCOM(sdc4_p_clk,	SDC4_P_CLK,	0);
+static DEFINE_CLK_PCOM(spi_clk,		SPI_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tsif_clk,	TSIF_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tsif_ref_clk,	TSIF_REF_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tv_dac_clk,	TV_DAC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(tv_enc_clk,	TV_ENC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(uart1_clk,	UART1_CLK,	0);
+static DEFINE_CLK_PCOM(uart2_clk,	UART2_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(uart3_clk,	UART3_CLK,	0);
+static DEFINE_CLK_PCOM(uart1dm_clk,	UART1DM_CLK,	0);
+static DEFINE_CLK_PCOM(uart2dm_clk,	UART2DM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(usb_hs_clk,	USB_HS_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,	0);
+static DEFINE_CLK_PCOM(usb_otg_clk,	USB_OTG_CLK,	CLKFLAG_SKIP_AUTO_OFF);
+static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	CLK_MIN);
+static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,	0);
+static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,	0);
+static DEFINE_CLK_PCOM(vfe_axi_clk,	VFE_AXI_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs2_clk,	USB_HS2_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs2_p_clk,	USB_HS2_P_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs3_clk,	USB_HS3_CLK,	0);
+static DEFINE_CLK_PCOM(usb_hs3_p_clk,	USB_HS3_P_CLK,	0);
+static DEFINE_CLK_PCOM(usb_phy_clk,	USB_PHY_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 
 static DEFINE_CLK_VOTER(ebi1_acpu_clk,	&ebi1_clk.c);
 static DEFINE_CLK_VOTER(ebi1_kgsl_clk,	&ebi1_clk.c);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 29/34] msm: clock: Expand CLK_MIN, CLK_MAX and CLK_MINMAX macros

[David Brown]

From: Matt Wagantall <mattw@codeaurora.org>

These were just defined to be the same as CLKFLAG_MIN,
CLKFLAG_MAX and (CLKFLAG_MIN | CLKFLAG_MAX). Expand them
to avoid the unnecessary level of redirection.

Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-7x30.c        |    4 ++--
 arch/arm/mach-msm/clock-debug.c       |    6 +++---
 arch/arm/mach-msm/clock-pcom-lookup.c |   10 +++++-----
 arch/arm/mach-msm/clock.h             |    7 ++-----
 arch/arm/mach-msm/devices-msm7x00.c   |    2 +-
 arch/arm/mach-msm/devices-qsd8x50.c   |   12 +++++++-----
 6 files changed, 20 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index ce0e73c..d917942 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -2265,11 +2265,11 @@ static struct branch_clk lpa_core_clk = {
 
 static DEFINE_CLK_PCOM(adsp_clk, ADSP_CLK, CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(codec_ssbi_clk,	CODEC_SSBI_CLK, CLKFLAG_SKIP_AUTO_OFF);
-static DEFINE_CLK_PCOM(ebi1_clk, EBI1_CLK, CLK_MIN);
+static DEFINE_CLK_PCOM(ebi1_clk, EBI1_CLK, CLKFLAG_SKIP_AUTO_OFF | CLKFLAG_MIN);
 static DEFINE_CLK_PCOM(ecodec_clk, ECODEC_CLK, CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(gp_clk, GP_CLK, CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(uart3_clk, UART3_CLK, 0);
-static DEFINE_CLK_PCOM(usb_phy_clk, USB_PHY_CLK, CLK_MIN);
+static DEFINE_CLK_PCOM(usb_phy_clk, USB_PHY_CLK, CLKFLAG_MIN);
 
 static DEFINE_CLK_PCOM(p_grp_2d_clk, GRP_2D_CLK, CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(p_grp_2d_p_clk, GRP_2D_P_CLK, CLKFLAG_SKIP_AUTO_OFF);
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index 1a08a9a..d5d4091 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -28,15 +28,15 @@ static int clock_debug_rate_set(void *data, u64 val)
 
 	/* Only increases to max rate will succeed, but that's actually good
 	 * for debugging purposes so we don't check for error. */
-	if (clock->flags & CLK_MAX)
+	if (clock->flags & CLKFLAG_MAX)
 		clk_set_max_rate(clock, val);
-	if (clock->flags & CLK_MIN)
+	if (clock->flags & CLKFLAG_MIN)
 		ret = clk_set_min_rate(clock, val);
 	else
 		ret = clk_set_rate(clock, val);
 	if (ret != 0)
 		printk(KERN_ERR "clk_set%s_rate failed (%d)\n",
-			(clock->flags & CLK_MIN) ? "_min" : "", ret);
+			(clock->flags & CLKFLAG_MIN) ? "_min" : "", ret);
 	return ret;
 }
 
diff --git a/arch/arm/mach-msm/clock-pcom-lookup.c b/arch/arm/mach-msm/clock-pcom-lookup.c
index 22f8145..9d83cba 100644
--- a/arch/arm/mach-msm/clock-pcom-lookup.c
+++ b/arch/arm/mach-msm/clock-pcom-lookup.c
@@ -66,10 +66,10 @@ static struct pcom_clk dsi_pixel_clk = {
 
 static DEFINE_CLK_PCOM(dsi_ref_clk,	DSI_REF_CLK,	0);
 static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,
-		CLKFLAG_SKIP_AUTO_OFF | CLK_MIN);
+		CLKFLAG_SKIP_AUTO_OFF | CLKFLAG_MIN);
 static DEFINE_CLK_PCOM(ebi2_clk,	EBI2_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
-static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	CLK_MINMAX);
+static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,   CLKFLAG_MIN | CLKFLAG_MAX);
 static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,		CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(grp_2d_clk,	GRP_2D_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(grp_2d_p_clk,	GRP_2D_P_CLK,	CLKFLAG_SKIP_AUTO_OFF);
@@ -95,9 +95,9 @@ static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK,
 static DEFINE_CLK_PCOM(mdp_vsync_clk,	MDP_VSYNC_CLK,	0);
 static DEFINE_CLK_PCOM(mdp_dsi_p_clk,	MDP_DSI_P_CLK,	0);
 static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,
-		CLKFLAG_SKIP_AUTO_OFF | CLK_MIN);
+		CLKFLAG_SKIP_AUTO_OFF | CLKFLAG_MIN);
 static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
-static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	CLK_MINMAX);
+static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,   CLKFLAG_MIN | CLKFLAG_MAX);
 static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,	0);
 static DEFINE_CLK_PCOM(sdc1_clk,	SDC1_CLK,	0);
 static DEFINE_CLK_PCOM(sdc1_p_clk,	SDC1_P_CLK,	0);
@@ -127,7 +127,7 @@ static DEFINE_CLK_PCOM(usb_hs_core_clk,	USB_HS_CORE_CLK, 0);
 static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,	0);
 static DEFINE_CLK_PCOM(usb_otg_clk,	USB_OTG_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(usb_phy_clk,	USB_PHY_CLK,	CLKFLAG_SKIP_AUTO_OFF);
-static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	CLK_MIN);
+static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	CLKFLAG_MIN);
 static DEFINE_CLK_PCOM(vfe_axi_clk,	VFE_AXI_CLK,	0);
 static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,	0);
 static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,	0);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 09afadd..a873a19 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -68,11 +68,8 @@ struct clk {
 	.children = LIST_HEAD_INIT((name).children), \
 	.siblings = LIST_HEAD_INIT((name).siblings)
 
-#define CLK_MIN CLKFLAG_MIN
-#define CLK_MAX CLKFLAG_MAX
-#define CLK_MINMAX (CLK_MIN | CLK_MAX)
-
-#if defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
+#if defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
+defined(CONFIG_ARCH_MSM8960)
 void __init msm_clk_soc_init(void);
 #else
 static inline void __init msm_clk_soc_init(void) { }
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index a7764bd..b4658e2 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -410,7 +410,7 @@ static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,	0);
 static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
-static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	CLK_MINMAX);
+static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK, CLKFLAG_MIN | CLKFLAG_MAX);
 static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,	0);
 static DEFINE_CLK_PCOM(sdc1_clk,	SDC1_CLK,	0);
 static DEFINE_CLK_PCOM(sdc1_p_clk,	SDC1_P_CLK,	0);
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index f4e65f0..ab15e69 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -294,10 +294,11 @@ int __init msm_add_sdcc(unsigned int controller,
 
 static DEFINE_CLK_PCOM(adm_clk,		ADM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(ce_clk,		CE_CLK,		CLKFLAG_SKIP_AUTO_OFF);
-static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,	CLK_MIN);
+static DEFINE_CLK_PCOM(ebi1_clk,	EBI1_CLK,	CLKFLAG_MIN);
 static DEFINE_CLK_PCOM(ebi2_clk,	EBI2_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(ecodec_clk,	ECODEC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
-static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	CLK_MINMAX);
+static DEFINE_CLK_PCOM(emdh_clk,	EMDH_CLK,	CLKFLAG_MIN |
+							CLKFLAG_MAX);
 static DEFINE_CLK_PCOM(gp_clk,		GP_CLK,		CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(grp_3d_clk,	GRP_3D_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(i2c_clk,		I2C_CLK,	CLKFLAG_SKIP_AUTO_OFF);
@@ -305,14 +306,15 @@ static DEFINE_CLK_PCOM(icodec_rx_clk,	ICODEC_RX_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(icodec_tx_clk,	ICODEC_TX_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(imem_clk,	IMEM_CLK,	0);
 static DEFINE_CLK_PCOM(mdc_clk,		MDC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
-static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	CLK_MINMAX);
+static DEFINE_CLK_PCOM(pmdh_clk,	PMDH_CLK,	CLKFLAG_MIN |
+							CLKFLAG_MAX);
 static DEFINE_CLK_PCOM(mdp_clk,		MDP_CLK,	0);
 static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk,	MDP_LCDC_PCLK_CLK,
 		CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(mdp_lcdc_pad_pclk_clk,	MDP_LCDC_PAD_PCLK_CLK,
 		CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(mdp_vsync_clk,	MDP_VSYNC_CLK,	CLKFLAG_SKIP_AUTO_OFF);
-static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,	CLK_MIN);
+static DEFINE_CLK_PCOM(pbus_clk,	PBUS_CLK,	CLKFLAG_MIN);
 static DEFINE_CLK_PCOM(pcm_clk,		PCM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(sdac_clk,	SDAC_CLK,	0);
 static DEFINE_CLK_PCOM(sdc1_clk,	SDC1_CLK,	0);
@@ -336,7 +338,7 @@ static DEFINE_CLK_PCOM(uart2dm_clk,	UART2DM_CLK,	CLKFLAG_SKIP_AUTO_OFF);
 static DEFINE_CLK_PCOM(usb_hs_clk,	USB_HS_CLK,	0);
 static DEFINE_CLK_PCOM(usb_hs_p_clk,	USB_HS_P_CLK,	0);
 static DEFINE_CLK_PCOM(usb_otg_clk,	USB_OTG_CLK,	CLKFLAG_SKIP_AUTO_OFF);
-static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	CLK_MIN);
+static DEFINE_CLK_PCOM(vdc_clk,		VDC_CLK,	CLKFLAG_MIN);
 static DEFINE_CLK_PCOM(vfe_clk,		VFE_CLK,	0);
 static DEFINE_CLK_PCOM(vfe_mdc_clk,	VFE_MDC_CLK,	0);
 static DEFINE_CLK_PCOM(vfe_axi_clk,	VFE_AXI_CLK,	0);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 30/34] msm: clock: Add EBI1 voter clocks for ADM on SoCs without them

[David Brown]

From: Matt Wagantall <mattw@codeaurora.org>

The ADM driver wishes to vote for EBI1 clock rates during ADM
transfers.  Add voter clocks for this purpose.

On msm8960, this also requires the creation of an EBI voter clock
for the msm_bus driver, since it was previously using the clock
directly.

Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-7x30.c        |    2 ++
 arch/arm/mach-msm/clock-pcom-lookup.c |    4 ++++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index d917942..019fdea 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -2373,6 +2373,7 @@ static DEFINE_CLK_VOTER(ebi_mddi_clk, &pbus_clk.c);
 static DEFINE_CLK_VOTER(ebi_tv_clk, &pbus_clk.c);
 static DEFINE_CLK_VOTER(ebi_vcd_clk, &pbus_clk.c);
 static DEFINE_CLK_VOTER(ebi_vfe_clk, &pbus_clk.c);
+static DEFINE_CLK_VOTER(ebi_adm_clk, &pbus_clk.c);
 
 /*
  * SoC-specific functions required by clock-local driver
@@ -2757,6 +2758,7 @@ static struct clk_local_ownership {
 	{ CLK_LOOKUP("ebi1_tv_clk",	ebi_tv_clk.c,	NULL) },
 	{ CLK_LOOKUP("ebi1_vcd_clk",	ebi_vcd_clk.c,	NULL) },
 	{ CLK_LOOKUP("ebi1_vfe_clk",	ebi_vfe_clk.c,	NULL) },
+	{ CLK_LOOKUP("ebi1_clk",	ebi_adm_clk.c,	"msm_dmov") },
 
 	/*
 	 * This is a many-to-one mapping because we don't know how the remote
diff --git a/arch/arm/mach-msm/clock-pcom-lookup.c b/arch/arm/mach-msm/clock-pcom-lookup.c
index 9d83cba..e74a556 100644
--- a/arch/arm/mach-msm/clock-pcom-lookup.c
+++ b/arch/arm/mach-msm/clock-pcom-lookup.c
@@ -139,6 +139,7 @@ static DEFINE_CLK_VOTER(ebi_mddi_clk,	&ebi1_clk.c);
 static DEFINE_CLK_VOTER(ebi_tv_clk,	&ebi1_clk.c);
 static DEFINE_CLK_VOTER(ebi_usb_clk,	&ebi1_clk.c);
 static DEFINE_CLK_VOTER(ebi_vfe_clk,	&ebi1_clk.c);
+static DEFINE_CLK_VOTER(ebi_adm_clk,	&ebi1_clk.c);
 
 struct clk_lookup msm_clocks_7x01a[] = {
 	CLK_LOOKUP("adm_clk",		adm_clk.c,	NULL),
@@ -236,6 +237,7 @@ struct clk_lookup msm_clocks_7x27[] = {
 	CLK_LOOKUP("ebi1_mddi_clk",	ebi_mddi_clk.c,	NULL),
 	CLK_LOOKUP("ebi1_usb_clk",	ebi_usb_clk.c,	NULL),
 	CLK_LOOKUP("ebi1_vfe_clk",	ebi_vfe_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi_adm_clk.c,	"msm_dmov"),
 };
 unsigned msm_num_clocks_7x27 = ARRAY_SIZE(msm_clocks_7x27);
 
@@ -307,6 +309,7 @@ struct clk_lookup msm_clocks_7x27a[] = {
 	CLK_LOOKUP("ebi1_mddi_clk",	ebi_mddi_clk.c,	NULL),
 	CLK_LOOKUP("ebi1_usb_clk",	ebi_usb_clk.c,	NULL),
 	CLK_LOOKUP("ebi1_vfe_clk",	ebi_vfe_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi_adm_clk.c,	"msm_dmov"),
 };
 unsigned msm_num_clocks_7x27a = ARRAY_SIZE(msm_clocks_7x27a);
 
@@ -371,6 +374,7 @@ struct clk_lookup msm_clocks_8x50[] = {
 	CLK_LOOKUP("ebi1_tv_clk",	ebi_tv_clk.c,	NULL),
 	CLK_LOOKUP("ebi1_usb_clk",	ebi_usb_clk.c,	NULL),
 	CLK_LOOKUP("ebi1_vfe_clk",	ebi_vfe_clk.c,	NULL),
+	CLK_LOOKUP("ebi1_clk",		ebi_adm_clk.c,	"msm_dmov"),
 
 	CLK_LOOKUP("grp_pclk",		grp_3d_p_clk.c,	NULL),
 	CLK_LOOKUP("grp_2d_clk",	grp_2d_clk.c,	NULL),
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 31/34] msm: clock: Remove msm_clk_soc_init()

[David Brown]

From: Stephen Boyd <sboyd@codeaurora.org>

Every board file calls msm_clock_init() to initialize the clocks
and msm_clock_init() in turn calls msm_clk_soc_init() to do any
SoC specific initialization. Invert the call order so that boards
that require SoC specific initialization call the SoC specific
function first which then calls the generic msm_clock_init().

This removes one more obstacle in the path of multi-arch kernels
in mach-msm.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/board-msm7x30.c      |    2 +-
 arch/arm/mach-msm/board-msm8960.c      |    2 +-
 arch/arm/mach-msm/board-msm8x60.c      |    2 +-
 arch/arm/mach-msm/clock-7x30.c         |    7 ++++---
 arch/arm/mach-msm/clock-8960.c         |    9 ++++-----
 arch/arm/mach-msm/clock-8x60.c         |    7 ++++---
 arch/arm/mach-msm/clock.c              |    3 ---
 arch/arm/mach-msm/clock.h              |   11 +++++------
 arch/arm/mach-msm/devices.h            |   10 +---------
 arch/arm/mach-msm/include/mach/board.h |    2 --
 10 files changed, 21 insertions(+), 34 deletions(-)

diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 71de506..c4fdace40 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -117,7 +117,7 @@ static void __init msm7x30_init(void)
 static void __init msm7x30_map_io(void)
 {
 	msm_map_msm7x30_io();
-	msm_clock_init(msm_clocks_7x30, msm_num_clocks_7x30);
+	msm7x30_clock_init();
 }
 
 MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 28eb287..a363a16 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -55,7 +55,7 @@ static void __init msm8960_map_io(void)
 
 static void __init msm8960_init_early(void)
 {
-	msm_clock_init(msm_clocks_8960, msm_num_clocks_8960);
+	msm8960_clock_init();
 }
 
 static void __init msm8960_init_irq(void)
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index f034bf5..fce150e 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -55,7 +55,7 @@ static void __init msm8x60_map_io(void)
 
 static void __init msm8x60_init_early(void)
 {
-	msm_clock_init(msm_clocks_8x60, msm_num_clocks_8x60);
+	msm8660_clock_init();
 }
 
 static void __init msm8x60_init_irq(void)
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index 019fdea..de303b4 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -2862,8 +2862,7 @@ static struct clk_local_ownership {
 		O(GLBL), BIT(8) },
 };
 
-struct clk_lookup msm_clocks_7x30[ARRAY_SIZE(ownership_map)];
-unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);
+static struct clk_lookup msm_clocks_7x30[ARRAY_SIZE(ownership_map)];
 
 static void __init set_clock_ownership(void)
 {
@@ -2927,7 +2926,7 @@ static const struct reg_init {
 };
 
 /* Local clock driver initialization. */
-void __init msm_clk_soc_init(void)
+void __init msm7x30_clock_init(void)
 {
 	int i;
 	u32 val;
@@ -2965,6 +2964,8 @@ void __init msm_clk_soc_init(void)
 	clk_set_rate(&lpa_codec_clk.c, 1);
 	/* Sync the GRP2D clock to AXI */
 	clk_set_rate(&grp_2d_clk.c, 1);
+
+	msm_clock_init(msm_clocks_7x30, ARRAY_SIZE(msm_clocks_7x30));
 }
 
 /*
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index d885644..4590e7a 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -3578,7 +3578,7 @@ static struct clk measure_clk = {
 	CLK_INIT(measure_clk),
 };
 
-struct clk_lookup msm_clocks_8960[] = {
+static struct clk_lookup msm_clocks_8960[] = {
 	CLK_LOOKUP("cxo",		cxo_clk.c,		NULL),
 	CLK_LOOKUP("pll2",		pll2_clk.c,		NULL),
 	CLK_LOOKUP("pll8",		pll8_clk.c,		NULL),
@@ -3752,8 +3752,6 @@ struct clk_lookup msm_clocks_8960[] = {
 	CLK_LOOKUP("iommu_clk",		gfx2d1_clk.c,		"msm_iommu.11"),
 };
 
-unsigned msm_num_clocks_8960 = ARRAY_SIZE(msm_clocks_8960);
-
 /*
  * Miscellaneous clock register initializations
  */
@@ -3892,9 +3890,8 @@ static int wr_pll_clk_enable(struct clk *clk)
 	return 0;
 }
 
-
 /* Local clock driver initialization. */
-void __init msm_clk_soc_init(void)
+void __init msm8960_clock_init(void)
 {
 	soc_update_sys_vdd = msm8960_update_sys_vdd;
 	local_vote_sys_vdd(HIGH);
@@ -3922,6 +3919,8 @@ void __init msm_clk_soc_init(void)
 	rcg_clk_disable(&pdm_clk.c);
 	rcg_clk_enable(&tssc_clk.c);
 	rcg_clk_disable(&tssc_clk.c);
+
+	msm_clock_init(msm_clocks_8960, ARRAY_SIZE(msm_clocks_8960));
 }
 
 static int __init msm_clk_soc_late_init(void)
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 4f999d2..201c478 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -3348,7 +3348,7 @@ static struct measure_clk measure_clk = {
 	.multiplier = 1,
 };
 
-struct clk_lookup msm_clocks_8x60[] = {
+static struct clk_lookup msm_clocks_8x60[] = {
 	CLK_LOOKUP("cxo",		cxo_clk.c,	NULL),
 	CLK_LOOKUP("pll4",		pll4_clk.c,	NULL),
 	CLK_LOOKUP("pll4",		pll4_clk.c,	"peripheral-reset"),
@@ -3518,7 +3518,6 @@ struct clk_lookup msm_clocks_8x60[] = {
 	CLK_LOOKUP("sc1_mclk",		sc1_m_clk, NULL),
 	CLK_LOOKUP("l2_mclk",		l2_m_clk,  NULL),
 };
-unsigned msm_num_clocks_8x60 = ARRAY_SIZE(msm_clocks_8x60);
 
 /*
  * Miscellaneous clock register initializations
@@ -3620,7 +3619,7 @@ static void __init reg_init(void)
 }
 
 /* Local clock driver initialization. */
-void __init msm_clk_soc_init(void)
+void __init msm8660_clock_init(void)
 {
 	soc_update_sys_vdd = msm8660_update_sys_vdd;
 	local_vote_sys_vdd(HIGH);
@@ -3643,6 +3642,8 @@ void __init msm_clk_soc_init(void)
 	rcg_clk_disable(&pdm_clk.c);
 	rcg_clk_enable(&tssc_clk.c);
 	rcg_clk_disable(&tssc_clk.c);
+
+	msm_clock_init(msm_clocks_8x60, ARRAY_SIZE(msm_clocks_8x60));
 }
 
 static int __init msm_clk_soc_late_init(void)
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 7daadb1..fbbc973 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -186,9 +186,6 @@ void __init msm_clock_init(struct clk_lookup *clock_tbl, size_t num_clocks)
 {
 	unsigned n;
 
-	/* Do SoC-speficic clock init operations. */
-	msm_clk_soc_init();
-
 	for (n = 0; n < num_clocks; n++) {
 		struct clk *clk = clock_tbl[n].clk;
 		struct clk *parent = clk_get_parent(clk);
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index a873a19..6c4b332 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/spinlock.h>
+#include <linux/clkdev.h>
 #include <mach/clk.h>
 
 #define CLKFLAG_INVERT			0x00000001
@@ -68,12 +69,10 @@ struct clk {
 	.children = LIST_HEAD_INIT((name).children), \
 	.siblings = LIST_HEAD_INIT((name).siblings)
 
-#if defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
-defined(CONFIG_ARCH_MSM8960)
-void __init msm_clk_soc_init(void);
-#else
-static inline void __init msm_clk_soc_init(void) { }
-#endif
+void msm_clock_init(struct clk_lookup *clock_tbl, size_t num_clocks);
+void msm7x30_clock_init(void);
+void msm8660_clock_init(void);
+void msm8960_clock_init(void);
 
 #ifdef CONFIG_DEBUG_FS
 int __init clock_debug_init(void);
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index b4d56d5..e4d5abe 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -17,6 +17,7 @@
 #define __ARCH_ARM_MACH_MSM_DEVICES_H
 
 #include <linux/clkdev.h>
+#include <linux/platform_device.h>
 
 #include "clock.h"
 
@@ -49,16 +50,7 @@ extern struct platform_device msm_device_mdp;
 extern struct clk_lookup msm_clocks_7x01a[];
 extern unsigned msm_num_clocks_7x01a;
 
-extern struct clk_lookup msm_clocks_7x30[];
-extern unsigned msm_num_clocks_7x30;
-
 extern struct clk_lookup msm_clocks_8x50[];
 extern unsigned msm_num_clocks_8x50;
 
-extern struct clk_lookup msm_clocks_8x60[];
-extern unsigned msm_num_clocks_8x60;
-
-extern struct clk_lookup msm_clocks_8960[];
-extern unsigned msm_num_clocks_8960;
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 1e4c50e..699461b 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -40,8 +40,6 @@ extern struct sys_timer msm_timer;
 void __init msm_add_devices(void);
 void __init msm_map_common_io(void);
 void __init msm_init_irq(void);
-void __init msm_init_gpio(void);
-void __init msm_clock_init(struct clk_lookup *clock_tbl, size_t num_clocks);
 void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
 int __init msm_add_sdcc(unsigned int controller,
 			struct msm_mmc_platform_data *plat,
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 32/34] msm: clock-8x60: Add local control of vpe_axi_clk and vpe_axi_clk

[David Brown]

From: Matt Wagantall <mattw@codeaurora.org>

The MAXI_EN2 register is no longer owned by the RPM. Add local
control of the VPE and Rotator AXI clocks which are in it.

Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-8x60.c |   19 ++++++++++++++++---
 1 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 201c478..21c2472 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -122,6 +122,7 @@
 #define JPEGD_CC_REG				REG_MM(0x00A4)
 #define JPEGD_NS_REG				REG_MM(0x00AC)
 #define MAXI_EN_REG				REG_MM(0x0018)
+#define MAXI_EN2_REG				REG_MM(0x0020)
 #define MAXI_EN3_REG				REG_MM(0x002C)
 #define MDP_CC_REG				REG_MM(0x00C0)
 #define MDP_MD0_REG				REG_MM(0x00C4)
@@ -603,24 +604,32 @@ static struct branch_clk vfe_axi_clk = {
 
 static struct branch_clk rot_axi_clk = {
 	.b = {
+		.ctl_reg = MAXI_EN2_REG,
+		.en_mask = BIT(24),
 		.reset_reg = SW_RESET_AXI_REG,
 		.reset_mask = BIT(6),
+		.halt_reg = DBG_BUS_VEC_E_REG,
+		.halt_bit = 2,
 	},
 	.c = {
 		.dbg_name = "rot_axi_clk",
-		.ops = &clk_ops_reset,
+		.ops = &clk_ops_branch,
 		CLK_INIT(rot_axi_clk.c),
 	},
 };
 
 static struct branch_clk vpe_axi_clk = {
 	.b = {
+		.ctl_reg = MAXI_EN2_REG,
+		.en_mask = BIT(26),
 		.reset_reg = SW_RESET_AXI_REG,
 		.reset_mask = BIT(15),
+		.halt_reg = DBG_BUS_VEC_E_REG,
+		.halt_bit = 1,
 	},
 	.c = {
 		.dbg_name = "vpe_axi_clk",
-		.ops = &clk_ops_reset,
+		.ops = &clk_ops_branch,
 		CLK_INIT(vpe_axi_clk.c),
 	},
 };
@@ -2545,6 +2554,7 @@ static struct rcg_clk rot_clk = {
 	.set_rate = set_rate_div_banked,
 	.freq_tbl = clk_tbl_rot,
 	.bank_masks = &bdiv_info_rot,
+	.depends = &rot_axi_clk.c,
 	.current_freq = &local_dummy_freq,
 	.c = {
 		.dbg_name = "rot_clk",
@@ -2767,6 +2777,7 @@ static struct rcg_clk vpe_clk = {
 	.ns_mask = (BM(15, 12) | BM(2, 0)),
 	.set_rate = set_rate_nop,
 	.freq_tbl = clk_tbl_vpe,
+	.depends = &vpe_axi_clk.c,
 	.current_freq = &local_dummy_freq,
 	.c = {
 		.dbg_name = "vpe_clk",
@@ -3154,8 +3165,10 @@ static struct measure_sel measure_mux[] = {
 	{ TEST_MM_HS(0x13), &imem_axi_clk.c },
 	{ TEST_MM_HS(0x14), &jpegd_axi_clk.c },
 	{ TEST_MM_HS(0x15), &mdp_axi_clk.c },
+	{ TEST_MM_HS(0x16), &rot_axi_clk.c },
 	{ TEST_MM_HS(0x17), &vcodec_axi_clk.c },
 	{ TEST_MM_HS(0x18), &vfe_axi_clk.c },
+	{ TEST_MM_HS(0x19), &vpe_axi_clk.c },
 	{ TEST_MM_HS(0x1A), &mdp_clk.c },
 	{ TEST_MM_HS(0x1B), &rot_clk.c },
 	{ TEST_MM_HS(0x1C), &vpe_clk.c },
@@ -3566,7 +3579,7 @@ static void __init reg_init(void)
 	 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
 	 * delays to safe values. */
 	rmwreg(0x000207F9, MAXI_EN_REG,  0x0FFFFFFF);
-	/* MAXI_EN2_REG is owned by the RPM.  Don't touch it. */
+	writel_relaxed(0x7027FCFF, MAXI_EN2_REG);
 	writel_relaxed(0x3FE7FCFF, MAXI_EN3_REG);
 	writel_relaxed(0x000001D8, SAXI_EN_REG);
 
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 33/34] ARM: msm: fix names of UART clocks

[David Brown]

Earlier code for MSM uarts had three separate drivers, one for the old
"legacy" hardware, one for the new DMA-based hardware, and a third
that used the DMA-based hardware in a legacy-compatible mode.

The current msm_serial driver handles both the older hardware and the
DMA-based hardware in non-DMA mode from the same driver.  Rename the
clocks for this device to support this usage.

Signed-off-by: David Brown <davidb@codeaurora.org>
---
 arch/arm/mach-msm/clock-8x60.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 21c2472..f398bd7 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -3378,7 +3378,7 @@ static struct clk_lookup msm_clocks_8x60[] = {
 	CLK_LOOKUP("gsbi_uart_clk",	gsbi9_uart_clk.c, "msm_serial_hsl.1"),
 	CLK_LOOKUP("gsbi_uart_clk",	gsbi10_uart_clk.c,	NULL),
 	CLK_LOOKUP("gsbi_uart_clk",	gsbi11_uart_clk.c,	NULL),
-	CLK_LOOKUP("gsbi_uart_clk",	gsbi12_uart_clk.c, "msm_serial_hsl.0"),
+	CLK_LOOKUP("gsbi_uart_clk",	gsbi12_uart_clk.c, "msm_serial.0"),
 	CLK_LOOKUP("spi_clk",		gsbi1_qup_clk.c, "spi_qsd.0"),
 	CLK_LOOKUP("gsbi_qup_clk",	gsbi2_qup_clk.c,		NULL),
 	CLK_LOOKUP("gsbi_qup_clk",	gsbi3_qup_clk.c, "qup_i2c.0"),
@@ -3425,7 +3425,7 @@ static struct clk_lookup msm_clocks_8x60[] = {
 	CLK_LOOKUP("spi_pclk",		gsbi10_p_clk.c, "spi_qsd.1"),
 	CLK_LOOKUP("gsbi_pclk",		gsbi11_p_clk.c,		NULL),
 	CLK_LOOKUP("gsbi_pclk",		gsbi12_p_clk.c, "msm_dsps.0"),
-	CLK_LOOKUP("gsbi_pclk",		gsbi12_p_clk.c, "msm_serial_hsl.0"),
+	CLK_LOOKUP("gsbi_pclk",		gsbi12_p_clk.c, "msm_serial.0"),
 	CLK_LOOKUP("gsbi_pclk",		gsbi12_p_clk.c, "qup_i2c.5"),
 	CLK_LOOKUP("ppss_pclk",		ppss_p_clk.c,		NULL),
 	CLK_LOOKUP("tsif_pclk",		tsif_p_clk.c,		NULL),
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 34/34] msm_serial: fix clock rate on DMA-based uarts

[David Brown]

The driver explicitly requests a clock rate for the UART, but it is
off by a factor of four from the dividers that it programs into the
UART.  Fix this by setting the rate to 1/4 of the current value.

Signed-off-by: David Brown <davidb@codeaurora.org>
---
 drivers/tty/serial/msm_serial.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 29cbfd8..b7baceb 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -891,7 +891,7 @@ static int __init msm_serial_probe(struct platform_device *pdev)
 			return PTR_ERR(msm_port->clk);
 
 	if (msm_port->is_uartdm)
-		clk_set_rate(msm_port->clk, 7372800);
+		clk_set_rate(msm_port->clk, 1843200);
 
 	port->uartclk = clk_get_rate(msm_port->clk);
 	printk(KERN_INFO "uartclk = %d\n", port->uartclk);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH 02/34] msm: clock: Always use an array to iterate over clocks

[Russell King - ARM Linux]

On Wed, Nov 02, 2011 at 11:35:59AM -0700, David Brown wrote:
> If the array of clk_lookups contains aliases for the same struct
> clk, msm_clock_init() will add the clock to the clocks list
> twice.  This would cause list corruption so let's just remove the
> clocks list and any associated code and iterate over the array
> instead.

Hmm...

> @@ -158,13 +152,13 @@ void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks)
>   */
>  static int __init clock_late_init(void)
>  {
> +	unsigned i, count = 0;
>  	unsigned long flags;
> -	struct clk *clk;
> -	unsigned count = 0;
>  
>  	clock_debug_init();
> -	mutex_lock(&clocks_mutex);
> -	list_for_each_entry(clk, &clocks, list) {
> +	for (i = 0; i < msm_num_clocks; i++) {
> +		struct clk *clk = msm_clocks[i].clk;
> +
>  		clock_debug_add(clk);

This means you'll end up calling clock_debug_add() twice for the same
struct clk - this sounds like a bad idea in itself.  It looks like
there's no protection within that function against it being called
twice with the same struct clk.

Are you sure this is safe?

[RFC PATCH 02/34] msm: clock: Always use an array to iterate over clocks

[Stephen Boyd]

On 11/02/11 12:45, Russell King - ARM Linux wrote:
> On Wed, Nov 02, 2011 at 11:35:59AM -0700, David Brown wrote:
>> If the array of clk_lookups contains aliases for the same struct
>> clk, msm_clock_init() will add the clock to the clocks list
>> twice.  This would cause list corruption so let's just remove the
>> clocks list and any associated code and iterate over the array
>> instead.
> Hmm...
>
>> @@ -158,13 +152,13 @@ void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks)
>>   */
>>  static int __init clock_late_init(void)
>>  {
>> +	unsigned i, count = 0;
>>  	unsigned long flags;
>> -	struct clk *clk;
>> -	unsigned count = 0;
>>  
>>  	clock_debug_init();
>> -	mutex_lock(&clocks_mutex);
>> -	list_for_each_entry(clk, &clocks, list) {
>> +	for (i = 0; i < msm_num_clocks; i++) {
>> +		struct clk *clk = msm_clocks[i].clk;
>> +
>>  		clock_debug_add(clk);
> This means you'll end up calling clock_debug_add() twice for the same
> struct clk - this sounds like a bad idea in itself.  It looks like
> there's no protection within that function against it being called
> twice with the same struct clk.
>
> Are you sure this is safe?

This hasn't proven to be a problem so far because debugfs returns an
error when you create a directory with the same name twice. If we ever
do something more in clock_debug_add() we would have a problem.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.