[PATCH 0/4] arm: exynos4: add irq domain and device tree support for wakeup interrupts

[PATCH 0/4] arm: exynos4: add irq domain and device tree support for wakeup interrupts

[Thomas Abraham]

Samsung Exynos4 includes 32 external wakeup interrupt sources. This patchset
adds irq domain and device tree support for these interrupts.

This patchset is based on the following tree.
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git  for-next

This patchset depends on the following patch from Jamie Iles.
irqdomain: export irq_domain._simple_op.s for !CONFIG_OF

Thomas Abraham (4):
  arm: exynos4: simplify EINT number to GIC irq number translation
  arm: exynos4: add irq_domain support for wakeup interrupts
  arm: exynos4: remove arch_initcall for wakeup interrupt source initialization
  arm: exynos4: add device tree support for external wakeup interrupt controller

 .../bindings/arm/samsung/wakeup-eint.txt           |   14 +++
 arch/arm/mach-exynos/cpu.c                         |    4 +
 arch/arm/mach-exynos/include/mach/regs-gpio.h      |    4 +-
 arch/arm/mach-exynos/irq-eint.c                    |  101 +++++++++++---------
 arch/arm/plat-samsung/include/plat/exynos4.h       |    1 +
 5 files changed, 75 insertions(+), 49 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt

[PATCH 1/4] arm: exynos4: simplify EINT number to linux irq number translation

[Thomas Abraham]

The exynos4_get_irq_nr function that converts a given wakeup interrupt
source number to a linux irq number is simplified and replaced with
the new macro exynos4_irq_eint_to_gic_irq.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/irq-eint.c |   25 +++----------------------
 1 files changed, 3 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
index badb8c6..5e89412 100644
--- a/arch/arm/mach-exynos/irq-eint.c
+++ b/arch/arm/mach-exynos/irq-eint.c
@@ -29,26 +29,7 @@ static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
 
-static unsigned int exynos4_get_irq_nr(unsigned int number)
-{
-	u32 ret = 0;
-
-	switch (number) {
-	case 0 ... 3:
-		ret = (number + IRQ_EINT0);
-		break;
-	case 4 ... 7:
-		ret = (number + (IRQ_EINT4 - 4));
-		break;
-	case 8 ... 15:
-		ret = (number + (IRQ_EINT8 - 8));
-		break;
-	default:
-		printk(KERN_ERR "number available : %d\n", number);
-	}
-
-	return ret;
-}
+#define exynos4_irq_eint_to_gic_irq(number) (IRQ_EINT0 + number)
 
 static inline void exynos4_irq_eint_mask(struct irq_data *data)
 {
@@ -225,9 +206,9 @@ int __init exynos4_init_irq_eint(void)
 	for (irq = 0 ; irq <= 15 ; irq++) {
 		eint0_15_data[irq] = IRQ_EINT(irq);
 
-		irq_set_handler_data(exynos4_get_irq_nr(irq),
+		irq_set_handler_data(exynos4_irq_eint_to_gic_irq(irq),
 				     &eint0_15_data[irq]);
-		irq_set_chained_handler(exynos4_get_irq_nr(irq),
+		irq_set_chained_handler(exynos4_irq_eint_to_gic_irq(irq),
 					exynos4_irq_eint0_15);
 	}
 
-- 
1.6.6.rc2

[PATCH 2/4] arm: exynos4: add irq_domain support for wakeup interrupts

[Thomas Abraham]

Add irq_domain support for the 32 wakeup interrupt sources.

Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/include/mach/regs-gpio.h |    4 +-
 arch/arm/mach-exynos/irq-eint.c               |   69 ++++++++++++++++---------
 2 files changed, 46 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index 1401b21..2e6ec6b 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -28,9 +28,9 @@
 #define EXYNOS4_EINT40PEND		(S5P_VA_GPIO2 + 0xF40)
 #define S5P_EINT_PEND(x)		(EXYNOS4_EINT40PEND + ((x) * 0x4))
 
-#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
+#define EINT_REG_NR(x)			((x) >> 3)
 
-#define eint_irq_to_bit(irq)		(1 << (EINT_OFFSET(irq) & 0x7))
+#define eint_irq_to_bit(irq)		(1 << ((irq) & 0x7))
 
 #define EINT_MODE			S3C_GPIO_SFN(0xf)
 
diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
index 5e89412..a65da64 100644
--- a/arch/arm/mach-exynos/irq-eint.c
+++ b/arch/arm/mach-exynos/irq-eint.c
@@ -16,6 +16,8 @@
 #include <linux/io.h>
 #include <linux/sysdev.h>
 #include <linux/gpio.h>
+#include <linux/irqdomain.h>
+#include <linux/export.h>
 
 #include <plat/pm.h>
 #include <plat/cpu.h>
@@ -28,17 +30,19 @@
 static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
+static struct irq_domain exynos4_eint_irq_domain;
 
 #define exynos4_irq_eint_to_gic_irq(number) (IRQ_EINT0 + number)
+#define EXYNOS4_EINT_NR 32
 
 static inline void exynos4_irq_eint_mask(struct irq_data *data)
 {
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-	mask |= eint_irq_to_bit(data->irq);
-	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->hwirq)));
+	mask |= eint_irq_to_bit(data->hwirq);
+	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->hwirq)));
 	spin_unlock(&eint_lock);
 }
 
@@ -47,16 +51,16 @@ static void exynos4_irq_eint_unmask(struct irq_data *data)
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-	mask &= ~(eint_irq_to_bit(data->irq));
-	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->hwirq)));
+	mask &= ~(eint_irq_to_bit(data->hwirq));
+	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->hwirq)));
 	spin_unlock(&eint_lock);
 }
 
 static inline void exynos4_irq_eint_ack(struct irq_data *data)
 {
-	__raw_writel(eint_irq_to_bit(data->irq),
-		     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+	__raw_writel(eint_irq_to_bit(data->hwirq),
+			S5P_EINT_PEND(EINT_REG_NR(data->hwirq)));
 }
 
 static void exynos4_irq_eint_maskack(struct irq_data *data)
@@ -67,7 +71,7 @@ static void exynos4_irq_eint_maskack(struct irq_data *data)
 
 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
-	int offs = EINT_OFFSET(data->irq);
+	int offs = data->hwirq;
 	int shift;
 	u32 ctrl, mask;
 	u32 newvalue = 0;
@@ -102,10 +106,10 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
 	mask = 0x7 << shift;
 
 	spin_lock(&eint_lock);
-	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->hwirq)));
 	ctrl &= ~mask;
 	ctrl |= newvalue << shift;
-	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->hwirq)));
 	spin_unlock(&eint_lock);
 
 	switch (offs) {
@@ -148,19 +152,19 @@ static struct irq_chip exynos4_irq_eint = {
  *
  * Each EINT pend/mask registers handle eight of them.
  */
-static inline void exynos4_irq_demux_eint(unsigned int start)
+static inline void exynos4_irq_demux_eint(unsigned int base, unsigned int offs)
 {
 	unsigned int irq;
 
-	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
-	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(offs)));
+	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(offs)));
 
 	status &= ~mask;
 	status &= 0xff;
 
 	while (status) {
 		irq = fls(status) - 1;
-		generic_handle_irq(irq + start);
+		generic_handle_irq(irq + offs + base);
 		status &= ~(1 << irq);
 	}
 }
@@ -168,9 +172,11 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_get_chip(irq);
+	u32 *irq_data = irq_get_handler_data(irq);
+
 	chained_irq_enter(chip, desc);
-	exynos4_irq_demux_eint(IRQ_EINT(16));
-	exynos4_irq_demux_eint(IRQ_EINT(24));
+	exynos4_irq_demux_eint(*irq_data, 16);
+	exynos4_irq_demux_eint(*irq_data, 24);
 	chained_irq_exit(chip, desc);
 }
 
@@ -193,22 +199,35 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 
 int __init exynos4_init_irq_eint(void)
 {
-	int irq;
+	int irq, hwirq;
+	struct irq_domain *domain = &exynos4_eint_irq_domain;
+
+	domain->irq_base = irq_alloc_descs(IRQ_EINT(0), IRQ_EINT(0),
+						EXYNOS4_EINT_NR, 0);
+	if (domain->irq_base < 0) {
+		pr_err("exynos4_init_irq_eint: Failed to alloc irq descs\n");
+		return -EBUSY;
+	}
+	domain->nr_irq = EXYNOS4_EINT_NR;
+	domain->ops = &irq_domain_simple_ops;
+	irq_domain_add(domain);
 
-	for (irq = 0 ; irq <= 31 ; irq++) {
-		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+	irq_domain_for_each_irq(domain, hwirq, irq) {
+		irq_set_chip_and_handler(irq, &exynos4_irq_eint,
 					 handle_level_irq);
-		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+		set_irq_flags(irq, IRQF_VALID);
 	}
 
 	irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+	irq_set_handler_data(IRQ_EINT16_31, &domain->irq_base);
 
-	for (irq = 0 ; irq <= 15 ; irq++) {
-		eint0_15_data[irq] = IRQ_EINT(irq);
+	for (hwirq = 0 ; hwirq <= 15 ; hwirq++) {
+		irq = irq_domain_to_irq(domain, hwirq);
+		eint0_15_data[irq] = irq;
 
-		irq_set_handler_data(exynos4_irq_eint_to_gic_irq(irq),
+		irq_set_handler_data(exynos4_irq_eint_to_gic_irq(hwirq),
 				     &eint0_15_data[irq]);
-		irq_set_chained_handler(exynos4_irq_eint_to_gic_irq(irq),
+		irq_set_chained_handler(exynos4_irq_eint_to_gic_irq(hwirq),
 					exynos4_irq_eint0_15);
 	}
 
-- 
1.6.6.rc2

[PATCH 3/4] arm: exynos4: remove arch_initcall for wakeup interrupt source initialization

[Thomas Abraham]

The of_irq_init function would be setup to invoke the exynos4_init_irq_eint
function when booting using device tree. The arch_initcall for
exynos4_init_irq_eint would duplicate its invocation in that case. Hence,
arch_initcall for exynos4_init_irq_eint is removed and this function is invoked
from the exynos4_init_irq for non-dt case.

Moreover, with single kernel image build, the exynos4_init_irq_eint has no checks
to ensure that it is running on a exynos4 platform. So it would be appropriate
to invoke it from exynos4_init_irq.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/cpu.c                   |    1 +
 arch/arm/mach-exynos/irq-eint.c              |    2 --
 arch/arm/plat-samsung/include/plat/exynos4.h |    1 +
 3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
index 8e09f34..6d27c36 100644
--- a/arch/arm/mach-exynos/cpu.c
+++ b/arch/arm/mach-exynos/cpu.c
@@ -278,6 +278,7 @@ void __init exynos4_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
+	exynos4_init_irq_eint();
 }
 
 struct sysdev_class exynos4_sysclass = {
diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
index a65da64..771b156 100644
--- a/arch/arm/mach-exynos/irq-eint.c
+++ b/arch/arm/mach-exynos/irq-eint.c
@@ -233,5 +233,3 @@ int __init exynos4_init_irq_eint(void)
 
 	return 0;
 }
-
-arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/plat-samsung/include/plat/exynos4.h b/arch/arm/plat-samsung/include/plat/exynos4.h
index f546e88..a501461 100644
--- a/arch/arm/plat-samsung/include/plat/exynos4.h
+++ b/arch/arm/plat-samsung/include/plat/exynos4.h
@@ -24,6 +24,7 @@ extern void exynos4_init_irq(void);
 extern void exynos4_map_io(void);
 extern void exynos4_init_clocks(int xtal);
 extern struct sys_timer exynos4_timer;
+extern int exynos4_init_irq_eint(void);
 
 #define exynos4_init_uarts exynos4_common_init_uarts
 
-- 
1.6.6.rc2

[PATCH 4/4] arm: exynos4: add device tree support for external wakeup interrupt controller

[Thomas Abraham]

Add device tree support for external wakeup source interrupt controller
on Exynos4.

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 .../bindings/arm/samsung/wakeup-eint.txt           |   14 ++++++++++++++
 arch/arm/mach-exynos/cpu.c                         |    5 ++++-
 arch/arm/mach-exynos/irq-eint.c                    |    9 +++++++++
 3 files changed, 27 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt

diff --git a/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
new file mode 100644
index 0000000..0ca5782
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
@@ -0,0 +1,14 @@
+* Samsung Exynos4 External Wakeup Interrupt Source Controller
+
+Samsung Exynos4 processor supports 32 external wakeup interrupt sources. First
+16 of these interrupts are directly connected to GIC and the rest 16 of the
+interrupts are grouped together to deliver a single interrupt to GIC.
+
+Required properties:
+
+- compatible: should be "samsung,exynos4210-wakeup-eint".
+- interrupt-controller: Identifies the node as an interrupt controller.
+- interrupt-cells: Specifies the number of cells required to specify the
+    interrupt source number. The value of should be <2>. The first cell
+    represents the wakeup interrupt source number and the second cell
+    should be zero (currently unused).
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
index 6d27c36..306c13c 100644
--- a/arch/arm/mach-exynos/cpu.c
+++ b/arch/arm/mach-exynos/cpu.c
@@ -245,6 +245,8 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d)
 #ifdef CONFIG_OF
 static const struct of_device_id exynos4_dt_irq_match[] = {
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ .compatible = "samsung,exynos4210-wakeup-eint",
+		.data = exynos4_init_irq_eint, },
 	{},
 };
 #endif
@@ -278,7 +280,8 @@ void __init exynos4_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
-	exynos4_init_irq_eint();
+	if (!of_have_populated_dt())
+		exynos4_init_irq_eint();
 }
 
 struct sysdev_class exynos4_sysclass = {
diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
index 771b156..e78fdfa 100644
--- a/arch/arm/mach-exynos/irq-eint.c
+++ b/arch/arm/mach-exynos/irq-eint.c
@@ -18,6 +18,7 @@
 #include <linux/gpio.h>
 #include <linux/irqdomain.h>
 #include <linux/export.h>
+#include <linux/of.h>
 
 #include <plat/pm.h>
 #include <plat/cpu.h>
@@ -210,6 +211,14 @@ int __init exynos4_init_irq_eint(void)
 	}
 	domain->nr_irq = EXYNOS4_EINT_NR;
 	domain->ops = &irq_domain_simple_ops;
+#ifdef CONFIG_OF
+	if (of_have_populated_dt()) {
+		domain->of_node = of_find_compatible_node(NULL, NULL,
+					"samsung,exynos4210-wakeup-eint");
+		if (!domain->of_node)
+			pr_info("exynos4_init_irq_eint: of_node not found\n");
+	}
+#endif
 	irq_domain_add(domain);
 
 	irq_domain_for_each_irq(domain, hwirq, irq) {
-- 
1.6.6.rc2

[PATCH 4/4] arm: exynos4: add device tree support for external wakeup interrupt controller

[Rob Herring]

On 12/07/2011 07:59 AM, Thomas Abraham wrote:
> Add device tree support for external wakeup source interrupt controller
> on Exynos4.
> 
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
>  .../bindings/arm/samsung/wakeup-eint.txt           |   14 ++++++++++++++
>  arch/arm/mach-exynos/cpu.c                         |    5 ++++-
>  arch/arm/mach-exynos/irq-eint.c                    |    9 +++++++++
>  3 files changed, 27 insertions(+), 1 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
> new file mode 100644
> index 0000000..0ca5782
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
> @@ -0,0 +1,14 @@
> +* Samsung Exynos4 External Wakeup Interrupt Source Controller
> +
> +Samsung Exynos4 processor supports 32 external wakeup interrupt sources. First
> +16 of these interrupts are directly connected to GIC and the rest 16 of the
> +interrupts are grouped together to deliver a single interrupt to GIC.
> +
> +Required properties:
> +
> +- compatible: should be "samsung,exynos4210-wakeup-eint".
> +- interrupt-controller: Identifies the node as an interrupt controller.
> +- interrupt-cells: Specifies the number of cells required to specify the
> +    interrupt source number. The value of should be <2>. The first cell
> +    represents the wakeup interrupt source number and the second cell
> +    should be zero (currently unused).

interrupt-parent needs to be set to the gic?

> diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
> index 6d27c36..306c13c 100644
> --- a/arch/arm/mach-exynos/cpu.c
> +++ b/arch/arm/mach-exynos/cpu.c
> @@ -245,6 +245,8 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d)
>  #ifdef CONFIG_OF
>  static const struct of_device_id exynos4_dt_irq_match[] = {
>  	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
> +	{ .compatible = "samsung,exynos4210-wakeup-eint",
> +		.data = exynos4_init_irq_eint, },
>  	{},
>  };
>  #endif
> @@ -278,7 +280,8 @@ void __init exynos4_init_irq(void)
>  	 * uses GIC instead of VIC.
>  	 */
>  	s5p_init_irq(NULL, 0);
> -	exynos4_init_irq_eint();
> +	if (!of_have_populated_dt())
> +		exynos4_init_irq_eint();
>  }
>  
>  struct sysdev_class exynos4_sysclass = {
> diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
> index 771b156..e78fdfa 100644
> --- a/arch/arm/mach-exynos/irq-eint.c
> +++ b/arch/arm/mach-exynos/irq-eint.c
> @@ -18,6 +18,7 @@
>  #include <linux/gpio.h>
>  #include <linux/irqdomain.h>
>  #include <linux/export.h>
> +#include <linux/of.h>
>  
>  #include <plat/pm.h>
>  #include <plat/cpu.h>
> @@ -210,6 +211,14 @@ int __init exynos4_init_irq_eint(void)
>  	}
>  	domain->nr_irq = EXYNOS4_EINT_NR;
>  	domain->ops = &irq_domain_simple_ops;
> +#ifdef CONFIG_OF
> +	if (of_have_populated_dt()) {
> +		domain->of_node = of_find_compatible_node(NULL, NULL,
> +					"samsung,exynos4210-wakeup-eint");
> +		if (!domain->of_node)
> +			pr_info("exynos4_init_irq_eint: of_node not found\n");
> +	}
> +#endif

Your function prototype is wrong for of_irq_init as it provides you the
node ptr.

Otherwise, the series looks pretty good.

Rob

[PATCH 4/4] arm: exynos4: add device tree support for external wakeup interrupt controller

[Thomas Abraham]

Hi Rob,

On 7 December 2011 21:46, Rob Herring <robherring2@gmail.com> wrote:
> On 12/07/2011 07:59 AM, Thomas Abraham wrote:
>> Add device tree support for external wakeup source interrupt controller
>> on Exynos4.
>>
>> Cc: Rob Herring <rob.herring@calxeda.com>
>> Cc: Grant Likely <grant.likely@secretlab.ca>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---

[...]

>> diff --git a/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
>> new file mode 100644
>> index 0000000..0ca5782
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
>> @@ -0,0 +1,14 @@
>> +* Samsung Exynos4 External Wakeup Interrupt Source Controller
>> +
>> +Samsung Exynos4 processor supports 32 external wakeup interrupt sources. First
>> +16 of these interrupts are directly connected to GIC and the rest 16 of the
>> +interrupts are grouped together to deliver a single interrupt to GIC.
>> +
>> +Required properties:
>> +
>> +- compatible: should be "samsung,exynos4210-wakeup-eint".
>> +- interrupt-controller: Identifies the node as an interrupt controller.
>> +- interrupt-cells: Specifies the number of cells required to specify the
>> + ? ?interrupt source number. The value of should be <2>. The first cell
>> + ? ?represents the wakeup interrupt source number and the second cell
>> + ? ?should be zero (currently unused).
>
> interrupt-parent needs to be set to the gic?

Yes, I missed that. gic is set as the interrupt parent in the root
node and all child nodes inherit it. I will add interrupt-parent as
the required property as list gic as the parent.

>
>> diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c

[...]

>> +#ifdef CONFIG_OF
>> + ? ? if (of_have_populated_dt()) {
>> + ? ? ? ? ? ? domain->of_node = of_find_compatible_node(NULL, NULL,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "samsung,exynos4210-wakeup-eint");
>> + ? ? ? ? ? ? if (!domain->of_node)
>> + ? ? ? ? ? ? ? ? ? ? pr_info("exynos4_init_irq_eint: of_node not found\n");
>> + ? ? }
>> +#endif
>
> Your function prototype is wrong for of_irq_init as it provides you the
> node ptr.

Thanks. I got this wrong. That would make the code above much simpler.
I will fix this.

>
> Otherwise, the series looks pretty good.
>
> Rob

Thanks for your review and comments.

Regards,
Thomas.

[PATCH 2/4] arm: exynos4: add irq_domain support for wakeup interrupts

[Rob Herring]

Thomas,

On 12/07/2011 07:59 AM, Thomas Abraham wrote:
> Add irq_domain support for the 32 wakeup interrupt sources.
> 
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
>  arch/arm/mach-exynos/include/mach/regs-gpio.h |    4 +-
>  arch/arm/mach-exynos/irq-eint.c               |   69 ++++++++++++++++---------
>  2 files changed, 46 insertions(+), 27 deletions(-)
> 

[snip]

> @@ -193,22 +199,35 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
>  
>  int __init exynos4_init_irq_eint(void)
>  {
> -	int irq;
> +	int irq, hwirq;
> +	struct irq_domain *domain = &exynos4_eint_irq_domain;
> +
> +	domain->irq_base = irq_alloc_descs(IRQ_EINT(0), IRQ_EINT(0),

Can this be dynamic and remove any compile time knowledge of the irq base?

> +						EXYNOS4_EINT_NR, 0);
> +	if (domain->irq_base < 0) {
> +		pr_err("exynos4_init_irq_eint: Failed to alloc irq descs\n");
> +		return -EBUSY;

You will hit this error with sparse irq unless you set nr_irq in mach
desc to NR_IRQ_LEGACY (16).

> +	}
> +	domain->nr_irq = EXYNOS4_EINT_NR;
> +	domain->ops = &irq_domain_simple_ops;
> +	irq_domain_add(domain);
>  
> -	for (irq = 0 ; irq <= 31 ; irq++) {
> -		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
> +	irq_domain_for_each_irq(domain, hwirq, irq) {
> +		irq_set_chip_and_handler(irq, &exynos4_irq_eint,
>  					 handle_level_irq);
> -		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
> +		set_irq_flags(irq, IRQF_VALID);
>  	}
>  
>  	irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
> +	irq_set_handler_data(IRQ_EINT16_31, &domain->irq_base);
>  
> -	for (irq = 0 ; irq <= 15 ; irq++) {
> -		eint0_15_data[irq] = IRQ_EINT(irq);
> +	for (hwirq = 0 ; hwirq <= 15 ; hwirq++) {
> +		irq = irq_domain_to_irq(domain, hwirq);
> +		eint0_15_data[irq] = irq;
>  
> -		irq_set_handler_data(exynos4_irq_eint_to_gic_irq(irq),
> +		irq_set_handler_data(exynos4_irq_eint_to_gic_irq(hwirq),
>  				     &eint0_15_data[irq]);
> -		irq_set_chained_handler(exynos4_irq_eint_to_gic_irq(irq),
> +		irq_set_chained_handler(exynos4_irq_eint_to_gic_irq(hwirq),
>  					exynos4_irq_eint0_15);
>  	}
>  

[PATCH 2/4] arm: exynos4: add irq_domain support for wakeup interrupts

[Thomas Abraham]

Hi Rob,

On 7 December 2011 21:54, Rob Herring <robherring2@gmail.com> wrote:
> Thomas,
>
> On 12/07/2011 07:59 AM, Thomas Abraham wrote:
>> Add irq_domain support for the 32 wakeup interrupt sources.
>>
>> Cc: Grant Likely <grant.likely@secretlab.ca>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> ?arch/arm/mach-exynos/include/mach/regs-gpio.h | ? ?4 +-
>> ?arch/arm/mach-exynos/irq-eint.c ? ? ? ? ? ? ? | ? 69 ++++++++++++++++---------
>> ?2 files changed, 46 insertions(+), 27 deletions(-)
>>
>
> [snip]
>
>> @@ -193,22 +199,35 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
>>
>> ?int __init exynos4_init_irq_eint(void)
>> ?{
>> - ? ? int irq;
>> + ? ? int irq, hwirq;
>> + ? ? struct irq_domain *domain = &exynos4_eint_irq_domain;
>> +
>> + ? ? domain->irq_base = irq_alloc_descs(IRQ_EINT(0), IRQ_EINT(0),
>
> Can this be dynamic and remove any compile time knowledge of the irq base?

There are macros in the mach-exynos code that define linux irq numbers
for specific uses. For instance, linux interrupt number for wakeup
interrupt 0 is defined as IRQ_EINT(0) and maps to one of the linux irq
number. Consumer using this interrupt would use IRQ_EINT(0) in
request_irq or setup_irq.

Since the linux irq numbers are currently assigned to specific uses
like this, I am not sure how to make irq_alloc_descs dynamic and still
be able to use the dynamic irq base in the rest of the mach-exynos
code with no other code changes. Is there any way to handle this case?

Thanks,
Thomas.

>
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? EXYNOS4_EINT_NR, 0);
>> + ? ? if (domain->irq_base < 0) {
>> + ? ? ? ? ? ? pr_err("exynos4_init_irq_eint: Failed to alloc irq descs\n");
>> + ? ? ? ? ? ? return -EBUSY;
>
> You will hit this error with sparse irq unless you set nr_irq in mach
> desc to NR_IRQ_LEGACY (16).

[...]