[PATCH V2 0/7] imx: add imx6 sabrelite board

[PATCH V2 0/7] imx: add imx6 sabrelite board

[Richard Zhao]

- add imx6q sabrelite board support
- add imx6q cpufreq support

Changes since V1:
 - rename gpio labels
 - imx6q-sabrelite.dts: remove fec_mac and bootargs
 - add clock_frequency in cpu0 node to check max cpu frequency
 - add item in Kconfig in alpha order

Thanks
Richard

[PATCH V2 1/7] dts/imx: rename gpio labels to consistent with hw spec

[Richard Zhao]

GPIO1/GPIO2/... is more readable than GPIO0/GPIO1/... .
Remove redundant gpio comments.

Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
---
 arch/arm/boot/dts/imx51-babbage.dts   |   11 +++++------
 arch/arm/boot/dts/imx51.dtsi          |    8 ++++----
 arch/arm/boot/dts/imx53-ard.dts       |   16 ++++++++--------
 arch/arm/boot/dts/imx53-evk.dts       |   15 +++++++--------
 arch/arm/boot/dts/imx53-qsb.dts       |   16 ++++++++--------
 arch/arm/boot/dts/imx53-smd.dts       |   13 ++++++-------
 arch/arm/boot/dts/imx53.dtsi          |   14 +++++++-------
 arch/arm/boot/dts/imx6q-sabreauto.dts |    6 +++---
 arch/arm/boot/dts/imx6q.dtsi          |   14 +++++++-------
 9 files changed, 55 insertions(+), 58 deletions(-)

diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index f8766af..ed09dc1 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -35,8 +35,8 @@
 				};
 
 				esdhc at 70008000 { /* ESDHC2 */
-					cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
-					wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
+					cd-gpios = <&gpio1 6 0>;
+					wp-gpios = <&gpio1 5 0>;
 					status = "okay";
 				};
 
@@ -47,8 +47,7 @@
 
 				ecspi at 70010000 { /* ECSPI1 */
 					fsl,spi-num-chipselects = <2>;
-					cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
-						   <&gpio3 25 0>; /* GPIO4_25 */
+					cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
 					status = "okay";
 
 					pmic: mc13892 at 0 {
@@ -57,7 +56,7 @@
 						compatible = "fsl,mc13892";
 						spi-max-frequency = <6000000>;
 						reg = <0>;
-						mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
+						mc13xxx-irq-gpios = <&gpio1 8 0>;
 						fsl,mc13xxx-uses-regulator;
 					};
 
@@ -127,7 +126,7 @@
 
 		power {
 			label = "Power Button";
-			gpios = <&gpio1 21 0>;
+			gpios = <&gpio2 21 0>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 327ab8e..57a790d 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -117,7 +117,7 @@
 				};
 			};
 
-			gpio0: gpio at 73f84000 { /* GPIO1 */
+			gpio1: gpio at 73f84000 {
 				compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 				reg = <0x73f84000 0x4000>;
 				interrupts = <50 51>;
@@ -127,7 +127,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio1: gpio at 73f88000 { /* GPIO2 */
+			gpio2: gpio at 73f88000 {
 				compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 				reg = <0x73f88000 0x4000>;
 				interrupts = <52 53>;
@@ -137,7 +137,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio2: gpio at 73f8c000 { /* GPIO3 */
+			gpio3: gpio at 73f8c000 {
 				compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 				reg = <0x73f8c000 0x4000>;
 				interrupts = <54 55>;
@@ -147,7 +147,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio3: gpio at 73f90000 { /* GPIO4 */
+			gpio4: gpio at 73f90000 {
 				compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 				reg = <0x73f90000 0x4000>;
 				interrupts = <56 57>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 2ab7f80..78c949e 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -29,8 +29,8 @@
 		aips at 50000000 { /* AIPS1 */
 			spba at 50000000 {
 				esdhc at 50004000 { /* ESDHC1 */
-					cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */
-					wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */
+					cd-gpios = <&gpio1 1 0>;
+					wp-gpios = <&gpio1 9 0>;
 					status = "okay";
 				};
 			};
@@ -67,7 +67,7 @@
 			compatible = "smsc,lan9220", "smsc,lan9115";
 			reg = <0xf4000000 0x2000000>;
 			phy-mode = "mii";
-			interrupt-parent = <&gpio1>;
+			interrupt-parent = <&gpio2>;
 			interrupts = <31>;
 			reg-io-width = <4>;
 			smsc,irq-push-pull;
@@ -79,34 +79,34 @@
 
 		home {
 			label = "Home";
-			gpios = <&gpio4 10 0>; /* GPIO5_10 */
+			gpios = <&gpio5 10 0>;
 			linux,code = <102>; /* KEY_HOME */
 			gpio-key,wakeup;
 		};
 
 		back {
 			label = "Back";
-			gpios = <&gpio4 11 0>; /* GPIO5_11 */
+			gpios = <&gpio5 11 0>;
 			linux,code = <158>; /* KEY_BACK */
 			gpio-key,wakeup;
 		};
 
 		program {
 			label = "Program";
-			gpios = <&gpio4 12 0>; /* GPIO5_12 */
+			gpios = <&gpio5 12 0>;
 			linux,code = <362>; /* KEY_PROGRAM */
 			gpio-key,wakeup;
 		};
 
 		volume-up {
 			label = "Volume Up";
-			gpios = <&gpio4 13 0>; /* GPIO5_13 */
+			gpios = <&gpio5 13 0>;
 			linux,code = <115>; /* KEY_VOLUMEUP */
 		};
 
 		volume-down {
 			label = "Volume Down";
-			gpios = <&gpio3 0 0>; /* GPIO4_0 */
+			gpios = <&gpio4 0 0>;
 			linux,code = <114>; /* KEY_VOLUMEDOWN */
 		};
 	};
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 3f3a881..964743e 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -29,15 +29,14 @@
 		aips at 50000000 { /* AIPS1 */
 			spba at 50000000 {
 				esdhc at 50004000 { /* ESDHC1 */
-					cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
-					wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */
+					cd-gpios = <&gpio3 13 0>;
+					wp-gpios = <&gpio3 14 0>;
 					status = "okay";
 				};
 
 				ecspi at 50010000 { /* ECSPI1 */
 					fsl,spi-num-chipselects = <2>;
-					cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
-						   <&gpio2 19 0>; /* GPIO3_19 */
+					cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
 					status = "okay";
 
 					flash: at45db321d at 1 {
@@ -61,8 +60,8 @@
 				};
 
 				esdhc at 50020000 { /* ESDHC3 */
-					cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
-					wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
+					cd-gpios = <&gpio3 11 0>;
+					wp-gpios = <&gpio3 12 0>;
 					status = "okay";
 				};
 			};
@@ -102,7 +101,7 @@
 
 			fec at 63fec000 {
 				phy-mode = "rmii";
-				phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+				phy-reset-gpios = <&gpio7 6 0>;
 				status = "okay";
 			};
 		};
@@ -113,7 +112,7 @@
 
 		green {
 			label = "Heartbeat";
-			gpios = <&gpio6 7 0>; /* GPIO7_7 */
+			gpios = <&gpio7 7 0>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index ae6de6d..cc43bde 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -29,13 +29,13 @@
 		aips at 50000000 { /* AIPS1 */
 			spba at 50000000 {
 				esdhc at 50004000 { /* ESDHC1 */
-					cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
+					cd-gpios = <&gpio3 13 0>;
 					status = "okay";
 				};
 
 				esdhc at 50020000 { /* ESDHC3 */
-					cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
-					wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
+					cd-gpios = <&gpio3 11 0>;
+					wp-gpios = <&gpio3 12 0>;
 					status = "okay";
 				};
 			};
@@ -84,7 +84,7 @@
 
 			fec at 63fec000 {
 				phy-mode = "rmii";
-				phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+				phy-reset-gpios = <&gpio7 6 0>;
 				status = "okay";
 			};
 		};
@@ -95,20 +95,20 @@
 
 		power {
 			label = "Power Button";
-			gpios = <&gpio0 8 0>; /* GPIO1_8 */
+			gpios = <&gpio1 8 0>;
 			linux,code = <116>; /* KEY_POWER */
 			gpio-key,wakeup;
 		};
 
 		volume-up {
 			label = "Volume Up";
-			gpios = <&gpio1 14 0>; /* GPIO2_14 */
+			gpios = <&gpio2 14 0>;
 			linux,code = <115>; /* KEY_VOLUMEUP */
 		};
 
 		volume-down {
 			label = "Volume Down";
-			gpios = <&gpio1 15 0>; /* GPIO2_15 */
+			gpios = <&gpio2 15 0>;
 			linux,code = <114>; /* KEY_VOLUMEDOWN */
 		};
 	};
@@ -118,7 +118,7 @@
 
 		user {
 			label = "Heartbeat";
-			gpios = <&gpio6 7 0>; /* GPIO7_7 */
+			gpios = <&gpio7 7 0>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index b1c062e..9e51bc3 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -29,8 +29,8 @@
 		aips at 50000000 { /* AIPS1 */
 			spba at 50000000 {
 				esdhc at 50004000 { /* ESDHC1 */
-					cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
-					wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */
+					cd-gpios = <&gpio3 13 0>;
+					wp-gpios = <&gpio4 11 0>;
 					status = "okay";
 				};
 
@@ -46,8 +46,7 @@
 
 				ecspi at 50010000 { /* ECSPI1 */
 					fsl,spi-num-chipselects = <2>;
-					cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
-						   <&gpio2 19 0>; /* GPIO3_19 */
+					cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
 					status = "okay";
 
 					zigbee: mc1323 at 0 {
@@ -145,7 +144,7 @@
 
 			fec at 63fec000 {
 				phy-mode = "rmii";
-				phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+				phy-reset-gpios = <&gpio7 6 0>;
 				status = "okay";
 			};
 		};
@@ -156,13 +155,13 @@
 
 		volume-up {
 			label = "Volume Up";
-			gpios = <&gpio1 14 0>; /* GPIO2_14 */
+			gpios = <&gpio2 14 0>;
 			linux,code = <115>; /* KEY_VOLUMEUP */
 		};
 
 		volume-down {
 			label = "Volume Down";
-			gpios = <&gpio1 15 0>; /* GPIO2_15 */
+			gpios = <&gpio2 15 0>;
 			linux,code = <114>; /* KEY_VOLUMEDOWN */
 		};
 	};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 099cd84..3b15cdc 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -119,7 +119,7 @@
 				};
 			};
 
-			gpio0: gpio at 53f84000 { /* GPIO1 */
+			gpio1: gpio at 53f84000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
 				reg = <0x53f84000 0x4000>;
 				interrupts = <50 51>;
@@ -129,7 +129,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio1: gpio at 53f88000 { /* GPIO2 */
+			gpio2: gpio at 53f88000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
 				reg = <0x53f88000 0x4000>;
 				interrupts = <52 53>;
@@ -139,7 +139,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio2: gpio at 53f8c000 { /* GPIO3 */
+			gpio3: gpio at 53f8c000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
 				reg = <0x53f8c000 0x4000>;
 				interrupts = <54 55>;
@@ -149,7 +149,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio3: gpio at 53f90000 { /* GPIO4 */
+			gpio4: gpio at 53f90000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
 				reg = <0x53f90000 0x4000>;
 				interrupts = <56 57>;
@@ -187,7 +187,7 @@
 				status = "disabled";
 			};
 
-			gpio4: gpio at 53fdc000 { /* GPIO5 */
+			gpio5: gpio at 53fdc000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
 				reg = <0x53fdc000 0x4000>;
 				interrupts = <103 104>;
@@ -197,7 +197,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio5: gpio at 53fe0000 { /* GPIO6 */
+			gpio6: gpio at 53fe0000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
 				reg = <0x53fe0000 0x4000>;
 				interrupts = <105 106>;
@@ -207,7 +207,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio6: gpio at 53fe4000 { /* GPIO7 */
+			gpio7: gpio at 53fe4000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
 				reg = <0x53fe4000 0x4000>;
 				interrupts = <107 108>;
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 072974e..cd11ab0 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -34,8 +34,8 @@
 			};
 
 			usdhc at 02198000 { /* uSDHC3 */
-				cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
-				wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
+				cd-gpios = <&gpio6 11 0>;
+				wp-gpios = <&gpio6 14 0>;
 				status = "okay";
 			};
 
@@ -55,7 +55,7 @@
 
 		debug-led {
 			label = "Heartbeat";
-			gpios = <&gpio2 25 0>; /* GPIO3_25 */
+			gpios = <&gpio3 25 0>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 7dda599..9d0bf4b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -247,7 +247,7 @@
 				interrupts = <0 55 0x04>;
 			};
 
-			gpio0: gpio at 0209c000 { /* GPIO1 */
+			gpio1: gpio at 0209c000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 				reg = <0x0209c000 0x4000>;
 				interrupts = <0 66 0x04 0 67 0x04>;
@@ -257,7 +257,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio1: gpio at 020a0000 { /* GPIO2 */
+			gpio2: gpio at 020a0000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 				reg = <0x020a0000 0x4000>;
 				interrupts = <0 68 0x04 0 69 0x04>;
@@ -267,7 +267,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio2: gpio at 020a4000 { /* GPIO3 */
+			gpio3: gpio at 020a4000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 				reg = <0x020a4000 0x4000>;
 				interrupts = <0 70 0x04 0 71 0x04>;
@@ -277,7 +277,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio3: gpio at 020a8000 { /* GPIO4 */
+			gpio4: gpio at 020a8000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 				reg = <0x020a8000 0x4000>;
 				interrupts = <0 72 0x04 0 73 0x04>;
@@ -287,7 +287,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio4: gpio at 020ac000 { /* GPIO5 */
+			gpio5: gpio at 020ac000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 				reg = <0x020ac000 0x4000>;
 				interrupts = <0 74 0x04 0 75 0x04>;
@@ -297,7 +297,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio5: gpio at 020b0000 { /* GPIO6 */
+			gpio6: gpio at 020b0000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 				reg = <0x020b0000 0x4000>;
 				interrupts = <0 76 0x04 0 77 0x04>;
@@ -307,7 +307,7 @@
 				#interrupt-cells = <1>;
 			};
 
-			gpio6: gpio at 020b4000 { /* GPIO7 */
+			gpio7: gpio at 020b4000 {
 				compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 				reg = <0x020b4000 0x4000>;
 				interrupts = <0 78 0x04 0 79 0x04>;
-- 
1.7.5.4

[PATCH V2 1/7] dts/imx: rename gpio labels to consistent with hw spec

[Shawn Guo]

On Tue, Dec 13, 2011 at 02:25:24PM +0800, Richard Zhao wrote:
> GPIO1/GPIO2/... is more readable than GPIO0/GPIO1/... .
> Remove redundant gpio comments.
> 
If we want to make this change, it's really more than just gpio, all
phandle name numbering should be changed to keep consistency.  You may
want to make the same change on uart as well.

-- 
Regards,
Shawn

> Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> ---
>  arch/arm/boot/dts/imx51-babbage.dts   |   11 +++++------
>  arch/arm/boot/dts/imx51.dtsi          |    8 ++++----
>  arch/arm/boot/dts/imx53-ard.dts       |   16 ++++++++--------
>  arch/arm/boot/dts/imx53-evk.dts       |   15 +++++++--------
>  arch/arm/boot/dts/imx53-qsb.dts       |   16 ++++++++--------
>  arch/arm/boot/dts/imx53-smd.dts       |   13 ++++++-------
>  arch/arm/boot/dts/imx53.dtsi          |   14 +++++++-------
>  arch/arm/boot/dts/imx6q-sabreauto.dts |    6 +++---
>  arch/arm/boot/dts/imx6q.dtsi          |   14 +++++++-------
>  9 files changed, 55 insertions(+), 58 deletions(-)

[PATCH V2 1/7] dts/imx: rename gpio labels to consistent with hw spec

[Richard Zhao]

On Tue, Dec 13, 2011 at 05:41:01PM +0800, Shawn Guo wrote:
> On Tue, Dec 13, 2011 at 02:25:24PM +0800, Richard Zhao wrote:
> > GPIO1/GPIO2/... is more readable than GPIO0/GPIO1/... .
> > Remove redundant gpio comments.
> > 
> If we want to make this change, it's really more than just gpio, all
> phandle name numbering should be changed to keep consistency.  You may
> want to make the same change on uart as well.
ok. I'll include uart renameing too in next version.

Thanks
Richard
> 
> -- 
> Regards,
> Shawn
> 
> > Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> > ---
> >  arch/arm/boot/dts/imx51-babbage.dts   |   11 +++++------
> >  arch/arm/boot/dts/imx51.dtsi          |    8 ++++----
> >  arch/arm/boot/dts/imx53-ard.dts       |   16 ++++++++--------
> >  arch/arm/boot/dts/imx53-evk.dts       |   15 +++++++--------
> >  arch/arm/boot/dts/imx53-qsb.dts       |   16 ++++++++--------
> >  arch/arm/boot/dts/imx53-smd.dts       |   13 ++++++-------
> >  arch/arm/boot/dts/imx53.dtsi          |   14 +++++++-------
> >  arch/arm/boot/dts/imx6q-sabreauto.dts |    6 +++---
> >  arch/arm/boot/dts/imx6q.dtsi          |   14 +++++++-------
> >  9 files changed, 55 insertions(+), 58 deletions(-)
> 
> 
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> linux-arm-kernel mailing list
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> 

[PATCH V2 2/7] arm/imx6: add imx6q sabrelite board support

[Richard Zhao]

- Add basic board dts file
- Add board compatible string to mach-imx6q.

Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |   55 +++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/mach-imx6q.c        |    1 +
 2 files changed, 56 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6q-sabrelite.dts

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
new file mode 100644
index 0000000..381f030
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx6q.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad SABRE Lite Board";
+	compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
+
+	cpus {
+		cpu at 0 {
+			clock-frequency = <996000000>;
+		};
+	};
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	soc {
+		aips-bus at 02100000 { /* AIPS2 */
+			enet at 02188000 {
+				phy-mode = "rgmii";
+				phy-reset-gpios = <&gpio3 23 0>;
+				status = "okay";
+			};
+
+			usdhc at 02198000 { /* uSDHC3 */
+				cd-gpios = <&gpio7 0 0>;
+				wp-gpios = <&gpio7 1 0>;
+				status = "okay";
+			};
+
+			usdhc at 0219c000 { /* uSDHC4 */
+				cd-gpios = <&gpio2 6 0>;
+				wp-gpios = <&gpio2 7 0>;
+				status = "okay";
+			};
+
+			uart1: uart at 021e8000 { /* UART2 */
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 8deb012..d24d6c4 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -73,6 +73,7 @@ static struct sys_timer imx6q_timer = {
 
 static const char *imx6q_dt_compat[] __initdata = {
 	"fsl,imx6q-sabreauto",
+	"fsl,imx6q-sabrelite",
 	NULL,
 };
 
-- 
1.7.5.4

[PATCH V2 2/7] arm/imx6: add imx6q sabrelite board support

[Shawn Guo]

On Tue, Dec 13, 2011 at 02:25:25PM +0800, Richard Zhao wrote:
> - Add basic board dts file
> - Add board compatible string to mach-imx6q.
> 
> Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> ---
>  arch/arm/boot/dts/imx6q-sabrelite.dts |   55 +++++++++++++++++++++++++++++++++
>  arch/arm/mach-imx/mach-imx6q.c        |    1 +
>  2 files changed, 56 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/imx6q-sabrelite.dts
> 

Documentation/devicetree/bindings/arm/fsl.txt needs to be updated to
include compatible string for this sabrelite board.

> diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
> new file mode 100644
> index 0000000..381f030
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
> @@ -0,0 +1,55 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "imx6q.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX6 Quad SABRE Lite Board";
> +	compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
> +
> +	cpus {
> +		cpu at 0 {
> +			clock-frequency = <996000000>;
> +		};

I do not follow why we need to have cpu frequency encoded in board
level dts.  To me, what frequency the cpu is capable of running at
is really soc specific thing.  So putting this data in
imx6q-sabrelite.dts is kinda suggesting that imx6q soc on this
sabrelite board can run at 996000000, while on other boards like
sabreauto/arm2 can only run at other frequency.  This is seems different
from what I heard from Freescale internal development team.

-- 
Regards,
Shawn

> +	};
> +
> +	memory {
> +		reg = <0x10000000 0x40000000>;
> +	};
> +
> +	soc {
> +		aips-bus at 02100000 { /* AIPS2 */
> +			enet at 02188000 {
> +				phy-mode = "rgmii";
> +				phy-reset-gpios = <&gpio3 23 0>;
> +				status = "okay";
> +			};
> +
> +			usdhc at 02198000 { /* uSDHC3 */
> +				cd-gpios = <&gpio7 0 0>;
> +				wp-gpios = <&gpio7 1 0>;
> +				status = "okay";
> +			};
> +
> +			usdhc at 0219c000 { /* uSDHC4 */
> +				cd-gpios = <&gpio2 6 0>;
> +				wp-gpios = <&gpio2 7 0>;
> +				status = "okay";
> +			};
> +
> +			uart1: uart at 021e8000 { /* UART2 */
> +				status = "okay";
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> index 8deb012..d24d6c4 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -73,6 +73,7 @@ static struct sys_timer imx6q_timer = {
>  
>  static const char *imx6q_dt_compat[] __initdata = {
>  	"fsl,imx6q-sabreauto",
> +	"fsl,imx6q-sabrelite",
>  	NULL,
>  };
>  
> -- 
> 1.7.5.4

[PATCH V2 2/7] arm/imx6: add imx6q sabrelite board support

[Richard Zhao]

Hi Shawn,
On Tue, Dec 13, 2011 at 07:56:55PM +0800, Shawn Guo wrote:
> On Tue, Dec 13, 2011 at 02:25:25PM +0800, Richard Zhao wrote:
> > - Add basic board dts file
> > - Add board compatible string to mach-imx6q.
> > 
> > Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> > ---
> >  arch/arm/boot/dts/imx6q-sabrelite.dts |   55 +++++++++++++++++++++++++++++++++
> >  arch/arm/mach-imx/mach-imx6q.c        |    1 +
> >  2 files changed, 56 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/boot/dts/imx6q-sabrelite.dts
> > 
> 
> Documentation/devicetree/bindings/arm/fsl.txt needs to be updated to
> include compatible string for this sabrelite board.
ah, thanks.
> 
> > diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
> > new file mode 100644
> > index 0000000..381f030
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
> > @@ -0,0 +1,55 @@
> > +/*
> > + * Copyright 2011 Freescale Semiconductor, Inc.
> > + * Copyright 2011 Linaro Ltd.
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/dts-v1/;
> > +/include/ "imx6q.dtsi"
> > +
> > +/ {
> > +	model = "Freescale i.MX6 Quad SABRE Lite Board";
> > +	compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
> > +
> > +	cpus {
> > +		cpu at 0 {
> > +			clock-frequency = <996000000>;
> > +		};
> 
> I do not follow why we need to have cpu frequency encoded in board
> level dts.  To me, what frequency the cpu is capable of running at
> is really soc specific thing.  So putting this data in
> imx6q-sabrelite.dts is kinda suggesting that imx6q soc on this
> sabrelite board can run at 996000000, while on other boards like
> sabreauto/arm2 can only run at other frequency.  This is seems different
> from what I heard from Freescale internal development team.
1G operation needs a certain external voltage condition, though we have
internal regulater. Boards that don't meet the condition have to fall back
to lower frequency.
>From software side view, I refer to Freescale software release. please see
http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=blob;f=arch/arm/mach-mx6/cpu_op-mx6.c;h=30a4346282ea5c332b4c48bf6a2d644abd9f31db;hb=imx_2.6.38_11.11.01

and for imx53, there' also different max freq board:
http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=blob;f=arch/arm/mach-mx5/mx53_wp.c;h=a63bae42fb661c161cab99d61f4a3108305b0f55;hb=refs/heads/imx_2.6.35_11.09.01

IMHO, even the board has limitations, we'd better give an option to support
it if it's possible.

Thanks
Richard

> 
> -- 
> Regards,
> Shawn
> 
> > +	};
> > +
> > +	memory {
> > +		reg = <0x10000000 0x40000000>;
> > +	};
> > +
> > +	soc {
> > +		aips-bus at 02100000 { /* AIPS2 */
> > +			enet at 02188000 {
> > +				phy-mode = "rgmii";
> > +				phy-reset-gpios = <&gpio3 23 0>;
> > +				status = "okay";
> > +			};
> > +
> > +			usdhc at 02198000 { /* uSDHC3 */
> > +				cd-gpios = <&gpio7 0 0>;
> > +				wp-gpios = <&gpio7 1 0>;
> > +				status = "okay";
> > +			};
> > +
> > +			usdhc at 0219c000 { /* uSDHC4 */
> > +				cd-gpios = <&gpio2 6 0>;
> > +				wp-gpios = <&gpio2 7 0>;
> > +				status = "okay";
> > +			};
> > +
> > +			uart1: uart at 021e8000 { /* UART2 */
> > +				status = "okay";
> > +			};
> > +		};
> > +	};
> > +};
> > diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> > index 8deb012..d24d6c4 100644
> > --- a/arch/arm/mach-imx/mach-imx6q.c
> > +++ b/arch/arm/mach-imx/mach-imx6q.c
> > @@ -73,6 +73,7 @@ static struct sys_timer imx6q_timer = {
> >  
> >  static const char *imx6q_dt_compat[] __initdata = {
> >  	"fsl,imx6q-sabreauto",
> > +	"fsl,imx6q-sabrelite",
> >  	NULL,
> >  };
> >  
> > -- 
> > 1.7.5.4
> 

[PATCH V2 2/7] arm/imx6: add imx6q sabrelite board support

[Shawn Guo]

On Tue, Dec 13, 2011 at 08:54:01PM +0800, Richard Zhao wrote:
> > > +	cpus {
> > > +		cpu at 0 {
> > > +			clock-frequency = <996000000>;
> > > +		};
> > 
> > I do not follow why we need to have cpu frequency encoded in board
> > level dts.  To me, what frequency the cpu is capable of running at
> > is really soc specific thing.  So putting this data in
> > imx6q-sabrelite.dts is kinda suggesting that imx6q soc on this
> > sabrelite board can run at 996000000, while on other boards like
> > sabreauto/arm2 can only run at other frequency.  This is seems different
> > from what I heard from Freescale internal development team.
> 1G operation needs a certain external voltage condition, though we have
> internal regulater. Boards that don't meet the condition have to fall back
> to lower frequency.
> From software side view, I refer to Freescale software release. please see
> http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=blob;f=arch/arm/mach-mx6/cpu_op-mx6.c;h=30a4346282ea5c332b4c48bf6a2d644abd9f31db;hb=imx_2.6.38_11.11.01
> 
> and for imx53, there' also different max freq board:
> http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=blob;f=arch/arm/mach-mx5/mx53_wp.c;h=a63bae42fb661c161cab99d61f4a3108305b0f55;hb=refs/heads/imx_2.6.35_11.09.01
> 
> IMHO, even the board has limitations, we'd better give an option to support
> it if it's possible.
> 
I understand all these things.  What I was suggesting is this option
should not be provided by the dts at all.  For example, you have one
sabrelite that can provide voltage for imx6q to run at 1GHz, while
I have another sabrelite board which can only provide voltage for imx6q
to run at 800MHz.  With your patches accepted, the same mainline
kernel/dtb will work on your sabrelite board while will not on mine.
Since both of us are running sabrelite board, how do I should know I
need to change the clock-frequency in imx6q-sabreauto.dts for my
sabrelite board?

-- 
Regards,
Shawn

[PATCH V2 2/7] arm/imx6: add imx6q sabrelite board support

[Sascha Hauer]

On Tue, Dec 13, 2011 at 09:33:50PM +0800, Shawn Guo wrote:
> On Tue, Dec 13, 2011 at 08:54:01PM +0800, Richard Zhao wrote:
> > > > +	cpus {
> > > > +		cpu at 0 {
> > > > +			clock-frequency = <996000000>;
> > > > +		};
> > > 
> > > I do not follow why we need to have cpu frequency encoded in board
> > > level dts.  To me, what frequency the cpu is capable of running at
> > > is really soc specific thing.  So putting this data in
> > > imx6q-sabrelite.dts is kinda suggesting that imx6q soc on this
> > > sabrelite board can run at 996000000, while on other boards like
> > > sabreauto/arm2 can only run at other frequency.  This is seems different
> > > from what I heard from Freescale internal development team.
> > 1G operation needs a certain external voltage condition, though we have
> > internal regulater. Boards that don't meet the condition have to fall back
> > to lower frequency.
> > From software side view, I refer to Freescale software release. please see
> > http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=blob;f=arch/arm/mach-mx6/cpu_op-mx6.c;h=30a4346282ea5c332b4c48bf6a2d644abd9f31db;hb=imx_2.6.38_11.11.01
> > 
> > and for imx53, there' also different max freq board:
> > http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=blob;f=arch/arm/mach-mx5/mx53_wp.c;h=a63bae42fb661c161cab99d61f4a3108305b0f55;hb=refs/heads/imx_2.6.35_11.09.01
> > 
> > IMHO, even the board has limitations, we'd better give an option to support
> > it if it's possible.
> > 
> I understand all these things.  What I was suggesting is this option
> should not be provided by the dts at all.

Yes. If it's not provided the cpufreq layer should either assume 800MHz
is the highest value which is safe on all boards or it could read the
current frequency from the hardware. If this is 1GHz this value is
obviously safe.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH V2 2/7] arm/imx6: add imx6q sabrelite board support

[Richard Zhao]

On Wed, Dec 14, 2011 at 12:05:58PM +0100, Sascha Hauer wrote:
> On Tue, Dec 13, 2011 at 09:33:50PM +0800, Shawn Guo wrote:
> > On Tue, Dec 13, 2011 at 08:54:01PM +0800, Richard Zhao wrote:
> > > > > +	cpus {
> > > > > +		cpu at 0 {
> > > > > +			clock-frequency = <996000000>;
> > > > > +		};
> > > > 
> > > > I do not follow why we need to have cpu frequency encoded in board
> > > > level dts.  To me, what frequency the cpu is capable of running at
> > > > is really soc specific thing.  So putting this data in
> > > > imx6q-sabrelite.dts is kinda suggesting that imx6q soc on this
> > > > sabrelite board can run at 996000000, while on other boards like
> > > > sabreauto/arm2 can only run at other frequency.  This is seems different
> > > > from what I heard from Freescale internal development team.
> > > 1G operation needs a certain external voltage condition, though we have
> > > internal regulater. Boards that don't meet the condition have to fall back
> > > to lower frequency.
> > > From software side view, I refer to Freescale software release. please see
> > > http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=blob;f=arch/arm/mach-mx6/cpu_op-mx6.c;h=30a4346282ea5c332b4c48bf6a2d644abd9f31db;hb=imx_2.6.38_11.11.01
> > > 
> > > and for imx53, there' also different max freq board:
> > > http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=blob;f=arch/arm/mach-mx5/mx53_wp.c;h=a63bae42fb661c161cab99d61f4a3108305b0f55;hb=refs/heads/imx_2.6.35_11.09.01
> > > 
> > > IMHO, even the board has limitations, we'd better give an option to support
> > > it if it's possible.
> > > 
> > I understand all these things.  What I was suggesting is this option
> > should not be provided by the dts at all.
> 
> Yes. If it's not provided the cpufreq layer should either assume 800MHz
> is the highest value which is safe on all boards or it could read the
> current frequency from the hardware. If this is 1GHz this value is
> obviously safe.
Actually, you'd better not depend on uboot to setting the highest cpu freq.
At least current freescale internel uboot don't set 1G.

Thanks
Richard
> 
> Sascha
> 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH V2 3/7] arm/imx: cpufreq: add multi-core support

[Richard Zhao]

Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
---
 arch/arm/plat-mxc/cpufreq.c |   99 ++++++++++++++++++++++++++++--------------
 1 files changed, 66 insertions(+), 33 deletions(-)

diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index adbff70..85d037f 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -22,6 +22,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <asm/cpu.h>
 #include <mach/hardware.h>
 #include <mach/clock.h>
 
@@ -34,6 +35,7 @@ static int cpu_freq_khz_min;
 static int cpu_freq_khz_max;
 
 static struct clk *cpu_clk;
+static DEFINE_MUTEX(cpu_lock);
 static struct cpufreq_frequency_table *imx_freq_table;
 
 static int cpu_op_nr;
@@ -59,17 +61,11 @@ static int set_cpu_freq(int freq)
 
 static int mxc_verify_speed(struct cpufreq_policy *policy)
 {
-	if (policy->cpu != 0)
-		return -EINVAL;
-
 	return cpufreq_frequency_table_verify(policy, imx_freq_table);
 }
 
 static unsigned int mxc_get_speed(unsigned int cpu)
 {
-	if (cpu)
-		return 0;
-
 	return clk_get_rate(cpu_clk) / 1000;
 }
 
@@ -77,23 +73,49 @@ static int mxc_set_target(struct cpufreq_policy *policy,
 			  unsigned int target_freq, unsigned int relation)
 {
 	struct cpufreq_freqs freqs;
-	int freq_Hz;
+	int freq_Hz, cpu;
 	int ret = 0;
 	unsigned int index;
 
+	mutex_lock(&cpu_lock);
+
 	cpufreq_frequency_table_target(policy, imx_freq_table,
 			target_freq, relation, &index);
 	freq_Hz = imx_freq_table[index].frequency * 1000;
 
 	freqs.old = clk_get_rate(cpu_clk) / 1000;
-	freqs.new = freq_Hz / 1000;
-	freqs.cpu = 0;
+	freqs.new = clk_round_rate(cpu_clk, freq_Hz);
+	freqs.new = (freqs.new ? freqs.new : freq_Hz) / 1000;
 	freqs.flags = 0;
-	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+	if (freqs.old == freqs.new) {
+		mutex_unlock(&cpu_lock);
+		return 0;
+	}
+
+	for_each_possible_cpu(cpu) {
+		freqs.cpu = cpu;
+		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+	}
 
 	ret = set_cpu_freq(freq_Hz);
 
-	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+#ifdef CONFIG_SMP
+	/* loops_per_jiffy is not updated by the cpufreq core for SMP systems.
+	 * So update it for all CPUs.
+	 */
+	for_each_possible_cpu(cpu)
+		per_cpu(cpu_data, cpu).loops_per_jiffy =
+		cpufreq_scale(per_cpu(cpu_data, cpu).loops_per_jiffy,
+					freqs.old, freqs.new);
+#endif
+
+	for_each_possible_cpu(cpu) {
+		freqs.cpu = cpu;
+		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+	}
+
+	mutex_unlock(&cpu_lock);
 
 	return ret;
 }
@@ -105,7 +127,7 @@ static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)
 
 	printk(KERN_INFO "i.MXC CPU frequency driver\n");
 
-	if (policy->cpu != 0)
+	if (policy->cpu >= num_possible_cpus())
 		return -EINVAL;
 
 	if (!get_cpu_op)
@@ -117,37 +139,45 @@ static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)
 		return PTR_ERR(cpu_clk);
 	}
 
-	cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+	mutex_lock(&cpu_lock);
+	if (!imx_freq_table) {
+		cpu_op_tbl = get_cpu_op(&cpu_op_nr);
 
-	cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
-	cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
+		cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
+		cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
 
-	imx_freq_table = kmalloc(
-		sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
-			GFP_KERNEL);
-	if (!imx_freq_table) {
-		ret = -ENOMEM;
-		goto err1;
-	}
+		imx_freq_table = kmalloc(sizeof(struct cpufreq_frequency_table)
+					* (cpu_op_nr + 1), GFP_KERNEL);
+		if (!imx_freq_table) {
+			ret = -ENOMEM;
+			mutex_unlock(&cpu_lock);
+			goto err1;
+		}
 
-	for (i = 0; i < cpu_op_nr; i++) {
-		imx_freq_table[i].index = i;
-		imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
+		for (i = 0; i < cpu_op_nr; i++) {
+			imx_freq_table[i].index = i;
+			imx_freq_table[i].frequency =
+					cpu_op_tbl[i].cpu_rate / 1000;
 
-		if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
-			cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
+			if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
+				cpu_freq_khz_min =
+					cpu_op_tbl[i].cpu_rate / 1000;
 
-		if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
-			cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
-	}
+			if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
+				cpu_freq_khz_max =
+					cpu_op_tbl[i].cpu_rate / 1000;
+		}
 
-	imx_freq_table[i].index = i;
-	imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
+		imx_freq_table[i].index = i;
+		imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
+	}
+	mutex_unlock(&cpu_lock);
 
 	policy->cur = clk_get_rate(cpu_clk) / 1000;
 	policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
 	policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
-
+	policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
+	cpumask_setall(policy->cpus);
 	/* Manual states, that PLL stabilizes in two CLK32 periods */
 	policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
 
@@ -174,7 +204,10 @@ static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
 
 	set_cpu_freq(cpu_freq_khz_max * 1000);
 	clk_put(cpu_clk);
+	mutex_lock(&cpu_lock);
 	kfree(imx_freq_table);
+	imx_freq_table = NULL;
+	mutex_unlock(&cpu_lock);
 	return 0;
 }
 
-- 
1.7.5.4

[PATCH V2 4/7] arm/imx: fix cpufreq section mismatch

[Richard Zhao]

WARNING: arch/arm/plat-mxc/built-in.o(.data+0x488): Section mismatch in reference from the variable mxc_driver to the function .init.text:mxc_cpufreq_init()
The variable mxc_driver references
the function __init mxc_cpufreq_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
---
 arch/arm/plat-mxc/cpufreq.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 85d037f..71e0d09 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -120,7 +120,7 @@ static int mxc_set_target(struct cpufreq_policy *policy,
 	return ret;
 }
 
-static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)
+static int mxc_cpufreq_init(struct cpufreq_policy *policy)
 {
 	int ret;
 	int i;
-- 
1.7.5.4

[PATCH V2 4/7] arm/imx: fix cpufreq section mismatch

[Richard Zhao]

can this fix go in?

Thanks
Richard
On Tue, Dec 13, 2011 at 02:25:27PM +0800, Richard Zhao wrote:
> WARNING: arch/arm/plat-mxc/built-in.o(.data+0x488): Section mismatch in reference from the variable mxc_driver to the function .init.text:mxc_cpufreq_init()
> The variable mxc_driver references
> the function __init mxc_cpufreq_init()
> If the reference is valid then annotate the
> variable with __init* or __refdata (see linux/init.h) or name the variable:
> *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
> 
> Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> ---
>  arch/arm/plat-mxc/cpufreq.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
> index 85d037f..71e0d09 100644
> --- a/arch/arm/plat-mxc/cpufreq.c
> +++ b/arch/arm/plat-mxc/cpufreq.c
> @@ -120,7 +120,7 @@ static int mxc_set_target(struct cpufreq_policy *policy,
>  	return ret;
>  }
>  
> -static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)
> +static int mxc_cpufreq_init(struct cpufreq_policy *policy)
>  {
>  	int ret;
>  	int i;
> -- 
> 1.7.5.4
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

[PATCH V2 5/7] arm/imx: add cpu_voltage to cpu_op

[Richard Zhao]

Help cpu_op table have cpu_voltage info and cpufreq driver
to change cpu voltage.

Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
---
 arch/arm/plat-mxc/include/mach/mxc.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a4d36d6..1ff7fe7 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -166,6 +166,7 @@ extern unsigned int __mxc_cpu_type;
 
 struct cpu_op {
 	u32 cpu_rate;
+	int cpu_voltage;
 };
 
 int tzic_enable_wake(int is_idle);
-- 
1.7.5.4

[PATCH V2 6/7] arm/imx6q: register arm_clk as cpu_clk to clkdev

[Richard Zhao]

cpufreq needs cpu_clk to change frequency.

Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
---
 arch/arm/mach-imx/clock-imx6q.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 039a7ab..2525380 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -1911,6 +1911,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
 	_REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
 	_REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
+	_REGISTER_CLOCK(NULL, "cpu_clk", arm_clk),
 };
 
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
-- 
1.7.5.4

[PATCH V2 7/7] arm/imx6q: add cpufreq support

[Richard Zhao]

use cpu0 node property clock-frequency to check max frequency.

Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
---
 arch/arm/mach-imx/Kconfig        |    1 +
 arch/arm/mach-imx/Makefile       |    2 +-
 arch/arm/mach-imx/cpu_op-imx6q.c |   69 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-imx/cpu_op-imx6q.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index fbd414b..21e472f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -834,6 +834,7 @@ comment "i.MX6 family:"
 
 config SOC_IMX6Q
 	bool "i.MX6 Quad support"
+	select ARCH_HAS_CPUFREQ
 	select ARM_GIC
 	select CACHE_L2X0
 	select CPU_V7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9cf630a..2dfe4a7 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -72,7 +72,7 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o cpu_op-imx6q.o
 
 # i.MX5 based machines
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
diff --git a/arch/arm/mach-imx/cpu_op-imx6q.c b/arch/arm/mach-imx/cpu_op-imx6q.c
new file mode 100644
index 0000000..d24e081
--- /dev/null
+++ b/arch/arm/mach-imx/cpu_op-imx6q.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/of.h>
+#include <mach/hardware.h>
+
+static int arm_max_freq_idx;
+
+/* operating point(op): 0 - 1GHz; 1 - 800MHz, 3 - 400MHz, 4  - 160MHz */
+static struct cpu_op mx6q_cpu_op[] = {
+	{
+		.cpu_rate = 996000000,
+		.cpu_voltage = 1225000,
+	},
+	{
+		.cpu_rate = 792000000,
+		.cpu_voltage = 1100000,
+	},
+	{
+		.cpu_rate = 396000000,
+		.cpu_voltage = 950000,
+	},
+	{
+		.cpu_rate = 198000000,
+		.cpu_voltage = 850000,
+	},
+};
+
+struct cpu_op *mx6q_get_cpu_op(int *op)
+{
+	struct device_node *cpu0;
+	u32 val;
+	int i;
+
+	cpu0 = of_find_node_by_path("/cpus/cpu at 0");
+	if (cpu0 && !of_property_read_u32(cpu0, "clock-frequency", &val)) {
+		for (i = 0; i < ARRAY_SIZE(mx6q_cpu_op); i++) {
+			if (val >= mx6q_cpu_op[i].cpu_rate) {
+				arm_max_freq_idx = i;
+				break;
+			}
+		}
+	}
+	if (cpu0)
+		of_node_put(cpu0);
+	*op = ARRAY_SIZE(mx6q_cpu_op) - arm_max_freq_idx;
+	return mx6q_cpu_op + arm_max_freq_idx;
+}
+
+static int __init mx6q_cpu_op_init(void)
+{
+	get_cpu_op = mx6q_get_cpu_op;
+	return 0;
+}
+
+core_initcall(mx6q_cpu_op_init);
-- 
1.7.5.4

[PATCH V2 7/7] arm/imx6q: add cpufreq support

[Sascha Hauer]

On Tue, Dec 13, 2011 at 02:25:30PM +0800, Richard Zhao wrote:
> use cpu0 node property clock-frequency to check max frequency.
> 
> Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> ---
>  arch/arm/mach-imx/Kconfig        |    1 +
>  arch/arm/mach-imx/Makefile       |    2 +-
>  arch/arm/mach-imx/cpu_op-imx6q.c |   69 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 71 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-imx/cpu_op-imx6q.c
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index fbd414b..21e472f 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -834,6 +834,7 @@ comment "i.MX6 family:"
>  
>  config SOC_IMX6Q
>  	bool "i.MX6 Quad support"
> +	select ARCH_HAS_CPUFREQ
>  	select ARM_GIC
>  	select CACHE_L2X0
>  	select CPU_V7
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index 9cf630a..2dfe4a7 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -72,7 +72,7 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
>  obj-$(CONFIG_SMP) += platsmp.o
>  obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
>  obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
> -obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
> +obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o cpu_op-imx6q.o
>  
>  # i.MX5 based machines
>  obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
> diff --git a/arch/arm/mach-imx/cpu_op-imx6q.c b/arch/arm/mach-imx/cpu_op-imx6q.c
> new file mode 100644
> index 0000000..d24e081
> --- /dev/null
> +++ b/arch/arm/mach-imx/cpu_op-imx6q.c
> @@ -0,0 +1,69 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/types.h>
> +#include <linux/kernel.h>
> +#include <linux/string.h>
> +#include <linux/of.h>
> +#include <mach/hardware.h>
> +
> +static int arm_max_freq_idx;

This is only used in mx6q_get_cpu_op()

Also shouldn't this be initialized with 1? From what you
said 800MHz is safe for all boards whereas 1GHz is not.

Sascha

> +
> +/* operating point(op): 0 - 1GHz; 1 - 800MHz, 3 - 400MHz, 4  - 160MHz */
> +static struct cpu_op mx6q_cpu_op[] = {
> +	{
> +		.cpu_rate = 996000000,
> +		.cpu_voltage = 1225000,
> +	},
> +	{
> +		.cpu_rate = 792000000,
> +		.cpu_voltage = 1100000,
> +	},
> +	{
> +		.cpu_rate = 396000000,
> +		.cpu_voltage = 950000,
> +	},
> +	{
> +		.cpu_rate = 198000000,
> +		.cpu_voltage = 850000,
> +	},
> +};
> +
> +struct cpu_op *mx6q_get_cpu_op(int *op)
> +{
> +	struct device_node *cpu0;
> +	u32 val;
> +	int i;
> +
> +	cpu0 = of_find_node_by_path("/cpus/cpu at 0");
> +	if (cpu0 && !of_property_read_u32(cpu0, "clock-frequency", &val)) {
> +		for (i = 0; i < ARRAY_SIZE(mx6q_cpu_op); i++) {
> +			if (val >= mx6q_cpu_op[i].cpu_rate) {
> +				arm_max_freq_idx = i;
> +				break;
> +			}
> +		}
> +	}
> +	if (cpu0)
> +		of_node_put(cpu0);
> +	*op = ARRAY_SIZE(mx6q_cpu_op) - arm_max_freq_idx;
> +	return mx6q_cpu_op + arm_max_freq_idx;
> +}
> +
> +static int __init mx6q_cpu_op_init(void)
> +{
> +	get_cpu_op = mx6q_get_cpu_op;
> +	return 0;
> +}
> +
> +core_initcall(mx6q_cpu_op_init);
> -- 
> 1.7.5.4
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH V2 7/7] arm/imx6q: add cpufreq support

[Richard Zhao]

On Tue, Dec 13, 2011 at 11:23:15AM +0100, Sascha Hauer wrote:
> On Tue, Dec 13, 2011 at 02:25:30PM +0800, Richard Zhao wrote:
> > use cpu0 node property clock-frequency to check max frequency.
> > 
> > Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> > ---
> >  arch/arm/mach-imx/Kconfig        |    1 +
> >  arch/arm/mach-imx/Makefile       |    2 +-
> >  arch/arm/mach-imx/cpu_op-imx6q.c |   69 ++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 71 insertions(+), 1 deletions(-)
> >  create mode 100644 arch/arm/mach-imx/cpu_op-imx6q.c
> > 
> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > index fbd414b..21e472f 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -834,6 +834,7 @@ comment "i.MX6 family:"
> >  
> >  config SOC_IMX6Q
> >  	bool "i.MX6 Quad support"
> > +	select ARCH_HAS_CPUFREQ
> >  	select ARM_GIC
> >  	select CACHE_L2X0
> >  	select CPU_V7
> > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> > index 9cf630a..2dfe4a7 100644
> > --- a/arch/arm/mach-imx/Makefile
> > +++ b/arch/arm/mach-imx/Makefile
> > @@ -72,7 +72,7 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
> >  obj-$(CONFIG_SMP) += platsmp.o
> >  obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
> >  obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
> > -obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
> > +obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o cpu_op-imx6q.o
> >  
> >  # i.MX5 based machines
> >  obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
> > diff --git a/arch/arm/mach-imx/cpu_op-imx6q.c b/arch/arm/mach-imx/cpu_op-imx6q.c
> > new file mode 100644
> > index 0000000..d24e081
> > --- /dev/null
> > +++ b/arch/arm/mach-imx/cpu_op-imx6q.c
> > @@ -0,0 +1,69 @@
> > +/*
> > + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> > + */
> > +
> > +/*
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +#include <linux/types.h>
> > +#include <linux/kernel.h>
> > +#include <linux/string.h>
> > +#include <linux/of.h>
> > +#include <mach/hardware.h>
> > +
> > +static int arm_max_freq_idx;
> 
> This is only used in mx6q_get_cpu_op()
I'll move to local var
> 
> Also shouldn't this be initialized with 1? From what you
> said 800MHz is safe for all boards whereas 1GHz is not.
I'll fix it in next version.

Thanks
Richard
> 
> Sascha
> 
> > +
> > +/* operating point(op): 0 - 1GHz; 1 - 800MHz, 3 - 400MHz, 4  - 160MHz */
> > +static struct cpu_op mx6q_cpu_op[] = {
> > +	{
> > +		.cpu_rate = 996000000,
> > +		.cpu_voltage = 1225000,
> > +	},
> > +	{
> > +		.cpu_rate = 792000000,
> > +		.cpu_voltage = 1100000,
> > +	},
> > +	{
> > +		.cpu_rate = 396000000,
> > +		.cpu_voltage = 950000,
> > +	},
> > +	{
> > +		.cpu_rate = 198000000,
> > +		.cpu_voltage = 850000,
> > +	},
> > +};
> > +
> > +struct cpu_op *mx6q_get_cpu_op(int *op)
> > +{
> > +	struct device_node *cpu0;
> > +	u32 val;
> > +	int i;
> > +
> > +	cpu0 = of_find_node_by_path("/cpus/cpu at 0");
> > +	if (cpu0 && !of_property_read_u32(cpu0, "clock-frequency", &val)) {
> > +		for (i = 0; i < ARRAY_SIZE(mx6q_cpu_op); i++) {
> > +			if (val >= mx6q_cpu_op[i].cpu_rate) {
> > +				arm_max_freq_idx = i;
> > +				break;
> > +			}
> > +		}
> > +	}
> > +	if (cpu0)
> > +		of_node_put(cpu0);
> > +	*op = ARRAY_SIZE(mx6q_cpu_op) - arm_max_freq_idx;
> > +	return mx6q_cpu_op + arm_max_freq_idx;
> > +}
> > +
> > +static int __init mx6q_cpu_op_init(void)
> > +{
> > +	get_cpu_op = mx6q_get_cpu_op;
> > +	return 0;
> > +}
> > +
> > +core_initcall(mx6q_cpu_op_init);
> > -- 
> > 1.7.5.4
> > 
> > 
> > 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

[PATCH V2 7/7] arm/imx6q: add cpufreq support

[Rob Lee]

On 13 December 2011 04:38, Richard Zhao <richard.zhao@freescale.com> wrote:
> On Tue, Dec 13, 2011 at 11:23:15AM +0100, Sascha Hauer wrote:
>> On Tue, Dec 13, 2011 at 02:25:30PM +0800, Richard Zhao wrote:
>> > use cpu0 node property clock-frequency to check max frequency.
>> >
>> > Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
>> > ---
>> > ?arch/arm/mach-imx/Kconfig ? ? ? ?| ? ?1 +
>> > ?arch/arm/mach-imx/Makefile ? ? ? | ? ?2 +-
>> > ?arch/arm/mach-imx/cpu_op-imx6q.c | ? 69 ++++++++++++++++++++++++++++++++++++++
>> > ?3 files changed, 71 insertions(+), 1 deletions(-)
>> > ?create mode 100644 arch/arm/mach-imx/cpu_op-imx6q.c
>> >
>> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
>> > index fbd414b..21e472f 100644
>> > --- a/arch/arm/mach-imx/Kconfig
>> > +++ b/arch/arm/mach-imx/Kconfig
>> > @@ -834,6 +834,7 @@ comment "i.MX6 family:"
>> >
>> > ?config SOC_IMX6Q
>> > ? ? bool "i.MX6 Quad support"
>> > + ? select ARCH_HAS_CPUFREQ
>> > ? ? select ARM_GIC
>> > ? ? select CACHE_L2X0
>> > ? ? select CPU_V7
>> > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
>> > index 9cf630a..2dfe4a7 100644
>> > --- a/arch/arm/mach-imx/Makefile
>> > +++ b/arch/arm/mach-imx/Makefile
>> > @@ -72,7 +72,7 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
>> > ?obj-$(CONFIG_SMP) += platsmp.o
>> > ?obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
>> > ?obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
>> > -obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
>> > +obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o cpu_op-imx6q.o
>> >
>> > ?# i.MX5 based machines
>> > ?obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
>> > diff --git a/arch/arm/mach-imx/cpu_op-imx6q.c b/arch/arm/mach-imx/cpu_op-imx6q.c
>> > new file mode 100644
>> > index 0000000..d24e081
>> > --- /dev/null
>> > +++ b/arch/arm/mach-imx/cpu_op-imx6q.c
>> > @@ -0,0 +1,69 @@
>> > +/*
>> > + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
>> > + */
>> > +
>> > +/*
>> > + * The code contained herein is licensed under the GNU General Public
>> > + * License. You may obtain a copy of the GNU General Public License
>> > + * Version 2 or later at the following locations:
>> > + *
>> > + * http://www.opensource.org/licenses/gpl-license.html
>> > + * http://www.gnu.org/copyleft/gpl.html
>> > + */
>> > +
>> > +#include <linux/types.h>
>> > +#include <linux/kernel.h>
>> > +#include <linux/string.h>
>> > +#include <linux/of.h>
>> > +#include <mach/hardware.h>
>> > +
>> > +static int arm_max_freq_idx;
>>
>> This is only used in mx6q_get_cpu_op()
> I'll move to local var
>>
>> Also shouldn't this be initialized with 1? From what you
>> said 800MHz is safe for all boards whereas 1GHz is not.
> I'll fix it in next version.
>

Richard, I communicated with Hui Liu a couple of weeks ago about the
possibility of adding a "max_freq" kernel parameter to the i.MX6q
community u-boot, similiar to what has been done for the BSP u-boot.
If he is or has done this, it may be better to read and use this
kernel parameter from u-boot so that the same kernel can be used
between boards with and without the fix.  I'm not that familiar with
device tree yet but perhaps it provides another way to handle this.
Also keep in

> Thanks
> Richard
>>
>> Sascha
>>
>> > +
>> > +/* operating point(op): 0 - 1GHz; 1 - 800MHz, 3 - 400MHz, 4 ?- 160MHz */
>> > +static struct cpu_op mx6q_cpu_op[] = {
>> > + ? {
>> > + ? ? ? ? ? .cpu_rate = 996000000,
>> > + ? ? ? ? ? .cpu_voltage = 1225000,
>> > + ? },
>> > + ? {
>> > + ? ? ? ? ? .cpu_rate = 792000000,
>> > + ? ? ? ? ? .cpu_voltage = 1100000,
>> > + ? },
>> > + ? {
>> > + ? ? ? ? ? .cpu_rate = 396000000,
>> > + ? ? ? ? ? .cpu_voltage = 950000,
>> > + ? },
>> > + ? {
>> > + ? ? ? ? ? .cpu_rate = 198000000,
>> > + ? ? ? ? ? .cpu_voltage = 850000,
>> > + ? },
>> > +};
>> > +
>> > +struct cpu_op *mx6q_get_cpu_op(int *op)
>> > +{
>> > + ? struct device_node *cpu0;
>> > + ? u32 val;
>> > + ? int i;
>> > +
>> > + ? cpu0 = of_find_node_by_path("/cpus/cpu at 0");
>> > + ? if (cpu0 && !of_property_read_u32(cpu0, "clock-frequency", &val)) {
>> > + ? ? ? ? ? for (i = 0; i < ARRAY_SIZE(mx6q_cpu_op); i++) {
>> > + ? ? ? ? ? ? ? ? ? if (val >= mx6q_cpu_op[i].cpu_rate) {
>> > + ? ? ? ? ? ? ? ? ? ? ? ? ? arm_max_freq_idx = i;
>> > + ? ? ? ? ? ? ? ? ? ? ? ? ? break;
>> > + ? ? ? ? ? ? ? ? ? }
>> > + ? ? ? ? ? }
>> > + ? }
>> > + ? if (cpu0)
>> > + ? ? ? ? ? of_node_put(cpu0);
>> > + ? *op = ARRAY_SIZE(mx6q_cpu_op) - arm_max_freq_idx;
>> > + ? return mx6q_cpu_op + arm_max_freq_idx;
>> > +}
>> > +
>> > +static int __init mx6q_cpu_op_init(void)
>> > +{
>> > + ? get_cpu_op = mx6q_get_cpu_op;
>> > + ? return 0;
>> > +}
>> > +
>> > +core_initcall(mx6q_cpu_op_init);
>> > --
>> > 1.7.5.4
>> >
>> >
>> >
>>
>> --
>> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
>> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
>> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
>> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>

[PATCH V2 7/7] arm/imx6q: add cpufreq support

[Richard Zhao]

> >> > +static int arm_max_freq_idx;
> >>
> >> This is only used in mx6q_get_cpu_op()
> > I'll move to local var
> >>
> >> Also shouldn't this be initialized with 1? From what you
> >> said 800MHz is safe for all boards whereas 1GHz is not.
> > I'll fix it in next version.
> >
> 
> Richard, I communicated with Hui Liu a couple of weeks ago about the
> possibility of adding a "max_freq" kernel parameter to the i.MX6q
> community u-boot, similiar to what has been done for the BSP u-boot.
> If he is or has done this, it may be better to read and use this
> kernel parameter from u-boot so that the same kernel can be used
> between boards with and without the fix.  I'm not that familiar with
> device tree yet but perhaps it provides another way to handle this.
> Also keep in
Using bootargs, it's what I did in V1 patch. I prefer that way too.

Thanks
Richard 

[PATCH V2 7/7] arm/imx6q: add cpufreq support

[Shawn Guo]

On Tue, Dec 13, 2011 at 02:25:30PM +0800, Richard Zhao wrote:
> use cpu0 node property clock-frequency to check max frequency.
> 
> Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> ---
>  arch/arm/mach-imx/Kconfig        |    1 +
>  arch/arm/mach-imx/Makefile       |    2 +-
>  arch/arm/mach-imx/cpu_op-imx6q.c |   69 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 71 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-imx/cpu_op-imx6q.c
> 
NAK.

We really need to push people to help with cleanup and consolidation
effort rather than accepting patches on top of something that needs
to be cleaned up and consolidated, which will make the effort later
more difficult.

-- 
Regards,
Shawn

[PATCH V2 7/7] arm/imx6q: add cpufreq support

[Sascha Hauer]

On Tue, Dec 13, 2011 at 08:19:42PM +0800, Shawn Guo wrote:
> On Tue, Dec 13, 2011 at 02:25:30PM +0800, Richard Zhao wrote:
> > use cpu0 node property clock-frequency to check max frequency.
> > 
> > Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> > ---
> >  arch/arm/mach-imx/Kconfig        |    1 +
> >  arch/arm/mach-imx/Makefile       |    2 +-
> >  arch/arm/mach-imx/cpu_op-imx6q.c |   69 ++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 71 insertions(+), 1 deletions(-)
> >  create mode 100644 arch/arm/mach-imx/cpu_op-imx6q.c
> > 
> NAK.
> 
> We really need to push people to help with cleanup and consolidation
> effort rather than accepting patches on top of something that needs
> to be cleaned up and consolidated, which will make the effort later
> more difficult.

+1

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH V2 7/7] arm/imx6q: add cpufreq support

[Richard Zhao]

On Tue, Dec 13, 2011 at 03:20:33PM +0100, Sascha Hauer wrote:
> On Tue, Dec 13, 2011 at 08:19:42PM +0800, Shawn Guo wrote:
> > On Tue, Dec 13, 2011 at 02:25:30PM +0800, Richard Zhao wrote:
> > > use cpu0 node property clock-frequency to check max frequency.
> > > 
> > > Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> > > ---
> > >  arch/arm/mach-imx/Kconfig        |    1 +
> > >  arch/arm/mach-imx/Makefile       |    2 +-
> > >  arch/arm/mach-imx/cpu_op-imx6q.c |   69 ++++++++++++++++++++++++++++++++++++++
> > >  3 files changed, 71 insertions(+), 1 deletions(-)
> > >  create mode 100644 arch/arm/mach-imx/cpu_op-imx6q.c
> > > 
> > NAK.
> > 
> > We really need to push people to help with cleanup and consolidation
> > effort rather than accepting patches on top of something that needs
> > to be cleaned up and consolidated, which will make the effort later
> > more difficult.
> 
> +1
ok, let's make it clear.
- move arch/arm/plat-mxc/cpufreq.c to drivers/cpufreq/
- consider whether opp help imx, at least for imx cpufreq drive to pass
operating table.
- fall back ways, maybe define in dts /soc like:
cpufreq {
	compatible = "fsl,imx-cpufreq";
	frequency = <100000000 800000000 500000000 200000000>;
	volatage = <1500000 1400000 1300000 1200000>;
};

Thanks
Richard
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 1/1] arm/imx6q-sabrelite: add enet phy ksz9021rn fixup

[Richard Zhao]

tune phy RGMII pad skew.

Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
---
 arch/arm/mach-imx/mach-imx6q.c |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index d24d6c4..b3dcdcb 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -16,6 +16,8 @@
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/phy.h>
+#include <linux/micrel_phy.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
@@ -23,8 +25,27 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 
+/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
+static int ksz9021rn_phy_fixup(struct phy_device *phydev)
+{
+	/* min rx data delay */
+	phy_write(phydev, 0x0b, 0x8105);
+	phy_write(phydev, 0x0c, 0x0000);
+
+	/* max rx/tx clock delay, min rx/tx control delay */
+	phy_write(phydev, 0x0b, 0x8104);
+	phy_write(phydev, 0x0c, 0xf0f0);
+	phy_write(phydev, 0x0b, 0x104);
+
+	return 0;
+}
+
 static void __init imx6q_init_machine(void)
 {
+	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
+		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+					 ksz9021rn_phy_fixup);
+
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
 	imx6q_pm_init();
-- 
1.7.5.4

[PATCH 1/1] arm/imx6q-sabrelite: add enet phy ksz9021rn fixup

[Shawn Guo]

On Tue, Dec 13, 2011 at 04:24:18PM +0800, Richard Zhao wrote:
> tune phy RGMII pad skew.
> 
> Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> ---
>  arch/arm/mach-imx/mach-imx6q.c |   21 +++++++++++++++++++++
>  1 files changed, 21 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> index d24d6c4..b3dcdcb 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -16,6 +16,8 @@
>  #include <linux/of.h>
>  #include <linux/of_irq.h>
>  #include <linux/of_platform.h>
> +#include <linux/phy.h>
> +#include <linux/micrel_phy.h>
>  #include <asm/hardware/cache-l2x0.h>
>  #include <asm/hardware/gic.h>
>  #include <asm/mach/arch.h>
> @@ -23,8 +25,27 @@
>  #include <mach/common.h>
>  #include <mach/hardware.h>
>  
> +/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */

Neither the comment nor the commit message can help me understand why
this fixup is needed.

> +static int ksz9021rn_phy_fixup(struct phy_device *phydev)
> +{
> +	/* min rx data delay */
> +	phy_write(phydev, 0x0b, 0x8105);
> +	phy_write(phydev, 0x0c, 0x0000);
> +
> +	/* max rx/tx clock delay, min rx/tx control delay */
> +	phy_write(phydev, 0x0b, 0x8104);
> +	phy_write(phydev, 0x0c, 0xf0f0);
> +	phy_write(phydev, 0x0b, 0x104);
> +
> +	return 0;
> +}
> +
>  static void __init imx6q_init_machine(void)
>  {
> +	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
> +		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
> +					 ksz9021rn_phy_fixup);
> +

I would suggest put any setup specific to particular board after the
common part, if we could.

Regards,
Shawn

>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  
>  	imx6q_pm_init();
> -- 
> 1.7.5.4

[PATCH 1/1] arm/imx6q-sabrelite: add enet phy ksz9021rn fixup

[Richard Zhao]

On Tue, Dec 13, 2011 at 08:07:55PM +0800, Shawn Guo wrote:
> On Tue, Dec 13, 2011 at 04:24:18PM +0800, Richard Zhao wrote:
> > tune phy RGMII pad skew.
> > 
> > Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> > ---
> >  arch/arm/mach-imx/mach-imx6q.c |   21 +++++++++++++++++++++
> >  1 files changed, 21 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> > index d24d6c4..b3dcdcb 100644
> > --- a/arch/arm/mach-imx/mach-imx6q.c
> > +++ b/arch/arm/mach-imx/mach-imx6q.c
> > @@ -16,6 +16,8 @@
> >  #include <linux/of.h>
> >  #include <linux/of_irq.h>
> >  #include <linux/of_platform.h>
> > +#include <linux/phy.h>
> > +#include <linux/micrel_phy.h>
> >  #include <asm/hardware/cache-l2x0.h>
> >  #include <asm/hardware/gic.h>
> >  #include <asm/mach/arch.h>
> > @@ -23,8 +25,27 @@
> >  #include <mach/common.h>
> >  #include <mach/hardware.h>
> >  
> > +/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
> 
> Neither the comment nor the commit message can help me understand why
> this fixup is needed.
As commit log tells, it's for tune pad skew.
> 
> > +static int ksz9021rn_phy_fixup(struct phy_device *phydev)
> > +{
> > +	/* min rx data delay */
> > +	phy_write(phydev, 0x0b, 0x8105);
> > +	phy_write(phydev, 0x0c, 0x0000);
> > +
> > +	/* max rx/tx clock delay, min rx/tx control delay */
> > +	phy_write(phydev, 0x0b, 0x8104);
> > +	phy_write(phydev, 0x0c, 0xf0f0);
> > +	phy_write(phydev, 0x0b, 0x104);
> > +
> > +	return 0;
> > +}
> > +
> >  static void __init imx6q_init_machine(void)
> >  {
> > +	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
> > +		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
> > +					 ksz9021rn_phy_fixup);
> > +
> 
> I would suggest put any setup specific to particular board after the
> common part, if we could.
For this case, it's ok  for me to put it after populate devices.
A little concern that, generally speaking, adding devices imply possiblely call
driver probe, fixups usually are added before driver probe.

Thanks
Richard
> 
> Regards,
> Shawn
> 
> >  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> >  
> >  	imx6q_pm_init();
> > -- 
> > 1.7.5.4
> 

[PATCH 1/1] arm/imx6q-sabrelite: add enet phy ksz9021rn fixup

[Shawn Guo]

On Tue, Dec 13, 2011 at 08:13:51PM +0800, Richard Zhao wrote:
> On Tue, Dec 13, 2011 at 08:07:55PM +0800, Shawn Guo wrote:
> > On Tue, Dec 13, 2011 at 04:24:18PM +0800, Richard Zhao wrote:
> > > tune phy RGMII pad skew.
> > > 
> > > Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
> > > ---
> > >  arch/arm/mach-imx/mach-imx6q.c |   21 +++++++++++++++++++++
> > >  1 files changed, 21 insertions(+), 0 deletions(-)
> > > 
> > > diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> > > index d24d6c4..b3dcdcb 100644
> > > --- a/arch/arm/mach-imx/mach-imx6q.c
> > > +++ b/arch/arm/mach-imx/mach-imx6q.c
> > > @@ -16,6 +16,8 @@
> > >  #include <linux/of.h>
> > >  #include <linux/of_irq.h>
> > >  #include <linux/of_platform.h>
> > > +#include <linux/phy.h>
> > > +#include <linux/micrel_phy.h>
> > >  #include <asm/hardware/cache-l2x0.h>
> > >  #include <asm/hardware/gic.h>
> > >  #include <asm/mach/arch.h>
> > > @@ -23,8 +25,27 @@
> > >  #include <mach/common.h>
> > >  #include <mach/hardware.h>
> > >  
> > > +/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
> > 
> > Neither the comment nor the commit message can help me understand why
> > this fixup is needed.
> As commit log tells, it's for tune pad skew.
> > 
> > > +static int ksz9021rn_phy_fixup(struct phy_device *phydev)
> > > +{
> > > +	/* min rx data delay */
> > > +	phy_write(phydev, 0x0b, 0x8105);
> > > +	phy_write(phydev, 0x0c, 0x0000);
> > > +
> > > +	/* max rx/tx clock delay, min rx/tx control delay */
> > > +	phy_write(phydev, 0x0b, 0x8104);
> > > +	phy_write(phydev, 0x0c, 0xf0f0);
> > > +	phy_write(phydev, 0x0b, 0x104);
> > > +
> > > +	return 0;
> > > +}
> > > +
> > >  static void __init imx6q_init_machine(void)
> > >  {
> > > +	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
> > > +		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
> > > +					 ksz9021rn_phy_fixup);
> > > +
> > 
> > I would suggest put any setup specific to particular board after the
> > common part, if we could.
> For this case, it's ok  for me to put it after populate devices.
> A little concern that, generally speaking, adding devices imply possiblely call
> driver probe, fixups usually are added before driver probe.
> 
Fair point.  I do not have a strong opinion on this.  You can leave
it as it is.  I will apply the patch after patch #2.

-- 
Regards,
Shawn