[PATCH 1/4] ARM: at91: add at91sam9g20 dtsi

[PATCH 1/4] ARM: at91: add at91sam9g20 dtsi

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/boot/dts/at91sam9g20.dtsi |  154 ++++++++++++++++++++++++++++++++++++
 1 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91sam9g20.dtsi

diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
new file mode 100644
index 0000000..d6afa5f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -0,0 +1,154 @@
+/*
+ * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *                2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9G20 family SoC";
+	compatible = "atmel,at91sam9g20";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		serial1 = &usart0;
+		serial2 = &usart1;
+		serial3 = &usart2;
+		serial4 = &usart3;
+		serial5 = &usart4;
+		serial6 = &usart5;
+	};
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory at 20000000 {
+		reg = <0x20000000 0x08000000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			aic: interrupt-controller at fffff000 {
+				#interrupt-cells = <1>;
+				compatible = "atmel,at91rm9200-aic";
+				interrupt-controller;
+				interrupt-parent;
+				reg = <0xfffff000 0x200>;
+			};
+
+			dbgu: serial at fffff200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffff200 0x200>;
+				interrupts = <1>;
+			};
+
+			usart0: serial at fffb0000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffb0000 0x200>;
+				interrupts = <6>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+			};
+
+			usart1: serial at fffb4000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffb4000 0x200>;
+				interrupts = <7>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+			};
+
+			usart2: serial at fffb8000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffb8000 0x200>;
+				interrupts = <8>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+			};
+
+			usart3: serial at fffd0000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffd0000 0x200>;
+				interrupts = <23>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+			};
+
+			usart4: serial at fffd4000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffd4000 0x200>;
+				interrupts = <24>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+			};
+
+			usart5: serial at fffd8000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffd8000 0x200>;
+				interrupts = <25>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+			};
+
+/*
+			smc0: smc at ffffec00 {
+				compatible = "atmel,at91sam9260-smc";
+				reg = <0xffffec00 0x10>;
+			};
+
+			smc1: smc at ffffec10 {
+				compatible = "atmel,at91sam9260-smc";
+				reg = <0xffffec00 0x10>;
+			};
+
+			smc2: smc at ffffec20 {
+				compatible = "atmel,at91sam9260-smc";
+				reg = <0xffffec00 0x10>;
+			};
+
+			smc3: smc at ffffec30 {
+				compatible = "atmel,at91sam9260-smc";
+				reg = <0xffffec00 0x10>;
+			};
+
+			smc4: smc at ffffec40 {
+				compatible = "atmel,at91sam9260-smc";
+				reg = <0xffffec00 0x10>;
+			};
+
+			smc5: smc at ffffec50 {
+				compatible = "atmel,at91sam9260-smc";
+				reg = <0xffffec00 0x10>;
+			};
+
+			smc6: smc at ffffec60 {
+				compatible = "atmel,at91sam9260-smc";
+				reg = <0xffffec00 0x10>;
+			};
+
+			smc7: smc at ffffec70 {
+				compatible = "atmel,at91sam9260-smc";
+				reg = <0xffffec00 0x10>;
+			};
+*/
+		};
+	};
+};
-- 
1.7.7

[PATCH 2/4] ARM: at91: add Calao USB A9G20 DT support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/boot/dts/usb_a9g20.dts  |   45 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/Makefile.boot |    2 +-
 arch/arm/mach-at91/board-dt.c    |    1 +
 3 files changed, 47 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/usb_a9g20.dts

diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
new file mode 100644
index 0000000..4432a29
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -0,0 +1,45 @@
+/*
+ * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
+ *
+ *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g20.dtsi"
+
+/ {
+	model = "Calao USB A9G20";
+	compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
+
+	chosen {
+		bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data) root=/dev/mtdblock1 rw rootfstype=jffs2";
+	};
+
+	memory at 70000000 {
+		reg = <0x20000000 0x4000000>;
+	};
+
+	ahb {
+		apb {
+			usart0: serial at fffb0000 {
+				status = "disabled";
+			};
+			usart1: serial at fffb4000 {
+				status = "disabled";
+			};
+			usart2: serial at fffb8000 {
+				status = "disabled";
+			};
+			usart3: serial at fffd0000 {
+				status = "disabled";
+			};
+			usart4: serial at fffd4000 {
+				status = "disabled";
+			};
+			usart5: serial at fffd8000 {
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index d278863..08c665a 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -17,4 +17,4 @@ params_phys-y	:= 0x20000100
 initrd_phys-y	:= 0x20410000
 endif
 
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index 066d362..fdcbf72 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -108,6 +108,7 @@ static void __init at91_dt_device_init(void)
 
 static const char *at91_dt_board_compat[] __initdata = {
 	"atmel,at91sam9m10g45ek",
+	"calao,usb-a9g20",
 	NULL
 };
 
-- 
1.7.7

[PATCH 3/4] ARM: at91/smc: add DT support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/boot/dts/at91sam9m10g45ek.dts |   16 ++++++
 arch/arm/boot/dts/usb_a9g20.dts        |   16 ++++++
 arch/arm/mach-at91/board-dt.c          |   28 ----------
 arch/arm/mach-at91/sam9_smc.c          |   85 ++++++++++++++++++++++++++++++++
 4 files changed, 117 insertions(+), 28 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index fb0042d..d98d115 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -32,6 +32,22 @@
 			usart3: serial at fff98000 {
 				status = "disabled";
 			};
+			smc03: smc at ffffec30 {
+				compatible = "atmel,at91sam9260-smc";
+				reg = <0xffffec30 0x10>;
+				ncs_read_setup = <0>;
+				nrd_setup = <2>;
+				ncs_write_setup = <0>;
+				nwe_setup = <2>;
+				ncs_read_pulse = <4>;
+				nrd_pulse = <4>;
+				ncs_write_pulse = <4>;
+				nwe_pulse = <4>;
+				read_cycle = <7>;
+				write_cycle = <7>;
+				mode = <3>;
+				tdf_cycles = <3>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 4432a29..89a3620 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -40,6 +40,22 @@
 			usart5: serial at fffd8000 {
 				status = "disabled";
 			};
+			smc03: smc at ffffec30 {
+				compatible = "atmel,at91sam9260-smc";
+				reg = <0xffffec30 0x10>;
+				ncs_read_setup = <0>;
+				nrd_setup = <2>;
+				ncs_write_setup = <0>;
+				nwe_setup = <2>;
+				ncs_read_pulse = <4>;
+				nrd_pulse = <4>;
+				ncs_write_pulse = <4>;
+				nwe_pulse = <4>;
+				read_cycle = <7>;
+				write_cycle = <7>;
+				mode = <3>;
+				tdf_cycles = <3>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index fdcbf72..f0a8e09 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -54,36 +54,8 @@ static struct atmel_nand_data __initdata ek_nand_data = {
 	.enable_pin	= AT91_PIN_PC14,
 };
 
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-	.ncs_read_setup		= 0,
-	.nrd_setup		= 2,
-	.ncs_write_setup	= 0,
-	.nwe_setup		= 2,
-
-	.ncs_read_pulse		= 4,
-	.nrd_pulse		= 4,
-	.ncs_write_pulse	= 4,
-	.nwe_pulse		= 4,
-
-	.read_cycle		= 7,
-	.write_cycle		= 7,
-
-	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-	.tdf_cycles		= 3,
-};
-
 static void __init ek_add_device_nand(void)
 {
-	ek_nand_data.bus_width_16 = board_have_nand_16bit();
-	/* setup bus-width (8 or 16) */
-	if (ek_nand_data.bus_width_16)
-		ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
-	else
-		ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
-
-	/* configure chip-select 3 (NAND) */
-	sam9_smc_configure(0, 3, &ek_nand_smc_config);
-
 	at91_add_device_nand(&ek_nand_data);
 }
 
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 86d7d9e..0e6dcf6 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -61,3 +61,88 @@ void __init sam9_smc_init(int id, u32 addr)
 		return;
 	smc_base_addr[id] = ioremap(addr, 512);
 }
+
+#ifdef CONFIG_OF
+static struct of_device_id smc_ids[]  = {
+	{ .compatible = "atmel,at91sam9260-smc" },
+};
+
+int __init sam9_smc_of_config(struct device_node *np)
+{
+	struct sam9_smc_config config;
+	const unsigned int *prop;
+	void __iomem *base;
+
+	if (!np)
+		return -EIO;
+
+	prop = of_get_property(np, "ncs_read_setup", NULL);
+	if (prop)
+		config.ncs_read_setup = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "nrd_setup", NULL);
+	if (prop)
+		config.nrd_setup = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "ncs_write_setup", NULL);
+	if (prop)
+		config.ncs_write_setup = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "nwe_setup", NULL);
+	if (prop)
+		config.nwe_setup = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "ncs_read_pulse", NULL);
+	if (prop)
+		config.ncs_read_pulse = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "nrd_pulse", NULL);
+	if (prop)
+		config.nrd_pulse = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "ncs_write_pulse", NULL);
+	if (prop)
+		config.ncs_write_pulse = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "nwe_pulse", NULL);
+	if (prop)
+		config.nwe_pulse = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "read_cycle", NULL);
+	if (prop)
+		config.read_cycle = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "write_cycle", NULL);
+	if (prop)
+		config.write_cycle = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "mode", NULL);
+	if (prop)
+		config.mode = be32_to_cpup(prop);
+
+	prop = of_get_property(np, "tdf_cycles", NULL);
+	if (prop)
+		config.tdf_cycles = be32_to_cpup(prop);
+
+	base = of_iomap(np, 0);
+	if (!base) {
+		panic("unable to map smc registers\n");
+		return -EIO;
+	}
+
+	sam9_smc_cs_configure(base, &config);
+
+	return 0;
+}
+
+static int __init sam9_smc_of_init(void)
+{
+	struct device_node *np;
+
+	for_each_matching_node(np, smc_ids)
+		sam9_smc_of_config(np);
+
+	return 0;
+}
+early_initcall(sam9_smc_of_init);
+#endif
-- 
1.7.7

[PATCH 4/4] ARM: at91/pit: add DT support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/boot/dts/at91sam9g20.dtsi    |    6 +++++
 arch/arm/boot/dts/at91sam9g45.dtsi    |    6 +++++
 arch/arm/mach-at91/at91sam926x_time.c |   37 +++++++++++++++++++++++++++++++-
 arch/arm/mach-at91/setup.c            |    2 +
 4 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index d6afa5f..de5fbb3 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -54,6 +54,12 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pit: timer at fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1>;
+			};
+
 			dbgu: serial at fffff200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index e092666..c1d0ab5 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -53,6 +53,12 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pit: timer at fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1>;
+			};
+
 			dma: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 20d0801..e5f8c38 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -14,6 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/mach/time.h>
 
@@ -133,7 +135,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 static struct irqaction at91sam926x_pit_irq = {
 	.name		= "at91_tick",
 	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-	.handler	= at91sam926x_pit_interrupt
+	.handler	= at91sam926x_pit_interrupt,
+	.irq		= AT91_ID_SYS,
 };
 
 static void at91sam926x_pit_reset(void)
@@ -149,6 +152,34 @@ static void at91sam926x_pit_reset(void)
 	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id timer_ids[] = {
+	{ .compatible = "atmel,at91sam9260-pit" },
+};
+
+void __init of_at91sam926x_pit_init(void)
+{
+	struct device_node *np;
+	const unsigned int *intspec;
+
+	np = of_find_matching_node(NULL, timer_ids);
+	if (!np)
+		panic("unable to find compatible timer node in dtb\n");
+	pit_base_addr = of_iomap(np, 0);
+	if (!pit_base_addr)
+		panic("unable to map timer cpu registers\n");
+
+	/* Get the interrupts property */
+	intspec = of_get_property(np, "interrupts", NULL);
+	BUG_ON(!intspec);
+	at91sam926x_pit_irq.irq = be32_to_cpup(intspec);
+
+	of_node_put(np);
+}
+#else
+static void __init of_at91sam926x_pit_init(void) {}
+#endif
+
 /*
  * Set up both clocksource and clockevent support.
  */
@@ -157,6 +188,8 @@ static void __init at91sam926x_pit_init(void)
 	unsigned long	pit_rate;
 	unsigned	bits;
 
+	of_at91sam926x_pit_init();
+
 	/*
 	 * Use our actual MCK to figure out how many MCK/16 ticks per
 	 * 1/HZ period (instead of a compile-time constant LATCH).
@@ -177,7 +210,7 @@ static void __init at91sam926x_pit_init(void)
 	clocksource_register_hz(&pit_clk, pit_rate);
 
 	/* Set up irq handler */
-	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
 
 	/* Set up and register clockevents */
 	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 007fd95..674b64c 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -287,7 +287,9 @@ void __init at91_map_io(void)
 
 void __init at91_initialize(unsigned long main_clock)
 {
+#ifndef CONFIG_OF
 	at91_boot_soc.map_register();
+#endif
 
 	/* Init clock subsystem */
 	at91_clock_init(main_clock);
-- 
1.7.7

[PATCH v2] ARM: at91: pit add DT support

[Nicolas Ferre]

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Retreive registers address and IRQ from device tree entry. Fall back
to built-in values if an error occurs.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
[nicolas.ferre at atmel.com: change error path and interrupts property handling]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
 arch/arm/mach-at91/at91sam926x_time.c              |   49 +++++++++++++++++++-
 4 files changed, 66 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
new file mode 100644
index 0000000..380f711
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -0,0 +1,8 @@
+Atmel AT91 device tree bindings.
+================================
+
+PIT Timer required properties:
+- compatible: Should be "atmel,at91sam9260-pit"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the PIT which is the IRQ line
+  shared across all System Controller members.
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 0d21872..5c4be7e 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -57,6 +57,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pit: timer at fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 4>;
+			};
 
 			pioA: gpio at fffff400 {
 				compatible = "atmel,at91rm9200-gpio";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index b977a79..0d21c8e 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -58,6 +58,12 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pit: timer at fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 4>;
+			};
+
 			dma: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index d89ead7..5d4c308 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -14,6 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/mach/time.h>
 
@@ -133,7 +135,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 static struct irqaction at91sam926x_pit_irq = {
 	.name		= "at91_tick",
 	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-	.handler	= at91sam926x_pit_interrupt
+	.handler	= at91sam926x_pit_interrupt,
+	.irq		= AT91_ID_SYS,
 };
 
 static void at91sam926x_pit_reset(void)
@@ -149,6 +152,46 @@ static void at91sam926x_pit_reset(void)
 	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id timer_ids[] = {
+	{ .compatible = "atmel,at91sam9260-pit" },
+	{ /* sentinel */ }
+};
+
+static int __init of_at91sam926x_pit_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, timer_ids);
+	if (!np)
+		goto err;
+
+	pit_base_addr = of_iomap(np, 0);
+	if (!pit_base_addr)
+		goto node_err;
+
+	/* Get the interrupts property */
+	if (of_property_read_u32(np, "interrupts", &at91sam926x_pit_irq.irq))
+		goto ioremap_err;
+
+	of_node_put(np);
+
+	return 0;
+
+ioremap_err:
+	iounmap(pit_base_addr);
+node_err:
+	of_node_put(np);
+err:
+	return -EINVAL;
+}
+#else
+static int __init of_at91sam926x_pit_init(void)
+{
+	return -EINVAL;
+}
+#endif
+
 /*
  * Set up both clocksource and clockevent support.
  */
@@ -177,7 +220,7 @@ static void __init at91sam926x_pit_init(void)
 	clocksource_register_hz(&pit_clk, pit_rate);
 
 	/* Set up irq handler */
-	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
 
 	/* Set up and register clockevents */
 	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
@@ -193,6 +236,8 @@ static void at91sam926x_pit_suspend(void)
 
 void __init at91sam926x_ioremap_pit(u32 addr)
 {
+	if (!of_at91sam926x_pit_init())
+		return;
 	pit_base_addr = ioremap(addr, 16);
 
 	if (!pit_base_addr)
-- 
1.7.5.4

[PATCH v2] ARM: at91: pit add DT support

[Jamie Iles]

Hi Nicolas, Jean-Christophe,

On Thu, Jan 05, 2012 at 02:48:28PM +0100, Nicolas Ferre wrote:
> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> 
> Retreive registers address and IRQ from device tree entry. Fall back
> to built-in values if an error occurs.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
[...]
> diff --git a/arch/arm/mach-at91/at91sam926x_time.c 
> b/arch/arm/mach-at91/at91sam926x_time.c
> index d89ead7..5d4c308 100644
> --- a/arch/arm/mach-at91/at91sam926x_time.c
> +++ b/arch/arm/mach-at91/at91sam926x_time.c
> @@ -14,6 +14,8 @@
[...]
> +static int __init of_at91sam926x_pit_init(void)
> +{
> +	struct device_node *np;
> +
> +	np = of_find_matching_node(NULL, timer_ids);
> +	if (!np)
> +		goto err;
> +
> +	pit_base_addr = of_iomap(np, 0);
> +	if (!pit_base_addr)
> +		goto node_err;
> +
> +	/* Get the interrupts property */
> +	if (of_property_read_u32(np, "interrupts", &at91sam926x_pit_irq.irq))
> +		goto ioremap_err;

I think you want:

	at91sam926x_pit_irq.irq = irq_of_parse_and_map(np, 0);

to make sure the IRQ is converted to a Linux IRQ and not a hwirq.  Other 
than that looks fine to me.

Jamie

[PATCH v2] ARM: at91: pit add DT support

[Nicolas Ferre]

On 01/05/2012 01:00 PM, Jamie Iles :
> Hi Nicolas, Jean-Christophe,
> 
> On Thu, Jan 05, 2012 at 02:48:28PM +0100, Nicolas Ferre wrote:
>> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>>
>> Retreive registers address and IRQ from device tree entry. Fall back
>> to built-in values if an error occurs.
>>
>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>> ---
> [...]
>> diff --git a/arch/arm/mach-at91/at91sam926x_time.c 
>> b/arch/arm/mach-at91/at91sam926x_time.c
>> index d89ead7..5d4c308 100644
>> --- a/arch/arm/mach-at91/at91sam926x_time.c
>> +++ b/arch/arm/mach-at91/at91sam926x_time.c
>> @@ -14,6 +14,8 @@
> [...]
>> +static int __init of_at91sam926x_pit_init(void)
>> +{
>> +	struct device_node *np;
>> +
>> +	np = of_find_matching_node(NULL, timer_ids);
>> +	if (!np)
>> +		goto err;
>> +
>> +	pit_base_addr = of_iomap(np, 0);
>> +	if (!pit_base_addr)
>> +		goto node_err;
>> +
>> +	/* Get the interrupts property */
>> +	if (of_property_read_u32(np, "interrupts", &at91sam926x_pit_irq.irq))
>> +		goto ioremap_err;
> 
> I think you want:
> 
> 	at91sam926x_pit_irq.irq = irq_of_parse_and_map(np, 0);
> 
> to make sure the IRQ is converted to a Linux IRQ and not a hwirq.

Yes, that definitively makes sense. BTW, without a DT entry, how should
I map a hwirq, with the irq_domain_to_irq() helper? But I will need
access to the interrupt controller "struct irq_domain"...

> Other than that looks fine to me.

Thanks a lot for your review, Jamie.

Best regards,
-- 
Nicolas Ferre

[PATCH v2] ARM: at91: pit add DT support

[Jamie Iles]

On Thu, Jan 05, 2012 at 03:50:09PM +0100, Nicolas Ferre wrote:
> On 01/05/2012 01:00 PM, Jamie Iles :
> > Hi Nicolas, Jean-Christophe,
> > 
> > On Thu, Jan 05, 2012 at 02:48:28PM +0100, Nicolas Ferre wrote:
> >> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> >>
> >> Retreive registers address and IRQ from device tree entry. Fall back
> >> to built-in values if an error occurs.
> >>
> >> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> >> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
> >> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> >> ---
> > [...]
> >> diff --git a/arch/arm/mach-at91/at91sam926x_time.c 
> >> b/arch/arm/mach-at91/at91sam926x_time.c
> >> index d89ead7..5d4c308 100644
> >> --- a/arch/arm/mach-at91/at91sam926x_time.c
> >> +++ b/arch/arm/mach-at91/at91sam926x_time.c
> >> @@ -14,6 +14,8 @@
> > [...]
> >> +static int __init of_at91sam926x_pit_init(void)
> >> +{
> >> +	struct device_node *np;
> >> +
> >> +	np = of_find_matching_node(NULL, timer_ids);
> >> +	if (!np)
> >> +		goto err;
> >> +
> >> +	pit_base_addr = of_iomap(np, 0);
> >> +	if (!pit_base_addr)
> >> +		goto node_err;
> >> +
> >> +	/* Get the interrupts property */
> >> +	if (of_property_read_u32(np, "interrupts", &at91sam926x_pit_irq.irq))
> >> +		goto ioremap_err;
> > 
> > I think you want:
> > 
> > 	at91sam926x_pit_irq.irq = irq_of_parse_and_map(np, 0);
> > 
> > to make sure the IRQ is converted to a Linux IRQ and not a hwirq.
> 
> Yes, that definitively makes sense. BTW, without a DT entry, how should
> I map a hwirq, with the irq_domain_to_irq() helper? But I will need
> access to the interrupt controller "struct irq_domain"...

If you aren't booting with DT then at the moment I think on AT91 you 
have statically assigned irq_descs and IRQ numbers so you don't need to 
map them, you just know what IRQ number to request at compile time.

Jamie

[PATCH v3] ARM: at91: pit add DT support

[Nicolas Ferre]

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Retreive registers address and IRQ from device tree entry. Fall back
to built-in values if an error occurs.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
[nicolas.ferre at atmel.com: change error path and interrupts property handling]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
      Correction proposed by Jamie Iles.

v2: - new specification of irq numbers in DT (due to modification of AIC code)
    - new error path in of_at91sam926x_pit_init()
    - fall back to built-in values if an error occurs
    - use of of_property_read_u32() to get irq property

 .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
 arch/arm/mach-at91/at91sam926x_time.c              |   53 +++++++++++++++++++-
 4 files changed, 70 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
new file mode 100644
index 0000000..380f711
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -0,0 +1,8 @@
+Atmel AT91 device tree bindings.
+================================
+
+PIT Timer required properties:
+- compatible: Should be "atmel,at91sam9260-pit"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the PIT which is the IRQ line
+  shared across all System Controller members.
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 0d21872..5c4be7e 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -57,6 +57,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pit: timer at fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 4>;
+			};
 
 			pioA: gpio at fffff400 {
 				compatible = "atmel,at91rm9200-gpio";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index b977a79..0d21c8e 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -58,6 +58,12 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pit: timer at fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 4>;
+			};
+
 			dma: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index d89ead7..534a992 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -14,6 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 
@@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 static struct irqaction at91sam926x_pit_irq = {
 	.name		= "at91_tick",
 	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-	.handler	= at91sam926x_pit_interrupt
+	.handler	= at91sam926x_pit_interrupt,
+	.irq		= AT91_ID_SYS,
 };
 
 static void at91sam926x_pit_reset(void)
@@ -149,6 +153,49 @@ static void at91sam926x_pit_reset(void)
 	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id timer_ids[] = {
+	{ .compatible = "atmel,at91sam9260-pit" },
+	{ /* sentinel */ }
+};
+
+static int __init of_at91sam926x_pit_init(void)
+{
+	struct device_node	*np;
+	int			ret;
+
+	np = of_find_matching_node(NULL, timer_ids);
+	if (!np)
+		goto err;
+
+	pit_base_addr = of_iomap(np, 0);
+	if (!pit_base_addr)
+		goto node_err;
+
+	/* Get the interrupts property */
+	ret = irq_of_parse_and_map(np, 0);
+	if (ret <= 0)
+		goto ioremap_err;
+	at91sam926x_pit_irq.irq = ret;
+
+	of_node_put(np);
+
+	return 0;
+
+ioremap_err:
+	iounmap(pit_base_addr);
+node_err:
+	of_node_put(np);
+err:
+	return -EINVAL;
+}
+#else
+static int __init of_at91sam926x_pit_init(void)
+{
+	return -EINVAL;
+}
+#endif
+
 /*
  * Set up both clocksource and clockevent support.
  */
@@ -177,7 +224,7 @@ static void __init at91sam926x_pit_init(void)
 	clocksource_register_hz(&pit_clk, pit_rate);
 
 	/* Set up irq handler */
-	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
 
 	/* Set up and register clockevents */
 	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
@@ -193,6 +240,8 @@ static void at91sam926x_pit_suspend(void)
 
 void __init at91sam926x_ioremap_pit(u32 addr)
 {
+	if (!of_at91sam926x_pit_init())
+		return;
 	pit_base_addr = ioremap(addr, 16);
 
 	if (!pit_base_addr)
-- 
1.7.5.4

[PATCH v3] ARM: at91: pit add DT support

[Jamie Iles]

On Thu, Jan 05, 2012 at 06:25:48PM +0100, Nicolas Ferre wrote:
> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> 
> Retreive registers address and IRQ from device tree entry. Fall back
> to built-in values if an error occurs.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Reviewed-by: Jamie Iles <jamie@jamieiles.com>

Jamie

[PATCH v3] ARM: at91: pit add DT support

[Rob Herring]

On 01/05/2012 11:25 AM, Nicolas Ferre wrote:
> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> 
> Retreive registers address and IRQ from device tree entry. Fall back
> to built-in values if an error occurs.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
>       Correction proposed by Jamie Iles.
> 
> v2: - new specification of irq numbers in DT (due to modification of AIC code)
>     - new error path in of_at91sam926x_pit_init()
>     - fall back to built-in values if an error occurs
>     - use of of_property_read_u32() to get irq property
> 
>  .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
>  arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
>  arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
>  arch/arm/mach-at91/at91sam926x_time.c              |   53 +++++++++++++++++++-
>  4 files changed, 70 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> new file mode 100644
> index 0000000..380f711
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> @@ -0,0 +1,8 @@
> +Atmel AT91 device tree bindings.
> +================================
> +
> +PIT Timer required properties:
> +- compatible: Should be "atmel,at91sam9260-pit"
> +- reg: Should contain registers location and length
> +- interrupts: Should contain interrupt for the PIT which is the IRQ line
> +  shared across all System Controller members.
> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> index 0d21872..5c4be7e 100644
> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> @@ -57,6 +57,11 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			pit: timer at fffffd30 {
> +				compatible = "atmel,at91sam9260-pit";
> +				reg = <0xfffffd30 0xf>;
> +				interrupts = <1 4>;
> +			};
>  
>  			pioA: gpio at fffff400 {
>  				compatible = "atmel,at91rm9200-gpio";
> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> index b977a79..0d21c8e 100644
> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> @@ -58,6 +58,12 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			pit: timer at fffffd30 {
> +				compatible = "atmel,at91sam9260-pit";
> +				reg = <0xfffffd30 0xf>;
> +				interrupts = <1 4>;
> +			};
> +
>  			dma: dma-controller at ffffec00 {
>  				compatible = "atmel,at91sam9g45-dma";
>  				reg = <0xffffec00 0x200>;
> diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
> index d89ead7..534a992 100644
> --- a/arch/arm/mach-at91/at91sam926x_time.c
> +++ b/arch/arm/mach-at91/at91sam926x_time.c
> @@ -14,6 +14,9 @@
>  #include <linux/kernel.h>
>  #include <linux/clk.h>
>  #include <linux/clockchips.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
>  
>  #include <asm/mach/time.h>
>  
> @@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
>  static struct irqaction at91sam926x_pit_irq = {
>  	.name		= "at91_tick",
>  	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
> -	.handler	= at91sam926x_pit_interrupt
> +	.handler	= at91sam926x_pit_interrupt,
> +	.irq		= AT91_ID_SYS,
>  };
>  
>  static void at91sam926x_pit_reset(void)
> @@ -149,6 +153,49 @@ static void at91sam926x_pit_reset(void)
>  	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
>  }
>  
> +#ifdef CONFIG_OF
> +static struct of_device_id timer_ids[] = {
> +	{ .compatible = "atmel,at91sam9260-pit" },
> +	{ /* sentinel */ }
> +};
> +
> +static int __init of_at91sam926x_pit_init(void)
> +{
> +	struct device_node	*np;
> +	int			ret;
> +
> +	np = of_find_matching_node(NULL, timer_ids);
> +	if (!np)
> +		goto err;
> +
> +	pit_base_addr = of_iomap(np, 0);
> +	if (!pit_base_addr)
> +		goto node_err;
> +
> +	/* Get the interrupts property */
> +	ret = irq_of_parse_and_map(np, 0);
> +	if (ret <= 0)
> +		goto ioremap_err;
> +	at91sam926x_pit_irq.irq = ret;
> +
> +	of_node_put(np);
> +
> +	return 0;
> +
> +ioremap_err:
> +	iounmap(pit_base_addr);
> +node_err:
> +	of_node_put(np);
> +err:
> +	return -EINVAL;
> +}
> +#else
> +static int __init of_at91sam926x_pit_init(void)
> +{
> +	return -EINVAL;
> +}
> +#endif
> +
>  /*
>   * Set up both clocksource and clockevent support.
>   */
> @@ -177,7 +224,7 @@ static void __init at91sam926x_pit_init(void)
>  	clocksource_register_hz(&pit_clk, pit_rate);
>  
>  	/* Set up irq handler */
> -	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
> +	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
>  
>  	/* Set up and register clockevents */
>  	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
> @@ -193,6 +240,8 @@ static void at91sam926x_pit_suspend(void)
>  
>  void __init at91sam926x_ioremap_pit(u32 addr)
>  {
> +	if (!of_at91sam926x_pit_init())
> +		return;

This seems backwards to me. I don't have the ioremap changes in my tree,
but shouldn't the caller of at91sam926x_ioremap_pit be changed to
something like this:

	if (of_at91sam926x_pit_init() < 0)
		at91sam926x_ioremap_pit(addr);

Otherwise,

Acked-by: Rob Herring <rob.herring@calxeda.com>

Rob

>  	pit_base_addr = ioremap(addr, 16);
>  
>  	if (!pit_base_addr)

[PATCH v3] ARM: at91: pit add DT support

[Nicolas Ferre]

On 01/05/2012 05:42 PM, Rob Herring :
> On 01/05/2012 11:25 AM, Nicolas Ferre wrote:
>> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>>
>> Retreive registers address and IRQ from device tree entry. Fall back
>> to built-in values if an error occurs.
>>
>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>> ---
>> v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
>>       Correction proposed by Jamie Iles.
>>
>> v2: - new specification of irq numbers in DT (due to modification of AIC code)
>>     - new error path in of_at91sam926x_pit_init()
>>     - fall back to built-in values if an error occurs
>>     - use of of_property_read_u32() to get irq property
>>
>>  .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
>>  arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
>>  arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
>>  arch/arm/mach-at91/at91sam926x_time.c              |   53 +++++++++++++++++++-
>>  4 files changed, 70 insertions(+), 2 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt

[..]

>> --- a/arch/arm/mach-at91/at91sam926x_time.c
>> +++ b/arch/arm/mach-at91/at91sam926x_time.c

[..]

>>  void __init at91sam926x_ioremap_pit(u32 addr)
>>  {
>> +	if (!of_at91sam926x_pit_init())
>> +		return;
> 
> This seems backwards to me. I don't have the ioremap changes in my tree,
> but shouldn't the caller of at91sam926x_ioremap_pit be changed to
> something like this:
> 
> 	if (of_at91sam926x_pit_init() < 0)
> 		at91sam926x_ioremap_pit(addr);

Yes, you are right, it will be more readable the other way around.

I repost another revision now.

> Otherwise,
> Acked-by: Rob Herring <rob.herring@calxeda.com>

Thanks for your review.

Best regards,
-- 
Nicolas Ferre

[PATCH v3] ARM: at91: pit add DT support

[Grant Likely]

On Thu, Jan 05, 2012 at 06:25:48PM +0100, Nicolas Ferre wrote:
> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> 
> Retreive registers address and IRQ from device tree entry. Fall back
> to built-in values if an error occurs.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
>       Correction proposed by Jamie Iles.
> 
> v2: - new specification of irq numbers in DT (due to modification of AIC code)
>     - new error path in of_at91sam926x_pit_init()
>     - fall back to built-in values if an error occurs
>     - use of of_property_read_u32() to get irq property
> 
>  .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
>  arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
>  arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
>  arch/arm/mach-at91/at91sam926x_time.c              |   53 +++++++++++++++++++-
>  4 files changed, 70 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> new file mode 100644
> index 0000000..380f711
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> @@ -0,0 +1,8 @@
> +Atmel AT91 device tree bindings.
> +================================
> +
> +PIT Timer required properties:
> +- compatible: Should be "atmel,at91sam9260-pit"
> +- reg: Should contain registers location and length
> +- interrupts: Should contain interrupt for the PIT which is the IRQ line
> +  shared across all System Controller members.
> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> index 0d21872..5c4be7e 100644
> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> @@ -57,6 +57,11 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			pit: timer at fffffd30 {
> +				compatible = "atmel,at91sam9260-pit";
> +				reg = <0xfffffd30 0xf>;
> +				interrupts = <1 4>;
> +			};
>  
>  			pioA: gpio at fffff400 {
>  				compatible = "atmel,at91rm9200-gpio";
> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> index b977a79..0d21c8e 100644
> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> @@ -58,6 +58,12 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			pit: timer at fffffd30 {
> +				compatible = "atmel,at91sam9260-pit";
> +				reg = <0xfffffd30 0xf>;
> +				interrupts = <1 4>;
> +			};
> +
>  			dma: dma-controller at ffffec00 {
>  				compatible = "atmel,at91sam9g45-dma";
>  				reg = <0xffffec00 0x200>;
> diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
> index d89ead7..534a992 100644
> --- a/arch/arm/mach-at91/at91sam926x_time.c
> +++ b/arch/arm/mach-at91/at91sam926x_time.c
> @@ -14,6 +14,9 @@
>  #include <linux/kernel.h>
>  #include <linux/clk.h>
>  #include <linux/clockchips.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
>  
>  #include <asm/mach/time.h>
>  
> @@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
>  static struct irqaction at91sam926x_pit_irq = {
>  	.name		= "at91_tick",
>  	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
> -	.handler	= at91sam926x_pit_interrupt
> +	.handler	= at91sam926x_pit_interrupt,
> +	.irq		= AT91_ID_SYS,
>  };
>  
>  static void at91sam926x_pit_reset(void)
> @@ -149,6 +153,49 @@ static void at91sam926x_pit_reset(void)
>  	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
>  }
>  
> +#ifdef CONFIG_OF
> +static struct of_device_id timer_ids[] = {
> +	{ .compatible = "atmel,at91sam9260-pit" },
> +	{ /* sentinel */ }
> +};
> +
> +static int __init of_at91sam926x_pit_init(void)
> +{
> +	struct device_node	*np;
> +	int			ret;
> +
> +	np = of_find_matching_node(NULL, timer_ids);
> +	if (!np)
> +		goto err;
> +
> +	pit_base_addr = of_iomap(np, 0);
> +	if (!pit_base_addr)
> +		goto node_err;
> +
> +	/* Get the interrupts property */
> +	ret = irq_of_parse_and_map(np, 0);
> +	if (ret <= 0)
> +		goto ioremap_err;

if (!ret)

The DT irq functions return 0 on failure.

g.

[PATCH v3] ARM: at91: pit add DT support

[Nicolas Ferre]

On 01/05/2012 07:00 PM, Grant Likely :
> On Thu, Jan 05, 2012 at 06:25:48PM +0100, Nicolas Ferre wrote:
>> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>>
>> Retreive registers address and IRQ from device tree entry. Fall back
>> to built-in values if an error occurs.
>>
>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>> ---
>> v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
>>       Correction proposed by Jamie Iles.
>>
>> v2: - new specification of irq numbers in DT (due to modification of AIC code)
>>     - new error path in of_at91sam926x_pit_init()
>>     - fall back to built-in values if an error occurs
>>     - use of of_property_read_u32() to get irq property
>>
>>  .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
>>  arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
>>  arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
>>  arch/arm/mach-at91/at91sam926x_time.c              |   53 +++++++++++++++++++-
>>  4 files changed, 70 insertions(+), 2 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt

[..]

>> --- a/arch/arm/mach-at91/at91sam926x_time.c
>> +++ b/arch/arm/mach-at91/at91sam926x_time.c

[..]

>> +	/* Get the interrupts property */
>> +	ret = irq_of_parse_and_map(np, 0);
>> +	if (ret <= 0)
>> +		goto ioremap_err;
> 
> if (!ret)
> 
> The DT irq functions return 0 on failure.

Ok, modified in new revision.

Best regards,
-- 
Nicolas Ferre

[PATCH v4] ARM: at91: pit add DT support

[Nicolas Ferre]

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Retreive registers address and IRQ from device tree entry. Fall back
to built-in values if an error occurs.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
[nicolas.ferre at atmel.com: change error path and interrupts property handling]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
---
v4: - change of_at91sam926x_pit_init() return value usage logic as
      suggested by Rob Herring
    - irq_of_parse_and_map() returns 0 on error: change test according to 
      Grant Likely note.

v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
      Correction proposed by Jamie Iles.

v2: - new specification of irq numbers in DT (due to modification of AIC code)
    - new error path in of_at91sam926x_pit_init()
    - fall back to built-in values if an error occurs
    - use of of_property_read_u32() to get irq property

 .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
 arch/arm/mach-at91/at91sam926x_time.c              |   60 ++++++++++++++++++--
 4 files changed, 73 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
new file mode 100644
index 0000000..380f711
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -0,0 +1,8 @@
+Atmel AT91 device tree bindings.
+================================
+
+PIT Timer required properties:
+- compatible: Should be "atmel,at91sam9260-pit"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the PIT which is the IRQ line
+  shared across all System Controller members.
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index ea942b5..e10842a 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -57,6 +57,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pit: timer at fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 4>;
+			};
 
 			pioA: gpio at fffff400 {
 				compatible = "atmel,at91rm9200-gpio";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index ebc9617..28a678f 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -58,6 +58,12 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pit: timer at fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 4>;
+			};
+
 			dma: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index d89ead7..802fea3 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -14,6 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 
@@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 static struct irqaction at91sam926x_pit_irq = {
 	.name		= "at91_tick",
 	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-	.handler	= at91sam926x_pit_interrupt
+	.handler	= at91sam926x_pit_interrupt,
+	.irq		= AT91_ID_SYS,
 };
 
 static void at91sam926x_pit_reset(void)
@@ -149,6 +153,49 @@ static void at91sam926x_pit_reset(void)
 	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id timer_ids[] = {
+	{ .compatible = "atmel,at91sam9260-pit" },
+	{ /* sentinel */ }
+};
+
+static int __init of_at91sam926x_pit_init(void)
+{
+	struct device_node	*np;
+	int			ret;
+
+	np = of_find_matching_node(NULL, timer_ids);
+	if (!np)
+		goto err;
+
+	pit_base_addr = of_iomap(np, 0);
+	if (!pit_base_addr)
+		goto node_err;
+
+	/* Get the interrupts property */
+	ret = irq_of_parse_and_map(np, 0);
+	if (!ret)
+		goto ioremap_err;
+	at91sam926x_pit_irq.irq = ret;
+
+	of_node_put(np);
+
+	return 0;
+
+ioremap_err:
+	iounmap(pit_base_addr);
+node_err:
+	of_node_put(np);
+err:
+	return -EINVAL;
+}
+#else
+static int __init of_at91sam926x_pit_init(void)
+{
+	return -EINVAL;
+}
+#endif
+
 /*
  * Set up both clocksource and clockevent support.
  */
@@ -177,7 +224,7 @@ static void __init at91sam926x_pit_init(void)
 	clocksource_register_hz(&pit_clk, pit_rate);
 
 	/* Set up irq handler */
-	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
 
 	/* Set up and register clockevents */
 	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
@@ -193,10 +240,11 @@ static void at91sam926x_pit_suspend(void)
 
 void __init at91sam926x_ioremap_pit(u32 addr)
 {
-	pit_base_addr = ioremap(addr, 16);
-
-	if (!pit_base_addr)
-		panic("Impossible to ioremap PIT\n");
+	if (of_at91sam926x_pit_init() < 0) {
+		pit_base_addr = ioremap(addr, 16);
+		if (!pit_base_addr)
+			panic("Impossible to ioremap PIT\n");
+	}
 }
 
 struct sys_timer at91sam926x_timer = {
-- 
1.7.5.4

[PATCH v4] ARM: at91: pit add DT support

[Rob Herring]

On 01/06/2012 10:20 AM, Nicolas Ferre wrote:
> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> 
> Retreive registers address and IRQ from device tree entry. Fall back
> to built-in values if an error occurs.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> Reviewed-by: Jamie Iles <jamie@jamieiles.com>
> Acked-by: Rob Herring <rob.herring@calxeda.com>
> ---
> v4: - change of_at91sam926x_pit_init() return value usage logic as
>       suggested by Rob Herring
>     - irq_of_parse_and_map() returns 0 on error: change test according to 
>       Grant Likely note.
> 
> v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
>       Correction proposed by Jamie Iles.
> 
> v2: - new specification of irq numbers in DT (due to modification of AIC code)
>     - new error path in of_at91sam926x_pit_init()
>     - fall back to built-in values if an error occurs
>     - use of of_property_read_u32() to get irq property
> 
>  .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
>  arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
>  arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
>  arch/arm/mach-at91/at91sam926x_time.c              |   60 ++++++++++++++++++--
>  4 files changed, 73 insertions(+), 6 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> new file mode 100644
> index 0000000..380f711
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> @@ -0,0 +1,8 @@
> +Atmel AT91 device tree bindings.
> +================================
> +
> +PIT Timer required properties:
> +- compatible: Should be "atmel,at91sam9260-pit"
> +- reg: Should contain registers location and length
> +- interrupts: Should contain interrupt for the PIT which is the IRQ line
> +  shared across all System Controller members.
> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> index ea942b5..e10842a 100644
> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> @@ -57,6 +57,11 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			pit: timer at fffffd30 {
> +				compatible = "atmel,at91sam9260-pit";
> +				reg = <0xfffffd30 0xf>;
> +				interrupts = <1 4>;
> +			};
>  
>  			pioA: gpio at fffff400 {
>  				compatible = "atmel,at91rm9200-gpio";
> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> index ebc9617..28a678f 100644
> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> @@ -58,6 +58,12 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			pit: timer at fffffd30 {
> +				compatible = "atmel,at91sam9260-pit";
> +				reg = <0xfffffd30 0xf>;
> +				interrupts = <1 4>;
> +			};
> +
>  			dma: dma-controller at ffffec00 {
>  				compatible = "atmel,at91sam9g45-dma";
>  				reg = <0xffffec00 0x200>;
> diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
> index d89ead7..802fea3 100644
> --- a/arch/arm/mach-at91/at91sam926x_time.c
> +++ b/arch/arm/mach-at91/at91sam926x_time.c
> @@ -14,6 +14,9 @@
>  #include <linux/kernel.h>
>  #include <linux/clk.h>
>  #include <linux/clockchips.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
>  
>  #include <asm/mach/time.h>
>  
> @@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
>  static struct irqaction at91sam926x_pit_irq = {
>  	.name		= "at91_tick",
>  	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
> -	.handler	= at91sam926x_pit_interrupt
> +	.handler	= at91sam926x_pit_interrupt,
> +	.irq		= AT91_ID_SYS,
>  };
>  
>  static void at91sam926x_pit_reset(void)
> @@ -149,6 +153,49 @@ static void at91sam926x_pit_reset(void)
>  	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
>  }
>  
> +#ifdef CONFIG_OF
> +static struct of_device_id timer_ids[] = {
> +	{ .compatible = "atmel,at91sam9260-pit" },
> +	{ /* sentinel */ }
> +};
> +
> +static int __init of_at91sam926x_pit_init(void)
> +{
> +	struct device_node	*np;
> +	int			ret;
> +
> +	np = of_find_matching_node(NULL, timer_ids);
> +	if (!np)
> +		goto err;
> +
> +	pit_base_addr = of_iomap(np, 0);
> +	if (!pit_base_addr)
> +		goto node_err;
> +
> +	/* Get the interrupts property */
> +	ret = irq_of_parse_and_map(np, 0);
> +	if (!ret)
> +		goto ioremap_err;
> +	at91sam926x_pit_irq.irq = ret;
> +
> +	of_node_put(np);
> +
> +	return 0;
> +
> +ioremap_err:
> +	iounmap(pit_base_addr);
> +node_err:
> +	of_node_put(np);
> +err:
> +	return -EINVAL;
> +}
> +#else
> +static int __init of_at91sam926x_pit_init(void)
> +{
> +	return -EINVAL;
> +}
> +#endif
> +
>  /*
>   * Set up both clocksource and clockevent support.
>   */
> @@ -177,7 +224,7 @@ static void __init at91sam926x_pit_init(void)
>  	clocksource_register_hz(&pit_clk, pit_rate);
>  
>  	/* Set up irq handler */
> -	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
> +	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
>  
>  	/* Set up and register clockevents */
>  	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
> @@ -193,10 +240,11 @@ static void at91sam926x_pit_suspend(void)
>  
>  void __init at91sam926x_ioremap_pit(u32 addr)
>  {
> -	pit_base_addr = ioremap(addr, 16);
> -
> -	if (!pit_base_addr)
> -		panic("Impossible to ioremap PIT\n");
> +	if (of_at91sam926x_pit_init() < 0) {
> +		pit_base_addr = ioremap(addr, 16);
> +		if (!pit_base_addr)
> +			panic("Impossible to ioremap PIT\n");
> +	}

This is not what I meant. I meant call either at91sam926x_ioremap_pit or
of_at91sam926x_pit_init. Don't nest the calls and keep the OF and non-OF
init somewhat separate. The fact that you are passing in the physical
address and then ignoring it for the OF case is what I have issue with.

Rob

>  }
>  
>  struct sys_timer at91sam926x_timer = {

[PATCH v4] ARM: at91: pit add DT support

[Nicolas Ferre]

On 01/06/2012 04:47 PM, Rob Herring :
> On 01/06/2012 10:20 AM, Nicolas Ferre wrote:
>> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>>
>> Retreive registers address and IRQ from device tree entry. Fall back
>> to built-in values if an error occurs.
>>
>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>> Reviewed-by: Jamie Iles <jamie@jamieiles.com>
>> Acked-by: Rob Herring <rob.herring@calxeda.com>
>> ---
>> v4: - change of_at91sam926x_pit_init() return value usage logic as
>>       suggested by Rob Herring
>>     - irq_of_parse_and_map() returns 0 on error: change test according to 
>>       Grant Likely note.
>>
>> v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
>>       Correction proposed by Jamie Iles.
>>
>> v2: - new specification of irq numbers in DT (due to modification of AIC code)
>>     - new error path in of_at91sam926x_pit_init()
>>     - fall back to built-in values if an error occurs
>>     - use of of_property_read_u32() to get irq property
>>
>>  .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
>>  arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
>>  arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
>>  arch/arm/mach-at91/at91sam926x_time.c              |   60 ++++++++++++++++++--
>>  4 files changed, 73 insertions(+), 6 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
>> new file mode 100644
>> index 0000000..380f711
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
>> @@ -0,0 +1,8 @@
>> +Atmel AT91 device tree bindings.
>> +================================
>> +
>> +PIT Timer required properties:
>> +- compatible: Should be "atmel,at91sam9260-pit"
>> +- reg: Should contain registers location and length
>> +- interrupts: Should contain interrupt for the PIT which is the IRQ line
>> +  shared across all System Controller members.
>> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
>> index ea942b5..e10842a 100644
>> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
>> @@ -57,6 +57,11 @@
>>  				reg = <0xfffff000 0x200>;
>>  			};
>>  
>> +			pit: timer at fffffd30 {
>> +				compatible = "atmel,at91sam9260-pit";
>> +				reg = <0xfffffd30 0xf>;
>> +				interrupts = <1 4>;
>> +			};
>>  
>>  			pioA: gpio at fffff400 {
>>  				compatible = "atmel,at91rm9200-gpio";
>> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
>> index ebc9617..28a678f 100644
>> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
>> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
>> @@ -58,6 +58,12 @@
>>  				reg = <0xfffff000 0x200>;
>>  			};
>>  
>> +			pit: timer at fffffd30 {
>> +				compatible = "atmel,at91sam9260-pit";
>> +				reg = <0xfffffd30 0xf>;
>> +				interrupts = <1 4>;
>> +			};
>> +
>>  			dma: dma-controller at ffffec00 {
>>  				compatible = "atmel,at91sam9g45-dma";
>>  				reg = <0xffffec00 0x200>;
>> diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
>> index d89ead7..802fea3 100644
>> --- a/arch/arm/mach-at91/at91sam926x_time.c
>> +++ b/arch/arm/mach-at91/at91sam926x_time.c
>> @@ -14,6 +14,9 @@
>>  #include <linux/kernel.h>
>>  #include <linux/clk.h>
>>  #include <linux/clockchips.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>>  
>>  #include <asm/mach/time.h>
>>  
>> @@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
>>  static struct irqaction at91sam926x_pit_irq = {
>>  	.name		= "at91_tick",
>>  	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
>> -	.handler	= at91sam926x_pit_interrupt
>> +	.handler	= at91sam926x_pit_interrupt,
>> +	.irq		= AT91_ID_SYS,
>>  };
>>  
>>  static void at91sam926x_pit_reset(void)
>> @@ -149,6 +153,49 @@ static void at91sam926x_pit_reset(void)
>>  	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
>>  }
>>  
>> +#ifdef CONFIG_OF
>> +static struct of_device_id timer_ids[] = {
>> +	{ .compatible = "atmel,at91sam9260-pit" },
>> +	{ /* sentinel */ }
>> +};
>> +
>> +static int __init of_at91sam926x_pit_init(void)
>> +{
>> +	struct device_node	*np;
>> +	int			ret;
>> +
>> +	np = of_find_matching_node(NULL, timer_ids);
>> +	if (!np)
>> +		goto err;
>> +
>> +	pit_base_addr = of_iomap(np, 0);
>> +	if (!pit_base_addr)
>> +		goto node_err;
>> +
>> +	/* Get the interrupts property */
>> +	ret = irq_of_parse_and_map(np, 0);
>> +	if (!ret)
>> +		goto ioremap_err;
>> +	at91sam926x_pit_irq.irq = ret;
>> +
>> +	of_node_put(np);
>> +
>> +	return 0;
>> +
>> +ioremap_err:
>> +	iounmap(pit_base_addr);
>> +node_err:
>> +	of_node_put(np);
>> +err:
>> +	return -EINVAL;
>> +}
>> +#else
>> +static int __init of_at91sam926x_pit_init(void)
>> +{
>> +	return -EINVAL;
>> +}
>> +#endif
>> +
>>  /*
>>   * Set up both clocksource and clockevent support.
>>   */
>> @@ -177,7 +224,7 @@ static void __init at91sam926x_pit_init(void)
>>  	clocksource_register_hz(&pit_clk, pit_rate);
>>  
>>  	/* Set up irq handler */
>> -	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
>> +	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
>>  
>>  	/* Set up and register clockevents */
>>  	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
>> @@ -193,10 +240,11 @@ static void at91sam926x_pit_suspend(void)
>>  
>>  void __init at91sam926x_ioremap_pit(u32 addr)
>>  {
>> -	pit_base_addr = ioremap(addr, 16);
>> -
>> -	if (!pit_base_addr)
>> -		panic("Impossible to ioremap PIT\n");
>> +	if (of_at91sam926x_pit_init() < 0) {
>> +		pit_base_addr = ioremap(addr, 16);
>> +		if (!pit_base_addr)
>> +			panic("Impossible to ioremap PIT\n");
>> +	}
> 
> This is not what I meant. I meant call either at91sam926x_ioremap_pit or
> of_at91sam926x_pit_init. Don't nest the calls and keep the OF and non-OF
> init somewhat separate. The fact that you are passing in the physical
> address and then ignoring it for the OF case is what I have issue with.

I see...

I did not understand this way because I was so obsessed by the fact to
not introduce another interface to the PIT.

But it is true that as our future SoCs will only rely on DT to get PIT
data, we will not have the knowledge of its physical address: this is
speaking in favor of what you are saying -> I should keep those init
separated and called from the <soc_name>_ioremap_registers() functions.

Jean-Christophe, do you agree with this? If yes, I have already the
patch ready and will send a v5 of this one...

Bye,
-- 
Nicolas Ferre

[PATCH v4] ARM: at91: pit add DT support

[Jean-Christophe PLAGNIOL-VILLARD]

On 09:47 Fri 06 Jan     , Rob Herring wrote:
> On 01/06/2012 10:20 AM, Nicolas Ferre wrote:
> > From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> > 
> > Retreive registers address and IRQ from device tree entry. Fall back
> > to built-in values if an error occurs.
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> > [nicolas.ferre at atmel.com: change error path and interrupts property handling]
> > Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> > Reviewed-by: Jamie Iles <jamie@jamieiles.com>
> > Acked-by: Rob Herring <rob.herring@calxeda.com>
> > ---
> > v4: - change of_at91sam926x_pit_init() return value usage logic as
> >       suggested by Rob Herring
> >     - irq_of_parse_and_map() returns 0 on error: change test according to 
> >       Grant Likely note.
> > 
> > v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
> >       Correction proposed by Jamie Iles.
> > 
> > v2: - new specification of irq numbers in DT (due to modification of AIC code)
> >     - new error path in of_at91sam926x_pit_init()
> >     - fall back to built-in values if an error occurs
> >     - use of of_property_read_u32() to get irq property
> > 
> >  .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
> >  arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
> >  arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
> >  arch/arm/mach-at91/at91sam926x_time.c              |   60 ++++++++++++++++++--
> >  4 files changed, 73 insertions(+), 6 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> > new file mode 100644
> > index 0000000..380f711
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> > @@ -0,0 +1,8 @@
> > +Atmel AT91 device tree bindings.
> > +================================
> > +
> > +PIT Timer required properties:
> > +- compatible: Should be "atmel,at91sam9260-pit"
> > +- reg: Should contain registers location and length
> > +- interrupts: Should contain interrupt for the PIT which is the IRQ line
> > +  shared across all System Controller members.
> > diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> > index ea942b5..e10842a 100644
> > --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> > +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> > @@ -57,6 +57,11 @@
> >  				reg = <0xfffff000 0x200>;
> >  			};
> >  
> > +			pit: timer at fffffd30 {
> > +				compatible = "atmel,at91sam9260-pit";
> > +				reg = <0xfffffd30 0xf>;
> > +				interrupts = <1 4>;
> > +			};
> >  
> >  			pioA: gpio at fffff400 {
> >  				compatible = "atmel,at91rm9200-gpio";
> > diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> > index ebc9617..28a678f 100644
> > --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> > +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> > @@ -58,6 +58,12 @@
> >  				reg = <0xfffff000 0x200>;
> >  			};
> >  
> > +			pit: timer at fffffd30 {
> > +				compatible = "atmel,at91sam9260-pit";
> > +				reg = <0xfffffd30 0xf>;
> > +				interrupts = <1 4>;
> > +			};
> > +
> >  			dma: dma-controller at ffffec00 {
> >  				compatible = "atmel,at91sam9g45-dma";
> >  				reg = <0xffffec00 0x200>;
> > diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
> > index d89ead7..802fea3 100644
> > --- a/arch/arm/mach-at91/at91sam926x_time.c
> > +++ b/arch/arm/mach-at91/at91sam926x_time.c
> > @@ -14,6 +14,9 @@
> >  #include <linux/kernel.h>
> >  #include <linux/clk.h>
> >  #include <linux/clockchips.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> >  
> >  #include <asm/mach/time.h>
> >  
> > @@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
> >  static struct irqaction at91sam926x_pit_irq = {
> >  	.name		= "at91_tick",
> >  	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
> > -	.handler	= at91sam926x_pit_interrupt
> > +	.handler	= at91sam926x_pit_interrupt,
> > +	.irq		= AT91_ID_SYS,
> >  };
> >  
> >  static void at91sam926x_pit_reset(void)
> > @@ -149,6 +153,49 @@ static void at91sam926x_pit_reset(void)
> >  	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
> >  }
> >  
> > +#ifdef CONFIG_OF
> > +static struct of_device_id timer_ids[] = {
> > +	{ .compatible = "atmel,at91sam9260-pit" },
> > +	{ /* sentinel */ }
> > +};
> > +
> > +static int __init of_at91sam926x_pit_init(void)
> > +{
> > +	struct device_node	*np;
> > +	int			ret;
> > +
> > +	np = of_find_matching_node(NULL, timer_ids);
> > +	if (!np)
> > +		goto err;
> > +
> > +	pit_base_addr = of_iomap(np, 0);
> > +	if (!pit_base_addr)
> > +		goto node_err;
> > +
> > +	/* Get the interrupts property */
> > +	ret = irq_of_parse_and_map(np, 0);
> > +	if (!ret)
> > +		goto ioremap_err;
> > +	at91sam926x_pit_irq.irq = ret;
> > +
> > +	of_node_put(np);
> > +
> > +	return 0;
> > +
> > +ioremap_err:
> > +	iounmap(pit_base_addr);
> > +node_err:
> > +	of_node_put(np);
> > +err:
> > +	return -EINVAL;
> > +}
> > +#else
> > +static int __init of_at91sam926x_pit_init(void)
> > +{
> > +	return -EINVAL;
> > +}
> > +#endif
> > +
> >  /*
> >   * Set up both clocksource and clockevent support.
> >   */
> > @@ -177,7 +224,7 @@ static void __init at91sam926x_pit_init(void)
> >  	clocksource_register_hz(&pit_clk, pit_rate);
> >  
> >  	/* Set up irq handler */
> > -	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
> > +	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
> >  
> >  	/* Set up and register clockevents */
> >  	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
> > @@ -193,10 +240,11 @@ static void at91sam926x_pit_suspend(void)
> >  
> >  void __init at91sam926x_ioremap_pit(u32 addr)
> >  {
> > -	pit_base_addr = ioremap(addr, 16);
> > -
> > -	if (!pit_base_addr)
> > -		panic("Impossible to ioremap PIT\n");
> > +	if (of_at91sam926x_pit_init() < 0) {
> > +		pit_base_addr = ioremap(addr, 16);
> > +		if (!pit_base_addr)
> > +			panic("Impossible to ioremap PIT\n");
> > +	}
> 
> This is not what I meant. I meant call either at91sam926x_ioremap_pit or
> of_at91sam926x_pit_init. Don't nest the calls and keep the OF and non-OF
> init somewhat separate. The fact that you are passing in the physical
> address and then ignoring it for the OF case is what I have issue with.

the DT pure soc will pass NULL for soc that support both or only non of we
pass the PHY addr

Best Regards,
J.

[PATCH v4] ARM: at91: pit add DT support

[Nicolas Ferre]

On 01/09/2012 06:39 PM, Jean-Christophe PLAGNIOL-VILLARD :
> On 09:47 Fri 06 Jan     , Rob Herring wrote:
>> On 01/06/2012 10:20 AM, Nicolas Ferre wrote:
>>> From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>>>
>>> Retreive registers address and IRQ from device tree entry. Fall back
>>> to built-in values if an error occurs.
>>>
>>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>>> [nicolas.ferre at atmel.com: change error path and interrupts property handling]
>>> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>>> Reviewed-by: Jamie Iles <jamie@jamieiles.com>
>>> Acked-by: Rob Herring <rob.herring@calxeda.com>
>>> ---
>>> v4: - change of_at91sam926x_pit_init() return value usage logic as
>>>       suggested by Rob Herring
>>>     - irq_of_parse_and_map() returns 0 on error: change test according to 
>>>       Grant Likely note.
>>>
>>> v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
>>>       Correction proposed by Jamie Iles.
>>>
>>> v2: - new specification of irq numbers in DT (due to modification of AIC code)
>>>     - new error path in of_at91sam926x_pit_init()
>>>     - fall back to built-in values if an error occurs
>>>     - use of of_property_read_u32() to get irq property
>>>
>>>  .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
>>>  arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
>>>  arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
>>>  arch/arm/mach-at91/at91sam926x_time.c              |   60 ++++++++++++++++++--
>>>  4 files changed, 73 insertions(+), 6 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
>>> new file mode 100644
>>> index 0000000..380f711
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
>>> @@ -0,0 +1,8 @@
>>> +Atmel AT91 device tree bindings.
>>> +================================
>>> +
>>> +PIT Timer required properties:
>>> +- compatible: Should be "atmel,at91sam9260-pit"
>>> +- reg: Should contain registers location and length
>>> +- interrupts: Should contain interrupt for the PIT which is the IRQ line
>>> +  shared across all System Controller members.
>>> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
>>> index ea942b5..e10842a 100644
>>> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
>>> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
>>> @@ -57,6 +57,11 @@
>>>  				reg = <0xfffff000 0x200>;
>>>  			};
>>>  
>>> +			pit: timer at fffffd30 {
>>> +				compatible = "atmel,at91sam9260-pit";
>>> +				reg = <0xfffffd30 0xf>;
>>> +				interrupts = <1 4>;
>>> +			};
>>>  
>>>  			pioA: gpio at fffff400 {
>>>  				compatible = "atmel,at91rm9200-gpio";
>>> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
>>> index ebc9617..28a678f 100644
>>> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
>>> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
>>> @@ -58,6 +58,12 @@
>>>  				reg = <0xfffff000 0x200>;
>>>  			};
>>>  
>>> +			pit: timer at fffffd30 {
>>> +				compatible = "atmel,at91sam9260-pit";
>>> +				reg = <0xfffffd30 0xf>;
>>> +				interrupts = <1 4>;
>>> +			};
>>> +
>>>  			dma: dma-controller at ffffec00 {
>>>  				compatible = "atmel,at91sam9g45-dma";
>>>  				reg = <0xffffec00 0x200>;
>>> diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
>>> index d89ead7..802fea3 100644
>>> --- a/arch/arm/mach-at91/at91sam926x_time.c
>>> +++ b/arch/arm/mach-at91/at91sam926x_time.c
>>> @@ -14,6 +14,9 @@
>>>  #include <linux/kernel.h>
>>>  #include <linux/clk.h>
>>>  #include <linux/clockchips.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/of_irq.h>
>>>  
>>>  #include <asm/mach/time.h>
>>>  
>>> @@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
>>>  static struct irqaction at91sam926x_pit_irq = {
>>>  	.name		= "at91_tick",
>>>  	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
>>> -	.handler	= at91sam926x_pit_interrupt
>>> +	.handler	= at91sam926x_pit_interrupt,
>>> +	.irq		= AT91_ID_SYS,
>>>  };
>>>  
>>>  static void at91sam926x_pit_reset(void)
>>> @@ -149,6 +153,49 @@ static void at91sam926x_pit_reset(void)
>>>  	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
>>>  }
>>>  
>>> +#ifdef CONFIG_OF
>>> +static struct of_device_id timer_ids[] = {
>>> +	{ .compatible = "atmel,at91sam9260-pit" },
>>> +	{ /* sentinel */ }
>>> +};
>>> +
>>> +static int __init of_at91sam926x_pit_init(void)
>>> +{
>>> +	struct device_node	*np;
>>> +	int			ret;
>>> +
>>> +	np = of_find_matching_node(NULL, timer_ids);
>>> +	if (!np)
>>> +		goto err;
>>> +
>>> +	pit_base_addr = of_iomap(np, 0);
>>> +	if (!pit_base_addr)
>>> +		goto node_err;
>>> +
>>> +	/* Get the interrupts property */
>>> +	ret = irq_of_parse_and_map(np, 0);
>>> +	if (!ret)
>>> +		goto ioremap_err;
>>> +	at91sam926x_pit_irq.irq = ret;
>>> +
>>> +	of_node_put(np);
>>> +
>>> +	return 0;
>>> +
>>> +ioremap_err:
>>> +	iounmap(pit_base_addr);
>>> +node_err:
>>> +	of_node_put(np);
>>> +err:
>>> +	return -EINVAL;
>>> +}
>>> +#else
>>> +static int __init of_at91sam926x_pit_init(void)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +#endif
>>> +
>>>  /*
>>>   * Set up both clocksource and clockevent support.
>>>   */
>>> @@ -177,7 +224,7 @@ static void __init at91sam926x_pit_init(void)
>>>  	clocksource_register_hz(&pit_clk, pit_rate);
>>>  
>>>  	/* Set up irq handler */
>>> -	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
>>> +	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
>>>  
>>>  	/* Set up and register clockevents */
>>>  	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
>>> @@ -193,10 +240,11 @@ static void at91sam926x_pit_suspend(void)
>>>  
>>>  void __init at91sam926x_ioremap_pit(u32 addr)
>>>  {
>>> -	pit_base_addr = ioremap(addr, 16);
>>> -
>>> -	if (!pit_base_addr)
>>> -		panic("Impossible to ioremap PIT\n");
>>> +	if (of_at91sam926x_pit_init() < 0) {
>>> +		pit_base_addr = ioremap(addr, 16);
>>> +		if (!pit_base_addr)
>>> +			panic("Impossible to ioremap PIT\n");
>>> +	}
>>
>> This is not what I meant. I meant call either at91sam926x_ioremap_pit or
>> of_at91sam926x_pit_init. Don't nest the calls and keep the OF and non-OF
>> init somewhat separate. The fact that you are passing in the physical
>> address and then ignoring it for the OF case is what I have issue with.
> 
> the DT pure soc will pass NULL for soc that support both or only non of we
> pass the PHY addr

Yes, but don't your prefer to have another call that we can use as the
interface? In the future we will only have DT enabled SoC so maintaining
the need for this NULL parameter does not make much sense...

Bye,
-- 
Nicolas Ferre

[PATCH v5 1/2] ARM: at91: pit add DT support

[Nicolas Ferre]

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Retreive registers address and IRQ from device tree entry.
Called from at91_dt_init_irq() so that timers are up-n-running
when timers initialization will occur.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
[nicolas.ferre at atmel.com: change error path and interrupts property handling]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
Hi,

I have removed Rob's "Acked-by" and Jamie's "Reviewed-by" because I have changed
the way PIT is initialized. Do you want to put it back? 

v5: - of_at91sam926x_pit_init() now called from at91sam926x_pit_init()
      which is the init function of the system tick timer.
    - get out of at91sam926x_ioremap_pit() if matching node found in DT.

v4: - change of_at91sam926x_pit_init() return value usage logic as
      suggested by Rob Herring
    - irq_of_parse_and_map() returns 0 on error: change test according to 
      Grant Likely note.

v3: - use irq_of_parse_and_map() for handling irq numbers specified by DT.
      Correction proposed by Jamie Iles.

v2: - new specification of irq numbers in DT (due to modification of AIC code)
    - new error path in of_at91sam926x_pit_init()
    - fall back to built-in values if an error occurs
    - use of of_property_read_u32() to get irq property

 .../devicetree/bindings/arm/atmel-at91.txt         |    8 +++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    6 ++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++
 arch/arm/mach-at91/at91sam926x_time.c              |   63 +++++++++++++++++++-
 arch/arm/mach-at91/at91sam9x5.c                    |    2 -
 arch/arm/mach-at91/generic.h                       |    1 +
 6 files changed, 82 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
new file mode 100644
index 0000000..380f711
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -0,0 +1,8 @@
+Atmel AT91 device tree bindings.
+================================
+
+PIT Timer required properties:
+- compatible: Should be "atmel,at91sam9260-pit"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the PIT which is the IRQ line
+  shared across all System Controller members.
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 325989a..04c56c4 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -57,6 +57,12 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pit: timer at fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 4>;
+			};
+
 			pioA: gpio at fffff400 {
 				compatible = "atmel,at91rm9200-gpio";
 				reg = <0xfffff400 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index a9dbbb5..3881cab 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -58,6 +58,12 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pit: timer at fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 4>;
+			};
+
 			dma: dma-controller at ffffec00 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffec00 0x200>;
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index d89ead7..8e5cc37 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -14,6 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 
@@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 static struct irqaction at91sam926x_pit_irq = {
 	.name		= "at91_tick",
 	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-	.handler	= at91sam926x_pit_interrupt
+	.handler	= at91sam926x_pit_interrupt,
+	.irq		= AT91_ID_SYS,
 };
 
 static void at91sam926x_pit_reset(void)
@@ -149,6 +153,49 @@ static void at91sam926x_pit_reset(void)
 	pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id pit_timer_ids[] = {
+	{ .compatible = "atmel,at91sam9260-pit" },
+	{ /* sentinel */ }
+};
+
+int __init of_at91sam926x_pit_init(void)
+{
+	struct device_node	*np;
+	int			ret;
+
+	np = of_find_matching_node(NULL, pit_timer_ids);
+	if (!np)
+		goto err;
+
+	pit_base_addr = of_iomap(np, 0);
+	if (!pit_base_addr)
+		goto node_err;
+
+	/* Get the interrupts property */
+	ret = irq_of_parse_and_map(np, 0);
+	if (!ret)
+		goto ioremap_err;
+	at91sam926x_pit_irq.irq = ret;
+
+	of_node_put(np);
+
+	return 0;
+
+ioremap_err:
+	iounmap(pit_base_addr);
+node_err:
+	of_node_put(np);
+err:
+	return -EINVAL;
+}
+#else
+int __init of_at91sam926x_pit_init(void)
+{
+	return -EINVAL;
+}
+#endif
+
 /*
  * Set up both clocksource and clockevent support.
  */
@@ -157,6 +204,9 @@ static void __init at91sam926x_pit_init(void)
 	unsigned long	pit_rate;
 	unsigned	bits;
 
+	/* For device tree enabled device: initialize here */
+	of_at91sam926x_pit_init();
+
 	/*
 	 * Use our actual MCK to figure out how many MCK/16 ticks per
 	 * 1/HZ period (instead of a compile-time constant LATCH).
@@ -177,7 +227,7 @@ static void __init at91sam926x_pit_init(void)
 	clocksource_register_hz(&pit_clk, pit_rate);
 
 	/* Set up irq handler */
-	setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
 
 	/* Set up and register clockevents */
 	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
@@ -193,6 +243,15 @@ static void at91sam926x_pit_suspend(void)
 
 void __init at91sam926x_ioremap_pit(u32 addr)
 {
+#if defined(CONFIG_OF)
+	struct device_node *np =
+		of_find_matching_node(NULL, pit_timer_ids);
+
+	if (np) {
+		of_node_put(np);
+		return;
+	}
+#endif
 	pit_base_addr = ioremap(addr, 16);
 
 	if (!pit_base_addr)
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 1c3444d..3e33711 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -301,8 +301,6 @@ static void __init at91sam9x5_map_io(void)
 
 static void __init at91sam9x5_ioremap_registers(void)
 {
-	if (of_at91sam926x_pit_init() < 0)
-		panic("Impossible to find PIT\n");
 }
 
 void __init at91sam9x5_initialize(void)
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 0726f42..c5d16e5 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -33,6 +33,7 @@ extern int  __init at91_aic_of_init(struct device_node *node,
  /* Timer */
 struct sys_timer;
 extern struct sys_timer at91rm9200_timer;
+extern int of_at91sam926x_pit_init(void);
 extern void at91sam926x_ioremap_pit(u32 addr);
 extern struct sys_timer at91sam926x_timer;
 extern struct sys_timer at91x40_timer;
-- 
1.7.9

[PATCH v5 2/2] ARM: at91/pit: add traces in case of error

[Nicolas Ferre]

Traces related to IRQ management are useful for timers in case of
non-working IRQ subsystem (switch to irq_domain for instance).

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/mach-at91/at91sam926x_time.c |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 8e5cc37..e4f7ba0 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -174,8 +174,10 @@ int __init of_at91sam926x_pit_init(void)
 
 	/* Get the interrupts property */
 	ret = irq_of_parse_and_map(np, 0);
-	if (!ret)
+	if (!ret) {
+		pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
 		goto ioremap_err;
+	}
 	at91sam926x_pit_irq.irq = ret;
 
 	of_node_put(np);
@@ -203,6 +205,7 @@ static void __init at91sam926x_pit_init(void)
 {
 	unsigned long	pit_rate;
 	unsigned	bits;
+	int		ret;
 
 	/* For device tree enabled device: initialize here */
 	of_at91sam926x_pit_init();
@@ -227,7 +230,9 @@ static void __init at91sam926x_pit_init(void)
 	clocksource_register_hz(&pit_clk, pit_rate);
 
 	/* Set up irq handler */
-	setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
+	ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
+	if (ret)
+		pr_crit("AT91: PIT: Unable to setup IRQ\n");
 
 	/* Set up and register clockevents */
 	pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
-- 
1.7.9