From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/3] ARM: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary
Date: Tue, 17 Jan 2012 16:47:55 +0000 [thread overview]
Message-ID: <1326818876-4818-2-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1326818876-4818-1-git-send-email-will.deacon@arm.com>
The exception fixup table is currently aligned to a 32-byte boundary.
Whilst this won't cause any problems, the exception_table_entry
structures contain only a pair of unsigned longs, so 4-byte alignment
is all that is required.
Cc: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/kernel/vmlinux.lds.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 1077e4f..1e19691 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -219,7 +219,7 @@ SECTIONS
/*
* The exception fixup table (might need resorting at runtime)
*/
- . = ALIGN(32);
+ . = ALIGN(4);
__start___ex_table = .;
#ifdef CONFIG_MMU
*(__ex_table)
--
1.7.4.1
next prev parent reply other threads:[~2012-01-17 16:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-17 16:47 [PATCH v3 1/3] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes Will Deacon
2012-01-17 16:47 ` Will Deacon [this message]
2012-01-17 18:18 ` [PATCH v3 2/3] ARM: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary Nicolas Pitre
2012-01-17 19:09 ` Will Deacon
2012-01-17 16:47 ` [PATCH v3 3/3] ARM: cache: assume 64-byte L1 cachelines for ARMv7 CPUs Will Deacon
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