[PATCH v3 1/3] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes

[PATCH v3 1/3] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes

[Will Deacon]

The linker script assumes a cacheline size of 32 bytes when aligning
the .data..cacheline_aligned and .data..percpu sections.

This patch updates the script to use L1_CACHE_BYTES, which should be set
to 64 on platforms that require it.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/kernel/vmlinux.lds.S |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index f76e755..1077e4f 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -4,6 +4,7 @@
  */
 
 #include <asm-generic/vmlinux.lds.h>
+#include <asm/cache.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/page.h>
@@ -181,7 +182,7 @@ SECTIONS
 	}
 #endif
 
-	PERCPU_SECTION(32)
+	PERCPU_SECTION(L1_CACHE_BYTES)
 
 #ifdef CONFIG_XIP_KERNEL
 	__data_loc = ALIGN(4);		/* location in binary */
@@ -212,8 +213,8 @@ SECTIONS
 #endif
 
 		NOSAVE_DATA
-		CACHELINE_ALIGNED_DATA(32)
-		READ_MOSTLY_DATA(32)
+		CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
+		READ_MOSTLY_DATA(L1_CACHE_BYTES)
 
 		/*
 		 * The exception fixup table (might need resorting at runtime)
-- 
1.7.4.1

[PATCH v3 2/3] ARM: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary

[Will Deacon]

The exception fixup table is currently aligned to a 32-byte boundary.
Whilst this won't cause any problems, the exception_table_entry
structures contain only a pair of unsigned longs, so 4-byte alignment
is all that is required.

Cc: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/kernel/vmlinux.lds.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 1077e4f..1e19691 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -219,7 +219,7 @@ SECTIONS
 		/*
 		 * The exception fixup table (might need resorting at runtime)
 		 */
-		. = ALIGN(32);
+		. = ALIGN(4);
 		__start___ex_table = .;
 #ifdef CONFIG_MMU
 		*(__ex_table)
-- 
1.7.4.1

[PATCH v3 2/3] ARM: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary

[Nicolas Pitre]

On Tue, 17 Jan 2012, Will Deacon wrote:

> The exception fixup table is currently aligned to a 32-byte boundary.
> Whilst this won't cause any problems, the exception_table_entry
> structures contain only a pair of unsigned longs, so 4-byte alignment
> is all that is required.

If the table was also walked from start to end, that could also be an 
argument for aligning it to a cache line so the first access always 
fetches a whole cache line worth of usable data.  But the access is done 
through a binary search which is totally random as far as access pattern 
goes.  That would be worth mentioning in the commit log.

With that:

Acked-by: Nicolas Pitre <nico@linaro.org>

> Cc: Nicolas Pitre <nico@fluxnic.net>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
>  arch/arm/kernel/vmlinux.lds.S |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
> index 1077e4f..1e19691 100644
> --- a/arch/arm/kernel/vmlinux.lds.S
> +++ b/arch/arm/kernel/vmlinux.lds.S
> @@ -219,7 +219,7 @@ SECTIONS
>  		/*
>  		 * The exception fixup table (might need resorting at runtime)
>  		 */
> -		. = ALIGN(32);
> +		. = ALIGN(4);
>  		__start___ex_table = .;
>  #ifdef CONFIG_MMU
>  		*(__ex_table)
> -- 
> 1.7.4.1
> 

[PATCH v3 2/3] ARM: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary

[Will Deacon]

On Tue, Jan 17, 2012 at 06:18:47PM +0000, Nicolas Pitre wrote:
> On Tue, 17 Jan 2012, Will Deacon wrote:
> 
> > The exception fixup table is currently aligned to a 32-byte boundary.
> > Whilst this won't cause any problems, the exception_table_entry
> > structures contain only a pair of unsigned longs, so 4-byte alignment
> > is all that is required.
> 
> If the table was also walked from start to end, that could also be an 
> argument for aligning it to a cache line so the first access always 
> fetches a whole cache line worth of usable data.  But the access is done 
> through a binary search which is totally random as far as access pattern 
> goes.  That would be worth mentioning in the commit log.

Good point, I'll add that to the message.

> With that:
> 
> Acked-by: Nicolas Pitre <nico@linaro.org>

Thanks Nicolas!

Will

[PATCH v3 3/3] ARM: cache: assume 64-byte L1 cachelines for ARMv7 CPUs

[Will Deacon]

To ensure correct alignment of cacheline-aligned data, the maximum
cacheline size needs to be known at compile time.

Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely
that there will be future ARMv7 implementations with the same line size)
then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline
size. For CPUs with smaller caches, this will result in some harmless
padding but will help with single zImage work and avoid hitting subtle
bugs with misaligned data structures.

Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/Kconfig            |    2 --
 arch/arm/mach-mx5/Kconfig   |    3 ---
 arch/arm/mach-omap2/Kconfig |    1 -
 arch/arm/mm/Kconfig         |    1 +
 4 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 24626b0..6e40039 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -825,7 +825,6 @@ config ARCH_S5PC100
 	select HAVE_CLK
 	select CLKDEV_LOOKUP
 	select CPU_V7
-	select ARM_L1_CACHE_SHIFT_6
 	select ARCH_USES_GETTIMEOFFSET
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C_RTC if RTC_CLASS
@@ -842,7 +841,6 @@ config ARCH_S5PV210
 	select HAVE_CLK
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
-	select ARM_L1_CACHE_SHIFT_6
 	select ARCH_HAS_CPUFREQ
 	select GENERIC_CLOCKEVENTS
 	select HAVE_SCHED_CLOCK
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index af0c212..9cf4c3c 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -15,7 +15,6 @@ config ARCH_MX53
 config SOC_IMX50
 	bool
 	select CPU_V7
-	select ARM_L1_CACHE_SHIFT_6
 	select MXC_TZIC
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MXC_AUDMUX_V2
@@ -25,7 +24,6 @@ config SOC_IMX50
 config	SOC_IMX51
 	bool
 	select CPU_V7
-	select ARM_L1_CACHE_SHIFT_6
 	select MXC_TZIC
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MXC_AUDMUX_V2
@@ -35,7 +33,6 @@ config	SOC_IMX51
 config	SOC_IMX53
 	bool
 	select CPU_V7
-	select ARM_L1_CACHE_SHIFT_6
 	select MXC_TZIC
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MX53
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 904bd1d..ac6b1d3 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -33,7 +33,6 @@ config ARCH_OMAP3
 	default y
 	select CPU_V7
 	select USB_ARCH_HAS_EHCI
-	select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
 	select ARCH_HAS_OPP
 	select PM_OPP if PM
 	select ARM_CPU_SUSPEND if PM
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 4cefb57..1a3ca24 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -882,6 +882,7 @@ config CACHE_XSC3L2
 
 config ARM_L1_CACHE_SHIFT_6
 	bool
+	default y if CPU_V7
 	help
 	  Setting ARM L1 cache line size to 64 Bytes.
 
-- 
1.7.4.1