[PATCH v3 0/4] ARM: Exynos4: Add irq domain and device tree support for wakeup interrupts

[PATCH v3 0/4] ARM: Exynos4: Add irq domain and device tree support for wakeup interrupts

[Thomas Abraham]

Changes since v2:
- Reworked irq domain support based on v5 of the irq_domain generalization
  patches.

Changes since v1: (only patch 4/4 has changes)
- Fixes based on Rob's comments:
  a. Fixed the function prototype of exynos4_init_irq_eint(void)
  b. Included interrupt-parent as an optional property for wakeup interrupt
      controller node.

Samsung Exynos4 includes 32 external wakeup interrupt sources. The first 16
of these interrupts are connected to GIC SPI[31:16]. The last 16 of these
interrupts are grouped together into one interrupt and connected to GIC
SPI[32].

This patchset adds irq domain and device tree support for these interrupts.
Since there are users of fixed linux irq numbers of the external wakeup
interrupts, the legacy mapping is used for the irq domain.

This patchset is based on
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]

with all irq_domain (v5) patches merged from
http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]

This patchset should be applied after applying the following patch.
[PATCH] ARM: Exynos: Add irq domain and device tree support for interrupt combiner

Thomas Abraham (4):
  ARM: Exynos4: Simplify EINT number to linux irq number translation
  ARM: Exynos4: Add irq_domain support for gpio wakeup interrupts
  ARM: Exynos4: Remove arch_initcall for wakeup interrupt initialization
  ARM: Exynos4: Add device tree support for gpio wakeup interrupt controller

 .../bindings/arm/samsung/wakeup-eint.txt           |   37 +++++
 arch/arm/mach-exynos/common.c                      |  148 ++++++++++++--------
 arch/arm/mach-exynos/include/mach/regs-gpio.h      |    4 +-
 3 files changed, 131 insertions(+), 58 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt

[PATCH v3 1/4] ARM: Exynos4: Simplify EINT number to linux irq number translation

[Thomas Abraham]

The exynos4_get_irq_nr function that converts a given wakeup interrupt
source number to a linux irq number is simplified and replaced with
the new macro exynos4_irq_eint_to_gic_irq.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/common.c |   26 +++-----------------------
 1 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ac5ac0e..7dd9dd0 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -550,27 +550,7 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
-
-static unsigned int exynos4_get_irq_nr(unsigned int number)
-{
-	u32 ret = 0;
-
-	switch (number) {
-	case 0 ... 3:
-		ret = (number + IRQ_EINT0);
-		break;
-	case 4 ... 7:
-		ret = (number + (IRQ_EINT4 - 4));
-		break;
-	case 8 ... 15:
-		ret = (number + (IRQ_EINT8 - 8));
-		break;
-	default:
-		printk(KERN_ERR "number available : %d\n", number);
-	}
-
-	return ret;
-}
+#define exynos4_irq_eint_to_gic_irq(number) (IRQ_EINT0 + number)
 
 static inline void exynos4_irq_eint_mask(struct irq_data *data)
 {
@@ -748,9 +728,9 @@ static int __init exynos4_init_irq_eint(void)
 	for (irq = 0 ; irq <= 15 ; irq++) {
 		eint0_15_data[irq] = IRQ_EINT(irq);
 
-		irq_set_handler_data(exynos4_get_irq_nr(irq),
+		irq_set_handler_data(exynos4_irq_eint_to_gic_irq(irq),
 				     &eint0_15_data[irq]);
-		irq_set_chained_handler(exynos4_get_irq_nr(irq),
+		irq_set_chained_handler(exynos4_irq_eint_to_gic_irq(irq),
 					exynos4_irq_eint0_15);
 	}
 
-- 
1.6.6.rc2

[PATCH v3 2/4] ARM: Exynos4: Add irq_domain support for gpio wakeup interrupts

[Thomas Abraham]

Add a irq_domain for all the 32 gpio external wakeup interrupt sources.
Since there are users of fixed linux irq numbers of the external wakeup
interrupts, the legacy mapping is used for the irq domain. The fixups
required to use irq domain based interrupt mapping is also included.

Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/common.c                 |  101 +++++++++++++++++--------
 arch/arm/mach-exynos/include/mach/regs-gpio.h |    4 +-
 2 files changed, 72 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 7dd9dd0..ed50185 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -547,9 +547,20 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 	s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
 }
 
+/**
+ * struct exynos4_eint_data: runtime data for exynos4 gpio wakeup interrupts
+ * @irq_domain	: irq_domain representing the gpio wakeup interrupts sources.
+ * @gic_irq_base: base gic linux irq number for gpio wakeup interrupts.
+ */
+struct exynos4_eint_data {
+	struct irq_domain *irq_domain;
+	int gic_irq_base;
+};
+
 static DEFINE_SPINLOCK(eint_lock);
+static struct exynos4_eint_data eint_data;
 
-static unsigned int eint0_15_data[16];
+#define EXYNOS4_EINT_NR 32
 #define exynos4_irq_eint_to_gic_irq(number) (IRQ_EINT0 + number)
 
 static inline void exynos4_irq_eint_mask(struct irq_data *data)
@@ -557,9 +568,9 @@ static inline void exynos4_irq_eint_mask(struct irq_data *data)
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-	mask |= eint_irq_to_bit(data->irq);
-	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->hwirq)));
+	mask |= eint_irq_to_bit(data->hwirq);
+	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->hwirq)));
 	spin_unlock(&eint_lock);
 }
 
@@ -568,16 +579,16 @@ static void exynos4_irq_eint_unmask(struct irq_data *data)
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-	mask &= ~(eint_irq_to_bit(data->irq));
-	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->hwirq)));
+	mask &= ~(eint_irq_to_bit(data->hwirq));
+	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->hwirq)));
 	spin_unlock(&eint_lock);
 }
 
 static inline void exynos4_irq_eint_ack(struct irq_data *data)
 {
-	__raw_writel(eint_irq_to_bit(data->irq),
-		     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+	__raw_writel(eint_irq_to_bit(data->hwirq),
+		     S5P_EINT_PEND(EINT_REG_NR(data->hwirq)));
 }
 
 static void exynos4_irq_eint_maskack(struct irq_data *data)
@@ -588,7 +599,7 @@ static void exynos4_irq_eint_maskack(struct irq_data *data)
 
 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
-	int offs = EINT_OFFSET(data->irq);
+	int offs = data->hwirq;
 	int shift;
 	u32 ctrl, mask;
 	u32 newvalue = 0;
@@ -623,10 +634,10 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
 	mask = 0x7 << shift;
 
 	spin_lock(&eint_lock);
-	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->hwirq)));
 	ctrl &= ~mask;
 	ctrl |= newvalue << shift;
-	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->hwirq)));
 	spin_unlock(&eint_lock);
 
 	switch (offs) {
@@ -670,19 +681,20 @@ static struct irq_chip exynos4_irq_eint = {
  *
  * Each EINT pend/mask registers handle eight of them.
  */
-static inline void exynos4_irq_demux_eint(unsigned int start)
+static inline void exynos4_irq_demux_eint(struct irq_domain *irq_domain,
+						unsigned int hwirq)
 {
 	unsigned int irq;
 
-	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
-	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(hwirq)));
+	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(hwirq)));
 
 	status &= ~mask;
 	status &= 0xff;
 
 	while (status) {
 		irq = fls(status) - 1;
-		generic_handle_irq(irq + start);
+		generic_handle_irq(irq_find_mapping(irq_domain, hwirq + irq));
 		status &= ~(1 << irq);
 	}
 }
@@ -690,16 +702,19 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_get_chip(irq);
+	struct exynos4_eint_data *eint_data = irq_get_handler_data(irq);
+
 	chained_irq_enter(chip, desc);
-	exynos4_irq_demux_eint(IRQ_EINT(16));
-	exynos4_irq_demux_eint(IRQ_EINT(24));
+	exynos4_irq_demux_eint(eint_data->irq_domain, 16);
+	exynos4_irq_demux_eint(eint_data->irq_domain, 24);
 	chained_irq_exit(chip, desc);
 }
 
 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
-	u32 *irq_data = irq_get_handler_data(irq);
+	struct exynos4_eint_data *eint_data = irq_get_handler_data(irq);
 	struct irq_chip *chip = irq_get_chip(irq);
+	int eint_irq;
 
 	chained_irq_enter(chip, desc);
 	chip->irq_mask(&desc->irq_data);
@@ -707,33 +722,57 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 	if (chip->irq_ack)
 		chip->irq_ack(&desc->irq_data);
 
-	generic_handle_irq(*irq_data);
+	eint_irq = irq_find_mapping(eint_data->irq_domain,
+					irq - eint_data->gic_irq_base);
+	generic_handle_irq(eint_irq);
 
 	chip->irq_unmask(&desc->irq_data);
 	chained_irq_exit(chip, desc);
 }
 
+static int exynos4_eint_irq_domain_map(struct irq_domain *d, unsigned int irq,
+					irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &exynos4_irq_eint, handle_level_irq);
+	set_irq_flags(irq, IRQF_VALID);
+	return 0;
+}
+
+static struct irq_domain_ops exynos4_eint_irq_domain_ops = {
+	.map = exynos4_eint_irq_domain_map,
+};
+
 static int __init exynos4_init_irq_eint(void)
 {
-	int irq;
+	int eint, irq_base;
+	struct irq_domain *irq_domain;
 
-	for (irq = 0 ; irq <= 31 ; irq++) {
-		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
-					 handle_level_irq);
-		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+	irq_base = irq_alloc_descs(IRQ_EINT(0), 1, EXYNOS4_EINT_NR, 0);
+	if (IS_ERR_VALUE(irq_base)) {
+		irq_base = IRQ_EINT(0);
+		pr_warning("exynos4_init_irq_eint: irq desc alloc failed. "
+			"Continuing with %d as linux irq base\n", irq_base);
 	}
 
-	irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+	irq_domain = irq_domain_add_legacy(NULL, EXYNOS4_EINT_NR, irq_base, 0,
+					&exynos4_eint_irq_domain_ops, NULL);
+	if (WARN_ON(!irq_domain)) {
+		pr_warning("exynos4_init_irq_eint: irq domain init failed\n");
+		return 0;
+	}
 
-	for (irq = 0 ; irq <= 15 ; irq++) {
-		eint0_15_data[irq] = IRQ_EINT(irq);
+	eint_data.irq_domain = irq_domain;
+	eint_data.gic_irq_base = exynos4_irq_eint_to_gic_irq(0);
 
-		irq_set_handler_data(exynos4_irq_eint_to_gic_irq(irq),
-				     &eint0_15_data[irq]);
-		irq_set_chained_handler(exynos4_irq_eint_to_gic_irq(irq),
+	for (eint = 0 ; eint <= 15 ; eint++) {
+		irq_set_handler_data(exynos4_irq_eint_to_gic_irq(eint),
+					&eint_data);
+		irq_set_chained_handler(exynos4_irq_eint_to_gic_irq(eint),
 					exynos4_irq_eint0_15);
 	}
 
+	irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+	irq_set_handler_data(IRQ_EINT16_31, &eint_data);
 	return 0;
 }
 arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index 1401b21..2e6ec6b 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -28,9 +28,9 @@
 #define EXYNOS4_EINT40PEND		(S5P_VA_GPIO2 + 0xF40)
 #define S5P_EINT_PEND(x)		(EXYNOS4_EINT40PEND + ((x) * 0x4))
 
-#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
+#define EINT_REG_NR(x)			((x) >> 3)
 
-#define eint_irq_to_bit(irq)		(1 << (EINT_OFFSET(irq) & 0x7))
+#define eint_irq_to_bit(irq)		(1 << ((irq) & 0x7))
 
 #define EINT_MODE			S3C_GPIO_SFN(0xf)
 
-- 
1.6.6.rc2

[PATCH v3 3/4] ARM: Exynos4: Remove arch_initcall for wakeup interrupt initialization

[Thomas Abraham]

The of_irq_init function would be setup to invoke the exynos4_init_irq_eint
function when booting using device tree. The arch_initcall for
exynos4_init_irq_eint would duplicate its invocation in that case. Hence,
arch_initcall for exynos4_init_irq_eint is removed and this function is invoked
from the exynos4_init_irq for non-dt case.

Moreover, with single kernel image build, the exynos4_init_irq_eint has no checks
to ensure that it is running on a exynos4 platform. So it would be appropriate
to invoke it from exynos4_init_irq.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/common.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ed50185..888e703 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -81,6 +81,8 @@ static struct cpu_table cpu_ids[] __initdata = {
 	},
 };
 
+static int exynos4_init_irq_eint(void);
+
 /* Initial IO mappings */
 
 static struct map_desc exynos_iodesc[] __initdata = {
@@ -485,6 +487,7 @@ void __init exynos4_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
+	exynos4_init_irq_eint();
 }
 
 struct bus_type exynos4_subsys = {
@@ -775,4 +778,3 @@ static int __init exynos4_init_irq_eint(void)
 	irq_set_handler_data(IRQ_EINT16_31, &eint_data);
 	return 0;
 }
-arch_initcall(exynos4_init_irq_eint);
-- 
1.6.6.rc2

[PATCH v3 4/4] ARM: Exynos4: Add device tree support for gpio wakeup interrupt controller

[Thomas Abraham]

Add device tree support for gpio wakeup source interrupt controller
on Exynos4.

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 .../bindings/arm/samsung/wakeup-eint.txt           |   37 +++++++++++++++++
 arch/arm/mach-exynos/common.c                      |   43 +++++++++++++------
 2 files changed, 66 insertions(+), 14 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt

diff --git a/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
new file mode 100644
index 0000000..ac9db41
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos4 GPIO Wakeup Interrupt Source Controller
+
+Samsung Exynos4 processor supports 32 external wakeup interrupt sources. First
+16 of these interrupts are directly connected to GIC and the rest 16 of the
+interrupts are grouped together to deliver a single interrupt to GIC.
+
+Required properties:
+
+- compatible: should be "samsung,exynos4210-wakeup-eint".
+- interrupt-controller: Identifies the node as an interrupt controller.
+- interrupt-cells: Specifies the number of cells required to specify the
+  interrupt source number. The value of should be <2>. The first cell
+  represents the wakeup interrupt source number and the second cell
+  should be zero (currently unused).
+- interrupts: List of interrupts generated by the gpio wakeup interrupt
+    controller which are connected to a parent interrupt controller. The
+    format of the interrupt specifier depends on the interrupt parent
+    controller.
+
+Optional properties:
+- interrupt-parent: phandle of the parent interrupt controller, required if
+  not inheriting the interrupt parent from the parent node.
+
+Example:
+
+	The following example is from the Exynos4210 dtsi file.
+
+	wakeup_eint: interrupt-controller-wakeup-eint {
+		compatible = "samsung,exynos4210-wakeup-eint";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+				<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+				<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+				<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
+				<0 32 0>;
+	};
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 888e703..615168e 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -49,6 +49,9 @@
 
 #include "common.h"
 
+static int exynos4_init_irq_eint(struct device_node *np,
+					struct device_node *parent);
+
 static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
@@ -81,8 +84,6 @@ static struct cpu_table cpu_ids[] __initdata = {
 	},
 };
 
-static int exynos4_init_irq_eint(void);
-
 /* Initial IO mappings */
 
 static struct map_desc exynos_iodesc[] __initdata = {
@@ -461,6 +462,8 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 	{ .compatible = "samsung,exynos4210-combiner",
 			.data = combiner_of_init, },
+	{ .compatible = "samsung,exynos4210-wakeup-eint",
+		.data = exynos4_init_irq_eint, },
 	{},
 };
 #endif
@@ -478,8 +481,10 @@ void __init exynos4_init_irq(void)
 		of_irq_init(exynos4_dt_irq_match);
 #endif
 
-	if (!of_have_populated_dt())
+	if (!of_have_populated_dt()) {
 		combiner_init(S5P_VA_COMBINER_BASE, NULL);
+		exynos4_init_irq_eint(NULL, NULL);
+	}
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
@@ -487,7 +492,6 @@ void __init exynos4_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
-	exynos4_init_irq_eint();
 }
 
 struct bus_type exynos4_subsys = {
@@ -745,9 +749,20 @@ static struct irq_domain_ops exynos4_eint_irq_domain_ops = {
 	.map = exynos4_eint_irq_domain_map,
 };
 
-static int __init exynos4_init_irq_eint(void)
+static int __init exynos4_eint_to_irq(struct device_node *np, int hwirq)
+{
+#ifdef CONFIG_OF
+	return np ? irq_of_parse_and_map(np, hwirq) :
+			exynos4_irq_eint_to_gic_irq(hwirq);
+#else
+	return exynos4_irq_eint_to_gic_irq(hwirq);
+#endif
+}
+
+static int __init exynos4_init_irq_eint(struct device_node *np,
+						struct device_node *parent)
 {
-	int eint, irq_base;
+	int eint, irq_base, irq;
 	struct irq_domain *irq_domain;
 
 	irq_base = irq_alloc_descs(IRQ_EINT(0), 1, EXYNOS4_EINT_NR, 0);
@@ -757,7 +772,7 @@ static int __init exynos4_init_irq_eint(void)
 			"Continuing with %d as linux irq base\n", irq_base);
 	}
 
-	irq_domain = irq_domain_add_legacy(NULL, EXYNOS4_EINT_NR, irq_base, 0,
+	irq_domain = irq_domain_add_legacy(np, EXYNOS4_EINT_NR, irq_base, 0,
 					&exynos4_eint_irq_domain_ops, NULL);
 	if (WARN_ON(!irq_domain)) {
 		pr_warning("exynos4_init_irq_eint: irq domain init failed\n");
@@ -765,16 +780,16 @@ static int __init exynos4_init_irq_eint(void)
 	}
 
 	eint_data.irq_domain = irq_domain;
-	eint_data.gic_irq_base = exynos4_irq_eint_to_gic_irq(0);
+	eint_data.gic_irq_base = exynos4_eint_to_irq(np, 0);
 
 	for (eint = 0 ; eint <= 15 ; eint++) {
-		irq_set_handler_data(exynos4_irq_eint_to_gic_irq(eint),
-					&eint_data);
-		irq_set_chained_handler(exynos4_irq_eint_to_gic_irq(eint),
-					exynos4_irq_eint0_15);
+		irq = exynos4_eint_to_irq(np, eint);
+		irq_set_handler_data(irq, &eint_data);
+		irq_set_chained_handler(irq, exynos4_irq_eint0_15);
 	}
 
-	irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
-	irq_set_handler_data(IRQ_EINT16_31, &eint_data);
+	irq = exynos4_eint_to_irq(np, eint);
+	irq_set_chained_handler(irq, exynos4_irq_demux_eint16_31);
+	irq_set_handler_data(irq, &eint_data);
 	return 0;
 }
-- 
1.6.6.rc2

[PATCH v3 4/4] ARM: Exynos4: Add device tree support for gpio wakeup interrupt controller

[Rob Herring]

On 02/22/2012 06:14 AM, Thomas Abraham wrote:
> Add device tree support for gpio wakeup source interrupt controller
> on Exynos4.
> 
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>

For the series:

Acked-by: Rob Herring <rob.herring@calxeda.com>

Rob

> ---
>  .../bindings/arm/samsung/wakeup-eint.txt           |   37 +++++++++++++++++
>  arch/arm/mach-exynos/common.c                      |   43 +++++++++++++------
>  2 files changed, 66 insertions(+), 14 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
> new file mode 100644
> index 0000000..ac9db41
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
> @@ -0,0 +1,37 @@
> +* Samsung Exynos4 GPIO Wakeup Interrupt Source Controller
> +
> +Samsung Exynos4 processor supports 32 external wakeup interrupt sources. First
> +16 of these interrupts are directly connected to GIC and the rest 16 of the
> +interrupts are grouped together to deliver a single interrupt to GIC.
> +
> +Required properties:
> +
> +- compatible: should be "samsung,exynos4210-wakeup-eint".
> +- interrupt-controller: Identifies the node as an interrupt controller.
> +- interrupt-cells: Specifies the number of cells required to specify the
> +  interrupt source number. The value of should be <2>. The first cell
> +  represents the wakeup interrupt source number and the second cell
> +  should be zero (currently unused).
> +- interrupts: List of interrupts generated by the gpio wakeup interrupt
> +    controller which are connected to a parent interrupt controller. The
> +    format of the interrupt specifier depends on the interrupt parent
> +    controller.
> +
> +Optional properties:
> +- interrupt-parent: phandle of the parent interrupt controller, required if
> +  not inheriting the interrupt parent from the parent node.
> +
> +Example:
> +
> +	The following example is from the Exynos4210 dtsi file.
> +
> +	wakeup_eint: interrupt-controller-wakeup-eint {
> +		compatible = "samsung,exynos4210-wakeup-eint";
> +		#interrupt-cells = <2>;
> +		interrupt-controller;
> +		interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
> +				<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
> +				<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
> +				<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
> +				<0 32 0>;
> +	};
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 888e703..615168e 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -49,6 +49,9 @@
>  
>  #include "common.h"
>  
> +static int exynos4_init_irq_eint(struct device_node *np,
> +					struct device_node *parent);
> +
>  static const char name_exynos4210[] = "EXYNOS4210";
>  static const char name_exynos4212[] = "EXYNOS4212";
>  static const char name_exynos4412[] = "EXYNOS4412";
> @@ -81,8 +84,6 @@ static struct cpu_table cpu_ids[] __initdata = {
>  	},
>  };
>  
> -static int exynos4_init_irq_eint(void);
> -
>  /* Initial IO mappings */
>  
>  static struct map_desc exynos_iodesc[] __initdata = {
> @@ -461,6 +462,8 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
>  	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
>  	{ .compatible = "samsung,exynos4210-combiner",
>  			.data = combiner_of_init, },
> +	{ .compatible = "samsung,exynos4210-wakeup-eint",
> +		.data = exynos4_init_irq_eint, },
>  	{},
>  };
>  #endif
> @@ -478,8 +481,10 @@ void __init exynos4_init_irq(void)
>  		of_irq_init(exynos4_dt_irq_match);
>  #endif
>  
> -	if (!of_have_populated_dt())
> +	if (!of_have_populated_dt()) {
>  		combiner_init(S5P_VA_COMBINER_BASE, NULL);
> +		exynos4_init_irq_eint(NULL, NULL);
> +	}
>  
>  	/*
>  	 * The parameters of s5p_init_irq() are for VIC init.
> @@ -487,7 +492,6 @@ void __init exynos4_init_irq(void)
>  	 * uses GIC instead of VIC.
>  	 */
>  	s5p_init_irq(NULL, 0);
> -	exynos4_init_irq_eint();
>  }
>  
>  struct bus_type exynos4_subsys = {
> @@ -745,9 +749,20 @@ static struct irq_domain_ops exynos4_eint_irq_domain_ops = {
>  	.map = exynos4_eint_irq_domain_map,
>  };
>  
> -static int __init exynos4_init_irq_eint(void)
> +static int __init exynos4_eint_to_irq(struct device_node *np, int hwirq)
> +{
> +#ifdef CONFIG_OF
> +	return np ? irq_of_parse_and_map(np, hwirq) :
> +			exynos4_irq_eint_to_gic_irq(hwirq);
> +#else
> +	return exynos4_irq_eint_to_gic_irq(hwirq);
> +#endif
> +}
> +
> +static int __init exynos4_init_irq_eint(struct device_node *np,
> +						struct device_node *parent)
>  {
> -	int eint, irq_base;
> +	int eint, irq_base, irq;
>  	struct irq_domain *irq_domain;
>  
>  	irq_base = irq_alloc_descs(IRQ_EINT(0), 1, EXYNOS4_EINT_NR, 0);
> @@ -757,7 +772,7 @@ static int __init exynos4_init_irq_eint(void)
>  			"Continuing with %d as linux irq base\n", irq_base);
>  	}
>  
> -	irq_domain = irq_domain_add_legacy(NULL, EXYNOS4_EINT_NR, irq_base, 0,
> +	irq_domain = irq_domain_add_legacy(np, EXYNOS4_EINT_NR, irq_base, 0,
>  					&exynos4_eint_irq_domain_ops, NULL);
>  	if (WARN_ON(!irq_domain)) {
>  		pr_warning("exynos4_init_irq_eint: irq domain init failed\n");
> @@ -765,16 +780,16 @@ static int __init exynos4_init_irq_eint(void)
>  	}
>  
>  	eint_data.irq_domain = irq_domain;
> -	eint_data.gic_irq_base = exynos4_irq_eint_to_gic_irq(0);
> +	eint_data.gic_irq_base = exynos4_eint_to_irq(np, 0);
>  
>  	for (eint = 0 ; eint <= 15 ; eint++) {
> -		irq_set_handler_data(exynos4_irq_eint_to_gic_irq(eint),
> -					&eint_data);
> -		irq_set_chained_handler(exynos4_irq_eint_to_gic_irq(eint),
> -					exynos4_irq_eint0_15);
> +		irq = exynos4_eint_to_irq(np, eint);
> +		irq_set_handler_data(irq, &eint_data);
> +		irq_set_chained_handler(irq, exynos4_irq_eint0_15);
>  	}
>  
> -	irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
> -	irq_set_handler_data(IRQ_EINT16_31, &eint_data);
> +	irq = exynos4_eint_to_irq(np, eint);
> +	irq_set_chained_handler(irq, exynos4_irq_demux_eint16_31);
> +	irq_set_handler_data(irq, &eint_data);
>  	return 0;
>  }

[PATCH v3 0/4] ARM: Exynos4: Add irq domain and device tree support for wakeup interrupts

[Kukjin Kim]

On 02/22/12 04:14, Thomas Abraham wrote:
> Changes since v2:
> - Reworked irq domain support based on v5 of the irq_domain generalization
>    patches.
>
> Changes since v1: (only patch 4/4 has changes)
> - Fixes based on Rob's comments:
>    a. Fixed the function prototype of exynos4_init_irq_eint(void)
>    b. Included interrupt-parent as an optional property for wakeup interrupt
>        controller node.
>
> Samsung Exynos4 includes 32 external wakeup interrupt sources. The first 16
> of these interrupts are connected to GIC SPI[31:16]. The last 16 of these
> interrupts are grouped together into one interrupt and connected to GIC
> SPI[32].
>
> This patchset adds irq domain and device tree support for these interrupts.
> Since there are users of fixed linux irq numbers of the external wakeup
> interrupts, the legacy mapping is used for the irq domain.
>
> This patchset is based on
> http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]
>
> with all irq_domain (v5) patches merged from
> http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]
>
> This patchset should be applied after applying the following patch.
> [PATCH] ARM: Exynos: Add irq domain and device tree support for interrupt combiner

Looks ok to me this series, but I lost above patch in my mail box.
Thomas, could you please send updated it so that I can apply this series?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

>
> Thomas Abraham (4):
>    ARM: Exynos4: Simplify EINT number to linux irq number translation
>    ARM: Exynos4: Add irq_domain support for gpio wakeup interrupts
>    ARM: Exynos4: Remove arch_initcall for wakeup interrupt initialization
>    ARM: Exynos4: Add device tree support for gpio wakeup interrupt controller
>
>   .../bindings/arm/samsung/wakeup-eint.txt           |   37 +++++
>   arch/arm/mach-exynos/common.c                      |  148 ++++++++++++--------
>   arch/arm/mach-exynos/include/mach/regs-gpio.h      |    4 +-
>   3 files changed, 131 insertions(+), 58 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt

[PATCH v3 0/4] ARM: Exynos4: Add irq domain and device tree support for wakeup interrupts

[Thomas Abraham]

On 9 March 2012 22:02, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 02/22/12 04:14, Thomas Abraham wrote:
>>
>> Changes since v2:
>> - Reworked irq domain support based on v5 of the irq_domain generalization
>> ? patches.
>>
>> Changes since v1: (only patch 4/4 has changes)
>> - Fixes based on Rob's comments:
>> ? a. Fixed the function prototype of exynos4_init_irq_eint(void)
>> ? b. Included interrupt-parent as an optional property for wakeup
>> interrupt
>> ? ? ? controller node.
>>
>> Samsung Exynos4 includes 32 external wakeup interrupt sources. The first
>> 16
>> of these interrupts are connected to GIC SPI[31:16]. The last 16 of these
>> interrupts are grouped together into one interrupt and connected to GIC
>> SPI[32].
>>
>> This patchset adds irq domain and device tree support for these
>> interrupts.
>> Since there are users of fixed linux irq numbers of the external wakeup
>> interrupts, the legacy mapping is used for the irq domain.
>>
>> This patchset is based on
>> http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> [for-next]
>>
>> with all irq_domain (v5) patches merged from
>> http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]
>>
>> This patchset should be applied after applying the following patch.
>> [PATCH] ARM: Exynos: Add irq domain and device tree support for interrupt
>> combiner
>
>
> Looks ok to me this series, but I lost above patch in my mail box.
> Thomas, could you please send updated it so that I can apply this series?

Dear Mr. Kim,

Sure. I will test and send the patchset based on the your latest
for-next branch.

Thanks,
Thomas.

[...]

[PATCH v3 0/4] ARM: Exynos4: Add irq domain and device tree support for wakeup interrupts

[Thomas Abraham]

Dear Mr. Kim,

On 9 March 2012 22:02, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 02/22/12 04:14, Thomas Abraham wrote:
>>
>> Changes since v2:
>> - Reworked irq domain support based on v5 of the irq_domain generalization
>> ? patches.
>>
>> Changes since v1: (only patch 4/4 has changes)
>> - Fixes based on Rob's comments:
>> ? a. Fixed the function prototype of exynos4_init_irq_eint(void)
>> ? b. Included interrupt-parent as an optional property for wakeup
>> interrupt
>> ? ? ? controller node.
>>
>> Samsung Exynos4 includes 32 external wakeup interrupt sources. The first
>> 16
>> of these interrupts are connected to GIC SPI[31:16]. The last 16 of these
>> interrupts are grouped together into one interrupt and connected to GIC
>> SPI[32].
>>
>> This patchset adds irq domain and device tree support for these
>> interrupts.
>> Since there are users of fixed linux irq numbers of the external wakeup
>> interrupts, the legacy mapping is used for the irq domain.
>>
>> This patchset is based on
>> http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> [for-next]
>>
>> with all irq_domain (v5) patches merged from
>> http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]
>>
>> This patchset should be applied after applying the following patch.
>> [PATCH] ARM: Exynos: Add irq domain and device tree support for interrupt
>> combiner
>
>
> Looks ok to me this series, but I lost above patch in my mail box.
> Thomas, could you please send updated it so that I can apply this series?

The device tree support patches for wakeup interrupts and interrupt
combiner do not apply cleanly to the for-next branch due to the
Exynos5 additions.  So I will rebase, test and post an updated version
of these patches.

Thanks,
Thomas.