* [PATCH v2 0/2] Assign RK3066 clocks at boot time
@ 2016-10-14 12:16 Paweł Jarosz
2016-10-14 12:16 ` [PATCH v2 1/2] clk: rockchip: Add bindings for cpu and peri clocks on rk3066 Paweł Jarosz
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Paweł Jarosz @ 2016-10-14 12:16 UTC (permalink / raw)
To: linux-arm-kernel
This patchset sets rk3066 PLL, CPU and PERI clocks while kernel init.
Pawe? Jarosz (2):
clk: rockchip: Add bindings for cpu and peri clocks on rk3066
ARM: dts: rockchip: initialize rk3066 PLL clock rate
arch/arm/boot/dts/rk3066a.dtsi | 9 +++++++++
drivers/clk/rockchip/clk-rk3188.c | 12 ++++++------
include/dt-bindings/clock/rk3188-cru-common.h | 8 +++++++-
3 files changed, 22 insertions(+), 7 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 1/2] clk: rockchip: Add bindings for cpu and peri clocks on rk3066 2016-10-14 12:16 [PATCH v2 0/2] Assign RK3066 clocks at boot time Paweł Jarosz @ 2016-10-14 12:16 ` Paweł Jarosz 2016-10-14 12:16 ` [PATCH v2 2/2] ARM: dts: rockchip: initialize rk3066 PLL clock rate Paweł Jarosz 2016-10-14 13:28 ` [PATCH v2 0/2] Assign RK3066 clocks at boot time Heiko Stuebner 2 siblings, 0 replies; 6+ messages in thread From: Paweł Jarosz @ 2016-10-14 12:16 UTC (permalink / raw) To: linux-arm-kernel Add bindings for ACLK_CPU, HCLK_CPU, PCLK_CPU, ACLK_PERI, HCLK_PERI, PCLK_PERI. We need this to init it's rate at boot time. Signed-off-by: Pawe? Jarosz <paweljarosz3691@gmail.com> --- Changes in v2: - none drivers/clk/rockchip/clk-rk3188.c | 12 ++++++------ include/dt-bindings/clock/rk3188-cru-common.h | 8 +++++++- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index d0e722a..a6d398f 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -306,14 +306,14 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(0), 2, GFLAGS), - GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, RK2928_CLKGATE_CON(0), 3, GFLAGS), GATE(0, "atclk_cpu", "pclk_cpu_pre", 0, RK2928_CLKGATE_CON(0), 6, GFLAGS), - GATE(0, "pclk_cpu", "pclk_cpu_pre", 0, + GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0, RK2928_CLKGATE_CON(0), 5, GFLAGS), - GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, + GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(0), 4, GFLAGS), COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, @@ -323,12 +323,12 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), - GATE(0, "aclk_peri", "aclk_peri_pre", 0, + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0, RK2928_CLKGATE_CON(2), 1, GFLAGS), - COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0, + COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0, RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 2, GFLAGS), - COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0, + COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0, RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 3, GFLAGS), diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 4f53e70..d141c1f 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -72,6 +72,8 @@ #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 +#define ACLK_CPU 203 +#define ACLK_PERI 204 /* pclk gates */ #define PCLK_GRF 320 @@ -104,6 +106,8 @@ #define PCLK_EFUSE 347 #define PCLK_TZPC 348 #define PCLK_TSADC 349 +#define PCLK_CPU 350 +#define PCLK_PERI 351 /* hclk gates */ #define HCLK_SDMMC 448 @@ -126,8 +130,10 @@ #define HCLK_IPP 465 #define HCLK_RGA 466 #define HCLK_NANDC0 467 +#define HCLK_CPU 468 +#define HCLK_PERI 469 -#define CLK_NR_CLKS (HCLK_NANDC0 + 1) +#define CLK_NR_CLKS (HCLK_PERI + 1) /* soft-reset indices */ #define SRST_MCORE 2 -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] ARM: dts: rockchip: initialize rk3066 PLL clock rate 2016-10-14 12:16 [PATCH v2 0/2] Assign RK3066 clocks at boot time Paweł Jarosz 2016-10-14 12:16 ` [PATCH v2 1/2] clk: rockchip: Add bindings for cpu and peri clocks on rk3066 Paweł Jarosz @ 2016-10-14 12:16 ` Paweł Jarosz 2016-10-14 13:28 ` [PATCH v2 0/2] Assign RK3066 clocks at boot time Heiko Stuebner 2 siblings, 0 replies; 6+ messages in thread From: Paweł Jarosz @ 2016-10-14 12:16 UTC (permalink / raw) To: linux-arm-kernel Initialize PLL, cpu bus and peripherial bus rate while kernel init. No other module does than. This gives us performance boost observable for example in mmc transfers. Signed-off-by: Pawe? Jarosz <paweljarosz3691@gmail.com> --- Changes in v2: - added peripherial and cpu bus - removed PLL_DPLL, PLL_APLL arch/arm/boot/dts/rk3066a.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 0d0dae3..29dd434 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -151,6 +151,15 @@ #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>; + + assigned-clock-rates = <400000000>, <594000000>, + <300000000>, <150000000>, + <75000000>, <300000000>, + <150000000>, <75000000>; }; timer at 2000e000 { -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 0/2] Assign RK3066 clocks at boot time 2016-10-14 12:16 [PATCH v2 0/2] Assign RK3066 clocks at boot time Paweł Jarosz 2016-10-14 12:16 ` [PATCH v2 1/2] clk: rockchip: Add bindings for cpu and peri clocks on rk3066 Paweł Jarosz 2016-10-14 12:16 ` [PATCH v2 2/2] ARM: dts: rockchip: initialize rk3066 PLL clock rate Paweł Jarosz @ 2016-10-14 13:28 ` Heiko Stuebner 2016-10-14 14:11 ` Paweł Jarosz 2 siblings, 1 reply; 6+ messages in thread From: Heiko Stuebner @ 2016-10-14 13:28 UTC (permalink / raw) To: linux-arm-kernel Am Freitag, 14. Oktober 2016, 14:16:21 CEST schrieb Pawe? Jarosz: > This patchset sets rk3066 PLL, CPU and PERI clocks while kernel init. > > Pawe? Jarosz (2): > clk: rockchip: Add bindings for cpu and peri clocks on rk3066 > ARM: dts: rockchip: initialize rk3066 PLL clock rate changes look good. One thing to keep in mind is that we need clock-id additions in a separate patch (as they need to be on a shared branch). I can do this split of patch1 on my own here, so no need to resend the series and will do that after 4.9-rc1 (probably somewhere after sunday) as I need a stable base for that shared branch. Heiko ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 0/2] Assign RK3066 clocks at boot time 2016-10-14 13:28 ` [PATCH v2 0/2] Assign RK3066 clocks at boot time Heiko Stuebner @ 2016-10-14 14:11 ` Paweł Jarosz 2016-10-21 13:44 ` Heiko Stuebner 0 siblings, 1 reply; 6+ messages in thread From: Paweł Jarosz @ 2016-10-14 14:11 UTC (permalink / raw) To: linux-arm-kernel W dniu 14.10.2016 o 15:28, Heiko Stuebner pisze: > changes look good. One thing to keep in mind is that we need clock-id > additions in a separate patch (as they need to be on a shared branch). > > I can do this split of patch1 on my own here, so no need to resend the series > and will do that after 4.9-rc1 (probably somewhere after sunday) as I need a > stable base for that shared branch. > > > Heiko Thanks Heiko. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 0/2] Assign RK3066 clocks at boot time 2016-10-14 14:11 ` Paweł Jarosz @ 2016-10-21 13:44 ` Heiko Stuebner 0 siblings, 0 replies; 6+ messages in thread From: Heiko Stuebner @ 2016-10-21 13:44 UTC (permalink / raw) To: linux-arm-kernel Am Freitag, 14. Oktober 2016, 16:11:26 CEST schrieb Pawe? Jarosz: > W dniu 14.10.2016 o 15:28, Heiko Stuebner pisze: > > changes look good. One thing to keep in mind is that we need clock-id > > additions in a separate patch (as they need to be on a shared branch). > > > > I can do this split of patch1 on my own here, so no need to resend the > > series and will do that after 4.9-rc1 (probably somewhere after sunday) > > as I need a stable base for that shared branch. > > As written before, I've now split up patch1 into two and applied all 3 patches for 4.10 Thanks Heiko ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-10-21 13:44 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-10-14 12:16 [PATCH v2 0/2] Assign RK3066 clocks at boot time Paweł Jarosz 2016-10-14 12:16 ` [PATCH v2 1/2] clk: rockchip: Add bindings for cpu and peri clocks on rk3066 Paweł Jarosz 2016-10-14 12:16 ` [PATCH v2 2/2] ARM: dts: rockchip: initialize rk3066 PLL clock rate Paweł Jarosz 2016-10-14 13:28 ` [PATCH v2 0/2] Assign RK3066 clocks at boot time Heiko Stuebner 2016-10-14 14:11 ` Paweł Jarosz 2016-10-21 13:44 ` Heiko Stuebner
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