[PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0

[PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0

[Thomas Abraham]

This patch series adds support for Samsung's Exynos5250 Rev1.0. It includes
fixes for device tree support, updates for rev1.0 silicon and device tree
discovery for combiner and wakeup interrupt controller. This patch series
depricates the existing support for Exynos5250 Rev0.0.

This patchset is based and tested on top of v3.4-rc5.

Boojin Kim (1):
  ARM: EXYNOS: Support DMA for EXYNOS5250 SoC

Changhwan Youn (2):
  ARM: EXYNOS: Modify the GIC physical address for static io-mapping
  ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition

Kisoo Yu (1):
  ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

Kukjin Kim (2):
  ARM: EXYNOS: fix ctrlbit for exynos5_clk_pdma1
  ARM: EXYNOS: update irqs for EXYNOS5250 evt1

Sangsu Park (1):
  ARM: EXYNOS: add GPC4 bank instance

Thomas Abraham (13):
  ARM: EXYNOS: Add watchdog timer clock instance
  ARM: Exynos: Remove a new bus_type instance for Exynos5
  of/irq: fix interrupt parent lookup procedure
  of/irq: add retry support for interrupt controller tree initialization
  ARM: Exynos: Add irq_domain support for interrupt combiner
  ARM: Exynos: Add device tree support for interrupt combiner
  ARM: Exynos: Simplify the wakeup interrupt setup code
  ARM: Exynos: Add irq_domain support for gpio wakeup interrupts
  ARM: Exynos: Remove arch_initcall for wakeup interrupt initialization
  ARM: Exynos: Add device tree support for gpio wakeup interrupt controller
  ARM: dts: Update device tree source files for EXYNOS5250
  ARM: Exynos5: Add combiner, wakeup interrupt controller and ethernet nodes
  ARM: Exynos5: Add AUXDATA for i2c controllers

 .../bindings/arm/samsung/interrupt-combiner.txt    |   52 +++
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |   63 ++++
 arch/arm/boot/dts/exynos5250.dtsi                  |   99 ++++--
 arch/arm/mach-exynos/Kconfig                       |    7 +-
 arch/arm/mach-exynos/Makefile                      |    2 +-
 arch/arm/mach-exynos/clock-exynos5.c               |   80 +++++-
 arch/arm/mach-exynos/common.c                      |  338 ++++++++++++++------
 arch/arm/mach-exynos/dma.c                         |  129 +++++++--
 arch/arm/mach-exynos/include/mach/gpio.h           |    9 +-
 arch/arm/mach-exynos/include/mach/irqs.h           |   40 ++-
 arch/arm/mach-exynos/include/mach/map.h            |    4 +-
 arch/arm/mach-exynos/include/mach/regs-clock.h     |    2 +
 arch/arm/mach-exynos/include/mach/regs-gpio.h      |    4 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    4 +
 arch/arm/mach-exynos/mct.c                         |   17 +-
 arch/arm/mach-exynos/pm.c                          |    2 +-
 arch/arm/plat-s5p/clock.c                          |   11 -
 arch/arm/plat-samsung/Kconfig                      |    2 +-
 arch/arm/plat-samsung/include/plat/cpu.h           |    2 +-
 arch/arm/plat-samsung/include/plat/dma-pl330.h     |    1 +
 drivers/gpio/gpio-samsung.c                        |   11 +-
 drivers/of/irq.c                                   |   29 ++-
 22 files changed, 698 insertions(+), 210 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt

-- 
1.7.5.4

[PATCH 01/20] ARM: EXYNOS: Add watchdog timer clock instance

[Thomas Abraham]

Add watchdog timer clock instance for EXYNOS5 watchdog controller.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/clock-exynos5.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 5cd7a8b..3dc3c50 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -454,6 +454,11 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_peris_ctrl,
 		.ctrlbit	= (1 << 20),
 	}, {
+		.name		= "watchdog",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peris_ctrl,
+		.ctrlbit	= (1 << 19),
+	}, {
 		.name		= "hsmmc",
 		.devname	= "exynos4-sdhci.0",
 		.parent		= &exynos5_clk_aclk_200.clk,
-- 
1.7.5.4

[PATCH 02/20] ARM: EXYNOS: Support DMA for EXYNOS5250 SoC

[Thomas Abraham]

From: Boojin Kim <boojin.kim@samsung.com>

mach-exynos/dma.c is updated to support both exynos4 and exynos5.

Signed-off-by: Boojin Kim <boojin.kim@samsung.com>
[kgene.kim at samsung.com: re-worked on top of v3.4-rc3]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/Kconfig                   |    7 +-
 arch/arm/mach-exynos/Makefile                  |    2 +-
 arch/arm/mach-exynos/dma.c                     |  129 ++++++++++++++++++++----
 arch/arm/plat-samsung/Kconfig                  |    2 +-
 arch/arm/plat-samsung/include/plat/dma-pl330.h |    1 +
 5 files changed, 115 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e81c35f..fbad6f1 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
 	bool "SAMSUNG EXYNOS5250"
 	default y
 	depends on ARCH_EXYNOS5
+	select SAMSUNG_DMADEV
 	help
 	  Enable EXYNOS5250 SoC support
 
@@ -70,7 +71,7 @@ config EXYNOS4_MCT
 	help
 	  Use MCT (Multi Core Timer) as kernel timers
 
-config EXYNOS4_DEV_DMA
+config EXYNOS_DEV_DMA
 	bool
 	help
 	  Compile in amba device definitions for DMA controller
@@ -223,7 +224,7 @@ config MACH_ARMLEX4210
 	select S3C_DEV_HSMMC2
 	select S3C_DEV_HSMMC3
 	select EXYNOS4_DEV_AHCI
-	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DMA
 	select EXYNOS4_DEV_SYSMMU
 	select EXYNOS4_SETUP_SDHCI
 	help
@@ -345,7 +346,7 @@ config MACH_SMDK4212
 	select SAMSUNG_DEV_BACKLIGHT
 	select SAMSUNG_DEV_KEYPAD
 	select SAMSUNG_DEV_PWM
-	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DMA
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_I2C3
 	select EXYNOS4_SETUP_I2C7
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8631840..839e78f 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -52,7 +52,7 @@ obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)	+= dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
-obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
+obj-$(CONFIG_EXYNOS_DEV_DMA)		+= dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o
 
 obj-$(CONFIG_ARCH_EXYNOS)		+= setup-i2c0.o
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 69aaa45..4ebe2ab 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -103,10 +103,45 @@ static u8 exynos4212_pdma0_peri[] = {
 	DMACH_MIPI_HSI5,
 };
 
-struct dma_pl330_platdata exynos4_pdma0_pdata;
+static u8 exynos5250_pdma0_peri[] = {
+	DMACH_PCM0_RX,
+	DMACH_PCM0_TX,
+	DMACH_PCM2_RX,
+	DMACH_PCM2_TX,
+	DMACH_SPI0_RX,
+	DMACH_SPI0_TX,
+	DMACH_SPI2_RX,
+	DMACH_SPI2_TX,
+	DMACH_I2S0S_TX,
+	DMACH_I2S0_RX,
+	DMACH_I2S0_TX,
+	DMACH_I2S2_RX,
+	DMACH_I2S2_TX,
+	DMACH_UART0_RX,
+	DMACH_UART0_TX,
+	DMACH_UART2_RX,
+	DMACH_UART2_TX,
+	DMACH_UART4_RX,
+	DMACH_UART4_TX,
+	DMACH_SLIMBUS0_RX,
+	DMACH_SLIMBUS0_TX,
+	DMACH_SLIMBUS2_RX,
+	DMACH_SLIMBUS2_TX,
+	DMACH_SLIMBUS4_RX,
+	DMACH_SLIMBUS4_TX,
+	DMACH_AC97_MICIN,
+	DMACH_AC97_PCMIN,
+	DMACH_AC97_PCMOUT,
+	DMACH_MIPI_HSI0,
+	DMACH_MIPI_HSI2,
+	DMACH_MIPI_HSI4,
+	DMACH_MIPI_HSI6,
+};
+
+static struct dma_pl330_platdata exynos_pdma0_pdata;
 
 static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
-	EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
+	EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
 
 static u8 exynos4210_pdma1_peri[] = {
 	DMACH_PCM0_RX,
@@ -169,10 +204,45 @@ static u8 exynos4212_pdma1_peri[] = {
 	DMACH_MIPI_HSI7,
 };
 
-static struct dma_pl330_platdata exynos4_pdma1_pdata;
+static u8 exynos5250_pdma1_peri[] = {
+	DMACH_PCM0_RX,
+	DMACH_PCM0_TX,
+	DMACH_PCM1_RX,
+	DMACH_PCM1_TX,
+	DMACH_SPI1_RX,
+	DMACH_SPI1_TX,
+	DMACH_PWM,
+	DMACH_SPDIF,
+	DMACH_I2S0S_TX,
+	DMACH_I2S0_RX,
+	DMACH_I2S0_TX,
+	DMACH_I2S1_RX,
+	DMACH_I2S1_TX,
+	DMACH_UART0_RX,
+	DMACH_UART0_TX,
+	DMACH_UART1_RX,
+	DMACH_UART1_TX,
+	DMACH_UART3_RX,
+	DMACH_UART3_TX,
+	DMACH_SLIMBUS1_RX,
+	DMACH_SLIMBUS1_TX,
+	DMACH_SLIMBUS3_RX,
+	DMACH_SLIMBUS3_TX,
+	DMACH_SLIMBUS5_RX,
+	DMACH_SLIMBUS5_TX,
+	DMACH_SLIMBUS0AUX_RX,
+	DMACH_SLIMBUS0AUX_TX,
+	DMACH_DISP1,
+	DMACH_MIPI_HSI1,
+	DMACH_MIPI_HSI3,
+	DMACH_MIPI_HSI5,
+	DMACH_MIPI_HSI7,
+};
+
+static struct dma_pl330_platdata exynos_pdma1_pdata;
 
 static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
-	EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
+	EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
 
 static u8 mdma_peri[] = {
 	DMACH_MTOM_0,
@@ -185,46 +255,63 @@ static u8 mdma_peri[] = {
 	DMACH_MTOM_7,
 };
 
-static struct dma_pl330_platdata exynos4_mdma1_pdata = {
+static struct dma_pl330_platdata exynos_mdma1_pdata = {
 	.nr_valid_peri = ARRAY_SIZE(mdma_peri),
 	.peri_id = mdma_peri,
 };
 
 static AMBA_AHB_DEVICE(exynos4_mdma1,  "dma-pl330.2", 0x00041330,
-	EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
+	EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
 
-static int __init exynos4_dma_init(void)
+static int __init exynos_dma_init(void)
 {
 	if (of_have_populated_dt())
 		return 0;
 
 	if (soc_is_exynos4210()) {
-		exynos4_pdma0_pdata.nr_valid_peri =
+		exynos_pdma0_pdata.nr_valid_peri =
 			ARRAY_SIZE(exynos4210_pdma0_peri);
-		exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
-		exynos4_pdma1_pdata.nr_valid_peri =
+		exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
+		exynos_pdma1_pdata.nr_valid_peri =
 			ARRAY_SIZE(exynos4210_pdma1_peri);
-		exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
+		exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
 	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-		exynos4_pdma0_pdata.nr_valid_peri =
+		exynos_pdma0_pdata.nr_valid_peri =
 			ARRAY_SIZE(exynos4212_pdma0_peri);
-		exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
-		exynos4_pdma1_pdata.nr_valid_peri =
+		exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
+		exynos_pdma1_pdata.nr_valid_peri =
 			ARRAY_SIZE(exynos4212_pdma1_peri);
-		exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+		exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+	} else if (soc_is_exynos5250()) {
+		exynos_pdma0_pdata.nr_valid_peri =
+			ARRAY_SIZE(exynos5250_pdma0_peri);
+		exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
+		exynos_pdma1_pdata.nr_valid_peri =
+			ARRAY_SIZE(exynos5250_pdma1_peri);
+		exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
+
+		exynos4_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
+		exynos4_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
+		exynos4_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
+		exynos4_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
+		exynos4_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
+		exynos4_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
+		exynos4_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
+		exynos4_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
+		exynos4_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
 	}
 
-	dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
-	dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
+	dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
+	dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
 	amba_device_register(&exynos4_pdma0_device, &iomem_resource);
 
-	dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
-	dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
+	dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
+	dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
 	amba_device_register(&exynos4_pdma1_device, &iomem_resource);
 
-	dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
+	dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
 	amba_device_register(&exynos4_mdma1_device, &iomem_resource);
 
 	return 0;
 }
-arch_initcall(exynos4_dma_init);
+arch_initcall(exynos_dma_init);
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index a0ffc77d..77e65b4 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -291,7 +291,7 @@ config S3C_DMA
 config SAMSUNG_DMADEV
 	bool
 	select DMADEVICES
-	select PL330_DMA if (CPU_EXYNOS4210 || CPU_S5PV210 || CPU_S5PC100 || \
+	select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \
 					CPU_S5P6450 || CPU_S5P6440)
 	select ARM_AMBA
 	help
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index 0670f37..d384a80 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -90,6 +90,7 @@ enum dma_ch {
 	DMACH_MIPI_HSI5,
 	DMACH_MIPI_HSI6,
 	DMACH_MIPI_HSI7,
+	DMACH_DISP1,
 	DMACH_MTOM_0,
 	DMACH_MTOM_1,
 	DMACH_MTOM_2,
-- 
1.7.5.4

[PATCH 03/20] ARM: EXYNOS: fix ctrlbit for exynos5_clk_pdma1

[Thomas Abraham]

From: Kukjin Kim <kgene.kim@samsung.com>

It should be (1 << 2) for ctrlbit of exynos5_clk_pdma1.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/clock-exynos5.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 3dc3c50..846741e 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -683,7 +683,7 @@ static struct clk exynos5_clk_pdma1 = {
 	.name		= "dma",
 	.devname	= "dma-pl330.1",
 	.enable		= exynos5_clk_ip_fsys_ctrl,
-	.ctrlbit	= (1 << 1),
+	.ctrlbit	= (1 << 2),
 };
 
 static struct clk exynos5_clk_mdma1 = {
-- 
1.7.5.4

[PATCH 04/20] ARM: EXYNOS: Modify the GIC physical address for static io-mapping

[Thomas Abraham]

From: Changhwan Youn <chaos.youn@samsung.com>

Adapt to changes in GIC physical address in rev1 of EXYNOS5.

Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/common.c           |    4 ++--
 arch/arm/mach-exynos/include/mach/map.h |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5ccd6e8..eff4446 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -265,12 +265,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
 	}, {
 		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
 		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
-		.length		= SZ_64K,
+		.length		= SZ_8K,
 		.type		= MT_DEVICE,
 	}, {
 		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
 		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
-		.length		= SZ_64K,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE,
 	},
 };
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 6e6d11f..cf7d200 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -78,8 +78,8 @@
 
 #define EXYNOS4_PA_GIC_CPU		0x10480000
 #define EXYNOS4_PA_GIC_DIST		0x10490000
-#define EXYNOS5_PA_GIC_CPU		0x10480000
-#define EXYNOS5_PA_GIC_DIST		0x10490000
+#define EXYNOS5_PA_GIC_CPU		0x10482000
+#define EXYNOS5_PA_GIC_DIST		0x10481000
 
 #define EXYNOS4_PA_COREPERI		0x10500000
 #define EXYNOS4_PA_TWD			0x10500600
-- 
1.7.5.4

[PATCH 05/20] ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition

[Thomas Abraham]

From: Changhwan Youn <chaos.youn@samsung.com>

Redefine IRQ_MCT_L0,1 irq definition as it is changed in rev1 of EXYNOS5.

Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/include/mach/irqs.h |    4 ++--
 arch/arm/mach-exynos/mct.c               |   17 +++++++++++------
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 591e7852..ef52f61 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -331,6 +331,8 @@
 #define EXYNOS5_IRQ_SATA		IRQ_SPI(115)
 #define EXYNOS5_IRQ_NFCON		IRQ_SPI(116)
 
+#define EXYNOS5_IRQ_MCT_L0		IRQ_SPI(120)
+#define EXYNOS5_IRQ_MCT_L1		IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44		IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1		IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0		IRQ_SPI(125)
@@ -410,8 +412,6 @@
 #define EXYNOS5_IRQ_FIMD1_SYSTEM	COMBINER_IRQ(18, 6)
 
 #define EXYNOS5_IRQ_EINT0		COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_L0		COMBINER_IRQ(23, 1)
-#define EXYNOS5_IRQ_MCT_L1		COMBINER_IRQ(23, 2)
 #define EXYNOS5_IRQ_MCT_G0		COMBINER_IRQ(23, 3)
 #define EXYNOS5_IRQ_MCT_G1		COMBINER_IRQ(23, 4)
 #define EXYNOS5_IRQ_MCT_G2		COMBINER_IRQ(23, 5)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 897d9a9..b601fb8 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 {
 	struct mct_clock_event_device *mevt;
 	unsigned int cpu = smp_processor_id();
+	int mct_lx_irq;
 
 	mevt = this_cpu_ptr(&percpu_mct_tick);
 	mevt->evt = evt;
@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 
 	if (mct_int_type == MCT_INT_SPI) {
 		if (cpu == 0) {
+			mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
+						EXYNOS5_IRQ_MCT_L0;
 			mct_tick0_event_irq.dev_id = mevt;
-			evt->irq = EXYNOS4_IRQ_MCT_L0;
-			setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
+			evt->irq = mct_lx_irq;
+			setup_irq(mct_lx_irq, &mct_tick0_event_irq);
 		} else {
+			mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
+						EXYNOS5_IRQ_MCT_L1;
 			mct_tick1_event_irq.dev_id = mevt;
-			evt->irq = EXYNOS4_IRQ_MCT_L1;
-			setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
-			irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
+			evt->irq = mct_lx_irq;
+			setup_irq(mct_lx_irq, &mct_tick1_event_irq);
+			irq_set_affinity(mct_lx_irq, cpumask_of(1));
 		}
 	} else {
 		enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
 
 static void __init exynos4_timer_init(void)
 {
-	if (soc_is_exynos4210())
+	if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
 		mct_int_type = MCT_INT_SPI;
 	else
 		mct_int_type = MCT_INT_PPI;
-- 
1.7.5.4

[PATCH 06/20] ARM: EXYNOS: add GPC4 bank instance

[Thomas Abraham]

From: Sangsu Park <sangsu4u.park@samsung.com>

Add GPC4 bank instance which is included in rev1 of EXYNOS5.

Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Sangsu Park <sangsu4u.park@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
[kgene.kim at samsung.com: re-worked on top of v3.4-rc3]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/include/mach/gpio.h |    9 ++++++---
 arch/arm/mach-exynos/include/mach/irqs.h |    2 +-
 drivers/gpio/gpio-samsung.c              |   11 ++++++++++-
 3 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index d7498af..eb24f1e 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
 #define EXYNOS5_GPIO_B2_NR	(4)
 #define EXYNOS5_GPIO_B3_NR	(4)
 #define EXYNOS5_GPIO_C0_NR	(7)
-#define EXYNOS5_GPIO_C1_NR	(7)
+#define EXYNOS5_GPIO_C1_NR	(4)
 #define EXYNOS5_GPIO_C2_NR	(7)
 #define EXYNOS5_GPIO_C3_NR	(7)
-#define EXYNOS5_GPIO_D0_NR	(8)
+#define EXYNOS5_GPIO_C4_NR	(7)
+#define EXYNOS5_GPIO_D0_NR	(4)
 #define EXYNOS5_GPIO_D1_NR	(8)
 #define EXYNOS5_GPIO_Y0_NR	(6)
 #define EXYNOS5_GPIO_Y1_NR	(4)
@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
 	EXYNOS5_GPIO_C1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
 	EXYNOS5_GPIO_C2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
 	EXYNOS5_GPIO_C3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_C4_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
 	EXYNOS5_GPIO_D1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
 	EXYNOS5_GPIO_Y0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
 	EXYNOS5_GPIO_Y1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
 #define EXYNOS5_GPC1(_nr)	(EXYNOS5_GPIO_C1_START + (_nr))
 #define EXYNOS5_GPC2(_nr)	(EXYNOS5_GPIO_C2_START + (_nr))
 #define EXYNOS5_GPC3(_nr)	(EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr)	(EXYNOS5_GPIO_C4_START + (_nr))
 #define EXYNOS5_GPD0(_nr)	(EXYNOS5_GPIO_D0_START + (_nr))
 #define EXYNOS5_GPD1(_nr)	(EXYNOS5_GPIO_D1_START + (_nr))
 #define EXYNOS5_GPY0(_nr)	(EXYNOS5_GPIO_Y0_START + (_nr))
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index ef52f61..ece5624 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -446,7 +446,7 @@
 
 #define EXYNOS5_MAX_COMBINER_NR		32
 
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS	13
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS	14
 #define EXYNOS5_IRQ_GPIO2_NR_GROUPS	9
 #define EXYNOS5_IRQ_GPIO3_NR_GROUPS	5
 #define EXYNOS5_IRQ_GPIO4_NR_GROUPS	1
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 19d6fc0..0a2087b 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
 		},
 	}, {
 		.chip	= {
+			.base	= EXYNOS5_GPC4(0),
+			.ngpio	= EXYNOS5_GPIO_C4_NR,
+			.label	= "GPC4",
+		},
+	}, {
+		.chip	= {
 			.base	= EXYNOS5_GPD0(0),
 			.ngpio	= EXYNOS5_GPIO_D0_NR,
 			.label	= "GPD0",
@@ -2874,8 +2880,11 @@ static __init int samsung_gpiolib_init(void)
 			goto err_ioremap1;
 		}
 
+		/* need to set base address for gpc4 */
+		exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;
+
 		/* need to set base address for gpx */
-		chip = &exynos5_gpios_1[20];
+		chip = &exynos5_gpios_1[21];
 		gpx_base = gpio_base1 + 0xC00;
 		for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
 			chip->base = gpx_base;
-- 
1.7.5.4

[PATCH 07/20] ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

[Thomas Abraham]

From: Kisoo Yu <ksoo.yu@samsung.com>

The fout clock of BPLL and MPLL have a selectable source in rev1 of
EXYNOS5. The clock options are a fixed divided by 2 clock and the
output of the PLL itself. Add support for these new clock instances.

Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
[kgene.kim at samsung.com: temporary apply this because I
don't want to add pll stuff in each clock not commonly]
Temporary-Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/clock-exynos5.c           |   73 +++++++++++++++++++++++-
 arch/arm/mach-exynos/include/mach/regs-clock.h |    2 +
 arch/arm/plat-s5p/clock.c                      |   11 ----
 3 files changed, 74 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 846741e..7c0f810 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -145,6 +145,39 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
 	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 };
 
+static struct clk clk_fout_bpll_div2 = {
+	.name	= "fout_bpll_div2",
+};
+
+static struct clk *exynos5_clkset_mout_bpll_fout_list[] = {
+	[0] = &clk_fout_bpll_div2,
+	[1] = &clk_fout_bpll,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_bpll_fout = {
+	.sources	= exynos5_clkset_mout_bpll_fout_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_bpll_fout_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+	.clk	= {
+		.name		= "mout_bpll_fout",
+	},
+	.sources = &exynos5_clkset_mout_bpll_fout,
+	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+/* Possible clock sources for BPLL Mux */
+static struct clk *clk_src_bpll_list[] = {
+	[0] = &clk_fin_bpll,
+	[1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+struct clksrc_sources clk_src_bpll = {
+	.sources	= clk_src_bpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
+};
+
 static struct clksrc_clk exynos5_clk_mout_bpll = {
 	.clk	= {
 		.name		= "mout_bpll",
@@ -187,11 +220,43 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
 	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 };
 
+static struct clk clk_fout_mpll_div2 = {
+	.name	= "fout_mpll_div2",
+};
+
+static struct clk *exynos5_clkset_mout_mpll_fout_list[] = {
+	[0] = &clk_fout_mpll_div2,
+	[1] = &clk_fout_mpll,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_mpll_fout = {
+	.sources	= exynos5_clkset_mout_mpll_fout_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_mpll_fout_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+	.clk	= {
+		.name		= "mout_mpll_fout",
+	},
+	.sources = &exynos5_clkset_mout_mpll_fout,
+	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_mpll_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+struct clksrc_sources exynos5_clk_src_mpll = {
+	.sources	= exynos5_clk_src_mpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_mpll_list),
+};
+
 struct clksrc_clk exynos5_clk_mout_mpll = {
 	.clk = {
 		.name		= "mout_mpll",
 	},
-	.sources = &clk_src_mpll,
+	.sources = &exynos5_clk_src_mpll,
 	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 };
 
@@ -946,10 +1011,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
 	&exynos5_clk_mout_apll,
 	&exynos5_clk_sclk_apll,
 	&exynos5_clk_mout_bpll,
+	&exynos5_clk_mout_bpll_fout,
 	&exynos5_clk_mout_bpll_user,
 	&exynos5_clk_mout_cpll,
 	&exynos5_clk_mout_epll,
 	&exynos5_clk_mout_mpll,
+	&exynos5_clk_mout_mpll_fout,
 	&exynos5_clk_mout_mpll_user,
 	&exynos5_clk_vpllsrc,
 	&exynos5_clk_sclk_vpll,
@@ -1013,6 +1080,8 @@ static struct clk *exynos5_clks[] __initdata = {
 	&exynos5_clk_sclk_hdmi27m,
 	&exynos5_clk_sclk_hdmiphy,
 	&clk_fout_bpll,
+	&clk_fout_bpll_div2,
+	&clk_fout_mpll_div2,
 	&clk_fout_cpll,
 	&exynos5_clk_armclk,
 };
@@ -1178,8 +1247,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
 
 	clk_fout_apll.ops = &exynos5_fout_apll_ops;
 	clk_fout_bpll.rate = bpll;
+	clk_fout_bpll_div2.rate = bpll >> 1;
 	clk_fout_cpll.rate = cpll;
 	clk_fout_mpll.rate = mpll;
+	clk_fout_mpll_div2.rate = mpll >> 1;
 	clk_fout_epll.rate = epll;
 	clk_fout_vpll.rate = vpll;
 
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index d9578a5..130034d 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -313,6 +313,8 @@
 #define EXYNOS5_CLKGATE_IP_PERIS		EXYNOS_CLKREG(0x10960)
 #define EXYNOS5_CLKGATE_BLOCK			EXYNOS_CLKREG(0x10980)
 
+#define EXYNOS5_PLL_DIV2_SEL			EXYNOS_CLKREG(0x20A24)
+
 #define EXYNOS5_BPLL_CON0			EXYNOS_CLKREG(0x20110)
 #define EXYNOS5_CLKSRC_CDREX			EXYNOS_CLKREG(0x20200)
 #define EXYNOS5_CLKDIV_CDREX			EXYNOS_CLKREG(0x20500)
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index f68a9bb..bea0907 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -115,17 +115,6 @@ struct clksrc_sources clk_src_apll = {
 	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
 };
 
-/* Possible clock sources for BPLL Mux */
-static struct clk *clk_src_bpll_list[] = {
-	[0] = &clk_fin_bpll,
-	[1] = &clk_fout_bpll,
-};
-
-struct clksrc_sources clk_src_bpll = {
-	.sources	= clk_src_bpll_list,
-	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
-};
-
 /* Possible clock sources for CPLL Mux */
 static struct clk *clk_src_cpll_list[] = {
 	[0] = &clk_fin_cpll,
-- 
1.7.5.4

[PATCH 08/20] ARM: EXYNOS: update irqs for EXYNOS5250 evt1

[Thomas Abraham]

From: Kukjin Kim <kgene.kim@samsung.com>

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/include/mach/irqs.h |   34 ++++++++++++++++++-----------
 1 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index ece5624..46d4734 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -297,6 +297,7 @@
 #define EXYNOS5_IRQ_MIPICSI1		IRQ_SPI(80)
 #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT	IRQ_SPI(81)
 #define EXYNOS5_IRQ_MIPIDSI0		IRQ_SPI(82)
+#define EXYNOS5_IRQ_WDT_IOP		IRQ_SPI(83)
 #define EXYNOS5_IRQ_ROTATOR		IRQ_SPI(84)
 #define EXYNOS5_IRQ_GSC0		IRQ_SPI(85)
 #define EXYNOS5_IRQ_GSC1		IRQ_SPI(86)
@@ -305,8 +306,8 @@
 #define EXYNOS5_IRQ_JPEG		IRQ_SPI(89)
 #define EXYNOS5_IRQ_EFNFCON_DMA		IRQ_SPI(90)
 #define EXYNOS5_IRQ_2D			IRQ_SPI(91)
-#define EXYNOS5_IRQ_SFMC0		IRQ_SPI(92)
-#define EXYNOS5_IRQ_SFMC1		IRQ_SPI(93)
+#define EXYNOS5_IRQ_EFNFCON_0		IRQ_SPI(92)
+#define EXYNOS5_IRQ_EFNFCON_1		IRQ_SPI(93)
 #define EXYNOS5_IRQ_MIXER		IRQ_SPI(94)
 #define EXYNOS5_IRQ_HDMI		IRQ_SPI(95)
 #define EXYNOS5_IRQ_MFC			IRQ_SPI(96)
@@ -320,7 +321,7 @@
 #define EXYNOS5_IRQ_PCM2		IRQ_SPI(104)
 #define EXYNOS5_IRQ_SPDIF		IRQ_SPI(105)
 #define EXYNOS5_IRQ_ADC0		IRQ_SPI(106)
-
+#define EXYNOS5_IRQ_ADC1		IRQ_SPI(107)
 #define EXYNOS5_IRQ_SATA_PHY		IRQ_SPI(108)
 #define EXYNOS5_IRQ_SATA_PMEMREQ	IRQ_SPI(109)
 #define EXYNOS5_IRQ_CAM_C		IRQ_SPI(110)
@@ -329,7 +330,6 @@
 #define EXYNOS5_IRQ_DP1_INTP1		IRQ_SPI(113)
 #define EXYNOS5_IRQ_CEC			IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA		IRQ_SPI(115)
-#define EXYNOS5_IRQ_NFCON		IRQ_SPI(116)
 
 #define EXYNOS5_IRQ_MCT_L0		IRQ_SPI(120)
 #define EXYNOS5_IRQ_MCT_L1		IRQ_SPI(121)
@@ -340,7 +340,6 @@
 #define EXYNOS5_IRQ_RP_TIMER		IRQ_SPI(127)
 
 #define EXYNOS5_IRQ_PMU			COMBINER_IRQ(1, 2)
-#define EXYNOS5_IRQ_PMU_CPU1		COMBINER_IRQ(1, 6)
 
 #define EXYNOS5_IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
 #define EXYNOS5_IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
@@ -351,6 +350,8 @@
 #define EXYNOS5_IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
 #define EXYNOS5_IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
 
+#define EXYNOS5_IRQ_SYSMMU_LITE2_0	COMBINER_IRQ(3, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE2_1	COMBINER_IRQ(3, 1)
 #define EXYNOS5_IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
 #define EXYNOS5_IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
 #define EXYNOS5_IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
@@ -374,8 +375,8 @@
 
 #define EXYNOS5_IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
 #define EXYNOS5_IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(6, 2)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(6, 3)
 #define EXYNOS5_IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
 #define EXYNOS5_IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
 #define EXYNOS5_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
@@ -387,11 +388,9 @@
 #define EXYNOS5_IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
 #define EXYNOS5_IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
 #define EXYNOS5_IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
-#define EXYNOS5_IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
-#define EXYNOS5_IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
 
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(8, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(8, 6)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(8, 6)
 
 #define EXYNOS5_IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
 #define EXYNOS5_IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
@@ -407,15 +406,24 @@
 #define EXYNOS5_IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
 #define EXYNOS5_IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
 
+#define EXYNOS5_IRQ_MDMA1_ABORT		COMBINER_IRQ(13, 1)
+
+#define EXYNOS5_IRQ_MDMA0_ABORT		COMBINER_IRQ(15, 3)
+
 #define EXYNOS5_IRQ_FIMD1_FIFO		COMBINER_IRQ(18, 4)
 #define EXYNOS5_IRQ_FIMD1_VSYNC		COMBINER_IRQ(18, 5)
 #define EXYNOS5_IRQ_FIMD1_SYSTEM	COMBINER_IRQ(18, 6)
 
+#define EXYNOS5_IRQ_ARMIOP_GIC		COMBINER_IRQ(19, 0)
+#define EXYNOS5_IRQ_ARMISP_GIC		COMBINER_IRQ(19, 1)
+#define EXYNOS5_IRQ_IOP_GIC		COMBINER_IRQ(19, 3)
+#define EXYNOS5_IRQ_ISP_GIC		COMBINER_IRQ(19, 4)
+
+#define EXYNOS5_IRQ_PMU_CPU1		COMBINER_IRQ(22, 4)
+
 #define EXYNOS5_IRQ_EINT0		COMBINER_IRQ(23, 0)
 #define EXYNOS5_IRQ_MCT_G0		COMBINER_IRQ(23, 3)
 #define EXYNOS5_IRQ_MCT_G1		COMBINER_IRQ(23, 4)
-#define EXYNOS5_IRQ_MCT_G2		COMBINER_IRQ(23, 5)
-#define EXYNOS5_IRQ_MCT_G3		COMBINER_IRQ(23, 6)
 
 #define EXYNOS5_IRQ_EINT1		COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
-- 
1.7.5.4

[PATCH 09/20] ARM: Exynos: Remove a new bus_type instance for Exynos5

[Thomas Abraham]

A seperate bus_type instance is not required for Exynos5. The existing bus_type
instance used with Exynos4 is sufficient for both Exynos4 and Exynos5. This
also solves issue of uninitialized usage of exynos4_subsys in Exynos4 power
management code that is reused for Exynos5 also. In addition to that, the
existing exynos4_subsys bus_type is renamed to exynos_subsys to indicate that
it is reused on both Exynos4 and Exynos5 platforms.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/common.c            |   27 ++++++---------------------
 arch/arm/mach-exynos/pm.c                |    2 +-
 arch/arm/plat-samsung/include/plat/cpu.h |    2 +-
 3 files changed, 8 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index eff4446..3302a8d 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -565,30 +565,18 @@ void __init exynos5_init_irq(void)
 	s5p_init_irq(NULL, 0);
 }
 
-struct bus_type exynos4_subsys = {
-	.name		= "exynos4-core",
-	.dev_name	= "exynos4-core",
-};
-
-struct bus_type exynos5_subsys = {
-	.name		= "exynos5-core",
-	.dev_name	= "exynos5-core",
+struct bus_type exynos_subsys = {
+	.name		= "exynos-core",
+	.dev_name	= "exynos-core",
 };
 
 static struct device exynos4_dev = {
-	.bus	= &exynos4_subsys,
-};
-
-static struct device exynos5_dev = {
-	.bus	= &exynos5_subsys,
+	.bus	= &exynos_subsys,
 };
 
 static int __init exynos_core_init(void)
 {
-	if (soc_is_exynos5250())
-		return subsys_system_register(&exynos5_subsys, NULL);
-	else
-		return subsys_system_register(&exynos4_subsys, NULL);
+	return subsys_system_register(&exynos_subsys, NULL);
 }
 core_initcall(exynos_core_init);
 
@@ -675,10 +663,7 @@ static int __init exynos_init(void)
 {
 	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 
-	if (soc_is_exynos5250())
-		return device_register(&exynos5_dev);
-	else
-		return device_register(&exynos4_dev);
+	return device_register(&exynos4_dev);
 }
 
 /* uart registration process */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 428cfeb..7164aa9 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -275,7 +275,7 @@ static void exynos4_restore_pll(void)
 
 static struct subsys_interface exynos4_pm_interface = {
 	.name		= "exynos4_pm",
-	.subsys		= &exynos4_subsys,
+	.subsys		= &exynos_subsys,
 	.add_dev	= exynos4_pm_add,
 };
 
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 787ceac..0721293 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -202,7 +202,7 @@ extern struct bus_type s3c2443_subsys;
 extern struct bus_type s3c6410_subsys;
 extern struct bus_type s5p64x0_subsys;
 extern struct bus_type s5pv210_subsys;
-extern struct bus_type exynos4_subsys;
+extern struct bus_type exynos_subsys;
 
 extern void (*s5pc1xx_idle)(void);
 
-- 
1.7.5.4

[PATCH 10/20] of/irq: fix interrupt parent lookup procedure

[Thomas Abraham]

The interrupt parent lookup fails for a node that is a interrupt-controller
but does not have an explict interrupt-parent property and instead inherits
this property from the root node.

Consider the nodes listed below.

    / {
        interrupt-parent = <&intc_level1>;

        intc_level1: interrupt-controller at xxx {
                interrupt-controller;
                #interrupt-cells = <3>;
                <rest of the properties here>;
        };

        intc_level2: interrupt-controller at yyy {
                interrupt-controller;
                #interrupt-cells = <2>;
                <rest of the properties here>;
        };
    };

The interrupt parent lookup for interrupt-controller at yyy fails. It inherits
the interrupt-parent property from the root node and the root node ('/')
specifies a 'interrupt-parent' property which represents the default interrupt
root controller. But, the property '#interrupt-cells' might not be specified
in the root node.

In case a interrupt controller node does not include a 'interrupt-parent'
property but inherits that property from the root node, the check for
'interrupt-cells' property in the root node fails. Fix this removing the
check for 'interrupt-cells' property.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 drivers/of/irq.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 9cf0060..a520363 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -66,14 +66,16 @@ struct device_node *of_irq_find_parent(struct device_node *child)
 		if (parp == NULL)
 			p = of_get_parent(child);
 		else {
+			of_node_put(child);
 			if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
 				p = of_node_get(of_irq_dflt_pic);
 			else
 				p = of_find_node_by_phandle(be32_to_cpup(parp));
+			return p;
 		}
 		of_node_put(child);
 		child = p;
-	} while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL);
+	} while (p);
 
 	return p;
 }
-- 
1.7.5.4

[PATCH 11/20] of/irq: add retry support for interrupt controller tree initialization

[Thomas Abraham]

Allow a interrupt-controller initializtion call to report -EAGAIN to notify
that its initializtion has not been completed since one or more of its
interrupt-parent has not yet been initialized.

Suggested-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 drivers/of/irq.c |   25 +++++++++++++++++++++----
 1 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index a520363..bbe6039 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -418,8 +418,6 @@ void __init of_irq_init(const struct of_device_id *matches)
 	INIT_LIST_HEAD(&intc_parent_list);
 
 	for_each_matching_node(np, matches) {
-		if (!of_find_property(np, "interrupt-controller", NULL))
-			continue;
 		/*
 		 * Here, we allocate and populate an intc_desc with the node
 		 * pointer, interrupt-parent device_node etc.
@@ -454,7 +452,6 @@ void __init of_irq_init(const struct of_device_id *matches)
 			if (desc->interrupt_parent != parent)
 				continue;
 
-			list_del(&desc->list);
 			match = of_match_node(matches, desc->dev);
 			if (WARN(!match->data,
 			    "of_irq_init: no init function for %s\n",
@@ -468,6 +465,15 @@ void __init of_irq_init(const struct of_device_id *matches)
 				 desc->dev, desc->interrupt_parent);
 			irq_init_cb = match->data;
 			ret = irq_init_cb(desc->dev, desc->interrupt_parent);
+			if (ret == -EAGAIN)
+				/* 
+				 * Interrupt controller's initialization did not
+				 * complete and should be retried. So let its
+				 * intc_desc be on intc_desc_list.
+				 */
+				continue;
+			list_del(&desc->list);
+
 			if (ret) {
 				kfree(desc);
 				continue;
@@ -484,7 +490,18 @@ void __init of_irq_init(const struct of_device_id *matches)
 		desc = list_first_entry(&intc_parent_list, typeof(*desc), list);
 		if (list_empty(&intc_parent_list) || !desc) {
 			pr_err("of_irq_init: children remain, but no parents\n");
-			break;
+			/*
+			 * If a search with NULL as parent did not result in any
+			 * new parent being found, then the scan for matching
+			 * interrupt controller nodes is considered as complete.
+			 * Otherwise, if there are pending elements on the
+			 * intc_desc_list, then retry this process again with
+			 * NULL as parent.
+			 */
+			if (!parent)
+				break;
+			parent = NULL;
+			continue;
 		}
 		list_del(&desc->list);
 		parent = desc->dev;
-- 
1.7.5.4

[PATCH 12/20] ARM: Exynos: Add irq_domain support for interrupt combiner

[Thomas Abraham]

Add irq_domain support for hardware interrupts of the interrupt combiner.
The hardware interrupts of all the instances of the combiner are grouped
in a single irq_domain.

Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Rob Herring <rob.herring@calxeda.com>
---
 arch/arm/mach-exynos/common.c |   87 +++++++++++++++++++++++-----------------
 1 files changed, 50 insertions(+), 37 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 3302a8d..5f6febb 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -19,6 +19,8 @@
 #include <linux/serial_core.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/export.h>
+#include <linux/irqdomain.h>
 
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
@@ -399,6 +401,7 @@ struct combiner_chip_data {
 	void __iomem *base;
 };
 
+static struct irq_domain *combiner_irq_domain;
 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 
 static inline void __iomem *combiner_base(struct irq_data *data)
@@ -411,14 +414,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
 
 static void combiner_mask_irq(struct irq_data *data)
 {
-	u32 mask = 1 << (data->irq % 32);
+	u32 mask = 1 << (data->hwirq % 32);
 
 	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 }
 
 static void combiner_unmask_irq(struct irq_data *data)
 {
-	u32 mask = 1 << (data->irq % 32);
+	u32 mask = 1 << (data->hwirq % 32);
 
 	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 }
@@ -474,36 +477,59 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
 	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 }
 
-static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
-			  unsigned int irq_start)
+static void __init combiner_init_one(unsigned int combiner_nr,
+						void __iomem *base)
 {
-	unsigned int i;
-	unsigned int max_nr;
-
-	if (soc_is_exynos5250())
-		max_nr = EXYNOS5_MAX_COMBINER_NR;
-	else
-		max_nr = EXYNOS4_MAX_COMBINER_NR;
-
-	if (combiner_nr >= max_nr)
-		BUG();
-
 	combiner_data[combiner_nr].base = base;
-	combiner_data[combiner_nr].irq_offset = irq_start;
+	combiner_data[combiner_nr].irq_offset = irq_find_mapping(
+		combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 
 	/* Disable all interrupts */
 
 	__raw_writel(combiner_data[combiner_nr].irq_mask,
 		     base + COMBINER_ENABLE_CLEAR);
+}
+
+static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
+					irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
+	irq_set_chip_data(irq, &combiner_data[hw >> 3]);
+	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+	return 0;
+}
+
+static struct irq_domain_ops combiner_irq_domain_ops = {
+	.map = combiner_irq_domain_map,
+};
 
-	/* Setup the Linux IRQ subsystem */
+void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
+{
+	int i, irq_base;
+	unsigned int max_nr, nr_irq;
+
+	max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
+						EXYNOS4_MAX_COMBINER_NR;
+	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
+
+	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
+	if (IS_ERR_VALUE(irq_base)) {
+		irq_base = COMBINER_IRQ(0, 0);
+		pr_warning("%s: irq desc alloc failed. Continuing with %d as "
+				"linux irq base\n", __func__, irq_base);
+	}
+
+	combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
+				&combiner_irq_domain_ops, &combiner_data);
+	if (WARN_ON(!combiner_irq_domain)) {
+		pr_warning("%s: irq domain init failed\n", __func__);
+		return;
+	}
 
-	for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
-				+ MAX_IRQ_IN_COMBINER; i++) {
-		irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
-		irq_set_chip_data(i, &combiner_data[combiner_nr]);
-		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+	for (i = 0; i < max_nr; i++) {
+		combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
+		combiner_cascade_irq(i, IRQ_SPI(i));
 	}
 }
 
@@ -516,7 +542,6 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
 
 void __init exynos4_init_irq(void)
 {
-	int irq;
 	unsigned int gic_bank_offset;
 
 	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
@@ -528,12 +553,7 @@ void __init exynos4_init_irq(void)
 		of_irq_init(exynos4_dt_irq_match);
 #endif
 
-	for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
-
-		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-				COMBINER_IRQ(irq, 0));
-		combiner_cascade_irq(irq, IRQ_SPI(irq));
-	}
+	combiner_init(S5P_VA_COMBINER_BASE, NULL);
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
@@ -545,17 +565,10 @@ void __init exynos4_init_irq(void)
 
 void __init exynos5_init_irq(void)
 {
-	int irq;
-
 #ifdef CONFIG_OF
 	of_irq_init(exynos4_dt_irq_match);
 #endif
-
-	for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
-		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-				COMBINER_IRQ(irq, 0));
-		combiner_cascade_irq(irq, IRQ_SPI(irq));
-	}
+	combiner_init(S5P_VA_COMBINER_BASE, NULL);
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
-- 
1.7.5.4

[PATCH 13/20] ARM: Exynos: Add device tree support for interrupt combiner

[Thomas Abraham]

Add device tree based instantiation of the interrupt combiner controller.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
---
 .../bindings/arm/samsung/interrupt-combiner.txt    |   52 ++++++++++++++++
 arch/arm/mach-exynos/common.c                      |   63 ++++++++++++++++++--
 2 files changed, 109 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt

diff --git a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
new file mode 100644
index 0000000..f2f2171
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
@@ -0,0 +1,52 @@
+* Samsung Exynos Interrupt Combiner Controller
+
+Samsung's Exynos4 architecture includes a interrupt combiner controller which
+can combine interrupt sources as a group and provide a single interrupt request
+for the group. The interrupt request from each group are connected to a parent
+interrupt controller, such as GIC in case of Exynos4210.
+
+The interrupt combiner controller consists of multiple combiners. Upto eight
+interrupt sources can be connected to a combiner. The combiner outputs one
+combined interrupt for its eight interrupt sources. The combined interrupt
+is usually connected to a parent interrupt controller.
+
+A single node in the device tree is used to describe the interrupt combiner
+controller module (which includes multiple combiners). A combiner in the
+interrupt controller module shares config/control registers with other
+combiners. For example, a 32-bit interrupt enable/disable config register
+can accommodate upto 4 interrupt combiners (with each combiner supporting
+upto 8 interrupt sources).
+
+Required properties:
+- compatible: should be "samsung,exynos4210-combiner".
+- interrupt-controller: Identifies the node as an interrupt controller.
+- #interrupt-cells: should be <2>. The meaning of the cells are
+	* First Cell: Combiner Group Number.
+	* Second Cell: Interrupt number within the group.
+- reg: Base address and size of interrupt combiner registers.
+- interrupts: The list of interrupts generated by the combiners which are then
+    connected to a parent interrupt controller. The format of the interrupt
+    specifier depends in the interrupt parent controller.
+
+Optional properties:
+- samsung,combiner-nr: The number of interrupt combiners supported. If this
+  property is not specified, the default number of combiners is assumed
+  to be 16.
+- interrupt-parent: pHandle of the parent interrupt controller, if not
+  inherited from the parent node.
+
+
+Example:
+
+	The following is a an example from the Exynos4210 SoC dtsi file.
+
+	combiner:interrupt-controller at 10440000 {
+		compatible = "samsung,exynos4210-combiner";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		reg = <0x10440000 0x1000>;
+		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+	};
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5f6febb..5c104d0 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -21,6 +21,7 @@
 #include <linux/of_irq.h>
 #include <linux/export.h>
 #include <linux/irqdomain.h>
+#include <linux/of_address.h>
 
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
@@ -491,6 +492,30 @@ static void __init combiner_init_one(unsigned int combiner_nr,
 		     base + COMBINER_ENABLE_CLEAR);
 }
 
+#ifdef CONFIG_OF
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+		struct device_node *controller, const u32 *intspec,
+		unsigned int intsize, unsigned long *out_hwirq,
+		unsigned int *out_type)
+{
+	if (d->of_node != controller)
+		return -EINVAL;
+	if (intsize < 2)
+		return -EINVAL;
+	*out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
+	*out_type = 0;
+	return 0;
+}
+#else
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+		struct device_node *controller, const u32 *intspec,
+		unsigned int intsize, unsigned long *out_hwirq,
+		unsigned int *out_type)
+{
+	return -EINVAL;
+}
+#endif
+
 static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
 					irq_hw_number_t hw)
 {
@@ -501,16 +526,26 @@ static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
 }
 
 static struct irq_domain_ops combiner_irq_domain_ops = {
+	.xlate = combiner_irq_domain_xlate,
 	.map = combiner_irq_domain_map,
 };
 
 void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
 {
-	int i, irq_base;
+	int i, irq, irq_base;
 	unsigned int max_nr, nr_irq;
 
-	max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
+	if (np) {
+		if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
+			pr_warning("%s: number of combiners not specified, "
+				"setting default as %d.\n",
+				__func__, EXYNOS4_MAX_COMBINER_NR);
+			max_nr = EXYNOS4_MAX_COMBINER_NR;
+		}
+	} else {
+		max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
 						EXYNOS4_MAX_COMBINER_NR;
+	}
 	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 
 	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
@@ -529,13 +564,30 @@ void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
 
 	for (i = 0; i < max_nr; i++) {
 		combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
-		combiner_cascade_irq(i, IRQ_SPI(i));
+		irq = np ? irq_of_parse_and_map(np, i) : IRQ_SPI(i);
+		combiner_cascade_irq(i, irq);
 	}
 }
 
 #ifdef CONFIG_OF
+int __init combiner_of_init(struct device_node *np, struct device_node *parent)
+{
+	void __iomem *combiner_base;
+
+	combiner_base = of_iomap(np, 0);
+	if (!combiner_base) {
+		pr_err("%s: failed to map combiner registers\n", __func__);
+		return -ENXIO;
+	}
+
+	combiner_init(combiner_base, np);
+	return 0;
+}
+
 static const struct of_device_id exynos4_dt_irq_match[] = {
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ .compatible = "samsung,exynos4210-combiner",
+			.data = combiner_of_init, },
 	{},
 };
 #endif
@@ -553,7 +605,8 @@ void __init exynos4_init_irq(void)
 		of_irq_init(exynos4_dt_irq_match);
 #endif
 
-	combiner_init(S5P_VA_COMBINER_BASE, NULL);
+	if (!of_have_populated_dt())
+		combiner_init(S5P_VA_COMBINER_BASE, NULL);
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
@@ -568,8 +621,6 @@ void __init exynos5_init_irq(void)
 #ifdef CONFIG_OF
 	of_irq_init(exynos4_dt_irq_match);
 #endif
-	combiner_init(S5P_VA_COMBINER_BASE, NULL);
-
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
 	 * Theses parameters should be NULL and 0 because EXYNOS4
-- 
1.7.5.4

[PATCH 14/20] ARM: Exynos: Simplify the wakeup interrupt setup code

[Thomas Abraham]

Simplify the wakeup interrupt setup code in order to add irq domain
and device tree support.

Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/common.c |   32 +++++++++++---------------------
 1 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5c104d0..810f804 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -988,16 +988,14 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 
 static int __init exynos_init_irq_eint(void)
 {
-	int irq;
+	int irq, *src_int;
+	unsigned int paddr;
 
-	if (soc_is_exynos5250())
-		exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
-	else
-		exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
-
-	if (exynos_eint_base == NULL) {
+	paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : EXYNOS4_PA_GPIO2;
+	exynos_eint_base = ioremap(paddr, SZ_4K);
+	if (!exynos_eint_base) {
 		pr_err("unable to ioremap for EINT base address\n");
-		return -ENOMEM;
+		return -ENXIO;
 	}
 
 	for (irq = 0 ; irq <= 31 ; irq++) {
@@ -1008,20 +1006,12 @@ static int __init exynos_init_irq_eint(void)
 
 	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 
-	for (irq = 0 ; irq <= 15 ; irq++) {
+	for (irq = 0 ; irq <= 15; irq++) {
 		eint0_15_data[irq] = IRQ_EINT(irq);
-
-		if (soc_is_exynos5250()) {
-			irq_set_handler_data(exynos5_eint0_15_src_int[irq],
-					     &eint0_15_data[irq]);
-			irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
-						exynos_irq_eint0_15);
-		} else {
-			irq_set_handler_data(exynos4_eint0_15_src_int[irq],
-					     &eint0_15_data[irq]);
-			irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
-						exynos_irq_eint0_15);
-		}
+		src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int :
+						exynos4_eint0_15_src_int;
+		irq_set_handler_data(src_int[irq], &eint0_15_data[irq]);
+		irq_set_chained_handler(src_int[irq], exynos_irq_eint0_15);
 	}
 
 	return 0;
-- 
1.7.5.4

[PATCH 15/20] ARM: Exynos: Add irq_domain support for gpio wakeup interrupts

[Thomas Abraham]

Add a irq_domain for all the 32 gpio external wakeup interrupt sources.
Since there are users of fixed linux irq numbers of the external wakeup
interrupts, the legacy mapping is used for the irq domain. The fixups
required to use irq domain based interrupt mapping is also included.

Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Rob Herring <rob.herring@calxeda.com>
---
 arch/arm/mach-exynos/common.c                 |   67 +++++++++++++++++--------
 arch/arm/mach-exynos/include/mach/regs-gpio.h |    4 +-
 2 files changed, 48 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 810f804..0d69412 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -752,6 +752,9 @@ static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
 
+#define EXYNOS_EINT_NR 32
+static struct irq_domain *irq_domain;
+
 static inline int exynos4_irq_to_gpio(unsigned int irq)
 {
 	if (irq < IRQ_EINT(0))
@@ -842,9 +845,9 @@ static inline void exynos_irq_eint_mask(struct irq_data *data)
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-	mask |= EINT_OFFSET_BIT(data->irq);
-	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
+	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->hwirq));
+	mask |= EINT_OFFSET_BIT(data->hwirq);
+	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->hwirq));
 	spin_unlock(&eint_lock);
 }
 
@@ -853,16 +856,16 @@ static void exynos_irq_eint_unmask(struct irq_data *data)
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-	mask &= ~(EINT_OFFSET_BIT(data->irq));
-	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
+	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->hwirq));
+	mask &= ~(EINT_OFFSET_BIT(data->hwirq));
+	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->hwirq));
 	spin_unlock(&eint_lock);
 }
 
 static inline void exynos_irq_eint_ack(struct irq_data *data)
 {
-	__raw_writel(EINT_OFFSET_BIT(data->irq),
-		     EINT_PEND(exynos_eint_base, data->irq));
+	__raw_writel(EINT_OFFSET_BIT(data->hwirq),
+		     EINT_PEND(exynos_eint_base, data->hwirq));
 }
 
 static void exynos_irq_eint_maskack(struct irq_data *data)
@@ -873,7 +876,7 @@ static void exynos_irq_eint_maskack(struct irq_data *data)
 
 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
-	int offs = EINT_OFFSET(data->irq);
+	int offs = data->hwirq;
 	int shift;
 	u32 ctrl, mask;
 	u32 newvalue = 0;
@@ -908,10 +911,10 @@ static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 	mask = 0x7 << shift;
 
 	spin_lock(&eint_lock);
-	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
+	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->hwirq));
 	ctrl &= ~mask;
 	ctrl |= newvalue << shift;
-	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
+	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->hwirq));
 	spin_unlock(&eint_lock);
 
 	if (soc_is_exynos5250())
@@ -955,7 +958,7 @@ static inline void exynos_irq_demux_eint(unsigned int start)
 
 	while (status) {
 		irq = fls(status) - 1;
-		generic_handle_irq(irq + start);
+		generic_handle_irq(irq_find_mapping(irq_domain, irq + start));
 		status &= ~(1 << irq);
 	}
 }
@@ -964,8 +967,8 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_get_chip(irq);
 	chained_irq_enter(chip, desc);
-	exynos_irq_demux_eint(IRQ_EINT(16));
-	exynos_irq_demux_eint(IRQ_EINT(24));
+	exynos_irq_demux_eint(16);
+	exynos_irq_demux_eint(24);
 	chained_irq_exit(chip, desc);
 }
 
@@ -973,6 +976,7 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
 	u32 *irq_data = irq_get_handler_data(irq);
 	struct irq_chip *chip = irq_get_chip(irq);
+	int eint_irq;
 
 	chained_irq_enter(chip, desc);
 	chip->irq_mask(&desc->irq_data);
@@ -980,15 +984,28 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 	if (chip->irq_ack)
 		chip->irq_ack(&desc->irq_data);
 
-	generic_handle_irq(*irq_data);
+	eint_irq = irq_find_mapping(irq_domain, *irq_data);
+	generic_handle_irq(eint_irq);
 
 	chip->irq_unmask(&desc->irq_data);
 	chained_irq_exit(chip, desc);
 }
 
+static int exynos_eint_irq_domain_map(struct irq_domain *d, unsigned int irq,
+					irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &exynos_irq_eint, handle_level_irq);
+	set_irq_flags(irq, IRQF_VALID);
+	return 0;
+}
+
+static struct irq_domain_ops exynos_eint_irq_domain_ops = {
+	.map = exynos_eint_irq_domain_map,
+};
+
 static int __init exynos_init_irq_eint(void)
 {
-	int irq, *src_int;
+	int irq, *src_int, irq_base;
 	unsigned int paddr;
 
 	paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : EXYNOS4_PA_GPIO2;
@@ -998,16 +1015,24 @@ static int __init exynos_init_irq_eint(void)
 		return -ENXIO;
 	}
 
-	for (irq = 0 ; irq <= 31 ; irq++) {
-		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
-					 handle_level_irq);
-		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+	irq_base = irq_alloc_descs(IRQ_EINT(0), 1, EXYNOS_EINT_NR, 0);
+	if (IS_ERR_VALUE(irq_base)) {
+		irq_base = IRQ_EINT(0);
+		pr_warning("%s: irq desc alloc failed. Continuing with %d as "
+				"linux irq base\n", __func__, irq_base);
+	}
+
+	irq_domain = irq_domain_add_legacy(NULL, EXYNOS_EINT_NR, irq_base, 0,
+					 &exynos_eint_irq_domain_ops, NULL);
+	if (WARN_ON(!irq_domain)) {
+		pr_warning("%s: irq domain init failed\n", __func__);
+		return 0;
 	}
 
 	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 
 	for (irq = 0 ; irq <= 15; irq++) {
-		eint0_15_data[irq] = IRQ_EINT(irq);
+		eint0_15_data[irq] = irq;
 		src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int :
 						exynos4_eint0_15_src_int;
 		irq_set_handler_data(src_int[irq], &eint0_15_data[irq]);
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index e4b5b60..24bf4ec 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -16,13 +16,13 @@
 #include <mach/map.h>
 #include <mach/irqs.h>
 
-#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
+#define EINT_REG_NR(x)			((x) >> 3)
 #define EINT_CON(b, x)			(b + 0xE00 + (EINT_REG_NR(x) * 4))
 #define EINT_FLTCON(b, x)		(b + 0xE80 + (EINT_REG_NR(x) * 4))
 #define EINT_MASK(b, x)			(b + 0xF00 + (EINT_REG_NR(x) * 4))
 #define EINT_PEND(b, x)			(b + 0xF40 + (EINT_REG_NR(x) * 4))
 
-#define EINT_OFFSET_BIT(x)		(1 << (EINT_OFFSET(x) & 0x7))
+#define EINT_OFFSET_BIT(x)		(1 << ((x) & 0x7))
 
 /* compatibility for plat-s5p/irq-pm.c */
 #define EXYNOS4_EINT40CON		(S5P_VA_GPIO2 + 0xE00)
-- 
1.7.5.4

[PATCH 16/20] ARM: Exynos: Remove arch_initcall for wakeup interrupt initialization

[Thomas Abraham]

The of_irq_init function would be setup to invoke the exynos4_init_irq_eint
function when booting using device tree. The arch_initcall for
exynos4_init_irq_eint would duplicate its invocation in that case. Hence,
arch_initcall for exynos4_init_irq_eint is removed and this function is invoked
from the exynos4_init_irq for non-dt case.

Moreover, with single kernel image build, the exynos4_init_irq_eint has no checks
to ensure that it is running on a exynos4 platform. So it would be appropriate
to invoke it from exynos4_init_irq.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Rob Herring <rob.herring@calxeda.com>
---
 arch/arm/mach-exynos/common.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 0d69412..544f8b5 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -64,6 +64,7 @@ static void exynos4_init_clocks(int xtal);
 static void exynos5_init_clocks(int xtal);
 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
+static int exynos_init_irq_eint(void);
 
 static struct cpu_table cpu_ids[] __initdata = {
 	{
@@ -614,6 +615,7 @@ void __init exynos4_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
+	exynos_init_irq_eint();
 }
 
 void __init exynos5_init_irq(void)
@@ -627,6 +629,7 @@ void __init exynos5_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
+	exynos_init_irq_eint();
 }
 
 struct bus_type exynos_subsys = {
@@ -1041,4 +1044,3 @@ static int __init exynos_init_irq_eint(void)
 
 	return 0;
 }
-arch_initcall(exynos_init_irq_eint);
-- 
1.7.5.4

[PATCH 17/20] ARM: Exynos: Add device tree support for gpio wakeup interrupt controller

[Thomas Abraham]

Add device tree support for gpio wakeup source interrupt controller
for Exynos platforms.

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/common.c |   92 +++++++++++++++++++++++++++++++++++------
 1 files changed, 79 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 544f8b5..074508f 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -64,7 +64,8 @@ static void exynos4_init_clocks(int xtal);
 static void exynos5_init_clocks(int xtal);
 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
-static int exynos_init_irq_eint(void);
+static int exynos_init_irq_eint(struct device_node *np,
+				struct device_node *parent);
 
 static struct cpu_table cpu_ids[] __initdata = {
 	{
@@ -589,6 +590,8 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 	{ .compatible = "samsung,exynos4210-combiner",
 			.data = combiner_of_init, },
+	{ .compatible = "samsung,exynos5210-wakeup-eint-map",
+			.data = exynos_init_irq_eint, },
 	{},
 };
 #endif
@@ -606,8 +609,10 @@ void __init exynos4_init_irq(void)
 		of_irq_init(exynos4_dt_irq_match);
 #endif
 
-	if (!of_have_populated_dt())
+	if (!of_have_populated_dt()) {
 		combiner_init(S5P_VA_COMBINER_BASE, NULL);
+		exynos_init_irq_eint(NULL, NULL);
+	}
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
@@ -615,7 +620,6 @@ void __init exynos4_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
-	exynos_init_irq_eint();
 }
 
 void __init exynos5_init_irq(void)
@@ -629,7 +633,6 @@ void __init exynos5_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
-	exynos_init_irq_eint();
 }
 
 struct bus_type exynos_subsys = {
@@ -1002,17 +1005,72 @@ static int exynos_eint_irq_domain_map(struct irq_domain *d, unsigned int irq,
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static int exynos_eint_irq_domain_xlate(struct irq_domain *d,
+		struct device_node *controller, const u32 *intspec,
+		unsigned int intsize, unsigned long *out_hwirq,
+		unsigned int *out_type)
+{
+	if (d->of_node != controller)
+		return -EINVAL;
+	if (intsize < 2)
+		return -EINVAL;
+	*out_hwirq = intspec[0];
+
+	switch (intspec[1]) {
+	case S5P_IRQ_TYPE_LEVEL_LOW:
+		*out_type = IRQ_TYPE_LEVEL_LOW;
+		break;
+	case S5P_IRQ_TYPE_LEVEL_HIGH:
+		*out_type = IRQ_TYPE_LEVEL_HIGH;
+		break;
+	case S5P_IRQ_TYPE_EDGE_FALLING:
+		*out_type = IRQ_TYPE_EDGE_FALLING;
+		break;
+	case S5P_IRQ_TYPE_EDGE_RISING:
+		*out_type = IRQ_TYPE_EDGE_RISING;
+		break;
+	case S5P_IRQ_TYPE_EDGE_BOTH:
+		*out_type = IRQ_TYPE_EDGE_BOTH;
+		break;
+	};
+
+	return 0;
+}
+#else
+static int exynos_eint_irq_domain_xlate(struct irq_domain *d,
+		struct device_node *controller, const u32 *intspec,
+		unsigned int intsize, unsigned long *out_hwirq,
+		unsigned int *out_type)
+{
+	return -EINVAL;
+}
+#endif
+
 static struct irq_domain_ops exynos_eint_irq_domain_ops = {
+	.xlate = exynos_eint_irq_domain_xlate,
 	.map = exynos_eint_irq_domain_map,
 };
 
-static int __init exynos_init_irq_eint(void)
+static int __init exynos_init_irq_eint(struct device_node *eint_np,
+					struct device_node *parent)
 {
-	int irq, *src_int, irq_base;
+	int irq, *src_int, irq_base, irq_eint;
 	unsigned int paddr;
+	static unsigned int retry = 0;
+	static struct device_node *np;
 
-	paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : EXYNOS4_PA_GPIO2;
-	exynos_eint_base = ioremap(paddr, SZ_4K);
+	if (retry)
+		goto retry_init;
+
+	if (!eint_np) {
+		paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 :
+						EXYNOS4_PA_GPIO2;
+		exynos_eint_base = ioremap(paddr, SZ_4K);
+	} else {
+		np = of_get_parent(eint_np);
+		exynos_eint_base = of_iomap(np, 0);
+	}
 	if (!exynos_eint_base) {
 		pr_err("unable to ioremap for EINT base address\n");
 		return -ENXIO;
@@ -1025,21 +1083,29 @@ static int __init exynos_init_irq_eint(void)
 				"linux irq base\n", __func__, irq_base);
 	}
 
-	irq_domain = irq_domain_add_legacy(NULL, EXYNOS_EINT_NR, irq_base, 0,
+	irq_domain = irq_domain_add_legacy(np, EXYNOS_EINT_NR, irq_base, 0,
 					 &exynos_eint_irq_domain_ops, NULL);
 	if (WARN_ON(!irq_domain)) {
 		pr_warning("%s: irq domain init failed\n", __func__);
 		return 0;
 	}
 
-	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
+	irq_eint = eint_np ? irq_of_parse_and_map(np, 16) : EXYNOS_IRQ_EINT16_31;
+	irq_set_chained_handler(irq_eint, exynos_irq_demux_eint16_31);
 
-	for (irq = 0 ; irq <= 15; irq++) {
+retry_init:
+	for (irq = 0; irq <= 15; irq++) {
 		eint0_15_data[irq] = irq;
 		src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int :
 						exynos4_eint0_15_src_int;
-		irq_set_handler_data(src_int[irq], &eint0_15_data[irq]);
-		irq_set_chained_handler(src_int[irq], exynos_irq_eint0_15);
+		irq_eint = eint_np ? irq_of_parse_and_map(np, irq) : src_int[irq];
+		if (!irq_eint) {
+			of_node_put(np);
+			retry = 1;
+			return -EAGAIN;
+		}
+		irq_set_handler_data(irq_eint, &eint0_15_data[irq]);
+		irq_set_chained_handler(irq_eint, exynos_irq_eint0_15);
 	}
 
 	return 0;
-- 
1.7.5.4

[PATCH 18/20] ARM: dts: Update device tree source files for EXYNOS5250

[Thomas Abraham]

Updated EXYNOS5 device tree source files to reflect changes in rev1
of EXYNOS5 SoC. This includes new additions to the EXYNOS5 dtsi and
SMDK5250 dts files and few minor fixes.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   52 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos5250.dtsi         |   44 +++++++-----------------
 2 files changed, 65 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 399d17b..bcc4b89 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -23,4 +23,56 @@
 	chosen {
 		bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
 	};
+
+	i2c at 12C60000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-max-bus-freq = <20000>;
+		gpios = <&gpb3 0 2 3 0>,
+			<&gpb3 1 2 3 0>;
+
+		eeprom at 50 {
+			compatible = "samsung,s524ad0xd1";
+			reg = <0x50>;
+		};
+	};
+
+	i2c at 12C70000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-max-bus-freq = <20000>;
+		gpios = <&gpb3 2 2 3 0>,
+			<&gpb3 3 2 3 0>;
+
+		eeprom at 51 {
+			compatible = "samsung,s524ad0xd1";
+			reg = <0x51>;
+		};
+	};
+
+	i2c at 12C80000 {
+		status = "disabled";
+	};
+
+	i2c at 12C90000 {
+		status = "disabled";
+	};
+
+	i2c at 12CA0000 {
+		status = "disabled";
+	};
+
+	i2c at 12CB0000 {
+		status = "disabled";
+	};
+
+	i2c at 12CC0000 {
+		status = "disabled";
+	};
+
+	i2c at 12CD0000 {
+		status = "disabled";
+	};
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dfc4335..76b7dba 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,11 +23,11 @@
 	compatible = "samsung,exynos5250";
 	interrupt-parent = <&gic>;
 
-	gic:interrupt-controller at 10490000 {
+	gic:interrupt-controller at 10481000 {
 		compatible = "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
 		interrupt-controller;
-		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+		reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
 	};
 
 	watchdog {
@@ -42,30 +42,6 @@
 		interrupts = <0 43 0>, <0 44 0>;
 	};
 
-	sdhci at 12200000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12200000 0x100>;
-		interrupts = <0 75 0>;
-	};
-
-	sdhci at 12210000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12210000 0x100>;
-		interrupts = <0 76 0>;
-	};
-
-	sdhci at 12220000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12220000 0x100>;
-		interrupts = <0 77 0>;
-	};
-
-	sdhci at 12230000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12230000 0x100>;
-		interrupts = <0 78 0>;
-	};
-
 	serial at 12C00000 {
 		compatible = "samsung,exynos4210-uart";
 		reg = <0x12C00000 0x100>;
@@ -157,13 +133,13 @@
 			interrupts = <0 35 0>;
 		};
 
-		mdma0: pdma at 10800000 {
+		mdma0: mdma at 10800000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x10800000 0x1000>;
 			interrupts = <0 33 0>;
 		};
 
-		mdma1: pdma at 11C10000 {
+		mdma1: mdma at 11C10000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x11C10000 0x1000>;
 			interrupts = <0 124 0>;
@@ -242,6 +218,12 @@
 			#gpio-cells = <4>;
 		};
 
+		gpc4: gpio-controller at 114002E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114002E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
 		gpd0: gpio-controller at 11400160 {
 			compatible = "samsung,exynos4-gpio";
 			reg = <0x11400160 0x20>;
@@ -388,19 +370,19 @@
 
 		gpv2: gpio-controller at 10D10040 {
 			compatible = "samsung,exynos4-gpio";
-			reg = <0x10D10040 0x20>;
+			reg = <0x10D10060 0x20>;
 			#gpio-cells = <4>;
 		};
 
 		gpv3: gpio-controller at 10D10060 {
 			compatible = "samsung,exynos4-gpio";
-			reg = <0x10D10060 0x20>;
+			reg = <0x10D10080 0x20>;
 			#gpio-cells = <4>;
 		};
 
 		gpv4: gpio-controller at 10D10080 {
 			compatible = "samsung,exynos4-gpio";
-			reg = <0x10D10080 0x20>;
+			reg = <0x10D100C0 0x20>;
 			#gpio-cells = <4>;
 		};
 
-- 
1.7.5.4

[PATCH 19/20] ARM: Exynos5: Add combiner, wakeup interrupt controller and ethernet nodes

[Thomas Abraham]

And interrupt combiner, external interrupt wakeup interrupt controller
and smsc9215 lan controller nodes.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   11 ++++++
 arch/arm/boot/dts/exynos5250.dtsi         |   55 +++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index bcc4b89..dbc4bdb 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -24,6 +24,17 @@
 		bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
 	};
 
+	lan9215 at 0x05000000 {
+		compatible = "smsc,lan9215", "smsc,lan9115";
+		reg = <0x05000000 0x20000>;
+		interrupts = <5 0>;
+		interrupt-parent = <&wakeup_eint>;
+		phy-mode = "mii";
+		smsc,irq-push-pull;
+		smsc,force-internal-phy;
+		local-mac-address = [00 80 00 23 45 67];
+	};
+
 	i2c at 12C60000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 76b7dba..af124917 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -26,10 +26,65 @@
 	gic:interrupt-controller at 10481000 {
 		compatible = "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		#size-cells = <0>;
 		interrupt-controller;
 		reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
 	};
 
+	combiner:interrupt-controller at 10440000 {
+		compatible = "samsung,exynos4210-combiner";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		samsung,combiner-nr = <32>;
+		reg = <0x10440000 0x1000>;
+		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+			     <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+			     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+			     <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+			     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+	};
+
+	wakeup_eint: interrupt-controller at 11400000 {
+		compatible = "samsung,exynos5210-wakeup-eint";
+		reg = <0x11400000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&wakeup_map>;
+		interrupts = <0x0 0>, <0x1 0>, <0x2 0>, <0x3 0>,
+			     <0x4 0>, <0x5 0>, <0x6 0>, <0x7 0>,
+			     <0x8 0>, <0x9 0>, <0xa 0>, <0xb 0>,
+			     <0xc 0>, <0xd 0>, <0xe 0>, <0xf 0>,
+			     <0x10 0>;
+
+                wakeup_map: interrupt-map {
+			compatible = "samsung,exynos5210-wakeup-eint-map";
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 0>,
+                                        <0x1 0 &combiner 24 0>,
+                                        <0x2 0 &combiner 25 0>,
+                                        <0x3 0 &combiner 25 1>,
+                                        <0x4 0 &combiner 26 0>,
+                                        <0x5 0 &combiner 26 1>,
+                                        <0x6 0 &combiner 27 0>,
+                                        <0x7 0 &combiner 27 1>,
+                                        <0x8 0 &combiner 28 0>,
+                                        <0x9 0 &combiner 28 1>,
+                                        <0xa 0 &combiner 29 0>,
+                                        <0xb 0 &combiner 29 1>,
+                                        <0xc 0 &combiner 30 0>,
+                                        <0xd 0 &combiner 30 1>,
+                                        <0xe 0 &combiner 31 0>,
+                                        <0xf 0 &combiner 31 1>,
+                                        <0x10 0 &gic 0 32 0>;
+                };
+        };
+
 	watchdog {
 		compatible = "samsung,s3c2410-wdt";
 		reg = <0x101D0000 0x100>;
-- 
1.7.5.4

[PATCH 20/20] ARM: Exynos5: Add AUXDATA for i2c controllers

[Thomas Abraham]

Use AUXDATA to set the device names for controller instances discovered
from device tree.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/mach-exynos5-dt.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 4711c89..cf5d222 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -43,6 +43,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"exynos4210-uart.2", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 				"exynos4210-uart.3", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
+				"s3c2440-i2c.0", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
+				"s3c2440-i2c.1", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
-- 
1.7.5.4

[PATCH 19/20] ARM: Exynos5: Add combiner, wakeup interrupt controller and ethernet nodes

[Olof Johansson]

Hi,

[adding devicetree-discuss]

On Mon, Apr 30, 2012 at 12:14 PM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> And interrupt combiner, external interrupt wakeup interrupt controller
> and smsc9215 lan controller nodes.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> ?arch/arm/boot/dts/exynos5250-smdk5250.dts | ? 11 ++++++
> ?arch/arm/boot/dts/exynos5250.dtsi ? ? ? ? | ? 55 +++++++++++++++++++++++++++++
> ?2 files changed, 66 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index bcc4b89..dbc4bdb 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -24,6 +24,17 @@
> ? ? ? ? ? ? ? ?bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
> ? ? ? ?};
>
> + ? ? ? lan9215 at 0x05000000 {
> + ? ? ? ? ? ? ? compatible = "smsc,lan9215", "smsc,lan9115";
> + ? ? ? ? ? ? ? reg = <0x05000000 0x20000>;
> + ? ? ? ? ? ? ? interrupts = <5 0>;
> + ? ? ? ? ? ? ? interrupt-parent = <&wakeup_eint>;
> + ? ? ? ? ? ? ? phy-mode = "mii";
> + ? ? ? ? ? ? ? smsc,irq-push-pull;
> + ? ? ? ? ? ? ? smsc,force-internal-phy;
> + ? ? ? ? ? ? ? local-mac-address = [00 80 00 23 45 67];
> + ? ? ? };
> +

since the 911x sits on a chipselect bus, you should instead add that
bus to the dtsi and define this on that bus.

Something like this in the dtsi:

       sromc-bus {
               #address-cells = <2>;
               #size-cells = <1>;
               ranges = < 0 0 0x04000000 0x20000
                          1 0 0x05000000 0x20000
                          2 0 0x06000000 0x20000
                          3 0 0x07000000 0x20000>;
       };

and in the dts:

       sromc-bus {
               lan9215 at 1,0 {
                       compatible = "smsc,lan9215", "smsc,lan9115";
                       reg = <1 0 0x20000>;
                       interrupts = <5 0>;
                       interrupt-parent = <&wakeup_eint>;
                       phy-mode = "mii";
                       smsc,irq-push-pull;
                       smsc,force-internal-phy;
                       local-mac-address = [00 80 00 23 45 67];
               };
        };


(You might be able to do just fine with one address cell, I'm not 100%
sure why Grant's example uses two, but I used the same above for
consistency).

Also, I don't think it's a good idea to hardcode the mac address in
the dts like this; have u-boot fill it in from the environment
variable there instead, if needed.



-Olof

[PATCH 18/20] ARM: dts: Update device tree source files for EXYNOS5250

[Olof Johansson]

Hi,

On Mon, Apr 30, 2012 at 12:14 PM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> Updated EXYNOS5 device tree source files to reflect changes in rev1
> of EXYNOS5 SoC. This includes new additions to the EXYNOS5 dtsi and
> SMDK5250 dts files and few minor fixes.
>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
> ?arch/arm/boot/dts/exynos5250-smdk5250.dts | ? 52 +++++++++++++++++++++++++++++
> ?arch/arm/boot/dts/exynos5250.dtsi ? ? ? ? | ? 44 +++++++-----------------
> ?2 files changed, 65 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 399d17b..bcc4b89 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -23,4 +23,56 @@
> ? ? ? ?chosen {
> ? ? ? ? ? ? ? ?bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
> ? ? ? ?};
> +
> + ? ? ? i2c at 12C60000 {
> + ? ? ? ? ? ? ? #address-cells = <1>;
> + ? ? ? ? ? ? ? #size-cells = <0>;

Two nits:

#a-c and #s-c is likely to always be 1/0, so you might as well move
these to the dtsi file for the SoC.

Also, we tend to use non-caps here and in other locations (so it
should be 12c60000 here).


-Olof

[PATCH 07/20] ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

[Kukjin Kim]

Thomas Abraham wrote:
> 
> From: Kisoo Yu <ksoo.yu@samsung.com>
> 
> The fout clock of BPLL and MPLL have a selectable source in rev1 of
> EXYNOS5. The clock options are a fixed divided by 2 clock and the
> output of the PLL itself. Add support for these new clock instances.
> 
> Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> [kgene.kim at samsung.com: temporary apply this because I
> don't want to add pll stuff in each clock not commonly]

As I commented, I won't apply this because pll stuff should be added in
common file such as plat-s5p/clock.c even though the plat-s5p files moved
into plat-samsung.

> Temporary-Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

No. I didn't sign on this in my topic branch.

> ---
>  arch/arm/mach-exynos/clock-exynos5.c           |   73
> +++++++++++++++++++++++-
>  arch/arm/mach-exynos/include/mach/regs-clock.h |    2 +
>  arch/arm/plat-s5p/clock.c                      |   11 ----
>  3 files changed, 74 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-
> exynos/clock-exynos5.c
> index 846741e..7c0f810 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -145,6 +145,39 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
>  	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
>  };
> 
> +static struct clk clk_fout_bpll_div2 = {
> +	.name	= "fout_bpll_div2",
> +};
> +
> +static struct clk *exynos5_clkset_mout_bpll_fout_list[] = {
> +	[0] = &clk_fout_bpll_div2,
> +	[1] = &clk_fout_bpll,
> +};
> +
> +static struct clksrc_sources exynos5_clkset_mout_bpll_fout = {
> +	.sources	= exynos5_clkset_mout_bpll_fout_list,
> +	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_bpll_fout_list),
> +};
> +
> +static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
> +	.clk	= {
> +		.name		= "mout_bpll_fout",
> +	},
> +	.sources = &exynos5_clkset_mout_bpll_fout,
> +	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
> +};
> +
> +/* Possible clock sources for BPLL Mux */
> +static struct clk *clk_src_bpll_list[] = {
> +	[0] = &clk_fin_bpll,
> +	[1] = &exynos5_clk_mout_bpll_fout.clk,
> +};
> +
> +struct clksrc_sources clk_src_bpll = {
> +	.sources	= clk_src_bpll_list,
> +	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
> +};
> +
>  static struct clksrc_clk exynos5_clk_mout_bpll = {
>  	.clk	= {
>  		.name		= "mout_bpll",
> @@ -187,11 +220,43 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
>  	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
>  };
> 
> +static struct clk clk_fout_mpll_div2 = {
> +	.name	= "fout_mpll_div2",
> +};
> +
> +static struct clk *exynos5_clkset_mout_mpll_fout_list[] = {
> +	[0] = &clk_fout_mpll_div2,
> +	[1] = &clk_fout_mpll,
> +};
> +
> +static struct clksrc_sources exynos5_clkset_mout_mpll_fout = {
> +	.sources	= exynos5_clkset_mout_mpll_fout_list,
> +	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_mpll_fout_list),
> +};
> +
> +static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
> +	.clk	= {
> +		.name		= "mout_mpll_fout",
> +	},
> +	.sources = &exynos5_clkset_mout_mpll_fout,
> +	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
> +};
> +
> +static struct clk *exynos5_clk_src_mpll_list[] = {
> +	[0] = &clk_fin_mpll,
> +	[1] = &exynos5_clk_mout_mpll_fout.clk,
> +};
> +
> +struct clksrc_sources exynos5_clk_src_mpll = {
> +	.sources	= exynos5_clk_src_mpll_list,
> +	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_mpll_list),
> +};
> +
>  struct clksrc_clk exynos5_clk_mout_mpll = {
>  	.clk = {
>  		.name		= "mout_mpll",
>  	},
> -	.sources = &clk_src_mpll,
> +	.sources = &exynos5_clk_src_mpll,
>  	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
>  };
> 
> @@ -946,10 +1011,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
>  	&exynos5_clk_mout_apll,
>  	&exynos5_clk_sclk_apll,
>  	&exynos5_clk_mout_bpll,
> +	&exynos5_clk_mout_bpll_fout,
>  	&exynos5_clk_mout_bpll_user,
>  	&exynos5_clk_mout_cpll,
>  	&exynos5_clk_mout_epll,
>  	&exynos5_clk_mout_mpll,
> +	&exynos5_clk_mout_mpll_fout,
>  	&exynos5_clk_mout_mpll_user,
>  	&exynos5_clk_vpllsrc,
>  	&exynos5_clk_sclk_vpll,
> @@ -1013,6 +1080,8 @@ static struct clk *exynos5_clks[] __initdata = {
>  	&exynos5_clk_sclk_hdmi27m,
>  	&exynos5_clk_sclk_hdmiphy,
>  	&clk_fout_bpll,
> +	&clk_fout_bpll_div2,
> +	&clk_fout_mpll_div2,
>  	&clk_fout_cpll,
>  	&exynos5_clk_armclk,
>  };
> @@ -1178,8 +1247,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
> 
>  	clk_fout_apll.ops = &exynos5_fout_apll_ops;
>  	clk_fout_bpll.rate = bpll;
> +	clk_fout_bpll_div2.rate = bpll >> 1;
>  	clk_fout_cpll.rate = cpll;
>  	clk_fout_mpll.rate = mpll;
> +	clk_fout_mpll_div2.rate = mpll >> 1;
>  	clk_fout_epll.rate = epll;
>  	clk_fout_vpll.rate = vpll;
> 
> diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h
> b/arch/arm/mach-exynos/include/mach/regs-clock.h
> index d9578a5..130034d 100644
> --- a/arch/arm/mach-exynos/include/mach/regs-clock.h
> +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
> @@ -313,6 +313,8 @@
>  #define EXYNOS5_CLKGATE_IP_PERIS		EXYNOS_CLKREG(0x10960)
>  #define EXYNOS5_CLKGATE_BLOCK
EXYNOS_CLKREG(0x10980)
> 
> +#define EXYNOS5_PLL_DIV2_SEL			EXYNOS_CLKREG(0x20A24)
> +
>  #define EXYNOS5_BPLL_CON0			EXYNOS_CLKREG(0x20110)
>  #define EXYNOS5_CLKSRC_CDREX			EXYNOS_CLKREG(0x20200)
>  #define EXYNOS5_CLKDIV_CDREX			EXYNOS_CLKREG(0x20500)
> diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
> index f68a9bb..bea0907 100644
> --- a/arch/arm/plat-s5p/clock.c
> +++ b/arch/arm/plat-s5p/clock.c
> @@ -115,17 +115,6 @@ struct clksrc_sources clk_src_apll = {
>  	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
>  };
> 
> -/* Possible clock sources for BPLL Mux */
> -static struct clk *clk_src_bpll_list[] = {
> -	[0] = &clk_fin_bpll,
> -	[1] = &clk_fout_bpll,
> -};
> -
> -struct clksrc_sources clk_src_bpll = {
> -	.sources	= clk_src_bpll_list,
> -	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
> -};
> -
>  /* Possible clock sources for CPLL Mux */
>  static struct clk *clk_src_cpll_list[] = {
>  	[0] = &clk_fin_cpll,
> --
> 1.7.5.4

[PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0

[Kukjin Kim]

Thomas Abraham wrote:
> 
> This patch series adds support for Samsung's Exynos5250 Rev1.0. It
> includes
> fixes for device tree support, updates for rev1.0 silicon and device tree
> discovery for combiner and wakeup interrupt controller. This patch series
> depricates the existing support for Exynos5250 Rev0.0.
> 
> This patchset is based and tested on top of v3.4-rc5.
> 
> Boojin Kim (1):
>   ARM: EXYNOS: Support DMA for EXYNOS5250 SoC
> 
> Changhwan Youn (2):
>   ARM: EXYNOS: Modify the GIC physical address for static io-mapping
>   ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
> 
> Kisoo Yu (1):
>   ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
> 
> Kukjin Kim (2):
>   ARM: EXYNOS: fix ctrlbit for exynos5_clk_pdma1
>   ARM: EXYNOS: update irqs for EXYNOS5250 evt1
> 
> Sangsu Park (1):
>   ARM: EXYNOS: add GPC4 bank instance
> 
> Thomas Abraham (13):
>   ARM: EXYNOS: Add watchdog timer clock instance
>   ARM: Exynos: Remove a new bus_type instance for Exynos5
>   of/irq: fix interrupt parent lookup procedure
>   of/irq: add retry support for interrupt controller tree initialization
>   ARM: Exynos: Add irq_domain support for interrupt combiner
>   ARM: Exynos: Add device tree support for interrupt combiner
>   ARM: Exynos: Simplify the wakeup interrupt setup code
>   ARM: Exynos: Add irq_domain support for gpio wakeup interrupts
>   ARM: Exynos: Remove arch_initcall for wakeup interrupt initialization
>   ARM: Exynos: Add device tree support for gpio wakeup interrupt
> controller
>   ARM: dts: Update device tree source files for EXYNOS5250
>   ARM: Exynos5: Add combiner, wakeup interrupt controller and ethernet
> nodes
>   ARM: Exynos5: Add AUXDATA for i2c controllers
> 
>  .../bindings/arm/samsung/interrupt-combiner.txt    |   52 +++
>  arch/arm/boot/dts/exynos5250-smdk5250.dts          |   63 ++++
>  arch/arm/boot/dts/exynos5250.dtsi                  |   99 ++++--
>  arch/arm/mach-exynos/Kconfig                       |    7 +-
>  arch/arm/mach-exynos/Makefile                      |    2 +-
>  arch/arm/mach-exynos/clock-exynos5.c               |   80 +++++-
>  arch/arm/mach-exynos/common.c                      |  338
++++++++++++++------
>  arch/arm/mach-exynos/dma.c                         |  129 +++++++--
>  arch/arm/mach-exynos/include/mach/gpio.h           |    9 +-
>  arch/arm/mach-exynos/include/mach/irqs.h           |   40 ++-
>  arch/arm/mach-exynos/include/mach/map.h            |    4 +-
>  arch/arm/mach-exynos/include/mach/regs-clock.h     |    2 +
>  arch/arm/mach-exynos/include/mach/regs-gpio.h      |    4 +-
>  arch/arm/mach-exynos/mach-exynos5-dt.c             |    4 +
>  arch/arm/mach-exynos/mct.c                         |   17 +-
>  arch/arm/mach-exynos/pm.c                          |    2 +-
>  arch/arm/plat-s5p/clock.c                          |   11 -
>  arch/arm/plat-samsung/Kconfig                      |    2 +-
>  arch/arm/plat-samsung/include/plat/cpu.h           |    2 +-
>  arch/arm/plat-samsung/include/plat/dma-pl330.h     |    1 +
>  drivers/gpio/gpio-samsung.c                        |   11 +-
>  drivers/of/irq.c                                   |   29 ++-
>  22 files changed, 698 insertions(+), 210 deletions(-)
>  create mode 100644
> Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
> 
> --
> 1.7.5.4

Hi,

Basically, it's ok to me on 1st~9th patches except #7 as I commented. Will
apply them but need to update #7. And I will look at the others again. If
any comments, let you know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 07/20] ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

[Kukjin Kim]

Kukjin Kim wrote:
> 
> Thomas Abraham wrote:
> >
> > From: Kisoo Yu <ksoo.yu@samsung.com>
> >
> > The fout clock of BPLL and MPLL have a selectable source in rev1 of
> > EXYNOS5. The clock options are a fixed divided by 2 clock and the
> > output of the PLL itself. Add support for these new clock instances.
> >
> > Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com>
> > Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> > [kgene.kim at samsung.com: temporary apply this because I
> > don't want to add pll stuff in each clock not commonly]
> 
> As I commented, I won't apply this because pll stuff should be added in
> common file such as plat-s5p/clock.c even though the plat-s5p files moved
> into plat-samsung.
> 
I updated this myself. See below and if any problems, please let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

From: Kisoo Yu <ksoo.yu@samsung.com>
Subject: [PATCH] ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250.
The clock options are a fixed divided by 2 clock and the output of the
PLL itself. Add support for these new clock instances.

Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
[kgene.kim at samsung.com: moved common pll stuff into s5p-clock.c]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos/clock-exynos5.c           |   46 ++++++++++++++++++++++-
 arch/arm/mach-exynos/include/mach/regs-clock.h |    2 +
 arch/arm/plat-samsung/include/plat/s5p-clock.h |    4 ++
 arch/arm/plat-samsung/s5p-clock.c              |   30 +++++++++++++++
 4 files changed, 80 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 3c1af23..22b2e8a 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
 	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+	.clk	= {
+		.name		= "mout_bpll_fout",
+	},
+	.sources = &clk_src_bpll_fout,
+	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_list[] = {
+	[0] = &clk_fin_bpll,
+	[1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll = {
+	.sources	= exynos5_clk_src_bpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_bpll_list),
+};
+
 static struct clksrc_clk exynos5_clk_mout_bpll = {
 	.clk	= {
 		.name		= "mout_bpll",
 	},
-	.sources = &clk_src_bpll,
+	.sources = &exynos5_clk_src_bpll,
 	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 };
 
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
 	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+	.clk	= {
+		.name		= "mout_mpll_fout",
+	},
+	.sources = &clk_src_mpll_fout,
+	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_mpll_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll = {
+	.sources	= exynos5_clk_src_mpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_mpll_list),
+};
+
 struct clksrc_clk exynos5_clk_mout_mpll = {
 	.clk = {
 		.name		= "mout_mpll",
 	},
-	.sources = &clk_src_mpll,
+	.sources = &exynos5_clk_src_mpll,
 	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 };
 
@@ -1036,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
 	&exynos5_clk_mout_apll,
 	&exynos5_clk_sclk_apll,
 	&exynos5_clk_mout_bpll,
+	&exynos5_clk_mout_bpll_fout,
 	&exynos5_clk_mout_bpll_user,
 	&exynos5_clk_mout_cpll,
 	&exynos5_clk_mout_epll,
 	&exynos5_clk_mout_mpll,
+	&exynos5_clk_mout_mpll_fout,
 	&exynos5_clk_mout_mpll_user,
 	&exynos5_clk_vpllsrc,
 	&exynos5_clk_sclk_vpll,
@@ -1103,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = {
 	&exynos5_clk_sclk_hdmi27m,
 	&exynos5_clk_sclk_hdmiphy,
 	&clk_fout_bpll,
+	&clk_fout_bpll_div2,
 	&clk_fout_cpll,
+	&clk_fout_mpll_div2,
 	&exynos5_clk_armclk,
 };
 
@@ -1268,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
 
 	clk_fout_apll.ops = &exynos5_fout_apll_ops;
 	clk_fout_bpll.rate = bpll;
+	clk_fout_bpll_div2.rate = bpll >> 1;
 	clk_fout_cpll.rate = cpll;
 	clk_fout_mpll.rate = mpll;
+	clk_fout_mpll_div2.rate = mpll >> 1;
 	clk_fout_epll.rate = epll;
 	clk_fout_vpll.rate = vpll;
 
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 7395236..1acf660 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -316,6 +316,8 @@
 #define EXYNOS5_CLKSRC_CDREX			EXYNOS_CLKREG(0x20200)
 #define EXYNOS5_CLKDIV_CDREX			EXYNOS_CLKREG(0x20500)
 
+#define EXYNOS5_PLL_DIV2_SEL			EXYNOS_CLKREG(0x20A24)
+
 #define EXYNOS5_EPLL_LOCK			EXYNOS_CLKREG(0x10030)
 
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT		(29)
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 1de4b32..8364b4b 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -32,8 +32,10 @@ extern struct clk clk_48m;
 extern struct clk s5p_clk_27m;
 extern struct clk clk_fout_apll;
 extern struct clk clk_fout_bpll;
+extern struct clk clk_fout_bpll_div2;
 extern struct clk clk_fout_cpll;
 extern struct clk clk_fout_mpll;
+extern struct clk clk_fout_mpll_div2;
 extern struct clk clk_fout_epll;
 extern struct clk clk_fout_dpll;
 extern struct clk clk_fout_vpll;
@@ -42,8 +44,10 @@ extern struct clk clk_vpll;
 
 extern struct clksrc_sources clk_src_apll;
 extern struct clksrc_sources clk_src_bpll;
+extern struct clksrc_sources clk_src_bpll_fout;
 extern struct clksrc_sources clk_src_cpll;
 extern struct clksrc_sources clk_src_mpll;
+extern struct clksrc_sources clk_src_mpll_fout;
 extern struct clksrc_sources clk_src_epll;
 extern struct clksrc_sources clk_src_dpll;
 
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c
index 41d3dfd..031a618 100644
--- a/arch/arm/plat-samsung/s5p-clock.c
+++ b/arch/arm/plat-samsung/s5p-clock.c
@@ -67,6 +67,11 @@ struct clk clk_fout_bpll = {
 	.id		= -1,
 };
 
+struct clk clk_fout_bpll_div2 = {
+	.name		= "fout_bpll_div2",
+	.id		= -1,
+};
+
 /* CPLL clock output */
 
 struct clk clk_fout_cpll = {
@@ -82,6 +87,11 @@ struct clk clk_fout_mpll = {
 	.id		= -1,
 };
 
+struct clk clk_fout_mpll_div2 = {
+	.name		= "fout_mpll_div2",
+	.id		= -1,
+};
+
 /* EPLL clock output */
 struct clk clk_fout_epll = {
 	.name		= "fout_epll",
@@ -125,6 +135,16 @@ struct clksrc_sources clk_src_bpll = {
 	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
 };
 
+static struct clk *clk_src_bpll_fout_list[] = {
+	[0] = &clk_fout_bpll_div2,
+	[1] = &clk_fout_bpll,
+};
+
+struct clksrc_sources clk_src_bpll_fout = {
+	.sources	= clk_src_bpll_fout_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_bpll_fout_list),
+};
+
 /* Possible clock sources for CPLL Mux */
 static struct clk *clk_src_cpll_list[] = {
 	[0] = &clk_fin_cpll,
@@ -147,6 +167,16 @@ struct clksrc_sources clk_src_mpll = {
 	.nr_sources	= ARRAY_SIZE(clk_src_mpll_list),
 };
 
+static struct clk *clk_src_mpll_fout_list[] = {
+	[0] = &clk_fout_mpll_div2,
+	[1] = &clk_fout_mpll,
+};
+
+struct clksrc_sources clk_src_mpll_fout = {
+	.sources	= clk_src_mpll_fout_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_mpll_fout_list),
+};
+
 /* Possible clock sources for EPLL Mux */
 static struct clk *clk_src_epll_list[] = {
 	[0] = &clk_fin_epll,
-- 
1.7.1

[PATCH 10/20] of/irq: fix interrupt parent lookup procedure

[Kukjin Kim]

Thomas Abraham wrote:
> 
> The interrupt parent lookup fails for a node that is a interrupt-controller
> but does not have an explict interrupt-parent property and instead inherits
> this property from the root node.
> 
> Consider the nodes listed below.
> 
>     / {
>         interrupt-parent = <&intc_level1>;
> 
>         intc_level1: interrupt-controller at xxx {
>                 interrupt-controller;
>                 #interrupt-cells = <3>;
>                 <rest of the properties here>;
>         };
> 
>         intc_level2: interrupt-controller at yyy {
>                 interrupt-controller;
>                 #interrupt-cells = <2>;
>                 <rest of the properties here>;
>         };
>     };
> 
> The interrupt parent lookup for interrupt-controller at yyy fails. It inherits
> the interrupt-parent property from the root node and the root node ('/')
> specifies a 'interrupt-parent' property which represents the default interrupt
> root controller. But, the property '#interrupt-cells' might not be specified
> in the root node.
> 
> In case a interrupt controller node does not include a 'interrupt-parent'
> property but inherits that property from the root node, the check for
> 'interrupt-cells' property in the root node fails. Fix this removing the
> check for 'interrupt-cells' property.
> 
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
>  drivers/of/irq.c |    4 +++-
>  1 files changed, 3 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/of/irq.c b/drivers/of/irq.c
> index 9cf0060..a520363 100644
> --- a/drivers/of/irq.c
> +++ b/drivers/of/irq.c
> @@ -66,14 +66,16 @@ struct device_node *of_irq_find_parent(struct device_node *child)
>  		if (parp == NULL)
>  			p = of_get_parent(child);
>  		else {
> +			of_node_put(child);
>  			if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
>  				p = of_node_get(of_irq_dflt_pic);
>  			else
>  				p = of_find_node_by_phandle(be32_to_cpup(parp));
> +			return p;
>  		}
>  		of_node_put(child);
>  		child = p;
> -	} while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL);
> +	} while (p);
> 
>  	return p;
>  }
> --
> 1.7.5.4

Hi Grant and Rob,

I'm ok on this and this patch and #11 patch in this series are required for patches that add device tree based support for wakeup
interrupts on EXYNOS5250.

So could you have a look at this patch and let us know if this is okay or any rework is required.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0

[Kukjin Kim]

Kukjin Kim wrote:
> 
> Thomas Abraham wrote:
> >
> > This patch series adds support for Samsung's Exynos5250 Rev1.0. It
> > includes
> > fixes for device tree support, updates for rev1.0 silicon and device tree
> > discovery for combiner and wakeup interrupt controller. This patch series
> > depricates the existing support for Exynos5250 Rev0.0.
> >
> > This patchset is based and tested on top of v3.4-rc5.
> >
> > Boojin Kim (1):
> >   ARM: EXYNOS: Support DMA for EXYNOS5250 SoC
> >
> > Changhwan Youn (2):
> >   ARM: EXYNOS: Modify the GIC physical address for static io-mapping
> >   ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
> >
> > Kisoo Yu (1):
> >   ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
> >
> > Kukjin Kim (2):
> >   ARM: EXYNOS: fix ctrlbit for exynos5_clk_pdma1
> >   ARM: EXYNOS: update irqs for EXYNOS5250 evt1
> >
> > Sangsu Park (1):
> >   ARM: EXYNOS: add GPC4 bank instance
> >
> > Thomas Abraham (13):
> >   ARM: EXYNOS: Add watchdog timer clock instance
> >   ARM: Exynos: Remove a new bus_type instance for Exynos5
> >   of/irq: fix interrupt parent lookup procedure
> >   of/irq: add retry support for interrupt controller tree initialization
> >   ARM: Exynos: Add irq_domain support for interrupt combiner
> >   ARM: Exynos: Add device tree support for interrupt combiner
> >   ARM: Exynos: Simplify the wakeup interrupt setup code
> >   ARM: Exynos: Add irq_domain support for gpio wakeup interrupts
> >   ARM: Exynos: Remove arch_initcall for wakeup interrupt initialization
> >   ARM: Exynos: Add device tree support for gpio wakeup interrupt
> > controller
> >   ARM: dts: Update device tree source files for EXYNOS5250
> >   ARM: Exynos5: Add combiner, wakeup interrupt controller and ethernet
> > nodes
> >   ARM: Exynos5: Add AUXDATA for i2c controllers
> >
> >  .../bindings/arm/samsung/interrupt-combiner.txt    |   52 +++
> >  arch/arm/boot/dts/exynos5250-smdk5250.dts          |   63 ++++
> >  arch/arm/boot/dts/exynos5250.dtsi                  |   99 ++++--
> >  arch/arm/mach-exynos/Kconfig                       |    7 +-
> >  arch/arm/mach-exynos/Makefile                      |    2 +-
> >  arch/arm/mach-exynos/clock-exynos5.c               |   80 +++++-
> >  arch/arm/mach-exynos/common.c                      |  338 ++++++++++++++------
> >  arch/arm/mach-exynos/dma.c                         |  129 +++++++--
> >  arch/arm/mach-exynos/include/mach/gpio.h           |    9 +-
> >  arch/arm/mach-exynos/include/mach/irqs.h           |   40 ++-
> >  arch/arm/mach-exynos/include/mach/map.h            |    4 +-
> >  arch/arm/mach-exynos/include/mach/regs-clock.h     |    2 +
> >  arch/arm/mach-exynos/include/mach/regs-gpio.h      |    4 +-
> >  arch/arm/mach-exynos/mach-exynos5-dt.c             |    4 +
> >  arch/arm/mach-exynos/mct.c                         |   17 +-
> >  arch/arm/mach-exynos/pm.c                          |    2 +-
> >  arch/arm/plat-s5p/clock.c                          |   11 -
> >  arch/arm/plat-samsung/Kconfig                      |    2 +-
> >  arch/arm/plat-samsung/include/plat/cpu.h           |    2 +-
> >  arch/arm/plat-samsung/include/plat/dma-pl330.h     |    1 +
> >  drivers/gpio/gpio-samsung.c                        |   11 +-
> >  drivers/of/irq.c                                   |   29 ++-
> >  22 files changed, 698 insertions(+), 210 deletions(-)
> >  create mode 100644
> > Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
> >
> > --
> > 1.7.5.4
> 
> Hi,
> 
> Basically, it's ok to me on 1st~9th patches except #7 as I commented. Will apply them but need to
> update #7. And I will look at the others again. If any comments, let you know.
> 
Hi,

Looks ok to me but some patches, #10 and #11 patches need to get the ack from Grant. And the #14 to #17 and #19 patches have a
dependency on that. However now other patches which are including my re-work can be applied, so I will.

Thomas, please address comments from Olof on 18th patch.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0

[Thomas Abraham]

On 15 May 2012 14:11, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Hi,
>
> Looks ok to me but some patches, #10 and #11 patches need to get the ack from Grant. And the #14 to #17 and #19 patches have a
> dependency on that. However now other patches which are including my re-work can be applied, so I will.
>
> Thomas, please address comments from Olof on 18th patch.

Dear Mr. Kim,

Thanks for reviewing Exynos5250 EVT1 patches. I will rework patch 18th
patch as per Olof's comment and resubmit.

Thanks,
Thomas.

[PATCH 18/20] ARM: dts: Update device tree source files for EXYNOS5250

[Thomas Abraham]

On 3 May 2012 01:25, Olof Johansson <olof@lixom.net> wrote:
> Hi,
>
> On Mon, Apr 30, 2012 at 12:14 PM, Thomas Abraham
> <thomas.abraham@linaro.org> wrote:
>> Updated EXYNOS5 device tree source files to reflect changes in rev1
>> of EXYNOS5 SoC. This includes new additions to the EXYNOS5 dtsi and
>> SMDK5250 dts files and few minor fixes.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
>> ---
>> ?arch/arm/boot/dts/exynos5250-smdk5250.dts | ? 52 +++++++++++++++++++++++++++++
>> ?arch/arm/boot/dts/exynos5250.dtsi ? ? ? ? | ? 44 +++++++-----------------
>> ?2 files changed, 65 insertions(+), 31 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> index 399d17b..bcc4b89 100644
>> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> @@ -23,4 +23,56 @@
>> ? ? ? ?chosen {
>> ? ? ? ? ? ? ? ?bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
>> ? ? ? ?};
>> +
>> + ? ? ? i2c at 12C60000 {
>> + ? ? ? ? ? ? ? #address-cells = <1>;
>> + ? ? ? ? ? ? ? #size-cells = <0>;
>
> Two nits:
>
> #a-c and #s-c is likely to always be 1/0, so you might as well move
> these to the dtsi file for the SoC.

This is fixed.

>
> Also, we tend to use non-caps here and in other locations (so it
> should be 12c60000 here).

The dtsi file uses 'C' instead of 'c'. So any change here in dts file
would require a change in the dtsi file as well. So adding this change
in this patch does not seem correct. So I will not do this change for
now.

Thanks,
Thomas.

>
>
> -Olof

[PATCH v2 18/20] ARM: dts: Update device tree source files for EXYNOS5250

[Thomas Abraham]

Update EXYNOS5 device tree source files to reflect changes in rev1
of EXYNOS5 SoC. This includes new additions to the EXYNOS5 dtsi and
SMDK5250 dts files and few minor fixes.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   48 +++++++++++++++++++++++
 arch/arm/boot/dts/exynos5250.dtsi         |   60 ++++++++++++++---------------
 2 files changed, 77 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 399d17b..49945cc 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -23,4 +23,52 @@
 	chosen {
 		bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
 	};
+
+	i2c at 12C60000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-max-bus-freq = <20000>;
+		gpios = <&gpb3 0 2 3 0>,
+			<&gpb3 1 2 3 0>;
+
+		eeprom at 50 {
+			compatible = "samsung,s524ad0xd1";
+			reg = <0x50>;
+		};
+	};
+
+	i2c at 12C70000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-max-bus-freq = <20000>;
+		gpios = <&gpb3 2 2 3 0>,
+			<&gpb3 3 2 3 0>;
+
+		eeprom at 51 {
+			compatible = "samsung,s524ad0xd1";
+			reg = <0x51>;
+		};
+	};
+
+	i2c at 12C80000 {
+		status = "disabled";
+	};
+
+	i2c at 12C90000 {
+		status = "disabled";
+	};
+
+	i2c at 12CA0000 {
+		status = "disabled";
+	};
+
+	i2c at 12CB0000 {
+		status = "disabled";
+	};
+
+	i2c at 12CC0000 {
+		status = "disabled";
+	};
+
+	i2c at 12CD0000 {
+		status = "disabled";
+	};
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dfc4335..5ca0cdb 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,11 +23,11 @@
 	compatible = "samsung,exynos5250";
 	interrupt-parent = <&gic>;
 
-	gic:interrupt-controller at 10490000 {
+	gic:interrupt-controller at 10481000 {
 		compatible = "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
 		interrupt-controller;
-		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+		reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
 	};
 
 	watchdog {
@@ -42,30 +42,6 @@
 		interrupts = <0 43 0>, <0 44 0>;
 	};
 
-	sdhci at 12200000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12200000 0x100>;
-		interrupts = <0 75 0>;
-	};
-
-	sdhci at 12210000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12210000 0x100>;
-		interrupts = <0 76 0>;
-	};
-
-	sdhci at 12220000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12220000 0x100>;
-		interrupts = <0 77 0>;
-	};
-
-	sdhci at 12230000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12230000 0x100>;
-		interrupts = <0 78 0>;
-	};
-
 	serial at 12C00000 {
 		compatible = "samsung,exynos4210-uart";
 		reg = <0x12C00000 0x100>;
@@ -94,48 +70,64 @@
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x12C60000 0x100>;
 		interrupts = <0 56 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 	};
 
 	i2c at 12C70000 {
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x12C70000 0x100>;
 		interrupts = <0 57 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 	};
 
 	i2c at 12C80000 {
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x12C80000 0x100>;
 		interrupts = <0 58 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 	};
 
 	i2c at 12C90000 {
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x12C90000 0x100>;
 		interrupts = <0 59 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 	};
 
 	i2c at 12CA0000 {
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x12CA0000 0x100>;
 		interrupts = <0 60 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 	};
 
 	i2c at 12CB0000 {
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x12CB0000 0x100>;
 		interrupts = <0 61 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 	};
 
 	i2c at 12CC0000 {
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x12CC0000 0x100>;
 		interrupts = <0 62 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 	};
 
 	i2c at 12CD0000 {
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x12CD0000 0x100>;
 		interrupts = <0 63 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 	};
 
 	amba {
@@ -157,13 +149,13 @@
 			interrupts = <0 35 0>;
 		};
 
-		mdma0: pdma at 10800000 {
+		mdma0: mdma at 10800000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x10800000 0x1000>;
 			interrupts = <0 33 0>;
 		};
 
-		mdma1: pdma at 11C10000 {
+		mdma1: mdma at 11C10000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x11C10000 0x1000>;
 			interrupts = <0 124 0>;
@@ -242,6 +234,12 @@
 			#gpio-cells = <4>;
 		};
 
+		gpc4: gpio-controller at 114002E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114002E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
 		gpd0: gpio-controller at 11400160 {
 			compatible = "samsung,exynos4-gpio";
 			reg = <0x11400160 0x20>;
@@ -388,19 +386,19 @@
 
 		gpv2: gpio-controller at 10D10040 {
 			compatible = "samsung,exynos4-gpio";
-			reg = <0x10D10040 0x20>;
+			reg = <0x10D10060 0x20>;
 			#gpio-cells = <4>;
 		};
 
 		gpv3: gpio-controller at 10D10060 {
 			compatible = "samsung,exynos4-gpio";
-			reg = <0x10D10060 0x20>;
+			reg = <0x10D10080 0x20>;
 			#gpio-cells = <4>;
 		};
 
 		gpv4: gpio-controller at 10D10080 {
 			compatible = "samsung,exynos4-gpio";
-			reg = <0x10D10080 0x20>;
+			reg = <0x10D100C0 0x20>;
 			#gpio-cells = <4>;
 		};
 
-- 
1.6.6.rc2

[PATCH 06/20] ARM: EXYNOS: add GPC4 bank instance

[Grant Likely]

On Mon, 30 Apr 2012 12:14:16 -0700, Thomas Abraham <thomas.abraham@linaro.org> wrote:
> From: Sangsu Park <sangsu4u.park@samsung.com>
> 
> Add GPC4 bank instance which is included in rev1 of EXYNOS5.
> 
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Signed-off-by: Sangsu Park <sangsu4u.park@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> [kgene.kim at samsung.com: re-worked on top of v3.4-rc3]
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Acked-by: Grant Likely <grant.likely@secretlab.ca>

Should be merged with the rest of the series I think.

g.

> ---
>  arch/arm/mach-exynos/include/mach/gpio.h |    9 ++++++---
>  arch/arm/mach-exynos/include/mach/irqs.h |    2 +-
>  drivers/gpio/gpio-samsung.c              |   11 ++++++++++-
>  3 files changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
> index d7498af..eb24f1e 100644
> --- a/arch/arm/mach-exynos/include/mach/gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> @@ -153,10 +153,11 @@ enum exynos4_gpio_number {
>  #define EXYNOS5_GPIO_B2_NR	(4)
>  #define EXYNOS5_GPIO_B3_NR	(4)
>  #define EXYNOS5_GPIO_C0_NR	(7)
> -#define EXYNOS5_GPIO_C1_NR	(7)
> +#define EXYNOS5_GPIO_C1_NR	(4)
>  #define EXYNOS5_GPIO_C2_NR	(7)
>  #define EXYNOS5_GPIO_C3_NR	(7)
> -#define EXYNOS5_GPIO_D0_NR	(8)
> +#define EXYNOS5_GPIO_C4_NR	(7)
> +#define EXYNOS5_GPIO_D0_NR	(4)
>  #define EXYNOS5_GPIO_D1_NR	(8)
>  #define EXYNOS5_GPIO_Y0_NR	(6)
>  #define EXYNOS5_GPIO_Y1_NR	(4)
> @@ -199,7 +200,8 @@ enum exynos5_gpio_number {
>  	EXYNOS5_GPIO_C1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
>  	EXYNOS5_GPIO_C2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
>  	EXYNOS5_GPIO_C3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
> -	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
> +	EXYNOS5_GPIO_C4_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
> +	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
>  	EXYNOS5_GPIO_D1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
>  	EXYNOS5_GPIO_Y0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
>  	EXYNOS5_GPIO_Y1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
> @@ -242,6 +244,7 @@ enum exynos5_gpio_number {
>  #define EXYNOS5_GPC1(_nr)	(EXYNOS5_GPIO_C1_START + (_nr))
>  #define EXYNOS5_GPC2(_nr)	(EXYNOS5_GPIO_C2_START + (_nr))
>  #define EXYNOS5_GPC3(_nr)	(EXYNOS5_GPIO_C3_START + (_nr))
> +#define EXYNOS5_GPC4(_nr)	(EXYNOS5_GPIO_C4_START + (_nr))
>  #define EXYNOS5_GPD0(_nr)	(EXYNOS5_GPIO_D0_START + (_nr))
>  #define EXYNOS5_GPD1(_nr)	(EXYNOS5_GPIO_D1_START + (_nr))
>  #define EXYNOS5_GPY0(_nr)	(EXYNOS5_GPIO_Y0_START + (_nr))
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> index ef52f61..ece5624 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -446,7 +446,7 @@
>  
>  #define EXYNOS5_MAX_COMBINER_NR		32
>  
> -#define EXYNOS5_IRQ_GPIO1_NR_GROUPS	13
> +#define EXYNOS5_IRQ_GPIO1_NR_GROUPS	14
>  #define EXYNOS5_IRQ_GPIO2_NR_GROUPS	9
>  #define EXYNOS5_IRQ_GPIO3_NR_GROUPS	5
>  #define EXYNOS5_IRQ_GPIO4_NR_GROUPS	1
> diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
> index 19d6fc0..0a2087b 100644
> --- a/drivers/gpio/gpio-samsung.c
> +++ b/drivers/gpio/gpio-samsung.c
> @@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
>  		},
>  	}, {
>  		.chip	= {
> +			.base	= EXYNOS5_GPC4(0),
> +			.ngpio	= EXYNOS5_GPIO_C4_NR,
> +			.label	= "GPC4",
> +		},
> +	}, {
> +		.chip	= {
>  			.base	= EXYNOS5_GPD0(0),
>  			.ngpio	= EXYNOS5_GPIO_D0_NR,
>  			.label	= "GPD0",
> @@ -2874,8 +2880,11 @@ static __init int samsung_gpiolib_init(void)
>  			goto err_ioremap1;
>  		}
>  
> +		/* need to set base address for gpc4 */
> +		exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;
> +
>  		/* need to set base address for gpx */
> -		chip = &exynos5_gpios_1[20];
> +		chip = &exynos5_gpios_1[21];
>  		gpx_base = gpio_base1 + 0xC00;
>  		for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
>  			chip->base = gpx_base;
> -- 
> 1.7.5.4
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.

[PATCH 15/20] ARM: Exynos: Add irq_domain support for gpio wakeup interrupts

[Grant Likely]

On Mon, 30 Apr 2012 12:14:25 -0700, Thomas Abraham <thomas.abraham@linaro.org> wrote:
> Add a irq_domain for all the 32 gpio external wakeup interrupt sources.
> Since there are users of fixed linux irq numbers of the external wakeup
> interrupts, the legacy mapping is used for the irq domain. The fixups
> required to use irq domain based interrupt mapping is also included.
> 
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> Acked-by: Rob Herring <rob.herring@calxeda.com>

Acked-by: Grant Likely <grant.likely@secretlab.ca>

> ---
>  arch/arm/mach-exynos/common.c                 |   67 +++++++++++++++++--------
>  arch/arm/mach-exynos/include/mach/regs-gpio.h |    4 +-
>  2 files changed, 48 insertions(+), 23 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 810f804..0d69412 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -752,6 +752,9 @@ static DEFINE_SPINLOCK(eint_lock);
>  
>  static unsigned int eint0_15_data[16];
>  
> +#define EXYNOS_EINT_NR 32
> +static struct irq_domain *irq_domain;
> +
>  static inline int exynos4_irq_to_gpio(unsigned int irq)
>  {
>  	if (irq < IRQ_EINT(0))
> @@ -842,9 +845,9 @@ static inline void exynos_irq_eint_mask(struct irq_data *data)
>  	u32 mask;
>  
>  	spin_lock(&eint_lock);
> -	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
> -	mask |= EINT_OFFSET_BIT(data->irq);
> -	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
> +	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->hwirq));
> +	mask |= EINT_OFFSET_BIT(data->hwirq);
> +	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->hwirq));
>  	spin_unlock(&eint_lock);
>  }
>  
> @@ -853,16 +856,16 @@ static void exynos_irq_eint_unmask(struct irq_data *data)
>  	u32 mask;
>  
>  	spin_lock(&eint_lock);
> -	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
> -	mask &= ~(EINT_OFFSET_BIT(data->irq));
> -	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
> +	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->hwirq));
> +	mask &= ~(EINT_OFFSET_BIT(data->hwirq));
> +	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->hwirq));
>  	spin_unlock(&eint_lock);
>  }
>  
>  static inline void exynos_irq_eint_ack(struct irq_data *data)
>  {
> -	__raw_writel(EINT_OFFSET_BIT(data->irq),
> -		     EINT_PEND(exynos_eint_base, data->irq));
> +	__raw_writel(EINT_OFFSET_BIT(data->hwirq),
> +		     EINT_PEND(exynos_eint_base, data->hwirq));
>  }
>  
>  static void exynos_irq_eint_maskack(struct irq_data *data)
> @@ -873,7 +876,7 @@ static void exynos_irq_eint_maskack(struct irq_data *data)
>  
>  static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
>  {
> -	int offs = EINT_OFFSET(data->irq);
> +	int offs = data->hwirq;
>  	int shift;
>  	u32 ctrl, mask;
>  	u32 newvalue = 0;
> @@ -908,10 +911,10 @@ static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
>  	mask = 0x7 << shift;
>  
>  	spin_lock(&eint_lock);
> -	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
> +	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->hwirq));
>  	ctrl &= ~mask;
>  	ctrl |= newvalue << shift;
> -	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
> +	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->hwirq));
>  	spin_unlock(&eint_lock);
>  
>  	if (soc_is_exynos5250())
> @@ -955,7 +958,7 @@ static inline void exynos_irq_demux_eint(unsigned int start)
>  
>  	while (status) {
>  		irq = fls(status) - 1;
> -		generic_handle_irq(irq + start);
> +		generic_handle_irq(irq_find_mapping(irq_domain, irq + start));
>  		status &= ~(1 << irq);
>  	}
>  }
> @@ -964,8 +967,8 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
>  {
>  	struct irq_chip *chip = irq_get_chip(irq);
>  	chained_irq_enter(chip, desc);
> -	exynos_irq_demux_eint(IRQ_EINT(16));
> -	exynos_irq_demux_eint(IRQ_EINT(24));
> +	exynos_irq_demux_eint(16);
> +	exynos_irq_demux_eint(24);
>  	chained_irq_exit(chip, desc);
>  }
>  
> @@ -973,6 +976,7 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
>  {
>  	u32 *irq_data = irq_get_handler_data(irq);
>  	struct irq_chip *chip = irq_get_chip(irq);
> +	int eint_irq;
>  
>  	chained_irq_enter(chip, desc);
>  	chip->irq_mask(&desc->irq_data);
> @@ -980,15 +984,28 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
>  	if (chip->irq_ack)
>  		chip->irq_ack(&desc->irq_data);
>  
> -	generic_handle_irq(*irq_data);
> +	eint_irq = irq_find_mapping(irq_domain, *irq_data);
> +	generic_handle_irq(eint_irq);
>  
>  	chip->irq_unmask(&desc->irq_data);
>  	chained_irq_exit(chip, desc);
>  }
>  
> +static int exynos_eint_irq_domain_map(struct irq_domain *d, unsigned int irq,
> +					irq_hw_number_t hw)
> +{
> +	irq_set_chip_and_handler(irq, &exynos_irq_eint, handle_level_irq);
> +	set_irq_flags(irq, IRQF_VALID);
> +	return 0;
> +}
> +
> +static struct irq_domain_ops exynos_eint_irq_domain_ops = {
> +	.map = exynos_eint_irq_domain_map,
> +};
> +
>  static int __init exynos_init_irq_eint(void)
>  {
> -	int irq, *src_int;
> +	int irq, *src_int, irq_base;
>  	unsigned int paddr;
>  
>  	paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : EXYNOS4_PA_GPIO2;
> @@ -998,16 +1015,24 @@ static int __init exynos_init_irq_eint(void)
>  		return -ENXIO;
>  	}
>  
> -	for (irq = 0 ; irq <= 31 ; irq++) {
> -		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
> -					 handle_level_irq);
> -		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
> +	irq_base = irq_alloc_descs(IRQ_EINT(0), 1, EXYNOS_EINT_NR, 0);
> +	if (IS_ERR_VALUE(irq_base)) {
> +		irq_base = IRQ_EINT(0);
> +		pr_warning("%s: irq desc alloc failed. Continuing with %d as "
> +				"linux irq base\n", __func__, irq_base);
> +	}
> +
> +	irq_domain = irq_domain_add_legacy(NULL, EXYNOS_EINT_NR, irq_base, 0,
> +					 &exynos_eint_irq_domain_ops, NULL);
> +	if (WARN_ON(!irq_domain)) {
> +		pr_warning("%s: irq domain init failed\n", __func__);
> +		return 0;
>  	}
>  
>  	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
>  
>  	for (irq = 0 ; irq <= 15; irq++) {
> -		eint0_15_data[irq] = IRQ_EINT(irq);
> +		eint0_15_data[irq] = irq;
>  		src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int :
>  						exynos4_eint0_15_src_int;
>  		irq_set_handler_data(src_int[irq], &eint0_15_data[irq]);
> diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
> index e4b5b60..24bf4ec 100644
> --- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
> @@ -16,13 +16,13 @@
>  #include <mach/map.h>
>  #include <mach/irqs.h>
>  
> -#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
> +#define EINT_REG_NR(x)			((x) >> 3)
>  #define EINT_CON(b, x)			(b + 0xE00 + (EINT_REG_NR(x) * 4))
>  #define EINT_FLTCON(b, x)		(b + 0xE80 + (EINT_REG_NR(x) * 4))
>  #define EINT_MASK(b, x)			(b + 0xF00 + (EINT_REG_NR(x) * 4))
>  #define EINT_PEND(b, x)			(b + 0xF40 + (EINT_REG_NR(x) * 4))
>  
> -#define EINT_OFFSET_BIT(x)		(1 << (EINT_OFFSET(x) & 0x7))
> +#define EINT_OFFSET_BIT(x)		(1 << ((x) & 0x7))
>  
>  /* compatibility for plat-s5p/irq-pm.c */
>  #define EXYNOS4_EINT40CON		(S5P_VA_GPIO2 + 0xE00)
> -- 
> 1.7.5.4
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.

[PATCH 17/20] ARM: Exynos: Add device tree support for gpio wakeup interrupt controller

[Grant Likely]

On Mon, 30 Apr 2012 12:14:27 -0700, Thomas Abraham <thomas.abraham@linaro.org> wrote:
> Add device tree support for gpio wakeup source interrupt controller
> for Exynos platforms.
> 
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
>  arch/arm/mach-exynos/common.c |   92 +++++++++++++++++++++++++++++++++++------
>  1 files changed, 79 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 544f8b5..074508f 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -64,7 +64,8 @@ static void exynos4_init_clocks(int xtal);
>  static void exynos5_init_clocks(int xtal);
>  static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
>  static int exynos_init(void);
> -static int exynos_init_irq_eint(void);
> +static int exynos_init_irq_eint(struct device_node *np,
> +				struct device_node *parent);
>  
>  static struct cpu_table cpu_ids[] __initdata = {
>  	{
> @@ -589,6 +590,8 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
>  	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
>  	{ .compatible = "samsung,exynos4210-combiner",
>  			.data = combiner_of_init, },
> +	{ .compatible = "samsung,exynos5210-wakeup-eint-map",
> +			.data = exynos_init_irq_eint, },
>  	{},
>  };
>  #endif
> @@ -606,8 +609,10 @@ void __init exynos4_init_irq(void)
>  		of_irq_init(exynos4_dt_irq_match);
>  #endif
>  
> -	if (!of_have_populated_dt())
> +	if (!of_have_populated_dt()) {
>  		combiner_init(S5P_VA_COMBINER_BASE, NULL);
> +		exynos_init_irq_eint(NULL, NULL);
> +	}
>  
>  	/*
>  	 * The parameters of s5p_init_irq() are for VIC init.
> @@ -615,7 +620,6 @@ void __init exynos4_init_irq(void)
>  	 * uses GIC instead of VIC.
>  	 */
>  	s5p_init_irq(NULL, 0);
> -	exynos_init_irq_eint();
>  }
>  
>  void __init exynos5_init_irq(void)
> @@ -629,7 +633,6 @@ void __init exynos5_init_irq(void)
>  	 * uses GIC instead of VIC.
>  	 */
>  	s5p_init_irq(NULL, 0);
> -	exynos_init_irq_eint();
>  }
>  
>  struct bus_type exynos_subsys = {
> @@ -1002,17 +1005,72 @@ static int exynos_eint_irq_domain_map(struct irq_domain *d, unsigned int irq,
>  	return 0;
>  }
>  
> +#ifdef CONFIG_OF
> +static int exynos_eint_irq_domain_xlate(struct irq_domain *d,
> +		struct device_node *controller, const u32 *intspec,
> +		unsigned int intsize, unsigned long *out_hwirq,
> +		unsigned int *out_type)
> +{
> +	if (d->of_node != controller)
> +		return -EINVAL;
> +	if (intsize < 2)
> +		return -EINVAL;
> +	*out_hwirq = intspec[0];
> +
> +	switch (intspec[1]) {
> +	case S5P_IRQ_TYPE_LEVEL_LOW:
> +		*out_type = IRQ_TYPE_LEVEL_LOW;
> +		break;
> +	case S5P_IRQ_TYPE_LEVEL_HIGH:
> +		*out_type = IRQ_TYPE_LEVEL_HIGH;
> +		break;
> +	case S5P_IRQ_TYPE_EDGE_FALLING:
> +		*out_type = IRQ_TYPE_EDGE_FALLING;
> +		break;
> +	case S5P_IRQ_TYPE_EDGE_RISING:
> +		*out_type = IRQ_TYPE_EDGE_RISING;
> +		break;
> +	case S5P_IRQ_TYPE_EDGE_BOTH:
> +		*out_type = IRQ_TYPE_EDGE_BOTH;
> +		break;
> +	};
> +
> +	return 0;

I'm recommending that new irq bindings use the Linux IRQ_TYPE_* values
just because it provides some commonality between irq controllers.
Using the S5P_IRQ_TYPE_ values doesn't make much sense when it only
gets immediately converted to another set of arbitrary values.

> +}
> +#else
> +static int exynos_eint_irq_domain_xlate(struct irq_domain *d,
> +		struct device_node *controller, const u32 *intspec,
> +		unsigned int intsize, unsigned long *out_hwirq,
> +		unsigned int *out_type)
> +{
> +	return -EINVAL;
> +}
> +#endif
> +
>  static struct irq_domain_ops exynos_eint_irq_domain_ops = {
> +	.xlate = exynos_eint_irq_domain_xlate,
>  	.map = exynos_eint_irq_domain_map,
>  };
>  
> -static int __init exynos_init_irq_eint(void)
> +static int __init exynos_init_irq_eint(struct device_node *eint_np,
> +					struct device_node *parent)
>  {
> -	int irq, *src_int, irq_base;
> +	int irq, *src_int, irq_base, irq_eint;
>  	unsigned int paddr;
> +	static unsigned int retry = 0;
> +	static struct device_node *np;
>  
> -	paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : EXYNOS4_PA_GPIO2;
> -	exynos_eint_base = ioremap(paddr, SZ_4K);
> +	if (retry)
> +		goto retry_init;
> +
> +	if (!eint_np) {
> +		paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 :
> +						EXYNOS4_PA_GPIO2;
> +		exynos_eint_base = ioremap(paddr, SZ_4K);
> +	} else {
> +		np = of_get_parent(eint_np);
> +		exynos_eint_base = of_iomap(np, 0);
> +	}
>  	if (!exynos_eint_base) {
>  		pr_err("unable to ioremap for EINT base address\n");
>  		return -ENXIO;
> @@ -1025,21 +1083,29 @@ static int __init exynos_init_irq_eint(void)
>  				"linux irq base\n", __func__, irq_base);
>  	}
>  
> -	irq_domain = irq_domain_add_legacy(NULL, EXYNOS_EINT_NR, irq_base, 0,
> +	irq_domain = irq_domain_add_legacy(np, EXYNOS_EINT_NR, irq_base, 0,
>  					 &exynos_eint_irq_domain_ops, NULL);
>  	if (WARN_ON(!irq_domain)) {
>  		pr_warning("%s: irq domain init failed\n", __func__);
>  		return 0;
>  	}
>  
> -	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
> +	irq_eint = eint_np ? irq_of_parse_and_map(np, 16) : EXYNOS_IRQ_EINT16_31;
> +	irq_set_chained_handler(irq_eint, exynos_irq_demux_eint16_31);
>  
> -	for (irq = 0 ; irq <= 15; irq++) {
> +retry_init:
> +	for (irq = 0; irq <= 15; irq++) {
>  		eint0_15_data[irq] = irq;
>  		src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int :
>  						exynos4_eint0_15_src_int;
> -		irq_set_handler_data(src_int[irq], &eint0_15_data[irq]);
> -		irq_set_chained_handler(src_int[irq], exynos_irq_eint0_15);
> +		irq_eint = eint_np ? irq_of_parse_and_map(np, irq) : src_int[irq];
> +		if (!irq_eint) {
> +			of_node_put(np);
> +			retry = 1;
> +			return -EAGAIN;
> +		}
> +		irq_set_handler_data(irq_eint, &eint0_15_data[irq]);
> +		irq_set_chained_handler(irq_eint, exynos_irq_eint0_15);

After switching to irq_domain, all of the contents of this loop should
be in the .map hook.

g.

[PATCH 10/20] of/irq: fix interrupt parent lookup procedure

[Grant Likely]

On Tue, 15 May 2012 17:29:14 +0900, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Thomas Abraham wrote:
> > 
> > The interrupt parent lookup fails for a node that is a interrupt-controller
> > but does not have an explict interrupt-parent property and instead inherits
> > this property from the root node.
> > 
> > Consider the nodes listed below.
> > 
> >     / {
> >         interrupt-parent = <&intc_level1>;
> > 
> >         intc_level1: interrupt-controller at xxx {
> >                 interrupt-controller;
> >                 #interrupt-cells = <3>;
> >                 <rest of the properties here>;
> >         };
> > 
> >         intc_level2: interrupt-controller at yyy {
> >                 interrupt-controller;
> >                 #interrupt-cells = <2>;
> >                 <rest of the properties here>;
> >         };
> >     };
> > 
> > The interrupt parent lookup for interrupt-controller at yyy fails. It inherits
> > the interrupt-parent property from the root node and the root node ('/')
> > specifies a 'interrupt-parent' property which represents the default interrupt
> > root controller. But, the property '#interrupt-cells' might not be specified
> > in the root node.
> > 
> > In case a interrupt controller node does not include a 'interrupt-parent'
> > property but inherits that property from the root node, the check for
> > 'interrupt-cells' property in the root node fails. Fix this removing the
> > check for 'interrupt-cells' property.

Hmmm... I dont see the bug...  From your description above, I see the
following sequence.

First iteration:
	child = &ic at yyy;
	cannot find "interrupt-parent" so take 'if' clause
		p = of_get_parent(child);  (root)
	iteration continues because #interrupt-cells not found in 'p'(root)
Second iteration:
	child = root;
	found "interrupt-parent", so take 'else' clause
		p = of_find_node_by_phandle();  (ic at xxx)
	iteration stops because #interrupt-cells is found in 'p'(ic at xxx)

What am I missing in my admittedly short look at the code?

g.

> > 
> > Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> > ---
> >  drivers/of/irq.c |    4 +++-
> >  1 files changed, 3 insertions(+), 1 deletions(-)
> > 
> > diff --git a/drivers/of/irq.c b/drivers/of/irq.c
> > index 9cf0060..a520363 100644
> > --- a/drivers/of/irq.c
> > +++ b/drivers/of/irq.c
> > @@ -66,14 +66,16 @@ struct device_node *of_irq_find_parent(struct device_node *child)
> >  		if (parp == NULL)
> >  			p = of_get_parent(child);
> >  		else {
> > +			of_node_put(child);
> >  			if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
> >  				p = of_node_get(of_irq_dflt_pic);
> >  			else
> >  				p = of_find_node_by_phandle(be32_to_cpup(parp));
> > +			return p;
> >  		}
> >  		of_node_put(child);
> >  		child = p;
> > -	} while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL);
> > +	} while (p);

This does break one use-case.  Sometimes the interrupt-parent is the
same node when an 
> > 
> >  	return p;
> >  }
> > --
> > 1.7.5.4
> 
> Hi Grant and Rob,
> 
> I'm ok on this and this patch and #11 patch in this series are required for patches that add device tree based support for wakeup
> interrupts on EXYNOS5250.
> 
> So could you have a look at this patch and let us know if this is okay or any rework is required.
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.

[PATCH 10/20] of/irq: fix interrupt parent lookup procedure

[Grant Likely]

On Tue, May 15, 2012 at 12:41 PM, Grant Likely
<grant.likely@secretlab.ca> wrote:
> On Tue, 15 May 2012 17:29:14 +0900, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> Thomas Abraham wrote:
>> >
>> > The interrupt parent lookup fails for a node that is a interrupt-controller
>> > but does not have an explict interrupt-parent property and instead inherits
>> > this property from the root node.
>> >
>> > Consider the nodes listed below.
>> >
>> > ? ? / {
>> > ? ? ? ? interrupt-parent = <&intc_level1>;
>> >
>> > ? ? ? ? intc_level1: interrupt-controller at xxx {
>> > ? ? ? ? ? ? ? ? interrupt-controller;
>> > ? ? ? ? ? ? ? ? #interrupt-cells = <3>;
>> > ? ? ? ? ? ? ? ? <rest of the properties here>;
>> > ? ? ? ? };
>> >
>> > ? ? ? ? intc_level2: interrupt-controller at yyy {
>> > ? ? ? ? ? ? ? ? interrupt-controller;
>> > ? ? ? ? ? ? ? ? #interrupt-cells = <2>;
>> > ? ? ? ? ? ? ? ? <rest of the properties here>;
>> > ? ? ? ? };
>> > ? ? };
>> >
>> > The interrupt parent lookup for interrupt-controller at yyy fails. It inherits
>> > the interrupt-parent property from the root node and the root node ('/')
>> > specifies a 'interrupt-parent' property which represents the default interrupt
>> > root controller. But, the property '#interrupt-cells' might not be specified
>> > in the root node.
>> >
>> > In case a interrupt controller node does not include a 'interrupt-parent'
>> > property but inherits that property from the root node, the check for
>> > 'interrupt-cells' property in the root node fails. Fix this removing the
>> > check for 'interrupt-cells' property.
>
> Hmmm... I dont see the bug... ?From your description above, I see the
> following sequence.
>
> First iteration:
> ? ? ? ?child = &ic at yyy;
> ? ? ? ?cannot find "interrupt-parent" so take 'if' clause
> ? ? ? ? ? ? ? ?p = of_get_parent(child); ?(root)
> ? ? ? ?iteration continues because #interrupt-cells not found in 'p'(root)
> Second iteration:
> ? ? ? ?child = root;
> ? ? ? ?found "interrupt-parent", so take 'else' clause
> ? ? ? ? ? ? ? ?p = of_find_node_by_phandle(); ?(ic at xxx)
> ? ? ? ?iteration stops because #interrupt-cells is found in 'p'(ic at xxx)
>
> What am I missing in my admittedly short look at the code?
>
> g.
>
>> >
>> > Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> > ---
>> > ?drivers/of/irq.c | ? ?4 +++-
>> > ?1 files changed, 3 insertions(+), 1 deletions(-)
>> >
>> > diff --git a/drivers/of/irq.c b/drivers/of/irq.c
>> > index 9cf0060..a520363 100644
>> > --- a/drivers/of/irq.c
>> > +++ b/drivers/of/irq.c
>> > @@ -66,14 +66,16 @@ struct device_node *of_irq_find_parent(struct device_node *child)
>> > ? ? ? ? ? ? if (parp == NULL)
>> > ? ? ? ? ? ? ? ? ? ? p = of_get_parent(child);
>> > ? ? ? ? ? ? else {
>> > + ? ? ? ? ? ? ? ? ? of_node_put(child);
>> > ? ? ? ? ? ? ? ? ? ? if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
>> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? p = of_node_get(of_irq_dflt_pic);
>> > ? ? ? ? ? ? ? ? ? ? else
>> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? p = of_find_node_by_phandle(be32_to_cpup(parp));
>> > + ? ? ? ? ? ? ? ? ? return p;
>> > ? ? ? ? ? ? }
>> > ? ? ? ? ? ? of_node_put(child);
>> > ? ? ? ? ? ? child = p;
>> > - ? } while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL);
>> > + ? } while (p);
>
> This does break one use-case. ?Sometimes the interrupt-parent is the
> same node when an

Oops, ignore this comment.  I meant to delete it before sending.

g.

[PATCH 19/20] ARM: Exynos5: Add combiner, wakeup interrupt controller and ethernet nodes

[Grant Likely]

On Wed, 2 May 2012 10:57:11 -0700, Olof Johansson <olof@lixom.net> wrote:
> Hi,
> 
> [adding devicetree-discuss]
> 
> On Mon, Apr 30, 2012 at 12:14 PM, Thomas Abraham
> <thomas.abraham@linaro.org> wrote:
> > And interrupt combiner, external interrupt wakeup interrupt controller
> > and smsc9215 lan controller nodes.
> >
> > Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> > ---
> > ??arch/arm/boot/dts/exynos5250-smdk5250.dts | ?? 11 ++++++
> > ??arch/arm/boot/dts/exynos5250.dtsi ?? ?? ?? ?? | ?? 55 +++++++++++++++++++++++++++++
> > ??2 files changed, 66 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> > index bcc4b89..dbc4bdb 100644
> > --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> > +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> > @@ -24,6 +24,17 @@
> > ?? ?? ?? ?? ?? ?? ?? ??bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
> > ?? ?? ?? ??};
> >
> > + ?? ?? ?? lan9215 at 0x05000000 {
> > + ?? ?? ?? ?? ?? ?? ?? compatible = "smsc,lan9215", "smsc,lan9115";
> > + ?? ?? ?? ?? ?? ?? ?? reg = <0x05000000 0x20000>;
> > + ?? ?? ?? ?? ?? ?? ?? interrupts = <5 0>;
> > + ?? ?? ?? ?? ?? ?? ?? interrupt-parent = <&wakeup_eint>;
> > + ?? ?? ?? ?? ?? ?? ?? phy-mode = "mii";
> > + ?? ?? ?? ?? ?? ?? ?? smsc,irq-push-pull;
> > + ?? ?? ?? ?? ?? ?? ?? smsc,force-internal-phy;
> > + ?? ?? ?? ?? ?? ?? ?? local-mac-address = [00 80 00 23 45 67];
> > + ?? ?? ?? };
> > +
> 
> since the 911x sits on a chipselect bus, you should instead add that
> bus to the dtsi and define this on that bus.
> 
> Something like this in the dtsi:
> 
>        sromc-bus {
>                #address-cells = <2>;
>                #size-cells = <1>;
>                ranges = < 0 0 0x04000000 0x20000
>                           1 0 0x05000000 0x20000
>                           2 0 0x06000000 0x20000
>                           3 0 0x07000000 0x20000>;
>        };
> 
> and in the dts:
> 
>        sromc-bus {
>                lan9215 at 1,0 {
>                        compatible = "smsc,lan9215", "smsc,lan9115";
>                        reg = <1 0 0x20000>;
>                        interrupts = <5 0>;
>                        interrupt-parent = <&wakeup_eint>;
>                        phy-mode = "mii";
>                        smsc,irq-push-pull;
>                        smsc,force-internal-phy;
>                        local-mac-address = [00 80 00 23 45 67];
>                };
>         };
> 
> 
> (You might be able to do just fine with one address cell, I'm not 100%
> sure why Grant's example uses two, but I used the same above for
> consistency).

Because otherwise there is no way to describe an offset from the base
of the chipselect base value, and the core code will try to apply the
size to the cs part of the address specifier. (so in the example
above the address range described by:

	reg = <1 0x20000>;

would mean cs values 1 to 0x20001; which is definitely wrong.

> Also, I don't think it's a good idea to hardcode the mac address in
> the dts like this; have u-boot fill it in from the environment
> variable there instead, if needed.

Very bad practice indeed.

[PATCH 19/20] ARM: Exynos5: Add combiner, wakeup interrupt controller and ethernet nodes

[Olof Johansson]

On Fri, May 18, 2012 at 11:11 PM, Grant Likely
<grant.likely@secretlab.ca> wrote:
> On Wed, 2 May 2012 10:57:11 -0700, Olof Johansson <olof@lixom.net> wrote:
>> Hi,
>>
>> [adding devicetree-discuss]
>>
>> On Mon, Apr 30, 2012 at 12:14 PM, Thomas Abraham
>> <thomas.abraham@linaro.org> wrote:
>> > And interrupt combiner, external interrupt wakeup interrupt controller
>> > and smsc9215 lan controller nodes.
>> >
>> > Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> > ---
>> > ?arch/arm/boot/dts/exynos5250-smdk5250.dts | ? 11 ++++++
>> > ?arch/arm/boot/dts/exynos5250.dtsi ? ? ? ? | ? 55 +++++++++++++++++++++++++++++
>> > ?2 files changed, 66 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> > index bcc4b89..dbc4bdb 100644
>> > --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> > +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> > @@ -24,6 +24,17 @@
>> > ? ? ? ? ? ? ? ?bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
>> > ? ? ? ?};
>> >
>> > + ? ? ? lan9215 at 0x05000000 {
>> > + ? ? ? ? ? ? ? compatible = "smsc,lan9215", "smsc,lan9115";
>> > + ? ? ? ? ? ? ? reg = <0x05000000 0x20000>;
>> > + ? ? ? ? ? ? ? interrupts = <5 0>;
>> > + ? ? ? ? ? ? ? interrupt-parent = <&wakeup_eint>;
>> > + ? ? ? ? ? ? ? phy-mode = "mii";
>> > + ? ? ? ? ? ? ? smsc,irq-push-pull;
>> > + ? ? ? ? ? ? ? smsc,force-internal-phy;
>> > + ? ? ? ? ? ? ? local-mac-address = [00 80 00 23 45 67];
>> > + ? ? ? };
>> > +
>>
>> since the 911x sits on a chipselect bus, you should instead add that
>> bus to the dtsi and define this on that bus.
>>
>> Something like this in the dtsi:
>>
>> ? ? ? ?sromc-bus {
>> ? ? ? ? ? ? ? ?#address-cells = <2>;
>> ? ? ? ? ? ? ? ?#size-cells = <1>;
>> ? ? ? ? ? ? ? ?ranges = < 0 0 0x04000000 0x20000
>> ? ? ? ? ? ? ? ? ? ? ? ? ? 1 0 0x05000000 0x20000
>> ? ? ? ? ? ? ? ? ? ? ? ? ? 2 0 0x06000000 0x20000
>> ? ? ? ? ? ? ? ? ? ? ? ? ? 3 0 0x07000000 0x20000>;
>> ? ? ? ?};
>>
>> and in the dts:
>>
>> ? ? ? ?sromc-bus {
>> ? ? ? ? ? ? ? ?lan9215 at 1,0 {
>> ? ? ? ? ? ? ? ? ? ? ? ?compatible = "smsc,lan9215", "smsc,lan9115";
>> ? ? ? ? ? ? ? ? ? ? ? ?reg = <1 0 0x20000>;
>> ? ? ? ? ? ? ? ? ? ? ? ?interrupts = <5 0>;
>> ? ? ? ? ? ? ? ? ? ? ? ?interrupt-parent = <&wakeup_eint>;
>> ? ? ? ? ? ? ? ? ? ? ? ?phy-mode = "mii";
>> ? ? ? ? ? ? ? ? ? ? ? ?smsc,irq-push-pull;
>> ? ? ? ? ? ? ? ? ? ? ? ?smsc,force-internal-phy;
>> ? ? ? ? ? ? ? ? ? ? ? ?local-mac-address = [00 80 00 23 45 67];
>> ? ? ? ? ? ? ? ?};
>> ? ? ? ? };
>>
>>
>> (You might be able to do just fine with one address cell, I'm not 100%
>> sure why Grant's example uses two, but I used the same above for
>> consistency).
>
> Because otherwise there is no way to describe an offset from the base
> of the chipselect base value, and the core code will try to apply the
> size to the cs part of the address specifier. (so in the example
> above the address range described by:
>
> ? ? ? ?reg = <1 0x20000>;
>
> would mean cs values 1 to 0x20001; which is definitely wrong.

Ah yes, that makes perfect sense. I can't seem to create an account to
update the 'Device_Tree_Usage' page on the devicetree.org wiki, but
it'd probably not be a bad idea to include the above for explanation
there.


-Olof

[PATCH 10/20] of/irq: fix interrupt parent lookup procedure

[Thomas Abraham]

On 16 May 2012 00:11, Grant Likely <grant.likely@secretlab.ca> wrote:
> On Tue, 15 May 2012 17:29:14 +0900, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> Thomas Abraham wrote:
>> >
>> > The interrupt parent lookup fails for a node that is a interrupt-controller
>> > but does not have an explict interrupt-parent property and instead inherits
>> > this property from the root node.
>> >
>> > Consider the nodes listed below.
>> >
>> > ? ? / {
>> > ? ? ? ? interrupt-parent = <&intc_level1>;
>> >
>> > ? ? ? ? intc_level1: interrupt-controller at xxx {
>> > ? ? ? ? ? ? ? ? interrupt-controller;
>> > ? ? ? ? ? ? ? ? #interrupt-cells = <3>;
>> > ? ? ? ? ? ? ? ? <rest of the properties here>;
>> > ? ? ? ? };
>> >
>> > ? ? ? ? intc_level2: interrupt-controller at yyy {
>> > ? ? ? ? ? ? ? ? interrupt-controller;
>> > ? ? ? ? ? ? ? ? #interrupt-cells = <2>;
>> > ? ? ? ? ? ? ? ? <rest of the properties here>;
>> > ? ? ? ? };
>> > ? ? };
>> >
>> > The interrupt parent lookup for interrupt-controller at yyy fails. It inherits
>> > the interrupt-parent property from the root node and the root node ('/')
>> > specifies a 'interrupt-parent' property which represents the default interrupt
>> > root controller. But, the property '#interrupt-cells' might not be specified
>> > in the root node.
>> >
>> > In case a interrupt controller node does not include a 'interrupt-parent'
>> > property but inherits that property from the root node, the check for
>> > 'interrupt-cells' property in the root node fails. Fix this removing the
>> > check for 'interrupt-cells' property.
>
> Hmmm... I dont see the bug... ?From your description above, I see the
> following sequence.
>
> First iteration:
> ? ? ? ?child = &ic at yyy;
> ? ? ? ?cannot find "interrupt-parent" so take 'if' clause
> ? ? ? ? ? ? ? ?p = of_get_parent(child); ?(root)
> ? ? ? ?iteration continues because #interrupt-cells not found in 'p'(root)
> Second iteration:
> ? ? ? ?child = root;
> ? ? ? ?found "interrupt-parent", so take 'else' clause
> ? ? ? ? ? ? ? ?p = of_find_node_by_phandle(); ?(ic at xxx)
> ? ? ? ?iteration stops because #interrupt-cells is found in 'p'(ic at xxx)
>
> What am I missing in my admittedly short look at the code?

Grant, sorry for the bad commit message for the patch. I got it
completely wrong. I intended to generalize a change which was need for
a using interrupt-map on Exynos5 for wakeup interrupts, and in process
I wrote down a incorrect commit message.

I will list out the problem I was trying to solve. The wakeup
interrupt controller on Exynos5 has two parents - GIC and Interrupt
Combiner. The node for the Exynos5 wakeup interrupt is listed below.

        wakeup_eint: interrupt-controller at 11400000 {
                compatible = "samsung,exynos5210-wakeup-eint";
                reg = <0x11400000 0x1000>;
                interrupt-controller;
                #interrupt-cells = <2>;
                interrupt-parent = <&wakeup_map>;
                interrupts = <0x0 0>, <0x1 0>, <0x2 0>, <0x3 0>,
                             <0x4 0>, <0x5 0>, <0x6 0>, <0x7 0>,
                             <0x8 0>, <0x9 0>, <0xa 0>, <0xb 0>,
                             <0xc 0>, <0xd 0>, <0xe 0>, <0xf 0>,
                             <0x10 0>;

                wakeup_map: interrupt-map {
                        compatible = "samsung,exynos5210-wakeup-eint-map";
                        #interrupt-cells = <2>;
                        #address-cells = <0>;
                        #size-cells = <0>;
                        interrupt-map = <0x0 0 &combiner 23 0>,
                                        <0x1 0 &combiner 24 0>,
                                        <0x2 0 &combiner 25 0>,
                                        <0x3 0 &combiner 25 1>,
                                        <0x4 0 &combiner 26 0>,
                                        <0x5 0 &combiner 26 1>,
                                        <0x6 0 &combiner 27 0>,
                                        <0x7 0 &combiner 27 1>,
                                        <0x8 0 &combiner 28 0>,
                                        <0x9 0 &combiner 28 1>,
                                        <0xa 0 &combiner 29 0>,
                                        <0xb 0 &combiner 29 1>,
                                        <0xc 0 &combiner 30 0>,
                                        <0xd 0 &combiner 30 1>,
                                        <0xe 0 &combiner 31 0>,
                                        <0xf 0 &combiner 31 1>,
                                        <0x10 0 &gic 0 32 0>;
                };
        };

The match table for of_irq_init() function is listed below (the third
in this list is for wakeup interrupt controller).

static const struct of_device_id exynos4_dt_irq_match[] = {
        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
        { .compatible = "samsung,exynos4210-combiner",
                        .data = combiner_of_init, },
        { .compatible = "samsung,exynos5210-wakeup-eint-map",
                        .data = exynos_init_irq_eint, },
        {},
};

Without this patch, of_irq_init() finds that the interrupt parent of
"interrupt-map" node is "interrupt-controller at 11400000" node. Which is
not correct. The interrupt parent of "interrupt-map" node should be
itself.

I feel that the check for "#interrupt-cells" property in do..while()
loop in of_irq_find_parent() function is not required. The presence of
"#interrupt-cells" property in the parent node should not be
considered as a necessary condition for the parent node to be
considered the interrupt-parent of the child node.

Thanks for reviewing this patch. Sorry for the delay in responding to
your email.

Thanks,
Thomas.

[PATCH 05/20] ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition

[Kyungmin Park]

Hi,

On Tue, May 1, 2012 at 4:14 AM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> From: Changhwan Youn <chaos.youn@samsung.com>
>
> Redefine IRQ_MCT_L0,1 irq definition as it is changed in rev1 of EXYNOS5.
>
> Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
> ?arch/arm/mach-exynos/include/mach/irqs.h | ? ?4 ++--
> ?arch/arm/mach-exynos/mct.c ? ? ? ? ? ? ? | ? 17 +++++++++++------
> ?2 files changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> index 591e7852..ef52f61 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -331,6 +331,8 @@
> ?#define EXYNOS5_IRQ_SATA ? ? ? ? ? ? ? IRQ_SPI(115)
> ?#define EXYNOS5_IRQ_NFCON ? ? ? ? ? ? ?IRQ_SPI(116)
>
> +#define EXYNOS5_IRQ_MCT_L0 ? ? ? ? ? ? IRQ_SPI(120)
> +#define EXYNOS5_IRQ_MCT_L1 ? ? ? ? ? ? IRQ_SPI(121)
> ?#define EXYNOS5_IRQ_MMC44 ? ? ? ? ? ? ?IRQ_SPI(123)
> ?#define EXYNOS5_IRQ_MDMA1 ? ? ? ? ? ? ?IRQ_SPI(124)
> ?#define EXYNOS5_IRQ_FIMC_LITE0 ? ? ? ? IRQ_SPI(125)
> @@ -410,8 +412,6 @@
> ?#define EXYNOS5_IRQ_FIMD1_SYSTEM ? ? ? COMBINER_IRQ(18, 6)
>
> ?#define EXYNOS5_IRQ_EINT0 ? ? ? ? ? ? ?COMBINER_IRQ(23, 0)
> -#define EXYNOS5_IRQ_MCT_L0 ? ? ? ? ? ? COMBINER_IRQ(23, 1)
> -#define EXYNOS5_IRQ_MCT_L1 ? ? ? ? ? ? COMBINER_IRQ(23, 2)
> ?#define EXYNOS5_IRQ_MCT_G0 ? ? ? ? ? ? COMBINER_IRQ(23, 3)
> ?#define EXYNOS5_IRQ_MCT_G1 ? ? ? ? ? ? COMBINER_IRQ(23, 4)
> ?#define EXYNOS5_IRQ_MCT_G2 ? ? ? ? ? ? COMBINER_IRQ(23, 5)
> diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
> index 897d9a9..b601fb8 100644
> --- a/arch/arm/mach-exynos/mct.c
> +++ b/arch/arm/mach-exynos/mct.c
> @@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
> ?{
> ? ? ? ?struct mct_clock_event_device *mevt;
> ? ? ? ?unsigned int cpu = smp_processor_id();
> + ? ? ? int mct_lx_irq;
>
> ? ? ? ?mevt = this_cpu_ptr(&percpu_mct_tick);
> ? ? ? ?mevt->evt = evt;
> @@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
>
> ? ? ? ?if (mct_int_type == MCT_INT_SPI) {
> ? ? ? ? ? ? ? ?if (cpu == 0) {
> + ? ? ? ? ? ? ? ? ? ? ? mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? EXYNOS5_IRQ_MCT_L0;
Does it still valid for exynos4x12?. It means exynos4x12 uses
EXYNOS5_IRQ_MCT_L0?
> ? ? ? ? ? ? ? ? ? ? ? ?mct_tick0_event_irq.dev_id = mevt;
> - ? ? ? ? ? ? ? ? ? ? ? evt->irq = EXYNOS4_IRQ_MCT_L0;
> - ? ? ? ? ? ? ? ? ? ? ? setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
> + ? ? ? ? ? ? ? ? ? ? ? evt->irq = mct_lx_irq;
> + ? ? ? ? ? ? ? ? ? ? ? setup_irq(mct_lx_irq, &mct_tick0_event_irq);
> ? ? ? ? ? ? ? ?} else {
> + ? ? ? ? ? ? ? ? ? ? ? mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? EXYNOS5_IRQ_MCT_L1;
ditto
> ? ? ? ? ? ? ? ? ? ? ? ?mct_tick1_event_irq.dev_id = mevt;
> - ? ? ? ? ? ? ? ? ? ? ? evt->irq = EXYNOS4_IRQ_MCT_L1;
> - ? ? ? ? ? ? ? ? ? ? ? setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
> - ? ? ? ? ? ? ? ? ? ? ? irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
> + ? ? ? ? ? ? ? ? ? ? ? evt->irq = mct_lx_irq;
> + ? ? ? ? ? ? ? ? ? ? ? setup_irq(mct_lx_irq, &mct_tick1_event_irq);
> + ? ? ? ? ? ? ? ? ? ? ? irq_set_affinity(mct_lx_irq, cpumask_of(1));
> ? ? ? ? ? ? ? ?}
> ? ? ? ?} else {
> ? ? ? ? ? ? ? ?enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
> @@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
>
> ?static void __init exynos4_timer_init(void)
> ?{
> - ? ? ? if (soc_is_exynos4210())
> + ? ? ? if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
> ? ? ? ? ? ? ? ?mct_int_type = MCT_INT_SPI;
> ? ? ? ?else
> ? ? ? ? ? ? ? ?mct_int_type = MCT_INT_PPI;

BTW exynos4x12 uses MCT_INT_PPI?

Kyungmin Park
> --
> 1.7.5.4
>
> --
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[PATCH 05/20] ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition

[Thomas Abraham]

Dear Mr. Park,

On 27 May 2012 06:59, Kyungmin Park <kmpark@infradead.org> wrote:
> Hi,
>
> On Tue, May 1, 2012 at 4:14 AM, Thomas Abraham
> <thomas.abraham@linaro.org> wrote:
>> From: Changhwan Youn <chaos.youn@samsung.com>
>>
>> Redefine IRQ_MCT_L0,1 irq definition as it is changed in rev1 of EXYNOS5.
>>
>> Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
>> ---
>> ?arch/arm/mach-exynos/include/mach/irqs.h | ? ?4 ++--
>> ?arch/arm/mach-exynos/mct.c ? ? ? ? ? ? ? | ? 17 +++++++++++------
>> ?2 files changed, 13 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
>> index 591e7852..ef52f61 100644
>> --- a/arch/arm/mach-exynos/include/mach/irqs.h
>> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
>> @@ -331,6 +331,8 @@
>> ?#define EXYNOS5_IRQ_SATA ? ? ? ? ? ? ? IRQ_SPI(115)
>> ?#define EXYNOS5_IRQ_NFCON ? ? ? ? ? ? ?IRQ_SPI(116)
>>
>> +#define EXYNOS5_IRQ_MCT_L0 ? ? ? ? ? ? IRQ_SPI(120)
>> +#define EXYNOS5_IRQ_MCT_L1 ? ? ? ? ? ? IRQ_SPI(121)
>> ?#define EXYNOS5_IRQ_MMC44 ? ? ? ? ? ? ?IRQ_SPI(123)
>> ?#define EXYNOS5_IRQ_MDMA1 ? ? ? ? ? ? ?IRQ_SPI(124)
>> ?#define EXYNOS5_IRQ_FIMC_LITE0 ? ? ? ? IRQ_SPI(125)
>> @@ -410,8 +412,6 @@
>> ?#define EXYNOS5_IRQ_FIMD1_SYSTEM ? ? ? COMBINER_IRQ(18, 6)
>>
>> ?#define EXYNOS5_IRQ_EINT0 ? ? ? ? ? ? ?COMBINER_IRQ(23, 0)
>> -#define EXYNOS5_IRQ_MCT_L0 ? ? ? ? ? ? COMBINER_IRQ(23, 1)
>> -#define EXYNOS5_IRQ_MCT_L1 ? ? ? ? ? ? COMBINER_IRQ(23, 2)
>> ?#define EXYNOS5_IRQ_MCT_G0 ? ? ? ? ? ? COMBINER_IRQ(23, 3)
>> ?#define EXYNOS5_IRQ_MCT_G1 ? ? ? ? ? ? COMBINER_IRQ(23, 4)
>> ?#define EXYNOS5_IRQ_MCT_G2 ? ? ? ? ? ? COMBINER_IRQ(23, 5)
>> diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
>> index 897d9a9..b601fb8 100644
>> --- a/arch/arm/mach-exynos/mct.c
>> +++ b/arch/arm/mach-exynos/mct.c
>> @@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
>> ?{
>> ? ? ? ?struct mct_clock_event_device *mevt;
>> ? ? ? ?unsigned int cpu = smp_processor_id();
>> + ? ? ? int mct_lx_irq;
>>
>> ? ? ? ?mevt = this_cpu_ptr(&percpu_mct_tick);
>> ? ? ? ?mevt->evt = evt;
>> @@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
>>
>> ? ? ? ?if (mct_int_type == MCT_INT_SPI) {
>> ? ? ? ? ? ? ? ?if (cpu == 0) {
>> + ? ? ? ? ? ? ? ? ? ? ? mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? EXYNOS5_IRQ_MCT_L0;
> Does it still valid for exynos4x12?. It means exynos4x12 uses
> EXYNOS5_IRQ_MCT_L0?

For Exynos4x12, PPI interrupts are used for the MCT local timer irqs
and hence the condition check "mct_int_type == MCT_INT_SPI" above will
ensure that this code portion is skipped for Exynos4x12.

>> ? ? ? ? ? ? ? ? ? ? ? ?mct_tick0_event_irq.dev_id = mevt;
>> - ? ? ? ? ? ? ? ? ? ? ? evt->irq = EXYNOS4_IRQ_MCT_L0;
>> - ? ? ? ? ? ? ? ? ? ? ? setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
>> + ? ? ? ? ? ? ? ? ? ? ? evt->irq = mct_lx_irq;
>> + ? ? ? ? ? ? ? ? ? ? ? setup_irq(mct_lx_irq, &mct_tick0_event_irq);
>> ? ? ? ? ? ? ? ?} else {
>> + ? ? ? ? ? ? ? ? ? ? ? mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? EXYNOS5_IRQ_MCT_L1;
> ditto
>> ? ? ? ? ? ? ? ? ? ? ? ?mct_tick1_event_irq.dev_id = mevt;
>> - ? ? ? ? ? ? ? ? ? ? ? evt->irq = EXYNOS4_IRQ_MCT_L1;
>> - ? ? ? ? ? ? ? ? ? ? ? setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
>> - ? ? ? ? ? ? ? ? ? ? ? irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
>> + ? ? ? ? ? ? ? ? ? ? ? evt->irq = mct_lx_irq;
>> + ? ? ? ? ? ? ? ? ? ? ? setup_irq(mct_lx_irq, &mct_tick1_event_irq);
>> + ? ? ? ? ? ? ? ? ? ? ? irq_set_affinity(mct_lx_irq, cpumask_of(1));
>> ? ? ? ? ? ? ? ?}
>> ? ? ? ?} else {
>> ? ? ? ? ? ? ? ?enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);

This else portion is applicable for Exynos4x12 and uses PPI interrupts.

>> @@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
>>
>> ?static void __init exynos4_timer_init(void)
>> ?{
>> - ? ? ? if (soc_is_exynos4210())
>> + ? ? ? if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
>> ? ? ? ? ? ? ? ?mct_int_type = MCT_INT_SPI;
>> ? ? ? ?else
>> ? ? ? ? ? ? ? ?mct_int_type = MCT_INT_PPI;
>
> BTW exynos4x12 uses MCT_INT_PPI?

Yes, PPI interrupts are used for 4x12. The mct local timer irqs can be
routed to either combiner or PPI. Since routing via combiner incurs
overhead in demuxing the interrupt, PPI is used for mct local timer
irq.

Thanks,
Thomas.