From: jean.pihet@newoldbits.com (jean.pihet at newoldbits.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/5] ARM: OMAP2+: PM: implement a caching mechanism on the power domains state registers
Date: Tue, 1 May 2012 15:07:38 +0200 [thread overview]
Message-ID: <1335877663-32649-1-git-send-email-j-pihet@ti.com> (raw)
From: Jean Pihet <j-pihet@ti.com>
The OMAP3 PRCM registers accesses are known to be slow, with a PRCM register
read taking up to 12-14us depending on the OPP.
This patch adds a caching mechanism on the power domains state registers.
When the cache is cold or has been invalidated a register access is
performed, otherwise the register value is retrieved from the registers
cache.
The API is made of read and write functions for fields in the cache, as well
as an invalidate and helper functions to invalidate parts of the cache
contents (i.e. previous, current power states and all fields in the cache).
The power domain code is converted to use the API to read and write the
previous, current and next states for the power domains states, logical
and memory states.
The PM debug code also uses the caching API instead of the internal
pwrdm->state variable.
Using the caching mechanism optimizes the performance of the system in the
transitions to and from the low power states.
Tested on Beagleboard using cpuidle in RET and OFF modes.
Based on the linux-omap git tree (3.4.0-rc2) [1] with the changes for the
functional power states [2] and the per-device PM QoS support for OMAP [3].
[1] git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
[2] http://marc.info/?l=linux-omap&m=133475291911194&w=2
[3] http://marc.info/?l=linux-omap&m=133475685213067&w=2
Jean Pihet (5):
ARM: OMAP2+: PM: implement a caching mechanism on the power domains
state registers
ARM: OMAP2+: PM: use the power domains registers cache for the power
states
ARM: OMAP2+: PM: use the power domains registers cache for the logic
and mem states
ARM: OMAP2+: PM: use the power domains registers cache invalidate API
ARM: OMAP2+: PM debug: use the power domains registers caching API
arch/arm/mach-omap2/pm-debug.c | 16 ++-
arch/arm/mach-omap2/pm34xx.c | 6 +
arch/arm/mach-omap2/powerdomain.c | 272 ++++++++++++++++++++++++++++++++-----
arch/arm/mach-omap2/powerdomain.h | 45 ++++++-
4 files changed, 297 insertions(+), 42 deletions(-)
--
1.7.7.6
next reply other threads:[~2012-05-01 13:07 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-01 13:07 jean.pihet at newoldbits.com [this message]
2012-05-01 13:07 ` [PATCH 1/5] ARM: OMAP2+: PM: implement a caching mechanism on the power domains state registers jean.pihet at newoldbits.com
2012-05-01 13:07 ` [PATCH 2/5] ARM: OMAP2+: PM: use the power domains registers cache for the power states jean.pihet at newoldbits.com
2012-05-01 15:37 ` Jon Hunter
2012-05-03 6:38 ` Bedia, Vaibhav
2012-05-03 7:28 ` Jean Pihet
2012-05-01 13:07 ` [PATCH 3/5] ARM: OMAP2+: PM: use the power domains registers cache for the logic and mem states jean.pihet at newoldbits.com
2012-05-01 15:37 ` Jon Hunter
2012-05-01 13:07 ` [PATCH 4/5] ARM: OMAP2+: PM: use the power domains registers cache invalidate API jean.pihet at newoldbits.com
2012-05-01 13:07 ` [PATCH 5/5] ARM: OMAP2+: PM debug: use the power domains registers caching API jean.pihet at newoldbits.com
2012-05-01 15:37 ` [PATCH 0/5] ARM: OMAP2+: PM: implement a caching mechanism on the power domains state registers Jon Hunter
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