* [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file
@ 2012-05-14 17:46 Alexander Shiyan
2012-05-14 17:46 ` [PATCH 2/4] ARM: clps711x: Added missing register definitions Alexander Shiyan
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Alexander Shiyan @ 2012-05-14 17:46 UTC (permalink / raw)
To: linux-arm-kernel
Patch created for arm-soc clps711x/cleanup branch.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/include/asm/hardware/clps7111.h | 234 ----------------------
arch/arm/mach-clps711x/include/mach/clps711x.h | 232 +++++++++++++++++++++
arch/arm/mach-clps711x/include/mach/hardware.h | 2 +-
arch/arm/mach-clps711x/include/mach/uncompress.h | 2 +-
4 files changed, 234 insertions(+), 236 deletions(-)
delete mode 100644 arch/arm/include/asm/hardware/clps7111.h
create mode 100644 arch/arm/mach-clps711x/include/mach/clps711x.h
diff --git a/arch/arm/include/asm/hardware/clps7111.h b/arch/arm/include/asm/hardware/clps7111.h
deleted file mode 100644
index 0998606..0000000
--- a/arch/arm/include/asm/hardware/clps7111.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * arch/arm/include/asm/hardware/clps7111.h
- *
- * This file contains the hardware definitions of the CLPS7111 internal
- * registers.
- *
- * Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_HARDWARE_CLPS7111_H
-#define __ASM_HARDWARE_CLPS7111_H
-
-#define CLPS711X_PHYS_BASE (0x80000000)
-
-#define PADR (0x0000)
-#define PBDR (0x0001)
-#define PCDR (0x0002)
-#define PDDR (0x0003)
-#define PADDR (0x0040)
-#define PBDDR (0x0041)
-#define PCDDR (0x0042)
-#define PDDDR (0x0043)
-#define PEDR (0x0080)
-#define PEDDR (0x00c0)
-#define SYSCON1 (0x0100)
-#define SYSFLG1 (0x0140)
-#define MEMCFG1 (0x0180)
-#define MEMCFG2 (0x01c0)
-#define DRFPR (0x0200)
-#define INTSR1 (0x0240)
-#define INTMR1 (0x0280)
-#define LCDCON (0x02c0)
-#define TC1D (0x0300)
-#define TC2D (0x0340)
-#define RTCDR (0x0380)
-#define RTCMR (0x03c0)
-#define PMPCON (0x0400)
-#define CODR (0x0440)
-#define UARTDR1 (0x0480)
-#define UBRLCR1 (0x04c0)
-#define SYNCIO (0x0500)
-#define PALLSW (0x0540)
-#define PALMSW (0x0580)
-#define STFCLR (0x05c0)
-#define BLEOI (0x0600)
-#define MCEOI (0x0640)
-#define TEOI (0x0680)
-#define TC1EOI (0x06c0)
-#define TC2EOI (0x0700)
-#define RTCEOI (0x0740)
-#define UMSEOI (0x0780)
-#define COEOI (0x07c0)
-#define HALT (0x0800)
-#define STDBY (0x0840)
-
-#define FBADDR (0x1000)
-#define SYSCON2 (0x1100)
-#define SYSFLG2 (0x1140)
-#define INTSR2 (0x1240)
-#define INTMR2 (0x1280)
-#define UARTDR2 (0x1480)
-#define UBRLCR2 (0x14c0)
-#define SS2DR (0x1500)
-#define SRXEOF (0x1600)
-#define SS2POP (0x16c0)
-#define KBDEOI (0x1700)
-
-#define DAIR (0x2000)
-#define DAIR0 (0x2040)
-#define DAIDR1 (0x2080)
-#define DAIDR2 (0x20c0)
-#define DAISR (0x2100)
-#define SYSCON3 (0x2200)
-#define INTSR3 (0x2240)
-#define INTMR3 (0x2280)
-#define LEDFLSH (0x22c0)
-#define SDCONF (0x2300)
-#define SDRFPR (0x2340)
-
-/* common bits: SYSCON1 / SYSCON2 */
-#define SYSCON_UARTEN (1 << 8)
-
-#define SYSCON1_KBDSCAN(x) ((x) & 15)
-#define SYSCON1_KBDSCANMASK (15)
-#define SYSCON1_TC1M (1 << 4)
-#define SYSCON1_TC1S (1 << 5)
-#define SYSCON1_TC2M (1 << 6)
-#define SYSCON1_TC2S (1 << 7)
-#define SYSCON1_UART1EN SYSCON_UARTEN
-#define SYSCON1_BZTOG (1 << 9)
-#define SYSCON1_BZMOD (1 << 10)
-#define SYSCON1_DBGEN (1 << 11)
-#define SYSCON1_LCDEN (1 << 12)
-#define SYSCON1_CDENTX (1 << 13)
-#define SYSCON1_CDENRX (1 << 14)
-#define SYSCON1_SIREN (1 << 15)
-#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
-#define SYSCON1_ADCKSEL_MASK (3 << 16)
-#define SYSCON1_EXCKEN (1 << 18)
-#define SYSCON1_WAKEDIS (1 << 19)
-#define SYSCON1_IRTXM (1 << 20)
-
-/* common bits: SYSFLG1 / SYSFLG2 */
-#define SYSFLG_UBUSY (1 << 11)
-#define SYSFLG_URXFE (1 << 22)
-#define SYSFLG_UTXFF (1 << 23)
-
-#define SYSFLG1_MCDR (1 << 0)
-#define SYSFLG1_DCDET (1 << 1)
-#define SYSFLG1_WUDR (1 << 2)
-#define SYSFLG1_WUON (1 << 3)
-#define SYSFLG1_CTS (1 << 8)
-#define SYSFLG1_DSR (1 << 9)
-#define SYSFLG1_DCD (1 << 10)
-#define SYSFLG1_UBUSY SYSFLG_UBUSY
-#define SYSFLG1_NBFLG (1 << 12)
-#define SYSFLG1_RSTFLG (1 << 13)
-#define SYSFLG1_PFFLG (1 << 14)
-#define SYSFLG1_CLDFLG (1 << 15)
-#define SYSFLG1_URXFE SYSFLG_URXFE
-#define SYSFLG1_UTXFF SYSFLG_UTXFF
-#define SYSFLG1_CRXFE (1 << 24)
-#define SYSFLG1_CTXFF (1 << 25)
-#define SYSFLG1_SSIBUSY (1 << 26)
-#define SYSFLG1_ID (1 << 29)
-
-#define SYSFLG2_SSRXOF (1 << 0)
-#define SYSFLG2_RESVAL (1 << 1)
-#define SYSFLG2_RESFRM (1 << 2)
-#define SYSFLG2_SS2RXFE (1 << 3)
-#define SYSFLG2_SS2TXFF (1 << 4)
-#define SYSFLG2_SS2TXUF (1 << 5)
-#define SYSFLG2_CKMODE (1 << 6)
-#define SYSFLG2_UBUSY SYSFLG_UBUSY
-#define SYSFLG2_URXFE SYSFLG_URXFE
-#define SYSFLG2_UTXFF SYSFLG_UTXFF
-
-#define LCDCON_GSEN (1 << 30)
-#define LCDCON_GSMD (1 << 31)
-
-#define SYSCON2_SERSEL (1 << 0)
-#define SYSCON2_KBD6 (1 << 1)
-#define SYSCON2_DRAMZ (1 << 2)
-#define SYSCON2_KBWEN (1 << 3)
-#define SYSCON2_SS2TXEN (1 << 4)
-#define SYSCON2_PCCARD1 (1 << 5)
-#define SYSCON2_PCCARD2 (1 << 6)
-#define SYSCON2_SS2RXEN (1 << 7)
-#define SYSCON2_UART2EN SYSCON_UARTEN
-#define SYSCON2_SS2MAEN (1 << 9)
-#define SYSCON2_OSTB (1 << 12)
-#define SYSCON2_CLKENSL (1 << 13)
-#define SYSCON2_BUZFREQ (1 << 14)
-
-/* common bits: UARTDR1 / UARTDR2 */
-#define UARTDR_FRMERR (1 << 8)
-#define UARTDR_PARERR (1 << 9)
-#define UARTDR_OVERR (1 << 10)
-
-/* common bits: UBRLCR1 / UBRLCR2 */
-#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
-#define UBRLCR_BREAK (1 << 12)
-#define UBRLCR_PRTEN (1 << 13)
-#define UBRLCR_EVENPRT (1 << 14)
-#define UBRLCR_XSTOP (1 << 15)
-#define UBRLCR_FIFOEN (1 << 16)
-#define UBRLCR_WRDLEN5 (0 << 17)
-#define UBRLCR_WRDLEN6 (1 << 17)
-#define UBRLCR_WRDLEN7 (2 << 17)
-#define UBRLCR_WRDLEN8 (3 << 17)
-#define UBRLCR_WRDLEN_MASK (3 << 17)
-
-#define SYNCIO_SMCKEN (1 << 13)
-#define SYNCIO_TXFRMEN (1 << 14)
-
-#define DAIR_DAIEN (1 << 16)
-#define DAIR_ECS (1 << 17)
-#define DAIR_LCTM (1 << 19)
-#define DAIR_LCRM (1 << 20)
-#define DAIR_RCTM (1 << 21)
-#define DAIR_RCRM (1 << 22)
-#define DAIR_LBM (1 << 23)
-
-#define DAIDR2_FIFOEN (1 << 15)
-#define DAIDR2_FIFOLEFT (0x0d << 16)
-#define DAIDR2_FIFORIGHT (0x11 << 16)
-
-#define DAISR_RCTS (1 << 0)
-#define DAISR_RCRS (1 << 1)
-#define DAISR_LCTS (1 << 2)
-#define DAISR_LCRS (1 << 3)
-#define DAISR_RCTU (1 << 4)
-#define DAISR_RCRO (1 << 5)
-#define DAISR_LCTU (1 << 6)
-#define DAISR_LCRO (1 << 7)
-#define DAISR_RCNF (1 << 8)
-#define DAISR_RCNE (1 << 9)
-#define DAISR_LCNF (1 << 10)
-#define DAISR_LCNE (1 << 11)
-#define DAISR_FIFO (1 << 12)
-
-#define SYSCON3_ADCCON (1 << 0)
-#define SYSCON3_DAISEL (1 << 3)
-#define SYSCON3_ADCCKNSEN (1 << 4)
-#define SYSCON3_FASTWAKE (1 << 8)
-#define SYSCON3_DAIEN (1 << 9)
-
-#define SDCONF_ACTIVE (1 << 10)
-#define SDCONF_CLKCTL (1 << 9)
-#define SDCONF_WIDTH_4 (0 << 7)
-#define SDCONF_WIDTH_8 (1 << 7)
-#define SDCONF_WIDTH_16 (2 << 7)
-#define SDCONF_WIDTH_32 (3 << 7)
-#define SDCONF_SIZE_16 (0 << 5)
-#define SDCONF_SIZE_64 (1 << 5)
-#define SDCONF_SIZE_128 (2 << 5)
-#define SDCONF_SIZE_256 (3 << 5)
-#define SDCONF_CASLAT_2 (2)
-#define SDCONF_CASLAT_3 (3)
-
-#endif /* __ASM_HARDWARE_CLPS7111_H */
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
new file mode 100644
index 0000000..3e07591
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -0,0 +1,232 @@
+/*
+ * This file contains the hardware definitions of the Cirrus Logic
+ * ARM7 CLPS711X internal registers.
+ *
+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __MACH_CLPS711X_H
+#define __MACH_CLPS711X_H
+
+#define CLPS711X_PHYS_BASE (0x80000000)
+
+#define PADR (0x0000)
+#define PBDR (0x0001)
+#define PCDR (0x0002)
+#define PDDR (0x0003)
+#define PADDR (0x0040)
+#define PBDDR (0x0041)
+#define PCDDR (0x0042)
+#define PDDDR (0x0043)
+#define PEDR (0x0080)
+#define PEDDR (0x00c0)
+#define SYSCON1 (0x0100)
+#define SYSFLG1 (0x0140)
+#define MEMCFG1 (0x0180)
+#define MEMCFG2 (0x01c0)
+#define DRFPR (0x0200)
+#define INTSR1 (0x0240)
+#define INTMR1 (0x0280)
+#define LCDCON (0x02c0)
+#define TC1D (0x0300)
+#define TC2D (0x0340)
+#define RTCDR (0x0380)
+#define RTCMR (0x03c0)
+#define PMPCON (0x0400)
+#define CODR (0x0440)
+#define UARTDR1 (0x0480)
+#define UBRLCR1 (0x04c0)
+#define SYNCIO (0x0500)
+#define PALLSW (0x0540)
+#define PALMSW (0x0580)
+#define STFCLR (0x05c0)
+#define BLEOI (0x0600)
+#define MCEOI (0x0640)
+#define TEOI (0x0680)
+#define TC1EOI (0x06c0)
+#define TC2EOI (0x0700)
+#define RTCEOI (0x0740)
+#define UMSEOI (0x0780)
+#define COEOI (0x07c0)
+#define HALT (0x0800)
+#define STDBY (0x0840)
+
+#define FBADDR (0x1000)
+#define SYSCON2 (0x1100)
+#define SYSFLG2 (0x1140)
+#define INTSR2 (0x1240)
+#define INTMR2 (0x1280)
+#define UARTDR2 (0x1480)
+#define UBRLCR2 (0x14c0)
+#define SS2DR (0x1500)
+#define SRXEOF (0x1600)
+#define SS2POP (0x16c0)
+#define KBDEOI (0x1700)
+
+#define DAIR (0x2000)
+#define DAIR0 (0x2040)
+#define DAIDR1 (0x2080)
+#define DAIDR2 (0x20c0)
+#define DAISR (0x2100)
+#define SYSCON3 (0x2200)
+#define INTSR3 (0x2240)
+#define INTMR3 (0x2280)
+#define LEDFLSH (0x22c0)
+#define SDCONF (0x2300)
+#define SDRFPR (0x2340)
+
+/* common bits: SYSCON1 / SYSCON2 */
+#define SYSCON_UARTEN (1 << 8)
+
+#define SYSCON1_KBDSCAN(x) ((x) & 15)
+#define SYSCON1_KBDSCANMASK (15)
+#define SYSCON1_TC1M (1 << 4)
+#define SYSCON1_TC1S (1 << 5)
+#define SYSCON1_TC2M (1 << 6)
+#define SYSCON1_TC2S (1 << 7)
+#define SYSCON1_UART1EN SYSCON_UARTEN
+#define SYSCON1_BZTOG (1 << 9)
+#define SYSCON1_BZMOD (1 << 10)
+#define SYSCON1_DBGEN (1 << 11)
+#define SYSCON1_LCDEN (1 << 12)
+#define SYSCON1_CDENTX (1 << 13)
+#define SYSCON1_CDENRX (1 << 14)
+#define SYSCON1_SIREN (1 << 15)
+#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
+#define SYSCON1_ADCKSEL_MASK (3 << 16)
+#define SYSCON1_EXCKEN (1 << 18)
+#define SYSCON1_WAKEDIS (1 << 19)
+#define SYSCON1_IRTXM (1 << 20)
+
+/* common bits: SYSFLG1 / SYSFLG2 */
+#define SYSFLG_UBUSY (1 << 11)
+#define SYSFLG_URXFE (1 << 22)
+#define SYSFLG_UTXFF (1 << 23)
+
+#define SYSFLG1_MCDR (1 << 0)
+#define SYSFLG1_DCDET (1 << 1)
+#define SYSFLG1_WUDR (1 << 2)
+#define SYSFLG1_WUON (1 << 3)
+#define SYSFLG1_CTS (1 << 8)
+#define SYSFLG1_DSR (1 << 9)
+#define SYSFLG1_DCD (1 << 10)
+#define SYSFLG1_UBUSY SYSFLG_UBUSY
+#define SYSFLG1_NBFLG (1 << 12)
+#define SYSFLG1_RSTFLG (1 << 13)
+#define SYSFLG1_PFFLG (1 << 14)
+#define SYSFLG1_CLDFLG (1 << 15)
+#define SYSFLG1_URXFE SYSFLG_URXFE
+#define SYSFLG1_UTXFF SYSFLG_UTXFF
+#define SYSFLG1_CRXFE (1 << 24)
+#define SYSFLG1_CTXFF (1 << 25)
+#define SYSFLG1_SSIBUSY (1 << 26)
+#define SYSFLG1_ID (1 << 29)
+
+#define SYSFLG2_SSRXOF (1 << 0)
+#define SYSFLG2_RESVAL (1 << 1)
+#define SYSFLG2_RESFRM (1 << 2)
+#define SYSFLG2_SS2RXFE (1 << 3)
+#define SYSFLG2_SS2TXFF (1 << 4)
+#define SYSFLG2_SS2TXUF (1 << 5)
+#define SYSFLG2_CKMODE (1 << 6)
+#define SYSFLG2_UBUSY SYSFLG_UBUSY
+#define SYSFLG2_URXFE SYSFLG_URXFE
+#define SYSFLG2_UTXFF SYSFLG_UTXFF
+
+#define LCDCON_GSEN (1 << 30)
+#define LCDCON_GSMD (1 << 31)
+
+#define SYSCON2_SERSEL (1 << 0)
+#define SYSCON2_KBD6 (1 << 1)
+#define SYSCON2_DRAMZ (1 << 2)
+#define SYSCON2_KBWEN (1 << 3)
+#define SYSCON2_SS2TXEN (1 << 4)
+#define SYSCON2_PCCARD1 (1 << 5)
+#define SYSCON2_PCCARD2 (1 << 6)
+#define SYSCON2_SS2RXEN (1 << 7)
+#define SYSCON2_UART2EN SYSCON_UARTEN
+#define SYSCON2_SS2MAEN (1 << 9)
+#define SYSCON2_OSTB (1 << 12)
+#define SYSCON2_CLKENSL (1 << 13)
+#define SYSCON2_BUZFREQ (1 << 14)
+
+/* common bits: UARTDR1 / UARTDR2 */
+#define UARTDR_FRMERR (1 << 8)
+#define UARTDR_PARERR (1 << 9)
+#define UARTDR_OVERR (1 << 10)
+
+/* common bits: UBRLCR1 / UBRLCR2 */
+#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
+#define UBRLCR_BREAK (1 << 12)
+#define UBRLCR_PRTEN (1 << 13)
+#define UBRLCR_EVENPRT (1 << 14)
+#define UBRLCR_XSTOP (1 << 15)
+#define UBRLCR_FIFOEN (1 << 16)
+#define UBRLCR_WRDLEN5 (0 << 17)
+#define UBRLCR_WRDLEN6 (1 << 17)
+#define UBRLCR_WRDLEN7 (2 << 17)
+#define UBRLCR_WRDLEN8 (3 << 17)
+#define UBRLCR_WRDLEN_MASK (3 << 17)
+
+#define SYNCIO_SMCKEN (1 << 13)
+#define SYNCIO_TXFRMEN (1 << 14)
+
+#define DAIR_DAIEN (1 << 16)
+#define DAIR_ECS (1 << 17)
+#define DAIR_LCTM (1 << 19)
+#define DAIR_LCRM (1 << 20)
+#define DAIR_RCTM (1 << 21)
+#define DAIR_RCRM (1 << 22)
+#define DAIR_LBM (1 << 23)
+
+#define DAIDR2_FIFOEN (1 << 15)
+#define DAIDR2_FIFOLEFT (0x0d << 16)
+#define DAIDR2_FIFORIGHT (0x11 << 16)
+
+#define DAISR_RCTS (1 << 0)
+#define DAISR_RCRS (1 << 1)
+#define DAISR_LCTS (1 << 2)
+#define DAISR_LCRS (1 << 3)
+#define DAISR_RCTU (1 << 4)
+#define DAISR_RCRO (1 << 5)
+#define DAISR_LCTU (1 << 6)
+#define DAISR_LCRO (1 << 7)
+#define DAISR_RCNF (1 << 8)
+#define DAISR_RCNE (1 << 9)
+#define DAISR_LCNF (1 << 10)
+#define DAISR_LCNE (1 << 11)
+#define DAISR_FIFO (1 << 12)
+
+#define SYSCON3_ADCCON (1 << 0)
+#define SYSCON3_DAISEL (1 << 3)
+#define SYSCON3_ADCCKNSEN (1 << 4)
+#define SYSCON3_FASTWAKE (1 << 8)
+#define SYSCON3_DAIEN (1 << 9)
+
+#define SDCONF_ACTIVE (1 << 10)
+#define SDCONF_CLKCTL (1 << 9)
+#define SDCONF_WIDTH_4 (0 << 7)
+#define SDCONF_WIDTH_8 (1 << 7)
+#define SDCONF_WIDTH_16 (2 << 7)
+#define SDCONF_WIDTH_32 (3 << 7)
+#define SDCONF_SIZE_16 (0 << 5)
+#define SDCONF_SIZE_64 (1 << 5)
+#define SDCONF_SIZE_128 (2 << 5)
+#define SDCONF_SIZE_256 (3 << 5)
+#define SDCONF_CASLAT_2 (2)
+#define SDCONF_CASLAT_3 (3)
+
+#endif /* __MACH_CLPS711X_H */
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index d31fc79..13a64fc 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -22,7 +22,7 @@
#ifndef __MACH_HARDWARE_H
#define __MACH_HARDWARE_H
-#include <asm/hardware/clps7111.h>
+#include <mach/clps711x.h>
#define CLPS711X_VIRT_BASE IOMEM(0xff000000)
diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h
index 263f839..7b28d6a 100644
--- a/arch/arm/mach-clps711x/include/mach/uncompress.h
+++ b/arch/arm/mach-clps711x/include/mach/uncompress.h
@@ -17,7 +17,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#include <asm/hardware/clps7111.h>
+#include <mach/clps711x.h>
#ifdef CONFIG_DEBUG_CLPS711X_UART2
#define SYSFLGx SYSFLG2
--
1.7.3.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/4] ARM: clps711x: Added missing register definitions
2012-05-14 17:46 [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file Alexander Shiyan
@ 2012-05-14 17:46 ` Alexander Shiyan
2012-05-14 17:46 ` [PATCH 3/4] ARM: clps711x: Added note about support EP731x CPU to Kconfig Alexander Shiyan
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Alexander Shiyan @ 2012-05-14 17:46 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/mach-clps711x/include/mach/clps711x.h | 46 ++++++++++++++++++++++++
1 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 3e07591..1dd806f 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -87,6 +87,14 @@
#define LEDFLSH (0x22c0)
#define SDCONF (0x2300)
#define SDRFPR (0x2340)
+#define UNIQID (0x2440)
+#define DAI64FS (0x2600)
+#define PLLW (0x2610)
+#define PLLR (0xa5a8)
+#define RANDID0 (0x2700)
+#define RANDID1 (0x2704)
+#define RANDID2 (0x2708)
+#define RANDID3 (0x270c)
/* common bits: SYSCON1 / SYSCON2 */
#define SYSCON_UARTEN (1 << 8)
@@ -134,6 +142,8 @@
#define SYSFLG1_CTXFF (1 << 25)
#define SYSFLG1_SSIBUSY (1 << 26)
#define SYSFLG1_ID (1 << 29)
+#define SYSFLG1_VERID(x) (((x) >> 30) & 3)
+#define SYSFLG1_VERID_MASK (3 << 30)
#define SYSFLG2_SSRXOF (1 << 0)
#define SYSFLG2_RESVAL (1 << 1)
@@ -181,9 +191,12 @@
#define UBRLCR_WRDLEN8 (3 << 17)
#define UBRLCR_WRDLEN_MASK (3 << 17)
+#define SYNCIO_FRMLEN(x) (((x) & 0x3f) << 7)
+#define SYNCIO_CFGLEN(x) ((x) & 0x7f)
#define SYNCIO_SMCKEN (1 << 13)
#define SYNCIO_TXFRMEN (1 << 14)
+#define DAIR_RESERVED (0x0404)
#define DAIR_DAIEN (1 << 16)
#define DAIR_ECS (1 << 17)
#define DAIR_LCTM (1 << 19)
@@ -210,11 +223,23 @@
#define DAISR_LCNE (1 << 11)
#define DAISR_FIFO (1 << 12)
+#define DAI64FS_I2SF64 (1 << 0)
+#define DAI64FS_AUDIOCLKEN (1 << 1)
+#define DAI64FS_AUDIOCLKSRC (1 << 2)
+#define DAI64FS_MCLK256EN (1 << 3)
+#define DAI64FS_LOOPBACK (1 << 5)
+
#define SYSCON3_ADCCON (1 << 0)
+#define SYSCON3_CLKCTL0 (1 << 1)
+#define SYSCON3_CLKCTL1 (1 << 2)
#define SYSCON3_DAISEL (1 << 3)
#define SYSCON3_ADCCKNSEN (1 << 4)
+#define SYSCON3_VERSN(x) (((x) >> 5) & 7)
+#define SYSCON3_VERSN_MASK (7 << 5)
#define SYSCON3_FASTWAKE (1 << 8)
#define SYSCON3_DAIEN (1 << 9)
+#define SYSCON3_128FS SYSCON3_DAIEN
+#define SYSCON3_ENPD67 (1 << 10)
#define SDCONF_ACTIVE (1 << 10)
#define SDCONF_CLKCTL (1 << 9)
@@ -229,4 +254,25 @@
#define SDCONF_CASLAT_2 (2)
#define SDCONF_CASLAT_3 (3)
+#define MEMCFG_BUS_WIDTH_32 (1)
+#define MEMCFG_BUS_WIDTH_16 (0)
+#define MEMCFG_BUS_WIDTH_8 (3)
+
+#define MEMCFG_WAITSTATE_8_3 (0 << 2)
+#define MEMCFG_WAITSTATE_7_3 (1 << 2)
+#define MEMCFG_WAITSTATE_6_3 (2 << 2)
+#define MEMCFG_WAITSTATE_5_3 (3 << 2)
+#define MEMCFG_WAITSTATE_4_2 (4 << 2)
+#define MEMCFG_WAITSTATE_3_2 (5 << 2)
+#define MEMCFG_WAITSTATE_2_2 (6 << 2)
+#define MEMCFG_WAITSTATE_1_2 (7 << 2)
+#define MEMCFG_WAITSTATE_8_1 (8 << 2)
+#define MEMCFG_WAITSTATE_7_1 (9 << 2)
+#define MEMCFG_WAITSTATE_6_1 (10 << 2)
+#define MEMCFG_WAITSTATE_5_1 (11 << 2)
+#define MEMCFG_WAITSTATE_4_0 (12 << 2)
+#define MEMCFG_WAITSTATE_3_0 (13 << 2)
+#define MEMCFG_WAITSTATE_2_0 (14 << 2)
+#define MEMCFG_WAITSTATE_1_0 (15 << 2)
+
#endif /* __MACH_CLPS711X_H */
--
1.7.3.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/4] ARM: clps711x: Added note about support EP731x CPU to Kconfig
2012-05-14 17:46 [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file Alexander Shiyan
2012-05-14 17:46 ` [PATCH 2/4] ARM: clps711x: Added missing register definitions Alexander Shiyan
@ 2012-05-14 17:46 ` Alexander Shiyan
2012-05-14 17:46 ` [PATCH 4/4] ARM clps711x: Removed unused header mach/time.h Alexander Shiyan
2012-05-14 18:46 ` [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file Arnd Bergmann
3 siblings, 0 replies; 6+ messages in thread
From: Alexander Shiyan @ 2012-05-14 17:46 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/Kconfig | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf006d4..2437ff2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -373,12 +373,12 @@ config ARCH_HIGHBANK
Support for the Calxeda Highbank SoC based boards.
config ARCH_CLPS711X
- bool "Cirrus Logic CLPS711x/EP721x-based"
+ bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select CPU_ARM720T
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_MEMORY_H
help
- Support for Cirrus Logic 711x/721x based boards.
+ Support for Cirrus Logic 711x/721x/731x based boards.
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family"
--
1.7.3.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] ARM clps711x: Removed unused header mach/time.h
2012-05-14 17:46 [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file Alexander Shiyan
2012-05-14 17:46 ` [PATCH 2/4] ARM: clps711x: Added missing register definitions Alexander Shiyan
2012-05-14 17:46 ` [PATCH 3/4] ARM: clps711x: Added note about support EP731x CPU to Kconfig Alexander Shiyan
@ 2012-05-14 17:46 ` Alexander Shiyan
2012-05-14 18:46 ` [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file Arnd Bergmann
3 siblings, 0 replies; 6+ messages in thread
From: Alexander Shiyan @ 2012-05-14 17:46 UTC (permalink / raw)
To: linux-arm-kernel
All functions from this header already provided by common.c
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/mach-clps711x/include/mach/time.h | 49 ----------------------------
1 files changed, 0 insertions(+), 49 deletions(-)
delete mode 100644 arch/arm/mach-clps711x/include/mach/time.h
diff --git a/arch/arm/mach-clps711x/include/mach/time.h b/arch/arm/mach-clps711x/include/mach/time.h
deleted file mode 100644
index 5f65865..0000000
--- a/arch/arm/mach-clps711x/include/mach/time.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * arch/arm/mach-clps711x/include/mach/time.h
- *
- * Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <asm/leds.h>
-#include <mach/hardware.h>
-
-extern void clps711x_setup_timer(void);
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-p720t_timer_interrupt(int irq, void *dev_id)
-{
- struct pt_regs *regs = get_irq_regs();
- do_leds();
- xtime_update(1);
-#ifndef CONFIG_SMP
- update_process_times(user_mode(regs));
-#endif
- do_profile(regs);
- return IRQ_HANDLED;
-}
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-void __init time_init(void)
-{
- clps711x_setup_timer();
- timer_irq.handler = p720t_timer_interrupt;
- setup_irq(IRQ_TC2OI, &timer_irq);
-}
--
1.7.3.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file
2012-05-14 17:46 [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file Alexander Shiyan
` (2 preceding siblings ...)
2012-05-14 17:46 ` [PATCH 4/4] ARM clps711x: Removed unused header mach/time.h Alexander Shiyan
@ 2012-05-14 18:46 ` Arnd Bergmann
[not found] ` <E1SU1SU-0003hN-FS.shc_work-mail-ru@f197.mail.ru>
3 siblings, 1 reply; 6+ messages in thread
From: Arnd Bergmann @ 2012-05-14 18:46 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 14 May 2012, Alexander Shiyan wrote:
>
> Patch created for arm-soc clps711x/cleanup branch.
>
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Hi Alexander,
I've applied these patches to the clps711x/cleanup branch, but I'm
not too happy with the submission form.
Most patches were missing a useful description, which I've had to add
from looking at the contents. In the future I'd expect you to add such
a description yourself, ideally one that explains why you need such a
change, which is something that is not always obvious from the patch
itself.
A comment like "Patch created for arm-soc clps711x/cleanup branch."
is completely meaningless for the changeset description. It should
either go into the [PATCH 0/4] cover letter that git-format-patch
can create for you, or if you send only a single patch, you can put
it between the '---' line and the diffstat, so it appears in the
email but not in the changelog.
Finally, don't send patches just one at a time when you know that
you have more of them. It's annoying for me that I have to go back
to the same branch and merge it repeatedly when you do this. Better
send the entire series at once, or for longer ones, send a git
pull request.
I have not pulled the branches into the main next/cleanup branch,
so they are not yet scheduled for the next merge window (the earlier
two ones are). Let me know whether you have more patches for this series,
I'll put it in once you are done.
Arnd
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file
[not found] ` <E1SU1SU-0003hN-FS.shc_work-mail-ru@f197.mail.ru>
@ 2012-05-14 20:13 ` Arnd Bergmann
0 siblings, 0 replies; 6+ messages in thread
From: Arnd Bergmann @ 2012-05-14 20:13 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 14 May 2012, Alexander Shiyan wrote:
> Mon, 14 May 2012 18:46:12 +0000 ?? Arnd Bergmann <arnd@arndb.de>:
> > On Monday 14 May 2012, Alexander Shiyan wrote:
> ...
> > I've applied these patches to the clps711x/cleanup branch, but I'm
> > not too happy with the submission form.
> >
> > Most patches were missing a useful description, which I've had to add
> > from looking at the contents. In the future I'd expect you to add such
> > a description yourself, ideally one that explains why you need such a
> > change, which is something that is not always obvious from the patch
> > itself.
> The main problem is that I very badly know English.
> I'll try to write in more detail later :)
Don't worry about the quality of the language. Any information is better
than no information here, and a lot of contributors to the kernel don't
write English very well.
> > A comment like "Patch created for arm-soc clps711x/cleanup branch."
> > is completely meaningless for the changeset description. It should
> > either go into the [PATCH 0/4] cover letter that git-format-patch
> > can create for you, or if you send only a single patch, you can put
> > it between the '---' line and the diffstat, so it appears in the
> > email but not in the changelog.
> I've recently been using git. Not yet studied all the features.
> Mean that the option "--compose" must be used for it. Right?
yes, or the --cover-letter option to 'git format-patch', followed
by manually editing the files before you send them out.
> > Finally, don't send patches just one at a time when you know that
> > you have more of them. It's annoying for me that I have to go back
> > to the same branch and merge it repeatedly when you do this. Better
> > send the entire series at once, or for longer ones, send a git
> > pull request.
> I understand that you do not want to frequently switch from one branch to another,
> but I do not quite understand the difference between the patch and pull-request.
A pull request tends to be less work for me than a patch, and if you
send many patches, it's more work than just one, but a pull request
is always the same amount of work (aside from reviewing, which has
to be done anyway).
The problem with sending multiple patch series (or pull requests) for the
same topic is mostly that it messes up the git history by creating extra
merge commits. The extra work for me is actually not all that much of a
problem.
> > I have not pulled the branches into the main next/cleanup branch,
> > so they are not yet scheduled for the next merge window (the earlier
> > two ones are). Let me know whether you have more patches for this series,
> > I'll put it in once you are done.
> Yes, there are two ready-made patch that I am willing to post it. I have a lot of other
> code for that platform, but not yet ready to give it to the kernel, because it requires
> more time to debug some things.
Ok. Just as a reminder, we are almost at the v3.5 merge window and I would prefer
to get patches earlier than this, so at some point in the next few days I'll just
stop taking more patches for 3.5 and everything after that will go into 3.6.
Arnd
^ permalink raw reply [flat|nested] 6+ messages in thread
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2012-05-14 17:46 [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file Alexander Shiyan
2012-05-14 17:46 ` [PATCH 2/4] ARM: clps711x: Added missing register definitions Alexander Shiyan
2012-05-14 17:46 ` [PATCH 3/4] ARM: clps711x: Added note about support EP731x CPU to Kconfig Alexander Shiyan
2012-05-14 17:46 ` [PATCH 4/4] ARM clps711x: Removed unused header mach/time.h Alexander Shiyan
2012-05-14 18:46 ` [PATCH 1/4] ARM: clps711x: Used own subarch directory for store header file Arnd Bergmann
[not found] ` <E1SU1SU-0003hN-FS.shc_work-mail-ru@f197.mail.ru>
2012-05-14 20:13 ` Arnd Bergmann
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