[PATCH] ARM: gic: add irq_set_affinity to gic_arch_extn

[PATCH] ARM: gic: add irq_set_affinity to gic_arch_extn

[Chao Xie]

From: Bin Wang <binw@marvell.com>

Some architectures would shut done the mp logic for certain low power
mode cases, thus it relies on an external interrupt controller to
wake up the cores. In order to keep the same interrupt distribute
mapping as in the gic, here export the irq_set_affinity hook in the
gic_arch_extn.

Signed-off-by: Bin Wang <binw@marvell.com>
---
 arch/arm/common/gic.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 5b60d5e..c3d5b31 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -54,6 +54,7 @@ struct irq_chip gic_arch_extn = {
 	.irq_retrigger	= NULL,
 	.irq_set_type	= NULL,
 	.irq_set_wake	= NULL,
+	.irq_set_affinity = NULL,
 };
 
 #ifndef MAX_GIC_NR
@@ -186,6 +187,10 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 
 	mask = 0xff << shift;
 	raw_spin_lock(&irq_controller_lock);
+
+	if (gic_arch_extn.irq_set_affinity)
+		gic_arch_extn.irq_set_affinity(d, mask_val, false);
+
 	d->node = cpu;
 #ifdef CONFIG_CPU_MMP3
 	cpu = smp_hardid[cpu];
-- 
1.7.0.4

[PATCH] ARM: gic: add irq_set_affinity to gic_arch_extn

[Chao Xie]

gic_arch_extn is used for ARCH specific interrupt controller.
It has added the callbacks for irq_mask/irq_unamsk and so, but
irq_set_affinity is not used.
For SMP architecure, when both cores are powered off, the GIC may
be powered off too. An external interrupt controller can be used
as a logic to detect the interrupt and acknowledge power managment
unitto wake up core.
Because the irqs may be bound to different cors, when set irq
affinity, the external interrupt controller should be set too. Then
it can acknowledge the power managment unit to wake up correct core.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
---
 arch/arm/common/gic.c |   17 +++++++++++------
 1 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 36ae03a..8e4bc8a 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -82,12 +82,15 @@ static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
  * Default make them NULL.
  */
 struct irq_chip gic_arch_extn = {
-	.irq_eoi	= NULL,
-	.irq_mask	= NULL,
-	.irq_unmask	= NULL,
-	.irq_retrigger	= NULL,
-	.irq_set_type	= NULL,
-	.irq_set_wake	= NULL,
+	.irq_eoi		= NULL,
+	.irq_mask		= NULL,
+	.irq_unmask		= NULL,
+	.irq_retrigger		= NULL,
+	.irq_set_type		= NULL,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= NULL,
+#endif
+	.irq_set_wake		= NULL,
 };
 
 #ifndef MAX_GIC_NR
@@ -253,6 +256,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 	bit = gic_cpu_map[cpu] << shift;
 
 	raw_spin_lock(&irq_controller_lock);
+	if (gic_arch_extn.irq_set_affinity)
+		return gic_arch_extn.irq_set_affinity(d, mask_val, force);
 	val = readl_relaxed(reg) & ~mask;
 	writel_relaxed(val | bit, reg);
 	raw_spin_unlock(&irq_controller_lock);
-- 
1.7.4.1

[PATCH] ARM: gic: add irq_set_affinity to gic_arch_extn

[Chao Xie]

On Tue, Jan 29, 2013 at 1:17 PM, Chao Xie <chao.xie@marvell.com> wrote:
> gic_arch_extn is used for ARCH specific interrupt controller.
> It has added the callbacks for irq_mask/irq_unamsk and so, but
> irq_set_affinity is not used.
> For SMP architecure, when both cores are powered off, the GIC may
> be powered off too. An external interrupt controller can be used
> as a logic to detect the interrupt and acknowledge power managment
> unitto wake up core.
> Because the irqs may be bound to different cors, when set irq
> affinity, the external interrupt controller should be set too. Then
> it can acknowledge the power managment unit to wake up correct core.
>
> Signed-off-by: Chao Xie <chao.xie@marvell.com>
> ---
>  arch/arm/common/gic.c |   17 +++++++++++------
>  1 files changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
> index 36ae03a..8e4bc8a 100644
> --- a/arch/arm/common/gic.c
> +++ b/arch/arm/common/gic.c
> @@ -82,12 +82,15 @@ static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
>   * Default make them NULL.
>   */
>  struct irq_chip gic_arch_extn = {
> -       .irq_eoi        = NULL,
> -       .irq_mask       = NULL,
> -       .irq_unmask     = NULL,
> -       .irq_retrigger  = NULL,
> -       .irq_set_type   = NULL,
> -       .irq_set_wake   = NULL,
> +       .irq_eoi                = NULL,
> +       .irq_mask               = NULL,
> +       .irq_unmask             = NULL,
> +       .irq_retrigger          = NULL,
> +       .irq_set_type           = NULL,
> +#ifdef CONFIG_SMP
> +       .irq_set_affinity       = NULL,
> +#endif
> +       .irq_set_wake           = NULL,
>  };
>
>  #ifndef MAX_GIC_NR
> @@ -253,6 +256,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
>         bit = gic_cpu_map[cpu] << shift;
>
>         raw_spin_lock(&irq_controller_lock);
> +       if (gic_arch_extn.irq_set_affinity)
> +               return gic_arch_extn.irq_set_affinity(d, mask_val, force);
>         val = readl_relaxed(reg) & ~mask;
>         writel_relaxed(val | bit, reg);
>         raw_spin_unlock(&irq_controller_lock);
> --
> 1.7.4.1
>

I send the wrong patch, please ignore it, and i will send new one.

[PATCH] ARM: gic: add irq_set_affinity to gic_arch_extn

[Chao Xie]

gic_arch_extn is used for ARCH specific interrupt controller.
It has added the callbacks for irq_mask/irq_unamsk and so, but
irq_set_affinity is not used.
For SMP architecure, when both cores are powered off, the GIC may
be powered off too. An external interrupt controller can be used
as a logic to detect the interrupt and acknowledge power managment
unitto wake up core.
Because the irqs may be bound to different cors, when set irq
affinity, the external interrupt controller should be set too. Then
it can acknowledge the power managment unit to wake up correct core.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
---
 arch/arm/common/gic.c |   27 ++++++++++++++++++---------
 1 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 36ae03a..49920a0 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -82,12 +82,15 @@ static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
  * Default make them NULL.
  */
 struct irq_chip gic_arch_extn = {
-	.irq_eoi	= NULL,
-	.irq_mask	= NULL,
-	.irq_unmask	= NULL,
-	.irq_retrigger	= NULL,
-	.irq_set_type	= NULL,
-	.irq_set_wake	= NULL,
+	.irq_eoi		= NULL,
+	.irq_mask		= NULL,
+	.irq_unmask		= NULL,
+	.irq_retrigger		= NULL,
+	.irq_set_type		= NULL,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= NULL,
+#endif
+	.irq_set_wake		= NULL,
 };
 
 #ifndef MAX_GIC_NR
@@ -245,6 +248,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 	unsigned int shift = (gic_irq(d) % 4) * 8;
 	unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
 	u32 val, mask, bit;
+	int ret = IRQ_SET_MASK_OK;
 
 	if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
 		return -EINVAL;
@@ -253,11 +257,16 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 	bit = gic_cpu_map[cpu] << shift;
 
 	raw_spin_lock(&irq_controller_lock);
-	val = readl_relaxed(reg) & ~mask;
-	writel_relaxed(val | bit, reg);
+	if (gic_arch_extn.irq_set_affinity)
+		ret = gic_arch_extn.irq_set_affinity(d, mask_val, force);
+
+	if (ret == IRQ_SET_MASK_OK) {
+		val = readl_relaxed(reg) & ~mask;
+		writel_relaxed(val | bit, reg);
+	}
 	raw_spin_unlock(&irq_controller_lock);
 
-	return IRQ_SET_MASK_OK;
+	return ret;
 }
 #endif
 
-- 
1.7.4.1