[RFC PATCHv3 0/2] arm: socfpga: Add initial support for Altera's SOCFPGA HW

[RFC PATCHv3 0/2] arm: socfpga: Add initial support for Altera's SOCFPGA HW

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

This patch series add minimal support for Altera's SOCFPGA hardward.

Changes since v2:
- Make use of COMMON_CLK - socfpga folder under drivers/clk
- Add maintainer entry for drivers/clk/socfpga
- Incorporated changes suggestd by Thomas Petazzoni, Arnd Bergmann,
and Rob Herring
- Added Reviewed-by: Rob Herring <rob.herring@calxeda.com>

Changes since v1:
- Incorporate changes suggested by Pavel Machek, Thommas Petazzoni,
  Arnd Bergmann, and Rob Herring
- Reduce the patch to a make as much use of DTS as possible

Dinh Nguyen (2):
  ARM: socfpga: initial support for Altera's SOCFPGA platform
  ARM: socfpga: Add DTS bindings for Altera's SOCFPGA

-- 
1.7.9.5

[RFC PATCHv3 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Adding core definitions for Altera's SOCFPGA ARM platform.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
---
 MAINTAINERS                                      |   10 ++++
 arch/arm/Kconfig                                 |   19 +++++++
 arch/arm/Makefile                                |    1 +
 arch/arm/mach-socfpga/Makefile                   |    5 ++
 arch/arm/mach-socfpga/Makefile.boot              |    1 +
 arch/arm/mach-socfpga/common.h                   |   24 +++++++++
 arch/arm/mach-socfpga/include/mach/debug-macro.S |   16 ++++++
 arch/arm/mach-socfpga/include/mach/timex.h       |   19 +++++++
 arch/arm/mach-socfpga/include/mach/uncompress.h  |    9 ++++
 arch/arm/mach-socfpga/socfpga.c                  |   62 ++++++++++++++++++++++
 drivers/clk/Makefile                             |    1 +
 drivers/clk/socfpga/Makefile                     |    1 +
 drivers/clk/socfpga/clk.c                        |   47 ++++++++++++++++
 13 files changed, 215 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/Makefile
 create mode 100644 arch/arm/mach-socfpga/Makefile.boot
 create mode 100644 arch/arm/mach-socfpga/common.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-socfpga/include/mach/timex.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-socfpga/socfpga.c
 create mode 100644 drivers/clk/socfpga/Makefile
 create mode 100644 drivers/clk/socfpga/clk.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 1b71f6c..0239cdb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1103,6 +1103,16 @@ S:	Supported
 F:	arch/arm/mach-shmobile/
 F:	drivers/sh/
 
+ARM/SOCFPGA ARCHITECTURE
+M:	Dinh Nguyen <dinguyen@altera.com>
+S:	Maintained
+F:	arch/arm/mach-socfpga/
+
+ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT
+M:	Dinh Nguyen <dinguyen@altera.com>
+S:	Maintained
+F:	drivers/clk/socfpga/
+
 ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
 M:	Lennert Buytenhek <kernel@wantstofly.org>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 57eb6ef..b9f5fc9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -250,6 +250,25 @@ choice
 	prompt "ARM system type"
 	default ARCH_VERSATILE
 
+config ARCH_SOCFPGA
+	bool "Altera SOCFPGA family"
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select CACHE_L2X0
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select CPU_V7
+	select DW_APB_TIMER
+	select DW_APB_TIMER_OF
+	select GENERIC_CLOCKEVENTS
+	select GPIO_PL061 if GPIOLIB
+	select HAVE_ARM_SCU
+	select SPARSE_IRQ
+	select USE_OF
+	help
+	  This enables support for Altera SOCFPGA Cyclone V platform
+
 config ARCH_INTEGRATOR
 	bool "ARM Ltd. Integrator family"
 	select ARM_AMBA
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0298b00..1fe5702 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -193,6 +193,7 @@ machine-$(CONFIG_MACH_SPEAR310)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR320)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR600)		:= spear6xx
 machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
+machine-$(CONFIG_ARCH_SOCFPGA) 	:= socfpga
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
new file mode 100644
index 0000000..4fb9324
--- /dev/null
+++ b/arch/arm/mach-socfpga/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y					:= socfpga.o
diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot
new file mode 100644
index 0000000..dae9661
--- /dev/null
+++ b/arch/arm/mach-socfpga/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y	:= 0x00008000
diff --git a/arch/arm/mach-socfpga/common.h b/arch/arm/mach-socfpga/common.h
new file mode 100644
index 0000000..edb7bde
--- /dev/null
+++ b/arch/arm/mach-socfpga/common.h
@@ -0,0 +1,24 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_SOCFPGA_COMMON_H
+#define __MACH_SOCFPGA_COMMON_H
+
+extern struct sys_timer dw_apb_timer;
+extern void socfpga_init_clocks(void);
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/debug-macro.S b/arch/arm/mach-socfpga/include/mach/debug-macro.S
new file mode 100644
index 0000000..d6f26d2
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/debug-macro.S
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+		.macro	addruart, rp, rv, tmp
+		mov	\rp, #DEBUG_LL_UART_OFFSET
+		orr	\rp, \rp, #0x00c00000
+		orr	\rv, \rp, #0xfe000000	@ virtual base
+		orr	\rp, \rp, #0xff000000	@ physical base
+		.endm
+
diff --git a/arch/arm/mach-socfpga/include/mach/timex.h b/arch/arm/mach-socfpga/include/mach/timex.h
new file mode 100644
index 0000000..43df435
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE		(50000000 / 16)
diff --git a/arch/arm/mach-socfpga/include/mach/uncompress.h b/arch/arm/mach-socfpga/include/mach/uncompress.h
new file mode 100644
index 0000000..bbe20e6
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/uncompress.h
@@ -0,0 +1,9 @@
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#define putc(c)
+#define flush()
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
new file mode 100644
index 0000000..022c233
--- /dev/null
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -0,0 +1,62 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/dw_apb_timer.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+const static struct of_device_id irq_match[] = {
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{}
+};
+
+static void __init gic_init_irq(void)
+{
+	of_irq_init(irq_match);
+}
+
+static void socfpga_cyclone5_restart(char mode, const char *cmd)
+{
+	/* TODO: */
+}
+
+static void __init socfpga_cyclone5_init(void)
+{
+	l2x0_of_init(0, ~0UL);
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	socfpga_init_clocks();
+}
+
+static const char *altera_dt_match[] = {
+	"altr,socfpga",
+	"altr,socfpga-cyclone5",
+	NULL
+};
+
+DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
+	.init_irq	= gic_init_irq,
+	.handle_irq     = gic_handle_irq,
+	.timer		= &dw_apb_timer,
+	.init_machine	= socfpga_cyclone5_init,
+	.restart	= socfpga_cyclone5_restart,
+	.dt_compat	= altera_dt_match,
+MACHINE_END
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b9a5158..96014e8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -4,4 +4,5 @@ obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
 				   clk-mux.o clk-divider.o clk-fixed-factor.o
 # SoCs specific
 obj-$(CONFIG_ARCH_MXS)		+= mxs/
+obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
new file mode 100644
index 0000000..0303c0b
--- /dev/null
+++ b/drivers/clk/socfpga/Makefile
@@ -0,0 +1 @@
+obj-y += clk.o
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
new file mode 100644
index 0000000..fcd71aa
--- /dev/null
+++ b/drivers/clk/socfpga/clk.c
@@ -0,0 +1,47 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+#define SOCFPGA_MPU_PERIHCLK_FREQ_HZ			(800000000 / 4)
+#define SOCFPGA_L4_MAIN_CLK					(400000000)
+
+struct clk {
+	unsigned long rate;
+};
+
+static struct clk apb_pclk = { .rate = 200000000};
+static struct clk i2c_clk = { .rate = 100000000};
+static struct clk spim_clk = { .rate = 100000000};
+static struct clk mpu_pclk = { .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ};
+static struct clk l4_main_clk = { .rate = SOCFPGA_L4_MAIN_CLK};
+
+static struct clk_lookup lookups[] = {
+	{ .clk = &apb_pclk, .con_id = "apb_pclk", },
+	{ .clk = &i2c_clk, .dev_id = "ffc04000.i2c", },
+	{ .clk = &i2c_clk, .dev_id = "ffc05000.i2c", },
+	{ .clk = &spim_clk, .dev_id = "dw-spi-mmio.0", },
+	{ .clk = &spim_clk, .dev_id = "dw-spi-mmio.1", },
+	{ .clk = &mpu_pclk, .dev_id = "smp_twd", },
+	{ .clk = &l4_main_clk, .dev_id = "dma-pl330", },
+};
+
+void __init socfpga_init_clocks(void)
+{
+	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+}
-- 
1.7.9.5

[RFC PATCHv3 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform

[Thomas Petazzoni]

Hello,

Le Tue, 17 Jul 2012 18:50:55 -0600,
<dinguyen@altera.com> a ?crit :

> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Adding core definitions for Altera's SOCFPGA ARM platform.

Looks much better, but I have one more comment, below.

> diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
> new file mode 100644
> index 0000000..fcd71aa
> --- /dev/null
> +++ b/drivers/clk/socfpga/clk.c
> @@ -0,0 +1,47 @@
> +/*
> + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +
> +#define SOCFPGA_MPU_PERIHCLK_FREQ_HZ			(800000000 / 4)
> +#define SOCFPGA_L4_MAIN_CLK					(400000000)
> +
> +struct clk {
> +	unsigned long rate;
> +};
> +
> +static struct clk apb_pclk = { .rate = 200000000};
> +static struct clk i2c_clk = { .rate = 100000000};
> +static struct clk spim_clk = { .rate = 100000000};
> +static struct clk mpu_pclk = { .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ};
> +static struct clk l4_main_clk = { .rate = SOCFPGA_L4_MAIN_CLK};
> +
> +static struct clk_lookup lookups[] = {
> +	{ .clk = &apb_pclk, .con_id = "apb_pclk", },
> +	{ .clk = &i2c_clk, .dev_id = "ffc04000.i2c", },
> +	{ .clk = &i2c_clk, .dev_id = "ffc05000.i2c", },
> +	{ .clk = &spim_clk, .dev_id = "dw-spi-mmio.0", },
> +	{ .clk = &spim_clk, .dev_id = "dw-spi-mmio.1", },
> +	{ .clk = &mpu_pclk, .dev_id = "smp_twd", },
> +	{ .clk = &l4_main_clk, .dev_id = "dma-pl330", },
> +};
> +
> +void __init socfpga_init_clocks(void)
> +{
> +	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
> +}

I am not sure this is the proper way of using the clock framework.
Individual platforms should no longer define their own "struct clk".
They should either use the common clock types (fixed rate, fixed
factor, divider, mux, gate, etc.). or implement their own specialized
clock types.

So in your case, since you apparently only have fixed rate clock, you
would use clk_register_fixed_rate() to register your clocks, and it
would return to you an opaque 'struct clk' reference.

For more details, you can look at Documentation/clk.txt.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[RFC PATCHv3 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform

[Pavel Machek]

Hi!

> > +struct clk {
> > +	unsigned long rate;
> > +};
> > +
> > +static struct clk apb_pclk = { .rate = 200000000};
> > +static struct clk i2c_clk = { .rate = 100000000};
> > +static struct clk spim_clk = { .rate = 100000000};
> > +static struct clk mpu_pclk = { .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ};
> > +static struct clk l4_main_clk = { .rate = SOCFPGA_L4_MAIN_CLK};
> > +
> > +static struct clk_lookup lookups[] = {
> > +	{ .clk = &apb_pclk, .con_id = "apb_pclk", },
> > +	{ .clk = &i2c_clk, .dev_id = "ffc04000.i2c", },
> > +	{ .clk = &i2c_clk, .dev_id = "ffc05000.i2c", },
> > +	{ .clk = &spim_clk, .dev_id = "dw-spi-mmio.0", },
> > +	{ .clk = &spim_clk, .dev_id = "dw-spi-mmio.1", },
> > +	{ .clk = &mpu_pclk, .dev_id = "smp_twd", },
> > +	{ .clk = &l4_main_clk, .dev_id = "dma-pl330", },
> > +};
> > +
> > +void __init socfpga_init_clocks(void)
> > +{
> > +	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
> > +}
> 
> I am not sure this is the proper way of using the clock framework.
> Individual platforms should no longer define their own "struct clk".
> They should either use the common clock types (fixed rate, fixed
> factor, divider, mux, gate, etc.). or implement their own specialized
> clock types.
> 
> So in your case, since you apparently only have fixed rate clock, you
> would use clk_register_fixed_rate() to register your clocks, and it
> would return to you an opaque 'struct clk' reference.
> 
> For more details, you can look at Documentation/clk.txt.

Ok, I had version that did that at one point. But... as bootloader
currently sets up the clock, this code is currently mostly unused. So
what about removing it from initial merge and re-adding it when it is
used/neccessary?

								Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[RFC PATCHv3 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform

[Arnd Bergmann]

On Wednesday 18 July 2012, dinguyen at altera.com wrote:
> +struct clk {
> +       unsigned long rate;
> +};
> +
> +static struct clk apb_pclk = { .rate = 200000000};
> +static struct clk i2c_clk = { .rate = 100000000};
> +static struct clk spim_clk = { .rate = 100000000};
> +static struct clk mpu_pclk = { .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ};
> +static struct clk l4_main_clk = { .rate = SOCFPGA_L4_MAIN_CLK};
> +
> +static struct clk_lookup lookups[] = {
> +       { .clk = &apb_pclk, .con_id = "apb_pclk", },

I have one comment left: You still define "struct clk" privately here,
which means that any driver using clk_get and clk_get_rate will
access an invalid data structure and not get the rate you put in here.

I believe you just need to be using clk_register_fixed_rate()
rather than defining the clk structures statically.

	Arnd

[RFC PATCHv3 2/2] ARM: socfpga: Add DTS bindings for Altera's SOCFPGA

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Add the dts, dtsi, and socfpga_defconfig for Altera's SOCFPGA
platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
---
 arch/arm/boot/dts/socfpga.dtsi         |  119 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/socfpga_cyclone5.dts |   71 +++++++++++++++++++
 arch/arm/configs/socfpga_defconfig     |   83 ++++++++++++++++++++++
 3 files changed, 273 insertions(+)
 create mode 100644 arch/arm/boot/dts/socfpga.dtsi
 create mode 100644 arch/arm/boot/dts/socfpga_cyclone5.dts
 create mode 100644 arch/arm/configs/socfpga_defconfig

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
new file mode 100644
index 0000000..903d4bb
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -0,0 +1,119 @@
+/*
+ *  Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+		cpu at 1 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	intc: intc at fffed000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0xfffed000 0x1000>,
+		      <0xfffec100 0x100>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		device_type = "soc";
+		interrupt-parent = <&intc>;
+		ranges;
+		
+		L2: l2-cache at fffef000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xfffef000 0x1000>;
+			interrupts = <0 38 0x04>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		/* Local timer */
+		timer at fffec600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xfffec600 0x100>;
+			interrupts = <1 13 0xf04>;
+		};
+
+		timer0: timer at ffc08000 {
+			compatible = "snps,dw-apb-timer-sp";
+			interrupts = <0 167 4>;
+			clock-frequency = <200000000>;
+			reg = <0xffc08000 0x1000>;
+		};
+
+		timer1: timer at ffc09000 {
+			compatible = "snps,dw-apb-timer-sp";
+			interrupts = <0 168 4>;
+			clock-frequency = <200000000>;
+			reg = <0xffc09000 0x1000>;
+		};
+
+		timer2: timer at ffd00000 {
+			compatible = "snps,dw-apb-timer-osc";
+			interrupts = <0 169 4>;
+			clock-frequency = <200000000>;
+			reg = <0xffd00000 0x1000>;
+		};
+
+		timer3: timer at ffd01000 {
+			compatible = "snps,dw-apb-timer-osc";
+			interrupts = <0 170 4>;
+			clock-frequency = <200000000>;
+			reg = <0xffd01000 0x1000>;
+		};
+
+		uart0: uart at ffc02000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xffc02000 0x1000>;
+			clock-frequency = <7372800>;
+			interrupts = <0 162 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+		};
+
+		uart1: uart at ffc03000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xffc03000 0x1000>;
+			clock-frequency = <7372800>;
+			interrupts = <0 163 4>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
new file mode 100644
index 0000000..3433ee3
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -0,0 +1,71 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+	model = "Altera SOCFPGA Cyclone V";
+	compatible = "altr,socfpga-cyclone5";
+
+	aliases {
+		ethernet0 = &gmac0;
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,57600";
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x10000000>; /* 256MB */
+	};
+
+	soc {
+		amba {
+			compatible = "arm,amba-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			pdma: pdma at ffe01000 {
+				compatible = "arm,pl330", "arm,primecell";
+				reg = <0xffe01000 0x1000>;
+				interrupts = <0 180 4>;
+			};
+		};
+
+		apb_periphs {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			gmac0: stmmac at ff700000 {
+				compatible = "st,spear600-gmac";
+				reg = <0xff700000 0x2000>;
+				interrupts = <0 115 4>;
+				interrupt-names = "macirq";
+				mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+				phy-mode = "gmii";
+			};
+		};
+	};
+};
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
new file mode 100644
index 0000000..0ac1293
--- /dev/null
+++ b/arch/arm/configs/socfpga_defconfig
@@ -0,0 +1,83 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_CPUSETS=y
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_MACH_SOCFPGA_CYCLONE5=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_NR_CPUS=2
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_RTC_HCTOSYS is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+CONFIG_DEBUG_USER=y
+CONFIG_XZ_DEC=y
-- 
1.7.9.5

[RFC PATCHv3 2/2] ARM: socfpga: Add DTS bindings for Altera's SOCFPGA

[Thomas Petazzoni]

Le Tue, 17 Jul 2012 18:50:56 -0600,
<dinguyen@altera.com> a ?crit :

> +	soc {
> +		amba {
> +			compatible = "arm,amba-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			pdma: pdma at ffe01000 {
> +				compatible = "arm,pl330", "arm,primecell";
> +				reg = <0xffe01000 0x1000>;
> +				interrupts = <0 180 4>;
> +			};
> +		};
> +
> +		apb_periphs {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			gmac0: stmmac at ff700000 {
> +				compatible = "st,spear600-gmac";
> +				reg = <0xff700000 0x2000>;
> +				interrupts = <0 115 4>;
> +				interrupt-names = "macirq";
> +				mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
> +				phy-mode = "gmii";
> +			};
> +		};

Are the pdma and gmac0 really specific to the cyclone board? Aren't
they similar to the uarts and timers in that they are part of the SoC
itself?

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[RFC PATCHv3 2/2] ARM: socfpga: Add DTS bindings for Altera's SOCFPGA

[Pavel Machek]

Hi!

> > +	soc {
> > +		amba {
> > +			compatible = "arm,amba-bus";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges;
> > +
> > +			pdma: pdma at ffe01000 {
> > +				compatible = "arm,pl330", "arm,primecell";
> > +				reg = <0xffe01000 0x1000>;
> > +				interrupts = <0 180 4>;
> > +			};
> > +		};
> > +
> > +		apb_periphs {
> > +			compatible = "simple-bus";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges;
> > +
> > +			gmac0: stmmac at ff700000 {
> > +				compatible = "st,spear600-gmac";
> > +				reg = <0xff700000 0x2000>;
> > +				interrupts = <0 115 4>;
> > +				interrupt-names = "macirq";
> > +				mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
> > +				phy-mode = "gmii";
> > +			};
> > +		};
> 
> Are the pdma and gmac0 really specific to the cyclone board? Aren't
> they similar to the uarts and timers in that they are part of the SoC
> itself?

I guess they are not. I'm not dts expert, but would something like
this be suitable? It boots :-). 

									Pavel

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 903d4bb..ee13a3e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -115,5 +115,27 @@
 			reg-shift = <2>;
 			reg-io-width = <4>;
 		};
+
+		gmac0: stmmac at ff700000 {
+			compatible = "st,spear600-gmac";
+			reg = <0xff700000 0x2000>;
+			interrupts = <0 115 4>;
+			interrupt-names = "macirq";
+			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+			phy-mode = "gmii";
+		};
+
+		amba {
+			compatible = "arm,amba-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			pdma: pdma at ffe01000 {
+				compatible = "arm,pl330", "arm,primecell";
+				reg = <0xffe01000 0x1000>;
+				interrupts = <0 180 4>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 3433ee3..683d035 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -37,35 +37,4 @@
 		device_type = "memory";
 		reg = <0x0 0x10000000>; /* 256MB */
 	};
-
-	soc {
-		amba {
-			compatible = "arm,amba-bus";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			pdma: pdma at ffe01000 {
-				compatible = "arm,pl330", "arm,primecell";
-				reg = <0xffe01000 0x1000>;
-				interrupts = <0 180 4>;
-			};
-		};
-
-		apb_periphs {
-			compatible = "simple-bus";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			gmac0: stmmac at ff700000 {
-				compatible = "st,spear600-gmac";
-				reg = <0xff700000 0x2000>;
-				interrupts = <0 115 4>;
-				interrupt-names = "macirq";
-				mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-				phy-mode = "gmii";
-			};
-		};
-	};
 };


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[RFC PATCHv3 2/2] ARM: socfpga: Add DTS bindings for Altera's SOCFPGA

[Thomas Petazzoni]

Le Wed, 18 Jul 2012 12:13:16 +0200,
Pavel Machek <pavel@denx.de> a ?crit :

> > Are the pdma and gmac0 really specific to the cyclone board? Aren't
> > they similar to the uarts and timers in that they are part of the SoC
> > itself?
> 
> I guess they are not. I'm not dts expert, but would something like
> this be suitable? It boots :-). 

Well, basically, .dtsi files define what is SoC-specific, and the .dts
files defined what is board-specific.

So, things like the internal SoC peripherals will always be same on all
boards that use this SoC (UARTs, timers, Ethernet controllers, I2C
controllers, USB controllers, etc.). These belong to the .dtsi.

Things like external peripherals (devices on I2C/SPI busses) or
additional properties (how the SoC is wired on the board, which pin is
used for this or that). These belong to the .dts.

I don't have the datasheet for your socfpga, so I can't see which
peripherals are internal to the SoC and which are not, especially with
those combined SoC/FPGA designs in which some peripherals can be
synthesized into the FPGA and therefore would probably not belong to
the .dtsi.

So, assuming your Ethernet controller and DMA controller are part of
the SoC itself and will therefore be present on all boards using your
SoC, then the fix you provided looks good.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com