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From: xiechao.mail@gmail.com (Chao Xie)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/7] ARM: cache: add cputype.h for tauros2
Date: Tue, 31 Jul 2012 14:13:11 +0800	[thread overview]
Message-ID: <1343715194-25900-4-git-send-email-xiechao.mail@gmail.com> (raw)
In-Reply-To: <1343715194-25900-1-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie@marvell.com>

Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
---
 arch/arm/mm/cache-tauros2.c |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 97e2ac8..4b787bb 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
+#include <asm/cputype.h>
 #include <asm/hardware/cache-tauros2.h>
 
 
@@ -161,8 +162,6 @@ static void __init disable_l2_prefetch(void)
 
 static inline int __init cpuid_scheme(void)
 {
-	extern int processor_id;
-
 	return !!((processor_id & 0x000f0000) == 0x000f0000);
 }
 
@@ -191,7 +190,6 @@ static inline void __init write_actlr(u32 actlr)
 
 void __init tauros2_init(void)
 {
-	extern int processor_id;
 	char *mode = NULL;
 
 	disable_l2_prefetch();
-- 
1.7.0.4

  parent reply	other threads:[~2012-07-31  6:13 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-31  6:13 [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Chao Xie
2012-07-31  6:13 ` [PATCH 2/7] gpio: pxa: add chain_eneter and chain_exit for irq handler Chao Xie
2012-07-31  6:13 ` [PATCH 3/7] arm: cache: fix uninitialized ptr in tauros2_init Chao Xie
2012-07-31  6:13 ` Chao Xie [this message]
2012-07-31  6:13 ` [PATCH 5/7] ARM: cache: add extra feature enable for tauros2 Chao Xie
2012-07-31  6:13 ` [PATCH 6/7] arm: mmp&dove: modify tauros2_init call Chao Xie
2012-07-31  6:13 ` [PATCH 7/7] arm: cache: add dt support for tauros2 cache Chao Xie
2012-08-04 16:06 ` [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Haojian Zhuang

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