* [PATCH 1/7] ARM: pxa: support CKENC in clk_enable
@ 2012-07-31 6:13 Chao Xie
2012-07-31 6:13 ` [PATCH 2/7] gpio: pxa: add chain_eneter and chain_exit for irq handler Chao Xie
` (6 more replies)
0 siblings, 7 replies; 13+ messages in thread
From: Chao Xie @ 2012-07-31 6:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Chao Xie <chao.xie@marvell.com>
Since more device clock is supported in PXA95x, add CKENC support.
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
---
arch/arm/mach-pxa/clock-pxa3xx.c | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
index 2a37a9a..d4e9499 100644
--- a/arch/arm/mach-pxa/clock-pxa3xx.c
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -127,8 +127,10 @@ void clk_pxa3xx_cken_enable(struct clk *clk)
if (clk->cken < 32)
CKENA |= mask;
- else
+ else if (clk->cken < 64)
CKENB |= mask;
+ else
+ CKENC |= mask;
}
void clk_pxa3xx_cken_disable(struct clk *clk)
@@ -137,8 +139,10 @@ void clk_pxa3xx_cken_disable(struct clk *clk)
if (clk->cken < 32)
CKENA &= ~mask;
- else
+ else if (clk->cken < 64)
CKENB &= ~mask;
+ else
+ CKENC &= ~mask;
}
const struct clkops clk_pxa3xx_cken_ops = {
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/7] gpio: pxa: add chain_eneter and chain_exit for irq handler
2012-07-31 6:13 [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Chao Xie
@ 2012-07-31 6:13 ` Chao Xie
2012-07-31 6:13 ` [PATCH 3/7] arm: cache: fix uninitialized ptr in tauros2_init Chao Xie
` (5 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Chao Xie @ 2012-07-31 6:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
---
drivers/gpio/gpio-pxa.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 58a6a63..97ade14 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -26,6 +26,8 @@
#include <linux/syscore_ops.h>
#include <linux/slab.h>
+#include <asm/mach/irq.h>
+
#include <mach/irqs.h>
/*
@@ -379,6 +381,9 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
struct pxa_gpio_chip *c;
int loop, gpio, gpio_base, n;
unsigned long gedr;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ chained_irq_enter(chip, desc);
do {
loop = 0;
@@ -398,6 +403,8 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
}
}
} while (loop);
+
+ chained_irq_exit(chip, desc);
}
static void pxa_ack_muxed_gpio(struct irq_data *d)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/7] arm: cache: fix uninitialized ptr in tauros2_init
2012-07-31 6:13 [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Chao Xie
2012-07-31 6:13 ` [PATCH 2/7] gpio: pxa: add chain_eneter and chain_exit for irq handler Chao Xie
@ 2012-07-31 6:13 ` Chao Xie
2012-07-31 6:13 ` [PATCH 4/7] ARM: cache: add cputype.h for tauros2 Chao Xie
` (4 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Chao Xie @ 2012-07-31 6:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Chao Xie <chao.xie@marvell.com>
init the variable "mode" to NULL to ensure the later NULL checking is
taking effect.
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
---
arch/arm/mm/cache-tauros2.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 23a7643..97e2ac8 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -192,7 +192,7 @@ static inline void __init write_actlr(u32 actlr)
void __init tauros2_init(void)
{
extern int processor_id;
- char *mode;
+ char *mode = NULL;
disable_l2_prefetch();
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/7] ARM: cache: add cputype.h for tauros2
2012-07-31 6:13 [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Chao Xie
2012-07-31 6:13 ` [PATCH 2/7] gpio: pxa: add chain_eneter and chain_exit for irq handler Chao Xie
2012-07-31 6:13 ` [PATCH 3/7] arm: cache: fix uninitialized ptr in tauros2_init Chao Xie
@ 2012-07-31 6:13 ` Chao Xie
2012-07-31 6:13 ` [PATCH 5/7] ARM: cache: add extra feature enable " Chao Xie
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Chao Xie @ 2012-07-31 6:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
---
arch/arm/mm/cache-tauros2.c | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 97e2ac8..4b787bb 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -17,6 +17,7 @@
#include <linux/init.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
+#include <asm/cputype.h>
#include <asm/hardware/cache-tauros2.h>
@@ -161,8 +162,6 @@ static void __init disable_l2_prefetch(void)
static inline int __init cpuid_scheme(void)
{
- extern int processor_id;
-
return !!((processor_id & 0x000f0000) == 0x000f0000);
}
@@ -191,7 +190,6 @@ static inline void __init write_actlr(u32 actlr)
void __init tauros2_init(void)
{
- extern int processor_id;
char *mode = NULL;
disable_l2_prefetch();
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/7] ARM: cache: add extra feature enable for tauros2
2012-07-31 6:13 [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Chao Xie
` (2 preceding siblings ...)
2012-07-31 6:13 ` [PATCH 4/7] ARM: cache: add cputype.h for tauros2 Chao Xie
@ 2012-07-31 6:13 ` Chao Xie
2012-07-31 6:13 ` [PATCH 6/7] arm: mmp&dove: modify tauros2_init call Chao Xie
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Chao Xie @ 2012-07-31 6:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Chao Xie <chao.xie@marvell.com>
The extra feature may be used by SOCs are prefetch, burst8,
write buffer coalesce
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
---
arch/arm/include/asm/hardware/cache-tauros2.h | 5 ++-
arch/arm/mm/cache-tauros2.c | 44 +++++++++++++++---------
2 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h
index 538f17c..295e2e4 100644
--- a/arch/arm/include/asm/hardware/cache-tauros2.h
+++ b/arch/arm/include/asm/hardware/cache-tauros2.h
@@ -8,4 +8,7 @@
* warranty of any kind, whether express or implied.
*/
-extern void __init tauros2_init(void);
+#define CACHE_TAUROS2_PREFETCH_ON (1 << 0)
+#define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
+
+extern void __init tauros2_init(unsigned int features);
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 4b787bb..e9f054f 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -145,21 +145,6 @@ static inline void __init write_extra_features(u32 u)
__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
}
-static void __init disable_l2_prefetch(void)
-{
- u32 u;
-
- /*
- * Read the CPU Extra Features register and verify that the
- * Disable L2 Prefetch bit is set.
- */
- u = read_extra_features();
- if (!(u & 0x01000000)) {
- printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n");
- write_extra_features(u | 0x01000000);
- }
-}
-
static inline int __init cpuid_scheme(void)
{
return !!((processor_id & 0x000f0000) == 0x000f0000);
@@ -188,11 +173,36 @@ static inline void __init write_actlr(u32 actlr)
__asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
}
-void __init tauros2_init(void)
+static void enable_extra_feature(unsigned int features)
+{
+ u32 u;
+
+ u = read_extra_features();
+
+ if (features & CACHE_TAUROS2_PREFETCH_ON)
+ u &= ~0x01000000;
+ else
+ u |= 0x01000000;
+ printk(KERN_INFO "Tauros2: %s L2 prefetch.\n",
+ (features & CACHE_TAUROS2_PREFETCH_ON)
+ ? "Enabling" : "Disabling");
+
+ if (features & CACHE_TAUROS2_LINEFILL_BURST8)
+ u |= 0x00100000;
+ else
+ u &= ~0x00100000;
+ printk(KERN_INFO "Tauros2: %s line fill burt8.\n",
+ (features & CACHE_TAUROS2_LINEFILL_BURST8)
+ ? "Enabling" : "Disabling");
+
+ write_extra_features(u);
+}
+
+void __init tauros2_init(unsigned int features)
{
char *mode = NULL;
- disable_l2_prefetch();
+ enable_extra_feature(features);
#ifdef CONFIG_CPU_32v5
if ((processor_id & 0xff0f0000) == 0x56050000) {
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 6/7] arm: mmp&dove: modify tauros2_init call
2012-07-31 6:13 [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Chao Xie
` (3 preceding siblings ...)
2012-07-31 6:13 ` [PATCH 5/7] ARM: cache: add extra feature enable " Chao Xie
@ 2012-07-31 6:13 ` Chao Xie
2012-07-31 6:13 ` [PATCH 7/7] arm: cache: add dt support for tauros2 cache Chao Xie
2012-08-04 16:06 ` [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Haojian Zhuang
6 siblings, 0 replies; 13+ messages in thread
From: Chao Xie @ 2012-07-31 6:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Chao Xie <chao.xie@marvell.com>
The tauros2_init has argument, change the calling of tauros2_init
to support argument.
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
---
arch/arm/mach-dove/common.c | 2 +-
arch/arm/mach-mmp/mmp2.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 9493076..aeca4e9 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -288,7 +288,7 @@ void __init dove_init(void)
printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
#ifdef CONFIG_CACHE_TAUROS2
- tauros2_init();
+ tauros2_init(0);
#endif
dove_setup_cpu_mbus();
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c709a24..c2bb95c 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -163,7 +163,7 @@ static int __init mmp2_init(void)
{
if (cpu_is_mmp2()) {
#ifdef CONFIG_CACHE_TAUROS2
- tauros2_init();
+ tauros2_init(0);
#endif
mfp_init_base(MFPR_VIRT_BASE);
mfp_init_addr(mmp2_addr_map);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 7/7] arm: cache: add dt support for tauros2 cache
2012-07-31 6:13 [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Chao Xie
` (4 preceding siblings ...)
2012-07-31 6:13 ` [PATCH 6/7] arm: mmp&dove: modify tauros2_init call Chao Xie
@ 2012-07-31 6:13 ` Chao Xie
2012-08-04 16:06 ` [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Haojian Zhuang
6 siblings, 0 replies; 13+ messages in thread
From: Chao Xie @ 2012-07-31 6:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
---
.../devicetree/bindings/arm/mrvl/tauros2.txt | 18 ++++++++++
arch/arm/mm/cache-tauros2.c | 35 +++++++++++++++++++-
2 files changed, 52 insertions(+), 1 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
new file mode 100644
index 0000000..3616b75
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
@@ -0,0 +1,18 @@
+* Marvell Tauros2 Cache
+
+Required properties:
+- compatible : Should be "marvell,tauros2-cache".
+- marvell,tauros2-cache-features : Specify the features supported for the
+ tauros2 cache.
+ The features including
+ CACHE_TAUROS2_PREFETCH_ON (1 << 0)
+ CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
+ The definition can be found at
+ arch/arm/include/asm/hardware/cache-tauros2.h
+
+Example:
+ L2: l2-cache {
+ compatible = "marvell,tauros2-cache";
+ marvell,tauros2-cache-features = <0x3>;
+ };
+
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index e9f054f..1be0f4e 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -15,6 +15,8 @@
*/
#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/cputype.h>
@@ -198,7 +200,7 @@ static void enable_extra_feature(unsigned int features)
write_extra_features(u);
}
-void __init tauros2_init(unsigned int features)
+static void __init tauros2_internal_init(unsigned int features)
{
char *mode = NULL;
@@ -294,3 +296,34 @@ void __init tauros2_init(unsigned int features)
printk(KERN_INFO "Tauros2: L2 cache support initialised "
"in %s mode.\n", mode);
}
+
+#ifdef CONFIG_OF
+static const struct of_device_id tauros2_ids[] __initconst = {
+ { .compatible = "marvell,tauros2-cache"},
+ {}
+};
+#endif
+
+void __init tauros2_init(unsigned int features)
+{
+#ifdef CONFIG_OF
+ struct device_node *node;
+ int ret;
+ unsigned int f;
+
+ node = of_find_matching_node(NULL, tauros2_ids);
+ if (!node) {
+ pr_info("Not found marvell,tauros2-cache, disable it\n");
+ return;
+ }
+
+ ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f);
+ if (ret) {
+ pr_info("Not found marvell,tauros-cache-features property, "
+ "disable extra features\n");
+ features = 0;
+ } else
+ features = f;
+#endif
+ tauros2_internal_init(features);
+}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 6/7] arm: mmp&dove: modify tauros2_init call
@ 2012-07-31 7:01 Andrew Lunn
2012-07-31 7:09 ` Chao Xie
0 siblings, 1 reply; 13+ messages in thread
From: Andrew Lunn @ 2012-07-31 7:01 UTC (permalink / raw)
To: linux-arm-kernel
Hi Chao
When making changes to Dove, or any other Orion system, please could
you CC: the orion maintainers:
ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
M: Jason Cooper <jason@lakedaemon.net>
M: Andrew Lunn <andrew@lunn.ch>
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-dove/
F: arch/arm/mach-kirkwood/
F: arch/arm/mach-mv78xx0/
F: arch/arm/mach-orion5x/
F: arch/arm/plat-orion/
Does this also affect Armada 370 and Armada XP SOC? I've no idea what
cache it uses.
Thanks
Andrew
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/7] arm: mmp&dove: modify tauros2_init call
2012-07-31 7:01 [PATCH 6/7] arm: mmp&dove: modify tauros2_init call Andrew Lunn
@ 2012-07-31 7:09 ` Chao Xie
2012-07-31 7:17 ` Andrew Lunn
2012-07-31 7:18 ` Gregory CLEMENT
0 siblings, 2 replies; 13+ messages in thread
From: Chao Xie @ 2012-07-31 7:09 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 31, 2012 at 3:01 PM, Andrew Lunn <andrew@lunn.ch> wrote:
> Hi Chao
>
> When making changes to Dove, or any other Orion system, please could
> you CC: the orion maintainers:
>
> ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
> M: Jason Cooper <jason@lakedaemon.net>
> M: Andrew Lunn <andrew@lunn.ch>
> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> S: Maintained
> F: arch/arm/mach-dove/
> F: arch/arm/mach-kirkwood/
> F: arch/arm/mach-mv78xx0/
> F: arch/arm/mach-orion5x/
> F: arch/arm/plat-orion/
>
> Does this also affect Armada 370 and Armada XP SOC? I've no idea what
> cache it uses.
>
> Thanks
> Andrew
It will impact Armada 370. The patch will make the user has choice to
enable extra features of tauros2
I have searched the code, only dove will use tauros2_init, and the
tauros2 default has its extra features off, so i directly pass 0x0 for
dove
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/7] arm: mmp&dove: modify tauros2_init call
2012-07-31 7:09 ` Chao Xie
@ 2012-07-31 7:17 ` Andrew Lunn
2012-07-31 7:18 ` Gregory CLEMENT
1 sibling, 0 replies; 13+ messages in thread
From: Andrew Lunn @ 2012-07-31 7:17 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 31, 2012 at 03:09:12PM +0800, Chao Xie wrote:
> On Tue, Jul 31, 2012 at 3:01 PM, Andrew Lunn <andrew@lunn.ch> wrote:
> > Hi Chao
> >
> > When making changes to Dove, or any other Orion system, please could
> > you CC: the orion maintainers:
> >
> > ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
> > M: Jason Cooper <jason@lakedaemon.net>
> > M: Andrew Lunn <andrew@lunn.ch>
> > L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> > S: Maintained
> > F: arch/arm/mach-dove/
> > F: arch/arm/mach-kirkwood/
> > F: arch/arm/mach-mv78xx0/
> > F: arch/arm/mach-orion5x/
> > F: arch/arm/plat-orion/
> >
> > Does this also affect Armada 370 and Armada XP SOC? I've no idea what
> > cache it uses.
> >
> > Thanks
> > Andrew
> It will impact Armada 370.
Then please keep Gregory Clement <gregory.clement@free-electrons.com>
in the loop as well.
> The patch will make the user has choice to
> enable extra features of tauros2
> I have searched the code, only dove will use tauros2_init, and the
> tauros2 default has its extra features off, so i directly pass 0x0 for
> dove
Can you recommend any benchmark tools, to see if its worth turning on
these features? Sebastian Hesselbarth is doing a lot of work on Dove
at the moment, so might be interested in investigating this.
Thanks
Andrew
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/7] arm: mmp&dove: modify tauros2_init call
2012-07-31 7:09 ` Chao Xie
2012-07-31 7:17 ` Andrew Lunn
@ 2012-07-31 7:18 ` Gregory CLEMENT
2012-08-04 4:13 ` Haojian Zhuang
1 sibling, 1 reply; 13+ messages in thread
From: Gregory CLEMENT @ 2012-07-31 7:18 UTC (permalink / raw)
To: linux-arm-kernel
On 07/31/2012 09:09 AM, Chao Xie wrote:
> On Tue, Jul 31, 2012 at 3:01 PM, Andrew Lunn <andrew@lunn.ch> wrote:
>> Hi Chao
>>
>> When making changes to Dove, or any other Orion system, please could
>> you CC: the orion maintainers:
>>
>> ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
>> M: Jason Cooper <jason@lakedaemon.net>
>> M: Andrew Lunn <andrew@lunn.ch>
>> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
>> S: Maintained
>> F: arch/arm/mach-dove/
>> F: arch/arm/mach-kirkwood/
>> F: arch/arm/mach-mv78xx0/
>> F: arch/arm/mach-orion5x/
>> F: arch/arm/plat-orion/
>>
>> Does this also affect Armada 370 and Armada XP SOC? I've no idea what
>> cache it uses.
>>
>> Thanks
>> Andrew
> It will impact Armada 370. The patch will make the user has choice to
> enable extra features of tauros2
As far as I know it wouldn't impact the Armada370 as it use an other L2
called Aurora. We are currently working on it to submit it really soon.
The ArmadaXP also use the Aurora L2 cache controller.
> I have searched the code, only dove will use tauros2_init, and the
> tauros2 default has its extra features off, so i directly pass 0x0 for
> dove
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/7] arm: mmp&dove: modify tauros2_init call
2012-07-31 7:18 ` Gregory CLEMENT
@ 2012-08-04 4:13 ` Haojian Zhuang
0 siblings, 0 replies; 13+ messages in thread
From: Haojian Zhuang @ 2012-08-04 4:13 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 31, 2012 at 3:18 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:
> On 07/31/2012 09:09 AM, Chao Xie wrote:
>> On Tue, Jul 31, 2012 at 3:01 PM, Andrew Lunn <andrew@lunn.ch> wrote:
>>> Hi Chao
>>>
>>> When making changes to Dove, or any other Orion system, please could
>>> you CC: the orion maintainers:
>>>
>>> ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
>>> M: Jason Cooper <jason@lakedaemon.net>
>>> M: Andrew Lunn <andrew@lunn.ch>
>>> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
>>> S: Maintained
>>> F: arch/arm/mach-dove/
>>> F: arch/arm/mach-kirkwood/
>>> F: arch/arm/mach-mv78xx0/
>>> F: arch/arm/mach-orion5x/
>>> F: arch/arm/plat-orion/
>>>
>>> Does this also affect Armada 370 and Armada XP SOC? I've no idea what
>>> cache it uses.
>>>
>>> Thanks
>>> Andrew
>> It will impact Armada 370. The patch will make the user has choice to
>> enable extra features of tauros2
>
> As far as I know it wouldn't impact the Armada370 as it use an other L2
> called Aurora. We are currently working on it to submit it really soon.
> The ArmadaXP also use the Aurora L2 cache controller.
>
OK. I'll merge these patches.
Regards
Haojian
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/7] ARM: pxa: support CKENC in clk_enable
2012-07-31 6:13 [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Chao Xie
` (5 preceding siblings ...)
2012-07-31 6:13 ` [PATCH 7/7] arm: cache: add dt support for tauros2 cache Chao Xie
@ 2012-08-04 16:06 ` Haojian Zhuang
6 siblings, 0 replies; 13+ messages in thread
From: Haojian Zhuang @ 2012-08-04 16:06 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 31, 2012 at 2:13 PM, Chao Xie <xiechao.mail@gmail.com> wrote:
> From: Chao Xie <chao.xie@marvell.com>
>
> Since more device clock is supported in PXA95x, add CKENC support.
>
> Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
> ---
> arch/arm/mach-pxa/clock-pxa3xx.c | 8 ++++++--
> 1 files changed, 6 insertions(+), 2 deletions(-)
>
Applied all.
Thanks
Haojian
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2012-08-04 16:06 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-07-31 6:13 [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Chao Xie
2012-07-31 6:13 ` [PATCH 2/7] gpio: pxa: add chain_eneter and chain_exit for irq handler Chao Xie
2012-07-31 6:13 ` [PATCH 3/7] arm: cache: fix uninitialized ptr in tauros2_init Chao Xie
2012-07-31 6:13 ` [PATCH 4/7] ARM: cache: add cputype.h for tauros2 Chao Xie
2012-07-31 6:13 ` [PATCH 5/7] ARM: cache: add extra feature enable " Chao Xie
2012-07-31 6:13 ` [PATCH 6/7] arm: mmp&dove: modify tauros2_init call Chao Xie
2012-07-31 6:13 ` [PATCH 7/7] arm: cache: add dt support for tauros2 cache Chao Xie
2012-08-04 16:06 ` [PATCH 1/7] ARM: pxa: support CKENC in clk_enable Haojian Zhuang
-- strict thread matches above, loose matches on Subject: below --
2012-07-31 7:01 [PATCH 6/7] arm: mmp&dove: modify tauros2_init call Andrew Lunn
2012-07-31 7:09 ` Chao Xie
2012-07-31 7:17 ` Andrew Lunn
2012-07-31 7:18 ` Gregory CLEMENT
2012-08-04 4:13 ` Haojian Zhuang
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