[PATCH 1/2] ARM: clk-imx35: Fix SSI clock registration

[PATCH 1/2] ARM: clk-imx35: Fix SSI clock registration

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@freescale.com>

SSI block has two types of clock:

ipg: bus clock, the clock needed for accessing registers.
per: peripheral clock, the clock needed for generating the bit rate.

Currently SSI driver only supports slave mode and only need to handle
the ipg clock, because the peripheral clock comes from the master codec.

Only register the ipg clock and do not register the peripheral clock for ssi.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/mach-imx/clk-imx35.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index c6422fb..f7910df 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -230,10 +230,8 @@ int __init mx35_clocks_init()
 	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
 	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
 	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
-	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
-	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
-	clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
+	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.1");
 	/* i.mx35 has the i.mx21 type uart */
 	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
-- 
1.7.9.5

[PATCH 2/2] ARM: clk-imx25: Fix SSI clock registration

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@freescale.com>

SSI block has two types of clock:

ipg: bus clock, the clock needed for accessing registers.
per: peripheral clock, the clock needed for generating the bit rate.

Currently SSI driver only supports slave mode and only need to handle
the ipg clock, because the peripheral clock comes from the master codec.

Only register the ipg clock and do not register the peripheral clock for ssi.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/mach-imx/clk-imx25.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index fdd8cc8..5ff9534 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -222,10 +222,8 @@ int __init mx25_clocks_init(void)
 	clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
 	clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
 	clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
-	clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0");
-	clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
-	clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
-	clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.0");
 	clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
 	clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
 	clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
-- 
1.7.9.5

[PATCH 1/2] ARM: clk-imx35: Fix SSI clock registration

[Sascha Hauer]

On Sun, Aug 19, 2012 at 11:09:05AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> SSI block has two types of clock:
> 
> ipg: bus clock, the clock needed for accessing registers.
> per: peripheral clock, the clock needed for generating the bit rate.
> 
> Currently SSI driver only supports slave mode and only need to handle
> the ipg clock, because the peripheral clock comes from the master codec.
> 
> Only register the ipg clock and do not register the peripheral clock for ssi.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Applied and added stable tag (I assume this should go to stable, right?)

Sascha

> ---
>  arch/arm/mach-imx/clk-imx35.c |    6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
> index c6422fb..f7910df 100644
> --- a/arch/arm/mach-imx/clk-imx35.c
> +++ b/arch/arm/mach-imx/clk-imx35.c
> @@ -230,10 +230,8 @@ int __init mx35_clocks_init()
>  	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
>  	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
>  	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
> -	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
> -	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
> -	clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
> +	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.1");
>  	/* i.mx35 has the i.mx21 type uart */
>  	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
>  	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
> -- 
> 1.7.9.5
> 
> 

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[PATCH 1/2] ARM: clk-imx35: Fix SSI clock registration

[Fabio Estevam]

On 8/28/12, Sascha Hauer <s.hauer@pengutronix.de> wrote:


> Applied and added stable tag (I assume this should go to stable, right?)

Yes, please apply v2 version and you can add the stable tag (only
applies to 3.5 stable branch though).

Thanks,

Fabio Estevam

[PATCH 1/2] ARM: clk-imx35: Fix SSI clock registration

[Sascha Hauer]

On Tue, Aug 28, 2012 at 08:47:10AM -0300, Fabio Estevam wrote:
> On 8/28/12, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> 
> 
> > Applied and added stable tag (I assume this should go to stable, right?)
> 
> Yes, please apply v2 version and you can add the stable tag (only
> applies to 3.5 stable branch though).

Yes I applied v2 (found it a bit later after writing the email)

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |