[PATCH v3 0/3] ARM: Exynos5: Add support for MSHC controller

[PATCH v3 0/3] ARM: Exynos5: Add support for MSHC controller

[Thomas Abraham]

This patch series adds Exynos5250 platform support for MSHC controllers.

Thomas Abraham (3):
  ARM: Samsung: Add support for MSHC controller clocks
  ARM: Exynos5: Add AUXDATA support for MSHC controllers
  ARM: dts: Add nodes for dw_mmc controllers for Samsung Exynos5250 platforms

 arch/arm/boot/dts/exynos5250-smdk5250.dts |   57 ++++++++++++++++++++++++++++-
 arch/arm/boot/dts/exynos5250.dtsi         |   32 ++++++++++++++++
 arch/arm/mach-exynos/clock-exynos5.c      |   45 ++++++++---------------
 arch/arm/mach-exynos/include/mach/map.h   |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c    |    8 ++++
 5 files changed, 113 insertions(+), 30 deletions(-)

[PATCH v3 1/3] ARM: Samsung: Add support for MSHC controller clocks

[Thomas Abraham]

Add clock instances for bus interface unit clock and card interface unit
clock of the all four MSHC controller instances.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/clock-exynos5.c |   45 ++++++++++++----------------------
 1 files changed, 16 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 3b00e29..16d8bef 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -564,35 +564,30 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_peris_ctrl,
 		.ctrlbit	= (1 << 19),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.0",
+		.name		= "biu",
+		.devname	= "dw_mmc.0",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 12),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.1",
+		.name		= "biu",
+		.devname	= "dw_mmc.1",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 13),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.2",
+		.name		= "biu",
+		.devname	= "dw_mmc.2",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 14),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.3",
+		.name		= "biu",
+		.devname	= "dw_mmc.3",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 15),
 	}, {
-		.name		= "dwmci",
-		.parent		= &exynos5_clk_aclk_200.clk,
-		.enable		= exynos5_clk_ip_fsys_ctrl,
-		.ctrlbit	= (1 << 16),
-	}, {
 		.name		= "sata",
 		.devname	= "ahci",
 		.enable		= exynos5_clk_ip_fsys_ctrl,
@@ -1006,8 +1001,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.0",
+		.name		= "ciu",
+		.devname	= "dw_mmc.0",
 		.parent		= &exynos5_clk_dout_mmc0.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 0),
@@ -1017,8 +1012,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.1",
+		.name		= "ciu",
+		.devname	= "dw_mmc.1",
 		.parent		= &exynos5_clk_dout_mmc1.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 4),
@@ -1028,8 +1023,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.2",
+		.name		= "ciu",
+		.devname	= "dw_mmc.2",
 		.parent		= &exynos5_clk_dout_mmc2.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 8),
@@ -1039,8 +1034,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.3",
+		.name		= "ciu",
+		.devname	= "dw_mmc.3",
 		.parent		= &exynos5_clk_dout_mmc3.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 12),
@@ -1114,14 +1109,6 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
 static struct clksrc_clk exynos5_clksrcs[] = {
 	{
 		.clk	= {
-			.name		= "sclk_dwmci",
-			.parent		= &exynos5_clk_dout_mmc4.clk,
-			.enable		= exynos5_clksrc_mask_fsys_ctrl,
-			.ctrlbit	= (1 << 16),
-		},
-		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-	}, {
-		.clk	= {
 			.name		= "sclk_fimd",
 			.devname	= "s3cfb.1",
 			.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
-- 
1.6.6.rc2

[PATCH v3 1/3] ARM: Samsung: Add support for MSHC controller clocks

[Kukjin Kim]

On 08/26/12 04:59, Thomas Abraham wrote:
> Add clock instances for bus interface unit clock and card interface unit
> clock of the all four MSHC controller instances.
>
> Signed-off-by: Abhilash Kesavan<a.kesavan@samsung.com>
> Signed-off-by: Thomas Abraham<thomas.abraham@linaro.org>
> ---
>   arch/arm/mach-exynos/clock-exynos5.c |   45 ++++++++++++----------------------
>   1 files changed, 16 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> index 3b00e29..16d8bef 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -564,35 +564,30 @@ static struct clk exynos5_init_clocks_off[] = {
>   		.enable		= exynos5_clk_ip_peris_ctrl,
>   		.ctrlbit	= (1<<  19),
>   	}, {
> -		.name		= "hsmmc",
> -		.devname	= "exynos4-sdhci.0",
> +		.name		= "biu",

I have no idea why we change the clock name to 'biu' (bus interface 
unit). Just let me know.

[...]

>   static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
>   	.clk	= {
> -		.name		= "sclk_mmc",
> -		.devname	= "exynos4-sdhci.0",
> +		.name		= "ciu",

Same as above.

[...]

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v3 1/3] ARM: Samsung: Add support for MSHC controller clocks

[Thomas Abraham]

On 28 August 2012 04:45, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 08/26/12 04:59, Thomas Abraham wrote:
>>
>> Add clock instances for bus interface unit clock and card interface unit
>> clock of the all four MSHC controller instances.
>>
>> Signed-off-by: Abhilash Kesavan<a.kesavan@samsung.com>
>> Signed-off-by: Thomas Abraham<thomas.abraham@linaro.org>
>> ---
>>   arch/arm/mach-exynos/clock-exynos5.c |   45
>> ++++++++++++----------------------
>>   1 files changed, 16 insertions(+), 29 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>> b/arch/arm/mach-exynos/clock-exynos5.c
>> index 3b00e29..16d8bef 100644
>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>> @@ -564,35 +564,30 @@ static struct clk exynos5_init_clocks_off[] = {
>>                 .enable         = exynos5_clk_ip_peris_ctrl,
>>                 .ctrlbit        = (1<<  19),
>>         }, {
>> -               .name           = "hsmmc",
>> -               .devname        = "exynos4-sdhci.0",
>> +               .name           = "biu",
>
>
> I have no idea why we change the clock name to 'biu' (bus interface unit).
> Just let me know.

The dw-mmc controller requires two clocks - bus interface unit and
card interface unit clock. Since this controller driver can be used on
platforms other than exynos, the name of the clock has to be generic.
Hence the name of the clocks used are "biu" and "ciu" as the per the
dw-mmc data sheet.

>
> [...]
>
>
>>   static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
>>         .clk    = {
>> -               .name           = "sclk_mmc",
>> -               .devname        = "exynos4-sdhci.0",
>> +               .name           = "ciu",
>
>
> Same as above.

Thanks,
Thomas.

[PATCH v3 2/3] ARM: Exynos5: Add AUXDATA support for MSHC controllers

[Thomas Abraham]

Add entries if MSHC controllers in AUXDATA table for correct device name
initialization.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/mach-exynos/include/mach/map.h |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c  |    8 ++++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 9d1f3ac..5b0ee41 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -172,6 +172,7 @@
 
 #define EXYNOS4_PA_HSMMC(x)		(0x12510000 + ((x) * 0x10000))
 #define EXYNOS4_PA_DWMCI		0x12550000
+#define EXYNOS5_PA_DWMCI(x)		(0x12200000 + ((x) * 0x10000))
 
 #define EXYNOS4_PA_HSOTG		0x12480000
 #define EXYNOS4_PA_USB_HSPHY		0x125B0000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc..4257cc1 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -47,6 +47,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"s3c2440-i2c.0", NULL),
 	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 				"s3c2440-i2c.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(0),
+				"dw_mmc.0", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(1),
+				"dw_mmc.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(2),
+				"dw_mmc.2", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(3),
+				"dw_mmc.3", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 				"exynos4210-spi.0", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
-- 
1.6.6.rc2

[PATCH v3 2/3] ARM: Exynos5: Add AUXDATA support for MSHC controllers

[Kukjin Kim]

On 08/26/12 04:59, Thomas Abraham wrote:
> Add entries if MSHC controllers in AUXDATA table for correct device name
> initialization.
>
> Signed-off-by: Abhilash Kesavan<a.kesavan@samsung.com>
> Signed-off-by: Thomas Abraham<thomas.abraham@linaro.org>
> ---
>   arch/arm/mach-exynos/include/mach/map.h |    1 +
>   arch/arm/mach-exynos/mach-exynos5-dt.c  |    8 ++++++++
>   2 files changed, 9 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 9d1f3ac..5b0ee41 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -172,6 +172,7 @@
>
>   #define EXYNOS4_PA_HSMMC(x)		(0x12510000 + ((x) * 0x10000))
>   #define EXYNOS4_PA_DWMCI		0x12550000
> +#define EXYNOS5_PA_DWMCI(x)		(0x12200000 + ((x) * 0x10000))

Just, how about EXYNOS5_PA_DWMMC0, EXYNOS5_PA_DWMMC1, ... EXYNOS_PA_DWMMC3?

And if the addresses are different on other EXYNOS5 SoC, how do we 
handle it for auxdata?

>
>   #define EXYNOS4_PA_HSOTG		0x12480000
>   #define EXYNOS4_PA_USB_HSPHY		0x125B0000
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index ef770bc..4257cc1 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -47,6 +47,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
>   				"s3c2440-i2c.0", NULL),
>   	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
>   				"s3c2440-i2c.1", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(0),

As I commented, how about just 'samsung,dw-mmc'? but I'm not sure.

> +				"dw_mmc.0", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(1),
> +				"dw_mmc.1", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(2),
> +				"dw_mmc.2", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(3),
> +				"dw_mmc.3", NULL),
>   	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
>   				"exynos4210-spi.0", NULL),
>   	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v3 2/3] ARM: Exynos5: Add AUXDATA support for MSHC controllers

[Thomas Abraham]

On 28 August 2012 04:41, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 08/26/12 04:59, Thomas Abraham wrote:
>>
>> Add entries if MSHC controllers in AUXDATA table for correct device name
>> initialization.
>>
>> Signed-off-by: Abhilash Kesavan<a.kesavan@samsung.com>
>> Signed-off-by: Thomas Abraham<thomas.abraham@linaro.org>
>> ---
>>   arch/arm/mach-exynos/include/mach/map.h |    1 +
>>   arch/arm/mach-exynos/mach-exynos5-dt.c  |    8 ++++++++
>>   2 files changed, 9 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/include/mach/map.h
>> b/arch/arm/mach-exynos/include/mach/map.h
>> index 9d1f3ac..5b0ee41 100644
>> --- a/arch/arm/mach-exynos/include/mach/map.h
>> +++ b/arch/arm/mach-exynos/include/mach/map.h
>> @@ -172,6 +172,7 @@
>>
>>   #define EXYNOS4_PA_HSMMC(x)           (0x12510000 + ((x) * 0x10000))
>>   #define EXYNOS4_PA_DWMCI              0x12550000
>> +#define EXYNOS5_PA_DWMCI(x)            (0x12200000 + ((x) * 0x10000))
>
>
> Just, how about EXYNOS5_PA_DWMMC0, EXYNOS5_PA_DWMMC1, ... EXYNOS_PA_DWMMC3?

Ok.

>
> And if the addresses are different on other EXYNOS5 SoC, how do we handle it
> for auxdata?

I hope that does not happen. So do you suggest that I change this to
EYNOS5250_PA_DWMMC0 ?

>
>
>>
>>   #define EXYNOS4_PA_HSOTG              0x12480000
>>   #define EXYNOS4_PA_USB_HSPHY          0x125B0000
>> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> index ef770bc..4257cc1 100644
>> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> @@ -47,6 +47,14 @@ static const struct of_dev_auxdata
>> exynos5250_auxdata_lookup[] __initconst = {
>>                                 "s3c2440-i2c.0", NULL),
>>         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
>>                                 "s3c2440-i2c.1", NULL),
>> +       OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(0),
>
>
> As I commented, how about just 'samsung,dw-mmc'? but I'm not sure.

The dw-mmc controllers on Exynos 4210/4412/5250 have incremental
features. So different compatible strings are required to identify the
type of the controller.

Thanks for reviewing this patch series.

Regards,
Thomas.

[PATCH v3 3/3] ARM: dts: Add nodes for dw_mmc controllers for Samsung Exynos5250 platforms

[Thomas Abraham]

Add device nodes for the four instances of dw_mmc controllers in Exynos5250
and enable instance 0 and 2 for the smdk5250 board.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   57 ++++++++++++++++++++++++++++-
 arch/arm/boot/dts/exynos5250.dtsi         |   32 ++++++++++++++++
 2 files changed, 88 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..6dc9faf 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -16,12 +16,19 @@
 	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
 	compatible = "samsung,smdk5250", "samsung,exynos5250";
 
+	aliases {
+		mshc0 = &mshc_0;
+		mshc1 = &mshc_1;
+		mshc2 = &mshc_2;
+		mshc3 = &mshc_3;
+	};
+
 	memory {
 		reg = <0x40000000 0x80000000>;
 	};
 
 	chosen {
-		bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
+		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
 	};
 
 	i2c at 12C60000 {
@@ -72,6 +79,54 @@
 		status = "disabled";
 	};
 
+	mshc_0: dwmmc0 at 12200000 {
+		num-slots = <1>;
+		supports-highspeed;
+		broken-cd;
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-sdr-timing = <2 3 3>;
+		samsung,dw-mshc-ddr-timing = <1 2 3>;
+
+		slot at 0 {
+			reg = <0>;
+			bus-width = <8>;
+			gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+				<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+				<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
+				<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+				<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
+		};
+	};
+
+	mshc_1: dwmmc1 at 12210000 {
+		status = "disabled";
+	};
+
+	mshc_2: dwmmc2 at 12220000 {
+		num-slots = <1>;
+		supports-highspeed;
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-sdr-timing = <2 3 3>;
+		samsung,dw-mshc-ddr-timing = <1 2 3>;
+
+		slot at 0 {
+			reg = <0>;
+			bus-width = <4>;
+			samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+			gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+				<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+				<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
+				<&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
+				<&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
+		};
+	};
+
+	mshc_3: dwmmc3 at 12230000 {
+		status = "disabled";
+	};
+
 	spi_0: spi at 12d20000 {
 		status = "disabled";
 	};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8..f69e389 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -182,6 +182,38 @@
 		#size-cells = <0>;
 	};
 
+	dwmmc0 at 12200000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12200000 0x1000>;
+		interrupts = <0 75 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc1 at 12210000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12210000 0x1000>;
+		interrupts = <0 76 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc2 at 12220000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12220000 0x1000>;
+		interrupts = <0 77 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc3 at 12230000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12230000 0x1000>;
+		interrupts = <0 78 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
 	amba {
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
1.6.6.rc2

[PATCH v3 3/3] ARM: dts: Add nodes for dw_mmc controllers for Samsung Exynos5250 platforms

[Kukjin Kim]

On 08/26/12 04:59, Thomas Abraham wrote:
> Add device nodes for the four instances of dw_mmc controllers in Exynos5250
> and enable instance 0 and 2 for the smdk5250 board.
>
> Signed-off-by: Thomas Abraham<thomas.abraham@linaro.org>
> ---
>   arch/arm/boot/dts/exynos5250-smdk5250.dts |   57 ++++++++++++++++++++++++++++-
>   arch/arm/boot/dts/exynos5250.dtsi         |   32 ++++++++++++++++
>   2 files changed, 88 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 8a5e348..6dc9faf 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -16,12 +16,19 @@
>   	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
>   	compatible = "samsung,smdk5250", "samsung,exynos5250";
>
> +	aliases {
> +		mshc0 =&mshc_0;
> +		mshc1 =&mshc_1;
> +		mshc2 =&mshc_2;
> +		mshc3 =&mshc_3;
> +	};
> +
>   	memory {
>   		reg =<0x40000000 0x80000000>;
>   	};
>
>   	chosen {
> -		bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
> +		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";

Yes, we need to sort out the 'bootargs' for using uart2 as a console, 
but you know, this should be separated :-)

>   	};
>
>   	i2c at 12C60000 {
> @@ -72,6 +79,54 @@
>   		status = "disabled";
>   	};
>
> +	mshc_0: dwmmc0 at 12200000 {

How about to keep the consistent naming? dwmmc or dw_mmc? I think, 
'dw_mmc' makes more sense?

> +		num-slots =<1>;
> +		supports-highspeed;
> +		broken-cd;
> +		fifo-depth =<0x80>;
> +		card-detect-delay =<200>;
> +		samsung,dw-mshc-sdr-timing =<2 3 3>;
> +		samsung,dw-mshc-ddr-timing =<1 2 3>;

We need to think again the name of dw-mshc-sdr-timing, dw-mshc-ddr-timing?

[...]

> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 004aaa8..f69e389 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -182,6 +182,38 @@
>   		#size-cells =<0>;
>   	};
>
> +	dwmmc0 at 12200000 {
> +		compatible = "samsung,exynos5250-dw-mshc";

I'm not sure, 'exynos5250-dw-mshc' is right here. Because it is just 
dw_mmc controller on exynos5250. So...hmm...

[...]

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v3 3/3] ARM: dts: Add nodes for dw_mmc controllers for Samsung Exynos5250 platforms

[Thomas Abraham]

On 28 August 2012 04:16, Kukjin Kim <kgene.kim@samsung.com> wrote:
> On 08/26/12 04:59, Thomas Abraham wrote:
>>
>> Add device nodes for the four instances of dw_mmc controllers in
>> Exynos5250
>> and enable instance 0 and 2 for the smdk5250 board.
>>
>> Signed-off-by: Thomas Abraham<thomas.abraham@linaro.org>
>> ---
>>   arch/arm/boot/dts/exynos5250-smdk5250.dts |   57
>> ++++++++++++++++++++++++++++-
>>   arch/arm/boot/dts/exynos5250.dtsi         |   32 ++++++++++++++++
>>   2 files changed, 88 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> index 8a5e348..6dc9faf 100644
>> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> @@ -16,12 +16,19 @@
>>         model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
>>         compatible = "samsung,smdk5250", "samsung,exynos5250";
>>
>> +       aliases {
>> +               mshc0 =&mshc_0;
>> +               mshc1 =&mshc_1;
>> +               mshc2 =&mshc_2;
>> +               mshc3 =&mshc_3;
>> +       };
>> +
>>         memory {
>>                 reg =<0x40000000 0x80000000>;
>>         };
>>
>>         chosen {
>> -               bootargs = "root=/dev/ram0 rw ramdisk=8192
>> console=ttySAC1,115200";
>> +               bootargs = "root=/dev/ram0 rw ramdisk=8192
>> initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
>
>
> Yes, we need to sort out the 'bootargs' for using uart2 as a console, but
> you know, this should be separated :-)
>

Sorry, that was never intended to be in this patch. My mistake.

>
>>         };
>>
>>         i2c at 12C60000 {
>> @@ -72,6 +79,54 @@
>>                 status = "disabled";
>>         };
>>
>> +       mshc_0: dwmmc0 at 12200000 {
>
>
> How about to keep the consistent naming? dwmmc or dw_mmc? I think, 'dw_mmc'
> makes more sense?

Ok.

>
>
>> +               num-slots =<1>;
>> +               supports-highspeed;
>> +               broken-cd;
>> +               fifo-depth =<0x80>;
>> +               card-detect-delay =<200>;
>> +               samsung,dw-mshc-sdr-timing =<2 3 3>;
>> +               samsung,dw-mshc-ddr-timing =<1 2 3>;
>
>
> We need to think again the name of dw-mshc-sdr-timing, dw-mshc-ddr-timing?

Synopsis calls this controller "Mobile Storage Host Controller (MSHC)"
in their online data sheets. Hence, all the bindings (which are used
on non-samsung platforms as well) follow the this name. For any
Samsung specific code for this controller, we are free to choose any
name.

>
> [...]
>
>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>> b/arch/arm/boot/dts/exynos5250.dtsi
>> index 004aaa8..f69e389 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -182,6 +182,38 @@
>>                 #size-cells =<0>;
>>         };
>>
>> +       dwmmc0 at 12200000 {
>> +               compatible = "samsung,exynos5250-dw-mshc";
>
>
> I'm not sure, 'exynos5250-dw-mshc' is right here. Because it is just dw_mmc
> controller on exynos5250. So...hmm...

There are differences in the implementation of the dw-mmc controller
in Exynos SoC's. So it has to be exynos5250-dw-mshc.

Thanks,
Thomas.