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From: wni@nvidia.com (Wei Ni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR directly for non-OOB
Date: Tue, 28 Aug 2012 19:13:33 +0800	[thread overview]
Message-ID: <1346152413.3516.211.camel@tegra-chromium-2> (raw)
In-Reply-To: <503BD345.6030501@wwwdotorg.org>

On Tue, 2012-08-28 at 04:06 +0800, Stephen Warren wrote:
> On 08/27/2012 09:24 AM, Arend van Spriel wrote:
> > On 08/27/2012 12:25 PM, Wei Ni wrote:
> >> In case of inband interrupts, if we handle the interrupt in dpc thread,
> >> two level of thread switching takes place to process wifi interrupts.
> >> One in SDHCI driver and the other in Wifi driver. This may cause the
> >> system
> >> instability.
> > 
> > Looking into the sdhci/mmc code indeed shows that the brcmfmac irq
> > handler is not called in true IRQ context. So the dpc thread may add
> > unnecessary complexity, but to me there is not indication that there is
> > a stability issue.

The brcmfmac irq handler is called in the thread sdio_irq_thread(), this
thread indeed is driven by the sdhci irq, although it's not the true IRQ
context. If the brcmfmac doesn't clear the IRQ condition ASAP, the
sdio_irq_thread will be triggered again and again, and in this condition
it's too difficult to run the brcmfmac dpc thread, more and more
interrupt can't be handled.

> > 
> >> Because the SDHCI calls sdio_irq_thread() to handle the irq, this
> >> thread locks
> >> mmc host and calls wifi handler. It expects WiFi handler to be quick and
> >> enables sdio interrupt from card at end. If wifi handler defers this
> >> work for
> >> a different thread, sdio_irq_thread() will be stuck on next wifi
> >> interrupt
> >> since mmc lock is not freed.
> > 
> > Not sure if I can follow this explanation. The isr is called with host
> > claimed (by sdio_irq_thread) and all it does is at a linked list member
> > and signal the dpc thread. After doing this the host is released.
> 
> Is the issue something like the ISR handler or first level of threading
> does:
> 
> * Trigger DPC
> * Re-enable interrupt
> 
> So that the interrupt then fires again before the triggered DPC can run
> to handle/clear it, thus causing an interrupt storm?
> 
> Whereas handling the interrupt directly prevents this race condition?

Above is my understanding.

  reply	other threads:[~2012-08-28 11:13 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-08-27 10:25 [PATCH 0/6] ARM: tegra: enable wlan for t20 and t30 Wei Ni
2012-08-27 10:25 ` [PATCH 1/6] ARM: tegra: set up wlan clocks for tegra dt Wei Ni
2012-08-27 10:25 ` [PATCH 2/6] brcmfmac: Handling the interrupt in ISR directly for non-OOB Wei Ni
2012-08-27 16:24   ` Arend van Spriel
2012-08-27 20:06     ` Stephen Warren
2012-08-28 11:13       ` Wei Ni [this message]
2012-08-28 16:45         ` Franky Lin
2012-08-28 22:39           ` Stephen Warren
2012-08-28 23:01             ` Franky Lin
2012-08-28 23:04               ` Stephen Warren
2012-08-28 23:10                 ` Franky Lin
2012-08-28  6:08     ` Wei Ni
2012-08-27 10:25 ` [PATCH 3/6] ARM: dt: t20 seaboard: turn on the power for wlan Wei Ni
2012-08-27 10:25 ` [PATCH 4/6] ARM: dt: t20 ventana: set pinmux and " Wei Ni
2012-08-27 10:25 ` [PATCH 5/6] ARM: dt: t30 cardhu: " Wei Ni
2012-08-27 10:25 ` [PATCH 6/6] ARM: tegra: enable wireless in defconfig Wei Ni

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