[PATCH 1/2] ARM: tegra: dt: add L2 cache controller

[PATCH 1/2] ARM: tegra: dt: add L2 cache controller

[Joseph Lo]

Add L2 cache controller binding into DT for Tegra.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/boot/dts/tegra20.dtsi |    9 +++++++++
 arch/arm/boot/dts/tegra30.dtsi |    9 +++++++++
 2 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 6934bca..be18361 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,15 @@
 	compatible = "nvidia,tegra20";
 	interrupt-parent = <&intc>;
 
+	L2: cache-controller at 50043000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x50043000 0x1000>;
+		arm,data-latency = <5 5 2>;
+		arm,tag-latency = <4 4 2>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	timer at 50004600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x50040600 0x20>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 81f5df4..71da933 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,15 @@
 	compatible = "nvidia,tegra30";
 	interrupt-parent = <&intc>;
 
+	L2: cache-controller at 50043000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x50043000 0x1000>;
+		arm,data-latency = <6 6 2>;
+		arm,tag-latency = <5 5 2>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	timer at 50004600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x50040600 0x20>;
-- 
1.7.0.4

[PATCH 2/2] ARM: tegra: common: using OF api for L2 cache init

[Joseph Lo]

Moving L2 cache init to DT support.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/common.c |   11 ++++-------
 1 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0e31f8c..a8f9175 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -114,20 +114,17 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
 #endif
 
 
-static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
+static void __init tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
 	void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
 	u32 aux_ctrl, cache_type;
 
-	writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
-	writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
-
 	cache_type = readl(p + L2X0_CACHE_TYPE);
 	aux_ctrl = (cache_type & 0x700) << (17-8);
 	aux_ctrl |= 0x6C000001;
 
-	l2x0_init(p, aux_ctrl, 0x8200c3fe);
+	l2x0_of_init(aux_ctrl, 0x8200c3fe);
 #endif
 
 }
@@ -139,7 +136,7 @@ void __init tegra20_init_early(void)
 	tegra_init_fuse();
 	tegra2_init_clocks();
 	tegra_clk_init_from_table(tegra20_clk_init_table);
-	tegra_init_cache(0x331, 0x441);
+	tegra_init_cache();
 	tegra_pmc_init();
 	tegra_powergate_init();
 	tegra20_hotplug_init();
@@ -152,7 +149,7 @@ void __init tegra30_init_early(void)
 	tegra_init_fuse();
 	tegra30_init_clocks();
 	tegra_clk_init_from_table(tegra30_clk_init_table);
-	tegra_init_cache(0x441, 0x551);
+	tegra_init_cache();
 	tegra_pmc_init();
 	tegra_powergate_init();
 	tegra30_hotplug_init();
-- 
1.7.0.4

[PATCH 1/2] ARM: tegra: dt: add L2 cache controller

[Stephen Warren]

On 10/26/2012 04:34 AM, Joseph Lo wrote:
> Add L2 cache controller binding into DT for Tegra.

> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi

> +	L2: cache-controller at 50043000 {
> +		compatible = "arm,pl310-cache";
> +		reg = <0x50043000 0x1000>;
> +		arm,data-latency = <5 5 2>;
> +		arm,tag-latency = <4 4 2>;
> +		cache-unified;
> +		cache-level = <2>;
> +	};

Do you need to specify arm,filter-ranges here? It's certainly parsed by
pl310_of_setup() and used if present, although I don't think we're
programming the register in the existing code, so I guess we don't need it.

The L2 label above isn't necessary unless something references those
nodes. Usually, that something is the cpu nodes' next-level-cache
property. I don't suppose you could amend this series to also fill in
Tegra's /cpus nodes in these files too?

Finally, is this series going to be a dependency for any of the cpuidle
or other work you're submitting? I assume it's completely independent
and hence I can throw it in any old branch in any order I feel like?

Thanks.

[PATCH 1/2] ARM: tegra: dt: add L2 cache controller

[Joseph Lo]

On Sat, 2012-10-27 at 01:04 +0800, Stephen Warren wrote:
> On 10/26/2012 04:34 AM, Joseph Lo wrote:
> > Add L2 cache controller binding into DT for Tegra.
> 
> > diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> 
> > +	L2: cache-controller at 50043000 {
> > +		compatible = "arm,pl310-cache";
> > +		reg = <0x50043000 0x1000>;
> > +		arm,data-latency = <5 5 2>;
> > +		arm,tag-latency = <4 4 2>;
> > +		cache-unified;
> > +		cache-level = <2>;
> > +	};
> 

Stephen,

Thanks for review.
> Do you need to specify arm,filter-ranges here? It's certainly parsed by
> pl310_of_setup() and used if present, although I don't think we're
> programming the register in the existing code, so I guess we don't need it.
> 
Yes, we don't need it. Because there are HW reset value for it. We don't
need to configure it.
> The L2 label above isn't necessary unless something references those
> nodes. Usually, that something is the cpu nodes' next-level-cache
> property. I don't suppose you could amend this series to also fill in
> Tegra's /cpus nodes in these files too?
OK. Will remove the label.
> 
> Finally, is this series going to be a dependency for any of the cpuidle
> or other work you're submitting? I assume it's completely independent
> and hence I can throw it in any old branch in any order I feel like?

No. We need this before the "powered-down" cpuidle support. Because the
L2 init function didn't help to hook the resume API to "outer_cache_fns"
interface currently. If we don't apply this before the "powered-down"
cpuidle, we will lost L2 support after one successful powered-down
cpuidle sequence.

Thanks,
Joseph

[PATCH 1/2] ARM: tegra: dt: add L2 cache controller

[Stephen Warren]

On 10/28/2012 08:28 PM, Joseph Lo wrote:
> On Sat, 2012-10-27 at 01:04 +0800, Stephen Warren wrote:
>> On 10/26/2012 04:34 AM, Joseph Lo wrote:
>>> Add L2 cache controller binding into DT for Tegra.
...
>> Finally, is this series going to be a dependency for any of the cpuidle
>> or other work you're submitting? I assume it's completely independent
>> and hence I can throw it in any old branch in any order I feel like?
> 
> No. We need this before the "powered-down" cpuidle support. Because the
> L2 init function didn't help to hook the resume API to "outer_cache_fns"
> interface currently. If we don't apply this before the "powered-down"
> cpuidle, we will lost L2 support after one successful powered-down
> cpuidle sequence.

OK, please do mention dependencies like this when posting the patches.
Thanks.