[PATCH v2 0/6] Adding support for SATA in EXYNO5

[PATCH v2 0/6] Adding support for SATA in EXYNO5

[Vasanth Ananthan]

The following set of patches provides drivers for SATA
and SATA PHY controller and also an interface for the
two entity to interact.

Vasanth Ananthan (6):
  ARM: EXYNOS5: Clock settings for SATA and SATA PHY
  ARM: EXYNOS5: DT Support for SATA and SATA PHY
  DRIVERS: ATA: SATA PHY utility framework
  DRIVERS:I2C: I2C driver polling mode support
  DRIVERS: ATA:  SATA controller driver
  DRIVERS: ATA: SATA PHY controller driver

 .../devicetree/bindings/ata/exynos-sata-phy.txt    |   14 +
 .../devicetree/bindings/ata/exynos-sata.txt        |   17 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |   15 +
 arch/arm/boot/dts/exynos5250.dtsi                  |   18 ++
 arch/arm/mach-exynos/clock-exynos5.c               |   21 ++-
 arch/arm/mach-exynos/include/mach/map.h            |    3 +
 arch/arm/mach-exynos/include/mach/regs-pmu.h       |    3 +
 arch/arm/mach-exynos/include/mach/regs-sata.h      |   29 ++
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    6 +
 drivers/ata/Kconfig                                |   22 ++
 drivers/ata/Makefile                               |    2 +
 drivers/ata/sata_exynos.c                          |  268 +++++++++++++++++
 drivers/ata/sata_exynos_phy.c                      |  300 ++++++++++++++++++++
 drivers/ata/sata_phy.c                             |  104 +++++++
 drivers/ata/sata_phy.h                             |   44 +++
 drivers/i2c/busses/i2c-s3c2410.c                   |   79 ++++--
 16 files changed, 923 insertions(+), 22 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
 create mode 100644 Documentation/devicetree/bindings/ata/exynos-sata.txt
 create mode 100644 arch/arm/mach-exynos/include/mach/regs-sata.h
 create mode 100644 drivers/ata/sata_exynos.c
 create mode 100644 drivers/ata/sata_exynos_phy.c
 create mode 100644 drivers/ata/sata_phy.c
 create mode 100644 drivers/ata/sata_phy.h

-- 
1.7.4.1

[PATCH v2 1/6] ARM: EXYNOS5: Clock settings for SATA and SATA PHY

[Vasanth Ananthan]

This patch adds neccessary clock entries for SATA, SATA PHY and
I2C_SATAPHY

Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
---
 arch/arm/mach-exynos/clock-exynos5.c |   21 ++++++++++++++++++---
 1 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index c44ca1e..124c54f 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -651,15 +651,20 @@ static struct clk exynos5_init_clocks_off[] = {
 		.ctrlbit	= (1 << 15),
 	}, {
 		.name		= "sata",
-		.devname	= "ahci",
+		.devname	= "exynos5-sata",
+		.parent         = &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 6),
 	}, {
-		.name		= "sata_phy",
+		.name		= "sata-phy",
+		.devname	= "exynos5-sata-phy",
+		.parent         = &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 24),
 	}, {
-		.name		= "sata_phy_i2c",
+		.name		= "i2c",
+		.devname	= "exynos5-sata-phy-i2c",
+		.parent         = &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 25),
 	}, {
@@ -1226,6 +1231,16 @@ static struct clksrc_clk exynos5_clksrcs[] = {
 		.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
 	}, {
 		.clk	= {
+			.name		= "sclk_sata",
+			.devname	= "exynos5-sata",
+			.enable		= exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.sources = &exynos5_clkset_aclk,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+	}, {
+		.clk	= {
 			.name		= "sclk_gscl_wrap",
 			.devname	= "s5p-mipi-csis.0",
 			.enable		= exynos5_clksrc_mask_gscl_ctrl,
-- 
1.7.4.1

[PATCH v2 2/6] ARM: EXYNOS5: DT Support for SATA and SATA PHY

[Vasanth Ananthan]

This patch adds Device Nodes for SATA and SATA PHY device.

Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
---
 .../devicetree/bindings/ata/exynos-sata-phy.txt    |   14 ++++++++++++++
 .../devicetree/bindings/ata/exynos-sata.txt        |   17 +++++++++++++++++
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |   15 +++++++++++++++
 arch/arm/boot/dts/exynos5250.dtsi                  |   18 ++++++++++++++++++
 arch/arm/mach-exynos/include/mach/map.h            |    3 +++
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    6 ++++++
 6 files changed, 73 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
 create mode 100644 Documentation/devicetree/bindings/ata/exynos-sata.txt

diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
new file mode 100644
index 0000000..37824fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
@@ -0,0 +1,14 @@
+* Samsung SATA PHY Controller
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible        : compatible list, contains "samsung,exynos5-sata-phy"
+- reg               : <registers mapping>
+
+Example:
+        sata at ffe07000 {
+                compatible = "samsung,exynos5-sata-phy";
+                reg = <0xffe07000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
new file mode 100644
index 0000000..0849f10
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -0,0 +1,17 @@
+* Samsung AHCI SATA Controller
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller should have its own node.
+
+Required properties:
+- compatible        : compatible list, contains "samsung,exynos5-sata"
+- interrupts        : <interrupt mapping for SATA IRQ>
+- reg               : <registers mapping>
+- samsung,sata-freq : <frequency in MHz>
+
+Example:
+        sata at ffe08000 {
+                compatible = "samsung,exynos5-sata";
+                reg = <0xffe08000 0x1000>;
+                interrupts = <115>;
+        };
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a352df4..6910deb 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -55,6 +55,21 @@
 		};
 	};
 
+	i2c at 121D0000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-max-bus-freq = <40000>;
+		samsung,i2c-slave-addr = <0x38>;
+
+		sata-phy {
+			compatible = "samsung,sata-phy";
+			reg = <0x38>;
+		};
+	};
+
+	sata at 122F0000 {
+		samsung,sata-freq = <66>;
+	};
+
 	i2c at 12C80000 {
 		status = "disabled";
 	};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dddfd6e..e41520f 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -92,6 +92,17 @@
 		interrupts = <0 54 0>;
 	};
 
+	sata at 122F0000 {
+		compatible = "samsung,exynos5-sata-ahci";
+		reg = <0x122F0000 0x1ff>;
+		interrupts = <0 115 0>;
+	};
+
+	sata-phy at 12170000 {
+		compatible = "samsung,exynos5-sata-phy";
+		reg = <0x12170000 0x1ff>;
+	};
+
 	i2c at 12C60000 {
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x12C60000 0x100>;
@@ -156,6 +167,13 @@
 		#size-cells = <0>;
 	};
 
+	i2c at 121D0000 {
+                compatible = "samsung,exynos5-sata-phy-i2c";
+                reg = <0x121D0000 0x100>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+	};
+
 	spi_0: spi at 12d20000 {
 		compatible = "samsung,exynos4210-spi";
 		reg = <0x12d20000 0x100>;
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 8480849..ffeb761 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -188,6 +188,9 @@
 #define EXYNOS4_PA_SATA			0x12560000
 #define EXYNOS4_PA_SATAPHY		0x125D0000
 #define EXYNOS4_PA_SATAPHY_CTRL		0x126B0000
+#define EXYNOS5_PA_SATA_PHY_CTRL	0x12170000
+#define EXYNOS5_PA_SATA_PHY_I2C		0x121D0000
+#define EXYNOS5_PA_SATA_BASE		0x122F0000
 
 #define EXYNOS4_PA_SROMC		0x12570000
 #define EXYNOS5_PA_SROMC		0x12250000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index db1cd8e..7dbd4cc 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -61,6 +61,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"exynos4210-spi.1", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
 				"exynos4210-spi.2", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", EXYNOS5_PA_SATA_BASE,
+				"exynos5-sata", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5-sata-phy", EXYNOS5_PA_SATA_PHY_CTRL,
+				"exynos5-sata-phy", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", EXYNOS5_PA_SATA_PHY_I2C,
+				"exynos5-sata-phy-i2c", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
-- 
1.7.4.1

[PATCH v2 3/6] DRIVERS: ATA: SATA PHY utility framework

[Vasanth Ananthan]

This patch adds SATA PHY utility framework APIs. The framework acts as an
interface between the SATA device and the PHY device. The SATA PHY device
registers itself with the framework through the APIs provided and the SATA
device finds and requests for an appropriate PHY device.

Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
---
 drivers/ata/Kconfig    |   10 +++++
 drivers/ata/Makefile   |    1 +
 drivers/ata/sata_phy.c |  104 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/ata/sata_phy.h |   44 ++++++++++++++++++++
 4 files changed, 159 insertions(+), 0 deletions(-)
 create mode 100644 drivers/ata/sata_phy.c
 create mode 100644 drivers/ata/sata_phy.h

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index e08d322..e3a2972 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -83,6 +83,16 @@ config SATA_AHCI_PLATFORM
 
 	  If unsure, say N.
 
+config SATA_PHY
+	bool "SATA PHY Framework"
+	default n
+	help
+	  This option enables the SATA PHY utility framework APIs.
+	  The framework acts as an interface between the SATA device
+	  and the PHY device. The SATA PHY device registers itself
+	  with the framework through the APIs provided and the SATA
+	  device finds and requests for an appropriate PHY device.
+
 config SATA_FSL
 	tristate "Freescale 3.0Gbps SATA support"
 	depends on FSL_SOC
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 9329daf..3d219a9 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X)	+= sata_inic162x.o
 obj-$(CONFIG_SATA_SIL24)	+= sata_sil24.o
 obj-$(CONFIG_SATA_DWC)		+= sata_dwc_460ex.o
 obj-$(CONFIG_SATA_HIGHBANK)	+= sata_highbank.o libahci.o
+obj-$(CONFIG_SATA_PHY)		+= sata_phy.o
 
 # SFF w/ custom DMA
 obj-$(CONFIG_PDC_ADMA)		+= pdc_adma.o
diff --git a/drivers/ata/sata_phy.c b/drivers/ata/sata_phy.c
new file mode 100644
index 0000000..e5631a9
--- /dev/null
+++ b/drivers/ata/sata_phy.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - SATA utility framework.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/err.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include "sata_phy.h"
+
+static LIST_HEAD(phy_list);
+static DEFINE_SPINLOCK(phy_lock);
+
+struct sata_phy *sata_get_phy(enum sata_phy_type type)
+{
+	struct sata_phy *x = NULL;
+	unsigned long flag;
+
+	if (list_empty(&phy_list))
+		return x;
+
+	spin_lock_irqsave(&phy_lock, flag);
+
+	list_for_each_entry(x, &phy_list, head) {
+		if (x->type == type) {
+			get_device(x->dev);
+			break;
+		}
+	}
+
+	spin_unlock_irqrestore(&phy_lock, flag);
+	return x;
+}
+EXPORT_SYMBOL(sata_get_phy);
+
+int sata_add_phy(struct sata_phy *phy, enum sata_phy_type type)
+{
+	unsigned long flag;
+	unsigned int ret = -EINVAL;
+	struct sata_phy *x;
+
+	spin_lock_irqsave(&phy_lock, flag);
+
+	if (!phy)
+		return ret;
+
+	list_for_each_entry(x, &phy_list, head) {
+		if (x->type == type) {
+			dev_err(phy->dev, "transceiver type already exists\n");
+			goto out;
+		}
+	}
+	phy->type = type;
+	list_add_tail(&phy->head, &phy_list);
+	ret = 0;
+
+ out:
+	spin_unlock_irqrestore(&phy_lock, flag);
+	return ret;
+}
+EXPORT_SYMBOL(sata_add_phy);
+
+void sata_remove_phy(struct sata_phy *phy)
+{
+	unsigned long flag;
+	struct sata_phy *x;
+
+	spin_lock_irqsave(&phy_lock, flag);
+
+	if (!phy)
+		return;
+
+	list_for_each_entry(x, &phy_list, head) {
+		if (x->type == phy->type)
+			list_del(&phy->head);
+	}
+
+	spin_unlock_irqrestore(&phy_lock, flag);
+}
+EXPORT_SYMBOL(sata_remove_phy);
+
+void sata_put_phy(struct sata_phy *phy)
+{
+	unsigned long flag;
+
+	spin_lock_irqsave(&phy_lock, flag);
+
+	if (!phy)
+		return;
+
+	put_device(phy->dev);
+	spin_unlock_irqrestore(&phy_lock, flag);
+
+}
+EXPORT_SYMBOL(sata_put_phy);
diff --git a/drivers/ata/sata_phy.h b/drivers/ata/sata_phy.h
new file mode 100644
index 0000000..dc38683
--- /dev/null
+++ b/drivers/ata/sata_phy.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - SATA utility framework definitions.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+enum sata_phy_type {
+	SATA_PHY_GENERATION1,
+	SATA_PHY_GENERATION2,
+	SATA_PHY_GENERATION3,
+};
+
+struct sata_phy {
+	int (*init) (struct sata_phy *);
+	int (*shutdown) (struct sata_phy *);
+	struct device *dev;
+	void *priv_data;
+	enum sata_phy_type type;
+	struct list_head head;
+};
+
+static inline int sata_init_phy(struct sata_phy *x)
+{
+	if (x && x->init)
+		return x->init(x);
+
+	return -EINVAL;
+}
+
+static inline void sata_shutdown_phy(struct sata_phy *x)
+{
+	if (x && x->shutdown)
+		x->shutdown(x);
+}
+
+struct sata_phy *sata_get_phy(enum sata_phy_type);
+int sata_add_phy(struct sata_phy *, enum sata_phy_type);
+void sata_remove_phy(struct sata_phy *);
+void sata_put_phy(struct sata_phy *);
-- 
1.7.4.1

[PATCH v2 4/6] DRIVERS:I2C: I2C driver polling mode support

[Vasanth Ananthan]

This patch adds polling mode support for i2c s3c-2410 driver.
The I2C_SATAPHY controller lacks an interrupt line but the s3c-2410 driver
is interrupt driven. Hence this support is required for functioning
of the I2C_SATAPHY controller.

Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
---
 drivers/i2c/busses/i2c-s3c2410.c |   79 ++++++++++++++++++++++++++++---------
 1 files changed, 60 insertions(+), 19 deletions(-)

diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 3e0335f..5712e40 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -48,6 +48,7 @@
 #define QUIRK_S3C2440		(1 << 0)
 #define QUIRK_HDMIPHY		(1 << 1)
 #define QUIRK_NO_GPIO		(1 << 2)
+#define QUIRK_SATAPHY		(1 << 3)
 
 /* i2c controller state */
 enum s3c24xx_i2c_state {
@@ -102,10 +103,14 @@ static struct platform_device_id s3c24xx_driver_ids[] = {
 };
 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 
+static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
+
 #ifdef CONFIG_OF
 static const struct of_device_id s3c24xx_i2c_match[] = {
 	{ .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
 	{ .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
+	{ .compatible = "samsung,exynos5-sata-phy-i2c",
+	  .data = (void *)(QUIRK_S3C2440 | QUIRK_SATAPHY | QUIRK_NO_GPIO) },
 	{ .compatible = "samsung,s3c2440-hdmiphy-i2c",
 	  .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
 	{},
@@ -146,7 +151,8 @@ static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 	if (ret)
 		i2c->msg_idx = ret;
 
-	wake_up(&i2c->wait);
+	if (!(i2c->quirks & QUIRK_SATAPHY))
+		wake_up(&i2c->wait);
 }
 
 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
@@ -184,6 +190,23 @@ static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 }
 
 
+static bool is_ack(struct s3c24xx_i2c *i2c)
+{
+	u32 time_out = i2c->tx_setup;
+
+	while (--time_out) {
+		if (readl(i2c->regs + S3C2410_IICCON)
+			& S3C2410_IICCON_IRQPEND) {
+			if (!(readl(i2c->regs + S3C2410_IICSTAT)
+				& S3C2410_IICSTAT_LASTBIT))
+				return true;
+		}
+		udelay(time_out);
+	}
+
+	return false;
+}
+
 /* s3c24xx_i2c_message_start
  *
  * put the start of a message onto the bus
@@ -227,6 +250,15 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 
 	stat |= S3C2410_IICSTAT_START;
 	writel(stat, i2c->regs + S3C2410_IICSTAT);
+
+	if (i2c->quirks & QUIRK_SATAPHY) {
+		while ((i2c->msg_num != 0) && is_ack(i2c)) {
+			i2c_s3c_irq_nextbyte(i2c, stat);
+			stat = readl(i2c->regs + S3C2410_IICSTAT);
+			if (stat & S3C2410_IICSTAT_ARBITR)
+				dev_err(i2c->dev, "deal with arbitration loss\n");
+		}
+	}
 }
 
 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
@@ -552,19 +584,23 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 	s3c24xx_i2c_message_start(i2c, msgs);
 	spin_unlock_irq(&i2c->lock);
 
-	timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
-
 	ret = i2c->msg_idx;
 
-	/* having these next two as dev_err() makes life very
-	 * noisy when doing an i2cdetect */
+	if (!(i2c->quirks & QUIRK_SATAPHY)) {
 
-	if (timeout == 0)
-		dev_dbg(i2c->dev, "timeout\n");
-	else if (ret != num)
-		dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
+		timeout = wait_event_timeout(i2c->wait,
+				i2c->msg_num == 0, HZ * 5);
 
-	/* ensure the stop has been through the bus */
+		/* having these next two as dev_err() makes life very
+		* noisy when doing an i2cdetect */
+
+		if (timeout == 0)
+			dev_dbg(i2c->dev, "timeout\n");
+		else if (ret != num)
+			dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
+
+		/* ensure the stop has been through the bus */
+	}
 
 	dev_dbg(i2c->dev, "waiting for bus idle\n");
 
@@ -710,6 +746,9 @@ static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 	if (div1 == 512)
 		iiccon |= S3C2410_IICCON_TXDIV_512;
 
+	if (i2c->quirks & QUIRK_SATAPHY)
+		iiccon |= S3C2410_IICCON_SCALE(2);
+
 	writel(iiccon, i2c->regs + S3C2410_IICCON);
 
 	if (i2c->quirks & QUIRK_S3C2440) {
@@ -1023,18 +1062,20 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
 	 * ensure no current IRQs pending
 	 */
 
-	i2c->irq = ret = platform_get_irq(pdev, 0);
-	if (ret <= 0) {
-		dev_err(&pdev->dev, "cannot find IRQ\n");
-		goto err_iomap;
-	}
+	if (!(i2c->quirks & QUIRK_SATAPHY)) {
+		i2c->irq = ret = platform_get_irq(pdev, 0);
+		if (ret <= 0) {
+			dev_err(&pdev->dev, "cannot find IRQ\n");
+			goto err_iomap;
+		}
 
-	ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0,
+		ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0,
 			  dev_name(&pdev->dev), i2c);
 
-	if (ret != 0) {
-		dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
-		goto err_iomap;
+		if (ret != 0) {
+			dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
+			goto err_iomap;
+		}
 	}
 
 	ret = s3c24xx_i2c_register_cpufreq(i2c);
-- 
1.7.4.1

[PATCH v2 5/6] DRIVERS: ATA: SATA controller driver

[Vasanth Ananthan]

This patch adds a platform driver for SATA controller.

Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
---
 arch/arm/mach-exynos/include/mach/regs-pmu.h |    3 +
 drivers/ata/Kconfig                          |   12 ++
 drivers/ata/Makefile                         |    1 +
 drivers/ata/sata_exynos.c                    |  268 ++++++++++++++++++++++++++
 4 files changed, 284 insertions(+), 0 deletions(-)
 create mode 100644 drivers/ata/sata_exynos.c

diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index d4e392b..3716ce8 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -367,4 +367,7 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)
 
+/* Only for EXYNOS5250 */
+#define EXYNOS5_SATA_PHY_CONTROL		S5P_PMUREG(0x0724)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index e3a2972..f3384ed 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -93,6 +93,18 @@ config SATA_PHY
 	  with the framework through the APIs provided and the SATA
 	  device finds and requests for an appropriate PHY device.
 
+config SATA_EXYNOS
+        bool "Exynos SATA AHCI support"
+        select I2C
+        select HAVE_S3C2410_I2C
+        select I2C_S3C2410
+        select SATA_PHY
+        help
+          This option enables support for Exynos AHCI Serial ATA
+          controllers.
+
+          If unsure, say N.
+
 config SATA_FSL
 	tristate "Freescale 3.0Gbps SATA support"
 	depends on FSL_SOC
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 3d219a9..43bb38e 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24)	+= sata_sil24.o
 obj-$(CONFIG_SATA_DWC)		+= sata_dwc_460ex.o
 obj-$(CONFIG_SATA_HIGHBANK)	+= sata_highbank.o libahci.o
 obj-$(CONFIG_SATA_PHY)		+= sata_phy.o
+obj-$(CONFIG_SATA_EXYNOS)	+= sata_exynos.o libahci.o
 
 # SFF w/ custom DMA
 obj-$(CONFIG_PDC_ADMA)		+= pdc_adma.o
diff --git a/drivers/ata/sata_exynos.c b/drivers/ata/sata_exynos.c
new file mode 100644
index 0000000..41dc17d
--- /dev/null
+++ b/drivers/ata/sata_exynos.c
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - SATA controller driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/gfp.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/libata.h>
+#include <linux/ahci_platform.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+
+#include "ahci.h"
+#include "sata_phy.h"
+
+#define MHZ            (1000 * 1000)
+
+static const struct ata_port_info ahci_port_info = {
+	.flags = AHCI_FLAG_COMMON,
+	.pio_mask = ATA_PIO4,
+	.udma_mask = ATA_UDMA6,
+	.port_ops = &ahci_ops,
+};
+
+static struct scsi_host_template ahci_platform_sht = {
+	AHCI_SHT("ahci_platform"),
+};
+
+struct exynos_sata {
+	struct clk *sclk;
+	struct clk *clk;
+	struct sata_phy *phy;
+	int irq;
+	unsigned int freq;
+};
+
+static void exynos_sata_parse_dt(struct device_node *np,
+					struct exynos_sata *sata)
+{
+	if (!np)
+		return;
+
+	of_property_read_u32(np, "samsung,sata-freq", &sata->freq);
+}
+
+static int __init exynos_sata_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ata_port_info pi = ahci_port_info;
+	const struct ata_port_info *ppi[] = { &pi, NULL };
+	struct ahci_host_priv *hpriv;
+	struct exynos_sata *sata;
+	struct ata_host *host;
+	struct resource *mem;
+	int n_ports, i, ret;
+
+	sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
+	if (!sata) {
+		dev_err(dev, "can't alloc sata\n");
+		return -EINVAL;
+	}
+
+	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
+	if (!hpriv) {
+		dev_err(dev, "can't alloc ahci_host_priv\n");
+		ret = -ENOMEM;
+		goto err1;
+	}
+
+	hpriv->flags |= (unsigned long)pi.private_data;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		dev_err(dev, "no mmio space\n");
+		ret = -EINVAL;
+		goto err2;
+	}
+
+	sata->irq = platform_get_irq(pdev, 0);
+	if (sata->irq <= 0) {
+		dev_err(dev, "no irq\n");
+		ret = -EINVAL;
+		goto err2;
+	}
+
+	hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
+	if (!hpriv->mmio) {
+		dev_err(dev, "can't map %pR\n", mem);
+		ret = -ENOMEM;
+		goto err2;
+	}
+
+	exynos_sata_parse_dt(dev->of_node, sata);
+
+	sata->sclk = devm_clk_get(dev, "sclk_sata");
+	if (IS_ERR(sata->sclk)) {
+		dev_err(dev, "failed to get sclk_sata\n");
+		ret = PTR_ERR(sata->sclk);
+		goto err3;
+	}
+	clk_enable(sata->sclk);
+
+	clk_set_rate(sata->sclk, sata->freq * MHZ);
+
+	sata->clk = devm_clk_get(dev, "sata");
+	if (IS_ERR(sata->clk)) {
+		dev_err(dev, "failed to get sata clock\n");
+		ret = PTR_ERR(sata->clk);
+		goto err4;
+	}
+	clk_enable(sata->clk);
+
+	/*  Get a gen 3 PHY controller */
+
+	sata->phy = sata_get_phy(SATA_PHY_GENERATION3);
+	if (!sata->phy) {
+		dev_err(dev, "failed to get sata phy\n");
+		ret = -EPROBE_DEFER;
+		goto err5;
+	}
+
+	/* Initialize the controller */
+
+	ret = sata_init_phy(sata->phy);
+	if (ret < 0) {
+		dev_err(dev, "failed to initialize sata phy\n");
+		goto err6;
+	}
+
+	ahci_save_initial_config(dev, hpriv, 0, 0);
+
+	/* prepare host */
+	if (hpriv->cap & HOST_CAP_NCQ)
+		pi.flags |= ATA_FLAG_NCQ;
+
+	if (hpriv->cap & HOST_CAP_PMP)
+		pi.flags |= ATA_FLAG_PMP;
+
+	ahci_set_em_messages(hpriv, &pi);
+
+	/* CAP.NP sometimes indicate the index of the last enabled
+	 * port, at other times, that of the last possible port, so
+	 * determining the maximum port number requires looking at
+	 * both CAP.NP and port_map.
+	 */
+	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
+
+	host = ata_host_alloc_pinfo(dev, ppi, n_ports);
+	if (!host) {
+		ret = -ENOMEM;
+		goto err7;
+	}
+
+	host->private_data = hpriv;
+
+	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
+		host->flags |= ATA_HOST_PARALLEL_SCAN;
+	else
+		pr_info(KERN_INFO
+		       "ahci: SSS flag set, parallel bus scan disabled\n");
+
+	if (pi.flags & ATA_FLAG_EM)
+		ahci_reset_em(host);
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap = host->ports[i];
+
+		ata_port_desc(ap, "mmio %pR", mem);
+		ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
+
+		/* set enclosure management message type */
+		if (ap->flags & ATA_FLAG_EM)
+			ap->em_message_type = hpriv->em_msg_type;
+
+		/* disabled/not-implemented port */
+		if (!(hpriv->port_map & (1 << i)))
+			ap->ops = &ata_dummy_port_ops;
+	}
+
+	ret = ahci_reset_controller(host);
+	if (ret)
+		goto err7;
+
+	ahci_init_controller(host);
+	ahci_print_info(host, "platform");
+
+	ret = ata_host_activate(host, sata->irq, ahci_interrupt, IRQF_SHARED,
+				&ahci_platform_sht);
+	if (ret)
+		goto err7;
+
+	platform_set_drvdata(pdev, sata);
+
+	return 0;
+
+ err7:
+	sata_shutdown_phy(sata->phy);
+
+ err6:
+	sata_put_phy(sata->phy);
+
+ err5:
+	clk_disable(sata->clk);
+	devm_clk_put(dev, sata->clk);
+
+ err4:
+	clk_disable(sata->sclk);
+	devm_clk_put(dev, sata->sclk);
+
+ err3:
+	devm_iounmap(dev, hpriv->mmio);
+
+ err2:
+	devm_kfree(dev, hpriv);
+
+ err1:
+	devm_kfree(dev, sata);
+
+	return ret;
+}
+
+static int __devexit exynos_sata_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ata_host *host = dev_get_drvdata(dev);
+	struct exynos_sata *sata = platform_get_drvdata(pdev);
+
+	ata_host_detach(host);
+
+	sata_shutdown_phy(sata->phy);
+	sata_put_phy(sata->phy);
+
+	return 0;
+}
+
+static const struct of_device_id ahci_of_match[] = {
+	{ .compatible = "samsung,exynos5-sata-ahci", },
+};
+
+MODULE_DEVICE_TABLE(of, ahci_of_match);
+
+static struct platform_driver exynos_sata_driver = {
+	.probe	= exynos_sata_probe,
+	.remove = exynos_sata_remove,
+	.driver = {
+		.name = "ahci-sata",
+		.owner = THIS_MODULE,
+		.of_match_table = ahci_of_match,
+	},
+};
+
+module_platform_driver(exynos_sata_driver);
+
+MODULE_DESCRIPTION("EXYNOS SATA DRIVER");
+MODULE_AUTHOR("Vasanth Ananthan, <vasanth.a@samsung.com>");
+MODULE_LICENSE("GPL");
-- 
1.7.4.1

[PATCH v2 6/6] DRIVERS: ATA: SATA PHY controller driver

[Vasanth Ananthan]

This patch adds a platform driver and I2C client driver for SATA PHY controller

Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
---
 arch/arm/mach-exynos/include/mach/regs-sata.h |   29 +++
 drivers/ata/Makefile                          |    2 +-
 drivers/ata/sata_exynos_phy.c                 |  300 +++++++++++++++++++++++++
 3 files changed, 330 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-exynos/include/mach/regs-sata.h
 create mode 100644 drivers/ata/sata_exynos_phy.c

diff --git a/arch/arm/mach-exynos/include/mach/regs-sata.h b/arch/arm/mach-exynos/include/mach/regs-sata.h
new file mode 100644
index 0000000..80dd564
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-sata.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - SATA PHY controller definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define EXYNOS5_SATA_RESET		0x4
+#define RESET_CMN_RST_N			(1 << 1)
+#define LINK_RESET			0xF0000
+
+#define EXYNOS5_SATA_MODE0		0x10
+
+#define EXYNOS5_SATA_CTRL0		0x14
+#define CTRL0_P0_PHY_CALIBRATED_SEL	(1 << 9)
+#define CTRL0_P0_PHY_CALIBRATED		(1 << 8)
+
+#define EXYNOS5_SATA_PHSATA_CTRLM	0xE0
+#define PHCTRLM_REF_RATE		(1 << 1)
+#define PHCTRLM_HIGH_SPEED		(1 << 0)
+
+#define EXYNOS5_SATA_PHSATA_STATM	0xF0
+#define PHSTATM_PLL_LOCKED		(1 << 0)
+
+#define SATA_PHY_CON_RESET              0xF003F
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 43bb38e..6a3a8ee 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_SATA_SIL24)	+= sata_sil24.o
 obj-$(CONFIG_SATA_DWC)		+= sata_dwc_460ex.o
 obj-$(CONFIG_SATA_HIGHBANK)	+= sata_highbank.o libahci.o
 obj-$(CONFIG_SATA_PHY)		+= sata_phy.o
-obj-$(CONFIG_SATA_EXYNOS)	+= sata_exynos.o libahci.o
+obj-$(CONFIG_SATA_EXYNOS)	+= sata_exynos.o sata_exynos_phy.o libahci.o
 
 # SFF w/ custom DMA
 obj-$(CONFIG_PDC_ADMA)		+= pdc_adma.o
diff --git a/drivers/ata/sata_exynos_phy.c b/drivers/ata/sata_exynos_phy.c
new file mode 100644
index 0000000..ec61db5
--- /dev/null
+++ b/drivers/ata/sata_exynos_phy.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - SATA PHY controller driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/ahci_platform.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/io.h>
+
+#include <plat/cpu.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <mach/regs-pmu.h>
+#include <mach/regs-sata.h>
+
+#include "sata_phy.h"
+
+#define	SATA_TIME_LIMIT		1000
+
+static struct i2c_client *i2c_client;
+
+static struct i2c_driver sataphy_i2c_driver;
+
+struct exynos_sata_phy {
+	void __iomem *mmio;
+	struct resource *mem;
+	struct clk *clk;
+};
+
+static bool sata_is_reg(void __iomem *base, u32 reg, u32 checkbit, u32 status)
+{
+	if ((readl(base + reg) & checkbit) == status)
+		return true;
+	else
+		return false;
+}
+
+static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
+				u32 status)
+{
+	u16 time_limit_cnt = 0;
+	while (!sata_is_reg(base, reg, checkbit, status)) {
+		if (time_limit_cnt == SATA_TIME_LIMIT)
+			return false;
+		udelay(1000);
+		time_limit_cnt++;
+	}
+	return true;
+}
+
+static int sataphy_init(struct sata_phy *phy)
+{
+	int ret;
+	u32 val;
+
+	/* Values to be written to enable 40 bits interface */
+	u8 buf[] = { 0x3A, 0x0B };
+
+	struct exynos_sata_phy *sata_phy;
+
+	if (!i2c_client)
+		return -EPROBE_DEFER;
+
+	sata_phy = (struct exynos_sata_phy *)phy->priv_data;
+
+	clk_enable(sata_phy->clk);
+
+	writel(S5P_PMU_SATA_PHY_CONTROL_EN, EXYNOS5_SATA_PHY_CONTROL);
+
+	val = 0;
+	writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
+
+	val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
+	val |= 0xFF;
+	writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
+
+	val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
+	val |= LINK_RESET;
+	writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
+
+	val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
+	val |= RESET_CMN_RST_N;
+	writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
+
+	val = readl(sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
+	val &= ~PHCTRLM_REF_RATE;
+	writel(val, sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
+
+	/* High speed enable for Gen3 */
+	val = readl(sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
+	val |= PHCTRLM_HIGH_SPEED;
+	writel(val, sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
+
+	val = readl(sata_phy->mmio + EXYNOS5_SATA_CTRL0);
+	val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
+	writel(val, sata_phy->mmio + EXYNOS5_SATA_CTRL0);
+
+	writel(SATA_PHY_GENERATION3, sata_phy->mmio + EXYNOS5_SATA_MODE0);
+
+	ret = i2c_master_send(i2c_client, buf, sizeof(buf));
+	if (ret < 0)
+		return -EINVAL;
+
+	/* release cmu reset */
+	val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
+	val &= ~RESET_CMN_RST_N;
+	writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
+
+	val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
+	val |= RESET_CMN_RST_N;
+	writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
+
+	if (wait_for_reg_status(sata_phy->mmio, EXYNOS5_SATA_PHSATA_STATM,
+				PHSTATM_PLL_LOCKED, 1)) {
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static int sataphy_shutdown(struct sata_phy *phy)
+{
+
+	struct exynos_sata_phy *sata_phy;
+
+	sata_phy = (struct exynos_sata_phy *)phy->priv_data;
+
+	clk_disable(sata_phy->clk);
+
+	return 0;
+}
+
+static int __init sata_i2c_probe(struct i2c_client *client,
+			  const struct i2c_device_id *i2c_id)
+{
+	i2c_client = client;
+	return 0;
+}
+
+static int __init sata_phy_probe(struct platform_device *pdev)
+{
+	struct exynos_sata_phy *sataphy;
+	struct sata_phy *phy;
+	struct resource *res;
+	struct device *dev = &pdev->dev;
+	int ret = 0;
+
+	phy = kzalloc(sizeof(struct sata_phy), GFP_KERNEL);
+	if (!phy) {
+		dev_err(&pdev->dev, "failed to allocate memory\n");
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	sataphy = kzalloc(sizeof(struct exynos_sata_phy), GFP_KERNEL);
+	if (!sataphy) {
+		dev_err(dev, "failed to allocate memory\n");
+		ret = -ENOMEM;
+		goto err0;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "Could not find IO resource\n");
+		ret = -EINVAL;
+		goto err1;
+	}
+
+	sataphy->mem = devm_request_mem_region(dev, res->start,
+					resource_size(res), pdev->name);
+	if (!sataphy->mem) {
+		dev_err(dev, "Could not request IO resource\n");
+		ret = -EINVAL;
+		goto err1;
+	}
+
+	sataphy->mmio =
+	    devm_ioremap(dev, res->start, resource_size(res));
+	if (!sataphy->mmio) {
+		dev_err(dev, "failed to remap IO\n");
+		ret = -ENOMEM;
+		goto err2;
+	}
+
+	sataphy->clk = devm_clk_get(dev, "sata-phy");
+	if (IS_ERR(sataphy->clk)) {
+		dev_err(dev, "failed to get clk for PHY\n");
+		ret = PTR_ERR(sataphy->clk);
+		goto err3;
+	}
+
+	phy->init = sataphy_init;
+	phy->shutdown = sataphy_shutdown;
+	phy->priv_data = (void *)sataphy;
+	phy->dev = dev;
+
+	ret = sata_add_phy(phy, SATA_PHY_GENERATION3);
+	if (ret < 0)
+		goto err4;
+
+	ret = i2c_add_driver(&sataphy_i2c_driver);
+	if (ret < 0)
+		goto err5;
+
+	platform_set_drvdata(pdev, phy);
+
+	return ret;
+
+ err5:
+	sata_remove_phy(phy);
+
+ err4:
+	clk_disable(sataphy->clk);
+	devm_clk_put(dev, sataphy->clk);
+
+ err3:
+	devm_iounmap(dev, sataphy->mmio);
+
+ err2:
+	devm_release_mem_region(dev, res->start, resource_size(res));
+
+ err1:
+	kfree(sataphy);
+
+ err0:
+	kfree(phy);
+
+ out:
+	return ret;
+}
+
+static int sata_phy_remove(struct platform_device *pdev)
+{
+	struct sata_phy *phy;
+	struct exynos_sata_phy *sataphy;
+
+	phy = platform_get_drvdata(pdev);
+
+	sataphy = (struct exynos_sata_phy *)phy->priv_data;
+	sata_remove_phy(phy);
+
+	kfree(sataphy);
+	kfree(phy);
+
+	return 0;
+}
+
+static const struct of_device_id sata_phy_of_match[] = {
+	{ .compatible = "samsung,exynos5-sata-phy", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, sata_phy_of_match);
+
+static const struct i2c_device_id phy_i2c_device_match[] = {
+	{ "sata-phy", 0 },
+};
+
+MODULE_DEVICE_TABLE(of, phy_i2c_device_match);
+
+static struct platform_driver sata_phy_driver = {
+	.probe = sata_phy_probe,
+	.remove = sata_phy_remove,
+	.driver = {
+		   .name = "sata-phy",
+		   .owner = THIS_MODULE,
+		   .of_match_table = sata_phy_of_match,
+	},
+};
+
+static struct i2c_driver sataphy_i2c_driver = {
+	.driver = {
+		   .name = "sata-phy-i2c",
+		   .owner = THIS_MODULE,
+		   .of_match_table = phy_i2c_device_match,
+	},
+	.probe = sata_i2c_probe,
+	.id_table = phy_i2c_device_match,
+};
+
+module_platform_driver(sata_phy_driver);
+
+MODULE_DESCRIPTION("EXYNOS SATA PHY DRIVER");
+MODULE_AUTHOR("Vasanth Ananthan, <vasanth.a@samsung.com>");
+MODULE_LICENSE("GPL");
-- 
1.7.4.1

[PATCH v2 1/6] ARM: EXYNOS5: Clock settings for SATA and SATA PHY

[Kukjin Kim]

Vasanth Ananthan wrote:
> 
> This patch adds neccessary clock entries for SATA, SATA PHY and
> I2C_SATAPHY
> 
> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> ---
>  arch/arm/mach-exynos/clock-exynos5.c |   21 ++++++++++++++++++---
>  1 files changed, 18 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-
> exynos/clock-exynos5.c
> index c44ca1e..124c54f 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -651,15 +651,20 @@ static struct clk exynos5_init_clocks_off[] = {
>  		.ctrlbit	= (1 << 15),
>  	}, {
>  		.name		= "sata",
> -		.devname	= "ahci",
> +		.devname	= "exynos5-sata",
> +		.parent         = &exynos5_clk_aclk_200.clk,
>  		.enable		= exynos5_clk_ip_fsys_ctrl,
>  		.ctrlbit	= (1 << 6),
>  	}, {
> -		.name		= "sata_phy",
> +		.name		= "sata-phy",
> +		.devname	= "exynos5-sata-phy",
> +		.parent         = &exynos5_clk_aclk_200.clk,
>  		.enable		= exynos5_clk_ip_fsys_ctrl,
>  		.ctrlbit	= (1 << 24),
>  	}, {
> -		.name		= "sata_phy_i2c",
> +		.name		= "i2c",
> +		.devname	= "exynos5-sata-phy-i2c",
> +		.parent         = &exynos5_clk_aclk_200.clk,
>  		.enable		= exynos5_clk_ip_fsys_ctrl,
>  		.ctrlbit	= (1 << 25),
>  	}, {
> @@ -1226,6 +1231,16 @@ static struct clksrc_clk exynos5_clksrcs[] = {
>  		.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size
> = 3 },
>  	}, {
>  		.clk	= {
> +			.name		= "sclk_sata",
> +			.devname	= "exynos5-sata",
> +			.enable		= exynos5_clksrc_mask_fsys_ctrl,
> +			.ctrlbit	= (1 << 24),
> +		},
> +		.sources = &exynos5_clkset_aclk,
> +		.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size
> = 1 },
> +		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size
> = 4 },
> +	}, {
> +		.clk	= {
>  			.name		= "sclk_gscl_wrap",
>  			.devname	= "s5p-mipi-csis.0",
>  			.enable		= exynos5_clksrc_mask_gscl_ctrl,
> --
> 1.7.4.1

Looks OK to me, need to think again about naming though?, anyway, this can
be handled separate from this series.

Let me take this into Samsung tree, if any problems, please let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 2/6] ARM: EXYNOS5: DT Support for SATA and SATA PHY

[Kukjin Kim]

Vasanth Ananthan wrote:
> 
> This patch adds Device Nodes for SATA and SATA PHY device.
> 

[...]

> @@ -188,6 +188,9 @@
>  #define EXYNOS4_PA_SATA			0x12560000
>  #define EXYNOS4_PA_SATAPHY		0x125D0000
>  #define EXYNOS4_PA_SATAPHY_CTRL		0x126B0000
> +#define EXYNOS5_PA_SATA_PHY_CTRL	0x12170000
> +#define EXYNOS5_PA_SATA_PHY_I2C		0x121D0000
> +#define EXYNOS5_PA_SATA_BASE		0x122F0000
> 
>  #define EXYNOS4_PA_SROMC		0x12570000
>  #define EXYNOS5_PA_SROMC		0x12250000
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-
> exynos/mach-exynos5-dt.c
> index db1cd8e..7dbd4cc 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -61,6 +61,12 @@ static const struct of_dev_auxdata
> exynos5250_auxdata_lookup[] __initconst = {
>  				"exynos4210-spi.1", NULL),
>  	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
>  				"exynos4210-spi.2", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", EXYNOS5_PA_SATA_BASE,
> +				"exynos5-sata", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5-sata-phy", EXYNOS5_PA_SATA_PHY_CTRL,
> +				"exynos5-sata-phy", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c",
> EXYNOS5_PA_SATA_PHY_I2C,
> +				"exynos5-sata-phy-i2c", NULL),
>  	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
>  	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
>  	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
> --
> 1.7.4.1

Just following is enough? Because we don't need the definitions only for
here...

8<-------
+	OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
+				"exynos5-sata", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x126B0000,
+				"exynos5-sata-phy", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
+				"exynos5-sata-phy-i2c", NULL),
8<-------

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 1/6] ARM: EXYNOS5: Clock settings for SATA and SATA PHY

[Kukjin Kim]

Kukjin Kim wrote:
> 
> Vasanth Ananthan wrote:
> >
> > This patch adds neccessary clock entries for SATA, SATA PHY and
> > I2C_SATAPHY
> >
> > Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> > ---
> >  arch/arm/mach-exynos/clock-exynos5.c |   21 ++++++++++++++++++---
> >  1 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-
> > exynos/clock-exynos5.c
> > index c44ca1e..124c54f 100644
> > --- a/arch/arm/mach-exynos/clock-exynos5.c
> > +++ b/arch/arm/mach-exynos/clock-exynos5.c
> > @@ -651,15 +651,20 @@ static struct clk exynos5_init_clocks_off[] = {
> >  		.ctrlbit	= (1 << 15),
> >  	}, {
> >  		.name		= "sata",
> > -		.devname	= "ahci",
> > +		.devname	= "exynos5-sata",
> > +		.parent         = &exynos5_clk_aclk_200.clk,
> >  		.enable		= exynos5_clk_ip_fsys_ctrl,
> >  		.ctrlbit	= (1 << 6),
> >  	}, {
> > -		.name		= "sata_phy",
> > +		.name		= "sata-phy",
> > +		.devname	= "exynos5-sata-phy",
> > +		.parent         = &exynos5_clk_aclk_200.clk,
> >  		.enable		= exynos5_clk_ip_fsys_ctrl,
> >  		.ctrlbit	= (1 << 24),
> >  	}, {
> > -		.name		= "sata_phy_i2c",
> > +		.name		= "i2c",
> > +		.devname	= "exynos5-sata-phy-i2c",
> > +		.parent         = &exynos5_clk_aclk_200.clk,
> >  		.enable		= exynos5_clk_ip_fsys_ctrl,
> >  		.ctrlbit	= (1 << 25),
> >  	}, {
> > @@ -1226,6 +1231,16 @@ static struct clksrc_clk exynos5_clksrcs[] = {
> >  		.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size
> > = 3 },
> >  	}, {
> >  		.clk	= {
> > +			.name		= "sclk_sata",
> > +			.devname	= "exynos5-sata",
> > +			.enable		= exynos5_clksrc_mask_fsys_ctrl,
> > +			.ctrlbit	= (1 << 24),
> > +		},
> > +		.sources = &exynos5_clkset_aclk,
> > +		.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size
> > = 1 },
> > +		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size
> > = 4 },
> > +	}, {
> > +		.clk	= {
> >  			.name		= "sclk_gscl_wrap",
> >  			.devname	= "s5p-mipi-csis.0",
> >  			.enable		= exynos5_clksrc_mask_gscl_ctrl,
> > --
> > 1.7.4.1
> 
> Looks OK to me, need to think again about naming though?, anyway, this can
> be handled separate from this series.
> 
> Let me take this into Samsung tree, if any problems, please let me know.
> 
Applied, thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 2/6] ARM: EXYNOS5: DT Support for SATA and SATA PHY

[Kukjin Kim]

Kukjin Kim wrote:
> 
> Vasanth Ananthan wrote:
> >
> > This patch adds Device Nodes for SATA and SATA PHY device.
> >
> 
> [...]
> 
> > @@ -188,6 +188,9 @@
> >  #define EXYNOS4_PA_SATA			0x12560000
> >  #define EXYNOS4_PA_SATAPHY		0x125D0000
> >  #define EXYNOS4_PA_SATAPHY_CTRL		0x126B0000
> > +#define EXYNOS5_PA_SATA_PHY_CTRL	0x12170000
> > +#define EXYNOS5_PA_SATA_PHY_I2C		0x121D0000
> > +#define EXYNOS5_PA_SATA_BASE		0x122F0000
> >
> >  #define EXYNOS4_PA_SROMC		0x12570000
> >  #define EXYNOS5_PA_SROMC		0x12250000
> > diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-
> > exynos/mach-exynos5-dt.c
> > index db1cd8e..7dbd4cc 100644
> > --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> > +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> > @@ -61,6 +61,12 @@ static const struct of_dev_auxdata
> > exynos5250_auxdata_lookup[] __initconst = {
> >  				"exynos4210-spi.1", NULL),
> >  	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
> >  				"exynos4210-spi.2", NULL),
> > +	OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", EXYNOS5_PA_SATA_BASE,
> > +				"exynos5-sata", NULL),
> > +	OF_DEV_AUXDATA("samsung,exynos5-sata-phy", EXYNOS5_PA_SATA_PHY_CTRL,
> > +				"exynos5-sata-phy", NULL),
> > +	OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c",
> > EXYNOS5_PA_SATA_PHY_I2C,
> > +				"exynos5-sata-phy-i2c", NULL),
> >  	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
> >  	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
> >  	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
> > --
> > 1.7.4.1
> 
> Just following is enough? Because we don't need the definitions only for
> here...
> 
> 8<-------
> +	OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
> +				"exynos5-sata", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x126B0000,
> +				"exynos5-sata-phy", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
> +				"exynos5-sata-phy-i2c", NULL),
> 8<-------
> 

Applied with above changes.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v2 1/6] ARM: EXYNOS5: Clock settings for SATA and SATA PHY

[Vasanth Ananthan]

Hi,

Missed to include Ben, for I2C patch, including him and copying others.

Thanks,
Vasanth.

On Tue, Oct 30, 2012 at 9:31 PM, Vasanth Ananthan
<vasanthananthan@gmail.com> wrote:
> This patch adds neccessary clock entries for SATA, SATA PHY and
> I2C_SATAPHY
>
> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> ---
>  arch/arm/mach-exynos/clock-exynos5.c |   21 ++++++++++++++++++---
>  1 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> index c44ca1e..124c54f 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -651,15 +651,20 @@ static struct clk exynos5_init_clocks_off[] = {
>                 .ctrlbit        = (1 << 15),
>         }, {
>                 .name           = "sata",
> -               .devname        = "ahci",
> +               .devname        = "exynos5-sata",
> +               .parent         = &exynos5_clk_aclk_200.clk,
>                 .enable         = exynos5_clk_ip_fsys_ctrl,
>                 .ctrlbit        = (1 << 6),
>         }, {
> -               .name           = "sata_phy",
> +               .name           = "sata-phy",
> +               .devname        = "exynos5-sata-phy",
> +               .parent         = &exynos5_clk_aclk_200.clk,
>                 .enable         = exynos5_clk_ip_fsys_ctrl,
>                 .ctrlbit        = (1 << 24),
>         }, {
> -               .name           = "sata_phy_i2c",
> +               .name           = "i2c",
> +               .devname        = "exynos5-sata-phy-i2c",
> +               .parent         = &exynos5_clk_aclk_200.clk,
>                 .enable         = exynos5_clk_ip_fsys_ctrl,
>                 .ctrlbit        = (1 << 25),
>         }, {
> @@ -1226,6 +1231,16 @@ static struct clksrc_clk exynos5_clksrcs[] = {
>                 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
>         }, {
>                 .clk    = {
> +                       .name           = "sclk_sata",
> +                       .devname        = "exynos5-sata",
> +                       .enable         = exynos5_clksrc_mask_fsys_ctrl,
> +                       .ctrlbit        = (1 << 24),
> +               },
> +               .sources = &exynos5_clkset_aclk,
> +               .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
> +               .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
> +       }, {
> +               .clk    = {
>                         .name           = "sclk_gscl_wrap",
>                         .devname        = "s5p-mipi-csis.0",
>                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
> --
> 1.7.4.1
>



-- 
Regards,

Vasanth K A

[PATCH v2 2/6] ARM: EXYNOS5: DT Support for SATA and SATA PHY

[Vasanth Ananthan]

Hi,

Missed to include Ben, for I2C patch, including him and copying others.

Thanks,
Vasanth.

On Tue, Oct 30, 2012 at 9:31 PM, Vasanth Ananthan
<vasanthananthan@gmail.com> wrote:
> This patch adds Device Nodes for SATA and SATA PHY device.
>
> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> ---
>  .../devicetree/bindings/ata/exynos-sata-phy.txt    |   14 ++++++++++++++
>  .../devicetree/bindings/ata/exynos-sata.txt        |   17 +++++++++++++++++
>  arch/arm/boot/dts/exynos5250-smdk5250.dts          |   15 +++++++++++++++
>  arch/arm/boot/dts/exynos5250.dtsi                  |   18 ++++++++++++++++++
>  arch/arm/mach-exynos/include/mach/map.h            |    3 +++
>  arch/arm/mach-exynos/mach-exynos5-dt.c             |    6 ++++++
>  6 files changed, 73 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
>  create mode 100644 Documentation/devicetree/bindings/ata/exynos-sata.txt
>
> diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
> new file mode 100644
> index 0000000..37824fa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
> @@ -0,0 +1,14 @@
> +* Samsung SATA PHY Controller
> +
> +SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
> +Each SATA PHY controller should have its own node.
> +
> +Required properties:
> +- compatible        : compatible list, contains "samsung,exynos5-sata-phy"
> +- reg               : <registers mapping>
> +
> +Example:
> +        sata at ffe07000 {
> +                compatible = "samsung,exynos5-sata-phy";
> +                reg = <0xffe07000 0x1000>;
> +        };
> diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
> new file mode 100644
> index 0000000..0849f10
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
> @@ -0,0 +1,17 @@
> +* Samsung AHCI SATA Controller
> +
> +SATA nodes are defined to describe on-chip Serial ATA controllers.
> +Each SATA controller should have its own node.
> +
> +Required properties:
> +- compatible        : compatible list, contains "samsung,exynos5-sata"
> +- interrupts        : <interrupt mapping for SATA IRQ>
> +- reg               : <registers mapping>
> +- samsung,sata-freq : <frequency in MHz>
> +
> +Example:
> +        sata at ffe08000 {
> +                compatible = "samsung,exynos5-sata";
> +                reg = <0xffe08000 0x1000>;
> +                interrupts = <115>;
> +        };
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index a352df4..6910deb 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -55,6 +55,21 @@
>                 };
>         };
>
> +       i2c at 121D0000 {
> +               samsung,i2c-sda-delay = <100>;
> +               samsung,i2c-max-bus-freq = <40000>;
> +               samsung,i2c-slave-addr = <0x38>;
> +
> +               sata-phy {
> +                       compatible = "samsung,sata-phy";
> +                       reg = <0x38>;
> +               };
> +       };
> +
> +       sata at 122F0000 {
> +               samsung,sata-freq = <66>;
> +       };
> +
>         i2c at 12C80000 {
>                 status = "disabled";
>         };
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index dddfd6e..e41520f 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -92,6 +92,17 @@
>                 interrupts = <0 54 0>;
>         };
>
> +       sata at 122F0000 {
> +               compatible = "samsung,exynos5-sata-ahci";
> +               reg = <0x122F0000 0x1ff>;
> +               interrupts = <0 115 0>;
> +       };
> +
> +       sata-phy at 12170000 {
> +               compatible = "samsung,exynos5-sata-phy";
> +               reg = <0x12170000 0x1ff>;
> +       };
> +
>         i2c at 12C60000 {
>                 compatible = "samsung,s3c2440-i2c";
>                 reg = <0x12C60000 0x100>;
> @@ -156,6 +167,13 @@
>                 #size-cells = <0>;
>         };
>
> +       i2c at 121D0000 {
> +                compatible = "samsung,exynos5-sata-phy-i2c";
> +                reg = <0x121D0000 0x100>;
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +       };
> +
>         spi_0: spi at 12d20000 {
>                 compatible = "samsung,exynos4210-spi";
>                 reg = <0x12d20000 0x100>;
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 8480849..ffeb761 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -188,6 +188,9 @@
>  #define EXYNOS4_PA_SATA                        0x12560000
>  #define EXYNOS4_PA_SATAPHY             0x125D0000
>  #define EXYNOS4_PA_SATAPHY_CTRL                0x126B0000
> +#define EXYNOS5_PA_SATA_PHY_CTRL       0x12170000
> +#define EXYNOS5_PA_SATA_PHY_I2C                0x121D0000
> +#define EXYNOS5_PA_SATA_BASE           0x122F0000
>
>  #define EXYNOS4_PA_SROMC               0x12570000
>  #define EXYNOS5_PA_SROMC               0x12250000
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index db1cd8e..7dbd4cc 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -61,6 +61,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
>                                 "exynos4210-spi.1", NULL),
>         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
>                                 "exynos4210-spi.2", NULL),
> +       OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", EXYNOS5_PA_SATA_BASE,
> +                               "exynos5-sata", NULL),
> +       OF_DEV_AUXDATA("samsung,exynos5-sata-phy", EXYNOS5_PA_SATA_PHY_CTRL,
> +                               "exynos5-sata-phy", NULL),
> +       OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", EXYNOS5_PA_SATA_PHY_I2C,
> +                               "exynos5-sata-phy-i2c", NULL),
>         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
>         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
>         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
> --
> 1.7.4.1
>



-- 
Regards,

Vasanth K A

[PATCH v2 3/6] DRIVERS: ATA: SATA PHY utility framework

[Vasanth Ananthan]

Hi,

Missed to include Ben, for I2C patch, including him and copying others.

Thanks,
Vasanth.

On Tue, Oct 30, 2012 at 9:31 PM, Vasanth Ananthan
<vasanthananthan@gmail.com> wrote:
> This patch adds SATA PHY utility framework APIs. The framework acts as an
> interface between the SATA device and the PHY device. The SATA PHY device
> registers itself with the framework through the APIs provided and the SATA
> device finds and requests for an appropriate PHY device.
>
> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> ---
>  drivers/ata/Kconfig    |   10 +++++
>  drivers/ata/Makefile   |    1 +
>  drivers/ata/sata_phy.c |  104 ++++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/ata/sata_phy.h |   44 ++++++++++++++++++++
>  4 files changed, 159 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/ata/sata_phy.c
>  create mode 100644 drivers/ata/sata_phy.h
>
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index e08d322..e3a2972 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -83,6 +83,16 @@ config SATA_AHCI_PLATFORM
>
>           If unsure, say N.
>
> +config SATA_PHY
> +       bool "SATA PHY Framework"
> +       default n
> +       help
> +         This option enables the SATA PHY utility framework APIs.
> +         The framework acts as an interface between the SATA device
> +         and the PHY device. The SATA PHY device registers itself
> +         with the framework through the APIs provided and the SATA
> +         device finds and requests for an appropriate PHY device.
> +
>  config SATA_FSL
>         tristate "Freescale 3.0Gbps SATA support"
>         depends on FSL_SOC
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index 9329daf..3d219a9 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X)   += sata_inic162x.o
>  obj-$(CONFIG_SATA_SIL24)       += sata_sil24.o
>  obj-$(CONFIG_SATA_DWC)         += sata_dwc_460ex.o
>  obj-$(CONFIG_SATA_HIGHBANK)    += sata_highbank.o libahci.o
> +obj-$(CONFIG_SATA_PHY)         += sata_phy.o
>
>  # SFF w/ custom DMA
>  obj-$(CONFIG_PDC_ADMA)         += pdc_adma.o
> diff --git a/drivers/ata/sata_phy.c b/drivers/ata/sata_phy.c
> new file mode 100644
> index 0000000..e5631a9
> --- /dev/null
> +++ b/drivers/ata/sata_phy.c
> @@ -0,0 +1,104 @@
> +/*
> + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
> + *              http://www.samsung.com
> + *
> + * EXYNOS - SATA utility framework.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/export.h>
> +#include <linux/err.h>
> +#include <linux/device.h>
> +#include <linux/slab.h>
> +#include <linux/list.h>
> +#include "sata_phy.h"
> +
> +static LIST_HEAD(phy_list);
> +static DEFINE_SPINLOCK(phy_lock);
> +
> +struct sata_phy *sata_get_phy(enum sata_phy_type type)
> +{
> +       struct sata_phy *x = NULL;
> +       unsigned long flag;
> +
> +       if (list_empty(&phy_list))
> +               return x;
> +
> +       spin_lock_irqsave(&phy_lock, flag);
> +
> +       list_for_each_entry(x, &phy_list, head) {
> +               if (x->type == type) {
> +                       get_device(x->dev);
> +                       break;
> +               }
> +       }
> +
> +       spin_unlock_irqrestore(&phy_lock, flag);
> +       return x;
> +}
> +EXPORT_SYMBOL(sata_get_phy);
> +
> +int sata_add_phy(struct sata_phy *phy, enum sata_phy_type type)
> +{
> +       unsigned long flag;
> +       unsigned int ret = -EINVAL;
> +       struct sata_phy *x;
> +
> +       spin_lock_irqsave(&phy_lock, flag);
> +
> +       if (!phy)
> +               return ret;
> +
> +       list_for_each_entry(x, &phy_list, head) {
> +               if (x->type == type) {
> +                       dev_err(phy->dev, "transceiver type already exists\n");
> +                       goto out;
> +               }
> +       }
> +       phy->type = type;
> +       list_add_tail(&phy->head, &phy_list);
> +       ret = 0;
> +
> + out:
> +       spin_unlock_irqrestore(&phy_lock, flag);
> +       return ret;
> +}
> +EXPORT_SYMBOL(sata_add_phy);
> +
> +void sata_remove_phy(struct sata_phy *phy)
> +{
> +       unsigned long flag;
> +       struct sata_phy *x;
> +
> +       spin_lock_irqsave(&phy_lock, flag);
> +
> +       if (!phy)
> +               return;
> +
> +       list_for_each_entry(x, &phy_list, head) {
> +               if (x->type == phy->type)
> +                       list_del(&phy->head);
> +       }
> +
> +       spin_unlock_irqrestore(&phy_lock, flag);
> +}
> +EXPORT_SYMBOL(sata_remove_phy);
> +
> +void sata_put_phy(struct sata_phy *phy)
> +{
> +       unsigned long flag;
> +
> +       spin_lock_irqsave(&phy_lock, flag);
> +
> +       if (!phy)
> +               return;
> +
> +       put_device(phy->dev);
> +       spin_unlock_irqrestore(&phy_lock, flag);
> +
> +}
> +EXPORT_SYMBOL(sata_put_phy);
> diff --git a/drivers/ata/sata_phy.h b/drivers/ata/sata_phy.h
> new file mode 100644
> index 0000000..dc38683
> --- /dev/null
> +++ b/drivers/ata/sata_phy.h
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
> + *              http://www.samsung.com
> + *
> + * EXYNOS - SATA utility framework definitions.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +enum sata_phy_type {
> +       SATA_PHY_GENERATION1,
> +       SATA_PHY_GENERATION2,
> +       SATA_PHY_GENERATION3,
> +};
> +
> +struct sata_phy {
> +       int (*init) (struct sata_phy *);
> +       int (*shutdown) (struct sata_phy *);
> +       struct device *dev;
> +       void *priv_data;
> +       enum sata_phy_type type;
> +       struct list_head head;
> +};
> +
> +static inline int sata_init_phy(struct sata_phy *x)
> +{
> +       if (x && x->init)
> +               return x->init(x);
> +
> +       return -EINVAL;
> +}
> +
> +static inline void sata_shutdown_phy(struct sata_phy *x)
> +{
> +       if (x && x->shutdown)
> +               x->shutdown(x);
> +}
> +
> +struct sata_phy *sata_get_phy(enum sata_phy_type);
> +int sata_add_phy(struct sata_phy *, enum sata_phy_type);
> +void sata_remove_phy(struct sata_phy *);
> +void sata_put_phy(struct sata_phy *);
> --
> 1.7.4.1
>



-- 
Regards,

Vasanth K A

[PATCH v2 4/6] DRIVERS:I2C: I2C driver polling mode support

[Vasanth Ananthan]

Hi,

Missed to include Ben, for I2C patch, including him and copying others.

Thanks,
Vasanth.

On Tue, Oct 30, 2012 at 9:31 PM, Vasanth Ananthan
<vasanthananthan@gmail.com> wrote:
> This patch adds polling mode support for i2c s3c-2410 driver.
> The I2C_SATAPHY controller lacks an interrupt line but the s3c-2410 driver
> is interrupt driven. Hence this support is required for functioning
> of the I2C_SATAPHY controller.
>
> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> ---
>  drivers/i2c/busses/i2c-s3c2410.c |   79 ++++++++++++++++++++++++++++---------
>  1 files changed, 60 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
> index 3e0335f..5712e40 100644
> --- a/drivers/i2c/busses/i2c-s3c2410.c
> +++ b/drivers/i2c/busses/i2c-s3c2410.c
> @@ -48,6 +48,7 @@
>  #define QUIRK_S3C2440          (1 << 0)
>  #define QUIRK_HDMIPHY          (1 << 1)
>  #define QUIRK_NO_GPIO          (1 << 2)
> +#define QUIRK_SATAPHY          (1 << 3)
>
>  /* i2c controller state */
>  enum s3c24xx_i2c_state {
> @@ -102,10 +103,14 @@ static struct platform_device_id s3c24xx_driver_ids[] = {
>  };
>  MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
>
> +static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
> +
>  #ifdef CONFIG_OF
>  static const struct of_device_id s3c24xx_i2c_match[] = {
>         { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
>         { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
> +       { .compatible = "samsung,exynos5-sata-phy-i2c",
> +         .data = (void *)(QUIRK_S3C2440 | QUIRK_SATAPHY | QUIRK_NO_GPIO) },
>         { .compatible = "samsung,s3c2440-hdmiphy-i2c",
>           .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
>         {},
> @@ -146,7 +151,8 @@ static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
>         if (ret)
>                 i2c->msg_idx = ret;
>
> -       wake_up(&i2c->wait);
> +       if (!(i2c->quirks & QUIRK_SATAPHY))
> +               wake_up(&i2c->wait);
>  }
>
>  static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
> @@ -184,6 +190,23 @@ static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
>  }
>
>
> +static bool is_ack(struct s3c24xx_i2c *i2c)
> +{
> +       u32 time_out = i2c->tx_setup;
> +
> +       while (--time_out) {
> +               if (readl(i2c->regs + S3C2410_IICCON)
> +                       & S3C2410_IICCON_IRQPEND) {
> +                       if (!(readl(i2c->regs + S3C2410_IICSTAT)
> +                               & S3C2410_IICSTAT_LASTBIT))
> +                               return true;
> +               }
> +               udelay(time_out);
> +       }
> +
> +       return false;
> +}
> +
>  /* s3c24xx_i2c_message_start
>   *
>   * put the start of a message onto the bus
> @@ -227,6 +250,15 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
>
>         stat |= S3C2410_IICSTAT_START;
>         writel(stat, i2c->regs + S3C2410_IICSTAT);
> +
> +       if (i2c->quirks & QUIRK_SATAPHY) {
> +               while ((i2c->msg_num != 0) && is_ack(i2c)) {
> +                       i2c_s3c_irq_nextbyte(i2c, stat);
> +                       stat = readl(i2c->regs + S3C2410_IICSTAT);
> +                       if (stat & S3C2410_IICSTAT_ARBITR)
> +                               dev_err(i2c->dev, "deal with arbitration loss\n");
> +               }
> +       }
>  }
>
>  static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
> @@ -552,19 +584,23 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
>         s3c24xx_i2c_message_start(i2c, msgs);
>         spin_unlock_irq(&i2c->lock);
>
> -       timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
> -
>         ret = i2c->msg_idx;
>
> -       /* having these next two as dev_err() makes life very
> -        * noisy when doing an i2cdetect */
> +       if (!(i2c->quirks & QUIRK_SATAPHY)) {
>
> -       if (timeout == 0)
> -               dev_dbg(i2c->dev, "timeout\n");
> -       else if (ret != num)
> -               dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
> +               timeout = wait_event_timeout(i2c->wait,
> +                               i2c->msg_num == 0, HZ * 5);
>
> -       /* ensure the stop has been through the bus */
> +               /* having these next two as dev_err() makes life very
> +               * noisy when doing an i2cdetect */
> +
> +               if (timeout == 0)
> +                       dev_dbg(i2c->dev, "timeout\n");
> +               else if (ret != num)
> +                       dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
> +
> +               /* ensure the stop has been through the bus */
> +       }
>
>         dev_dbg(i2c->dev, "waiting for bus idle\n");
>
> @@ -710,6 +746,9 @@ static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
>         if (div1 == 512)
>                 iiccon |= S3C2410_IICCON_TXDIV_512;
>
> +       if (i2c->quirks & QUIRK_SATAPHY)
> +               iiccon |= S3C2410_IICCON_SCALE(2);
> +
>         writel(iiccon, i2c->regs + S3C2410_IICCON);
>
>         if (i2c->quirks & QUIRK_S3C2440) {
> @@ -1023,18 +1062,20 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
>          * ensure no current IRQs pending
>          */
>
> -       i2c->irq = ret = platform_get_irq(pdev, 0);
> -       if (ret <= 0) {
> -               dev_err(&pdev->dev, "cannot find IRQ\n");
> -               goto err_iomap;
> -       }
> +       if (!(i2c->quirks & QUIRK_SATAPHY)) {
> +               i2c->irq = ret = platform_get_irq(pdev, 0);
> +               if (ret <= 0) {
> +                       dev_err(&pdev->dev, "cannot find IRQ\n");
> +                       goto err_iomap;
> +               }
>
> -       ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0,
> +               ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0,
>                           dev_name(&pdev->dev), i2c);
>
> -       if (ret != 0) {
> -               dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
> -               goto err_iomap;
> +               if (ret != 0) {
> +                       dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
> +                       goto err_iomap;
> +               }
>         }
>
>         ret = s3c24xx_i2c_register_cpufreq(i2c);
> --
> 1.7.4.1
>



-- 
Regards,

Vasanth K A

[PATCH v2 5/6] DRIVERS: ATA: SATA controller driver

[Vasanth Ananthan]

Hi,

Missed to include Ben, for I2C patch, including him and copying others.

Thanks,
Vasanth.

On Tue, Oct 30, 2012 at 9:31 PM, Vasanth Ananthan
<vasanthananthan@gmail.com> wrote:
> This patch adds a platform driver for SATA controller.
>
> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> ---
>  arch/arm/mach-exynos/include/mach/regs-pmu.h |    3 +
>  drivers/ata/Kconfig                          |   12 ++
>  drivers/ata/Makefile                         |    1 +
>  drivers/ata/sata_exynos.c                    |  268 ++++++++++++++++++++++++++
>  4 files changed, 284 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/ata/sata_exynos.c
>
> diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
> index d4e392b..3716ce8 100644
> --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
> +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
> @@ -367,4 +367,7 @@
>
>  #define EXYNOS5_OPTION_USE_RETENTION                           (1 << 4)
>
> +/* Only for EXYNOS5250 */
> +#define EXYNOS5_SATA_PHY_CONTROL               S5P_PMUREG(0x0724)
> +
>  #endif /* __ASM_ARCH_REGS_PMU_H */
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index e3a2972..f3384ed 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -93,6 +93,18 @@ config SATA_PHY
>           with the framework through the APIs provided and the SATA
>           device finds and requests for an appropriate PHY device.
>
> +config SATA_EXYNOS
> +        bool "Exynos SATA AHCI support"
> +        select I2C
> +        select HAVE_S3C2410_I2C
> +        select I2C_S3C2410
> +        select SATA_PHY
> +        help
> +          This option enables support for Exynos AHCI Serial ATA
> +          controllers.
> +
> +          If unsure, say N.
> +
>  config SATA_FSL
>         tristate "Freescale 3.0Gbps SATA support"
>         depends on FSL_SOC
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index 3d219a9..43bb38e 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24)      += sata_sil24.o
>  obj-$(CONFIG_SATA_DWC)         += sata_dwc_460ex.o
>  obj-$(CONFIG_SATA_HIGHBANK)    += sata_highbank.o libahci.o
>  obj-$(CONFIG_SATA_PHY)         += sata_phy.o
> +obj-$(CONFIG_SATA_EXYNOS)      += sata_exynos.o libahci.o
>
>  # SFF w/ custom DMA
>  obj-$(CONFIG_PDC_ADMA)         += pdc_adma.o
> diff --git a/drivers/ata/sata_exynos.c b/drivers/ata/sata_exynos.c
> new file mode 100644
> index 0000000..41dc17d
> --- /dev/null
> +++ b/drivers/ata/sata_exynos.c
> @@ -0,0 +1,268 @@
> +/*
> + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
> + *              http://www.samsung.com
> + *
> + * EXYNOS - SATA controller driver
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/gfp.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/device.h>
> +#include <linux/platform_device.h>
> +#include <linux/libata.h>
> +#include <linux/ahci_platform.h>
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/of.h>
> +
> +#include "ahci.h"
> +#include "sata_phy.h"
> +
> +#define MHZ            (1000 * 1000)
> +
> +static const struct ata_port_info ahci_port_info = {
> +       .flags = AHCI_FLAG_COMMON,
> +       .pio_mask = ATA_PIO4,
> +       .udma_mask = ATA_UDMA6,
> +       .port_ops = &ahci_ops,
> +};
> +
> +static struct scsi_host_template ahci_platform_sht = {
> +       AHCI_SHT("ahci_platform"),
> +};
> +
> +struct exynos_sata {
> +       struct clk *sclk;
> +       struct clk *clk;
> +       struct sata_phy *phy;
> +       int irq;
> +       unsigned int freq;
> +};
> +
> +static void exynos_sata_parse_dt(struct device_node *np,
> +                                       struct exynos_sata *sata)
> +{
> +       if (!np)
> +               return;
> +
> +       of_property_read_u32(np, "samsung,sata-freq", &sata->freq);
> +}
> +
> +static int __init exynos_sata_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct ata_port_info pi = ahci_port_info;
> +       const struct ata_port_info *ppi[] = { &pi, NULL };
> +       struct ahci_host_priv *hpriv;
> +       struct exynos_sata *sata;
> +       struct ata_host *host;
> +       struct resource *mem;
> +       int n_ports, i, ret;
> +
> +       sata = devm_kzalloc(dev, sizeof(*sata), GFP_KERNEL);
> +       if (!sata) {
> +               dev_err(dev, "can't alloc sata\n");
> +               return -EINVAL;
> +       }
> +
> +       hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
> +       if (!hpriv) {
> +               dev_err(dev, "can't alloc ahci_host_priv\n");
> +               ret = -ENOMEM;
> +               goto err1;
> +       }
> +
> +       hpriv->flags |= (unsigned long)pi.private_data;
> +
> +       mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       if (!mem) {
> +               dev_err(dev, "no mmio space\n");
> +               ret = -EINVAL;
> +               goto err2;
> +       }
> +
> +       sata->irq = platform_get_irq(pdev, 0);
> +       if (sata->irq <= 0) {
> +               dev_err(dev, "no irq\n");
> +               ret = -EINVAL;
> +               goto err2;
> +       }
> +
> +       hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
> +       if (!hpriv->mmio) {
> +               dev_err(dev, "can't map %pR\n", mem);
> +               ret = -ENOMEM;
> +               goto err2;
> +       }
> +
> +       exynos_sata_parse_dt(dev->of_node, sata);
> +
> +       sata->sclk = devm_clk_get(dev, "sclk_sata");
> +       if (IS_ERR(sata->sclk)) {
> +               dev_err(dev, "failed to get sclk_sata\n");
> +               ret = PTR_ERR(sata->sclk);
> +               goto err3;
> +       }
> +       clk_enable(sata->sclk);
> +
> +       clk_set_rate(sata->sclk, sata->freq * MHZ);
> +
> +       sata->clk = devm_clk_get(dev, "sata");
> +       if (IS_ERR(sata->clk)) {
> +               dev_err(dev, "failed to get sata clock\n");
> +               ret = PTR_ERR(sata->clk);
> +               goto err4;
> +       }
> +       clk_enable(sata->clk);
> +
> +       /*  Get a gen 3 PHY controller */
> +
> +       sata->phy = sata_get_phy(SATA_PHY_GENERATION3);
> +       if (!sata->phy) {
> +               dev_err(dev, "failed to get sata phy\n");
> +               ret = -EPROBE_DEFER;
> +               goto err5;
> +       }
> +
> +       /* Initialize the controller */
> +
> +       ret = sata_init_phy(sata->phy);
> +       if (ret < 0) {
> +               dev_err(dev, "failed to initialize sata phy\n");
> +               goto err6;
> +       }
> +
> +       ahci_save_initial_config(dev, hpriv, 0, 0);
> +
> +       /* prepare host */
> +       if (hpriv->cap & HOST_CAP_NCQ)
> +               pi.flags |= ATA_FLAG_NCQ;
> +
> +       if (hpriv->cap & HOST_CAP_PMP)
> +               pi.flags |= ATA_FLAG_PMP;
> +
> +       ahci_set_em_messages(hpriv, &pi);
> +
> +       /* CAP.NP sometimes indicate the index of the last enabled
> +        * port, at other times, that of the last possible port, so
> +        * determining the maximum port number requires looking at
> +        * both CAP.NP and port_map.
> +        */
> +       n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
> +
> +       host = ata_host_alloc_pinfo(dev, ppi, n_ports);
> +       if (!host) {
> +               ret = -ENOMEM;
> +               goto err7;
> +       }
> +
> +       host->private_data = hpriv;
> +
> +       if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
> +               host->flags |= ATA_HOST_PARALLEL_SCAN;
> +       else
> +               pr_info(KERN_INFO
> +                      "ahci: SSS flag set, parallel bus scan disabled\n");
> +
> +       if (pi.flags & ATA_FLAG_EM)
> +               ahci_reset_em(host);
> +
> +       for (i = 0; i < host->n_ports; i++) {
> +               struct ata_port *ap = host->ports[i];
> +
> +               ata_port_desc(ap, "mmio %pR", mem);
> +               ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
> +
> +               /* set enclosure management message type */
> +               if (ap->flags & ATA_FLAG_EM)
> +                       ap->em_message_type = hpriv->em_msg_type;
> +
> +               /* disabled/not-implemented port */
> +               if (!(hpriv->port_map & (1 << i)))
> +                       ap->ops = &ata_dummy_port_ops;
> +       }
> +
> +       ret = ahci_reset_controller(host);
> +       if (ret)
> +               goto err7;
> +
> +       ahci_init_controller(host);
> +       ahci_print_info(host, "platform");
> +
> +       ret = ata_host_activate(host, sata->irq, ahci_interrupt, IRQF_SHARED,
> +                               &ahci_platform_sht);
> +       if (ret)
> +               goto err7;
> +
> +       platform_set_drvdata(pdev, sata);
> +
> +       return 0;
> +
> + err7:
> +       sata_shutdown_phy(sata->phy);
> +
> + err6:
> +       sata_put_phy(sata->phy);
> +
> + err5:
> +       clk_disable(sata->clk);
> +       devm_clk_put(dev, sata->clk);
> +
> + err4:
> +       clk_disable(sata->sclk);
> +       devm_clk_put(dev, sata->sclk);
> +
> + err3:
> +       devm_iounmap(dev, hpriv->mmio);
> +
> + err2:
> +       devm_kfree(dev, hpriv);
> +
> + err1:
> +       devm_kfree(dev, sata);
> +
> +       return ret;
> +}
> +
> +static int __devexit exynos_sata_remove(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct ata_host *host = dev_get_drvdata(dev);
> +       struct exynos_sata *sata = platform_get_drvdata(pdev);
> +
> +       ata_host_detach(host);
> +
> +       sata_shutdown_phy(sata->phy);
> +       sata_put_phy(sata->phy);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id ahci_of_match[] = {
> +       { .compatible = "samsung,exynos5-sata-ahci", },
> +};
> +
> +MODULE_DEVICE_TABLE(of, ahci_of_match);
> +
> +static struct platform_driver exynos_sata_driver = {
> +       .probe  = exynos_sata_probe,
> +       .remove = exynos_sata_remove,
> +       .driver = {
> +               .name = "ahci-sata",
> +               .owner = THIS_MODULE,
> +               .of_match_table = ahci_of_match,
> +       },
> +};
> +
> +module_platform_driver(exynos_sata_driver);
> +
> +MODULE_DESCRIPTION("EXYNOS SATA DRIVER");
> +MODULE_AUTHOR("Vasanth Ananthan, <vasanth.a@samsung.com>");
> +MODULE_LICENSE("GPL");
> --
> 1.7.4.1
>



-- 
Regards,

Vasanth K A

[PATCH v2 6/6] DRIVERS: ATA: SATA PHY controller driver

[Vasanth Ananthan]

Hi,

Missed to include Ben, for I2C patch, including him and copying others.

Thanks,
Vasanth.

On Tue, Oct 30, 2012 at 9:31 PM, Vasanth Ananthan
<vasanthananthan@gmail.com> wrote:
> This patch adds a platform driver and I2C client driver for SATA PHY controller
>
> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> ---
>  arch/arm/mach-exynos/include/mach/regs-sata.h |   29 +++
>  drivers/ata/Makefile                          |    2 +-
>  drivers/ata/sata_exynos_phy.c                 |  300 +++++++++++++++++++++++++
>  3 files changed, 330 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-exynos/include/mach/regs-sata.h
>  create mode 100644 drivers/ata/sata_exynos_phy.c
>
> diff --git a/arch/arm/mach-exynos/include/mach/regs-sata.h b/arch/arm/mach-exynos/include/mach/regs-sata.h
> new file mode 100644
> index 0000000..80dd564
> --- /dev/null
> +++ b/arch/arm/mach-exynos/include/mach/regs-sata.h
> @@ -0,0 +1,29 @@
> +/*
> + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
> + *              http://www.samsung.com
> + *
> + * EXYNOS - SATA PHY controller definition
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#define EXYNOS5_SATA_RESET             0x4
> +#define RESET_CMN_RST_N                        (1 << 1)
> +#define LINK_RESET                     0xF0000
> +
> +#define EXYNOS5_SATA_MODE0             0x10
> +
> +#define EXYNOS5_SATA_CTRL0             0x14
> +#define CTRL0_P0_PHY_CALIBRATED_SEL    (1 << 9)
> +#define CTRL0_P0_PHY_CALIBRATED                (1 << 8)
> +
> +#define EXYNOS5_SATA_PHSATA_CTRLM      0xE0
> +#define PHCTRLM_REF_RATE               (1 << 1)
> +#define PHCTRLM_HIGH_SPEED             (1 << 0)
> +
> +#define EXYNOS5_SATA_PHSATA_STATM      0xF0
> +#define PHSTATM_PLL_LOCKED             (1 << 0)
> +
> +#define SATA_PHY_CON_RESET              0xF003F
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index 43bb38e..6a3a8ee 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -11,7 +11,7 @@ obj-$(CONFIG_SATA_SIL24)      += sata_sil24.o
>  obj-$(CONFIG_SATA_DWC)         += sata_dwc_460ex.o
>  obj-$(CONFIG_SATA_HIGHBANK)    += sata_highbank.o libahci.o
>  obj-$(CONFIG_SATA_PHY)         += sata_phy.o
> -obj-$(CONFIG_SATA_EXYNOS)      += sata_exynos.o libahci.o
> +obj-$(CONFIG_SATA_EXYNOS)      += sata_exynos.o sata_exynos_phy.o libahci.o
>
>  # SFF w/ custom DMA
>  obj-$(CONFIG_PDC_ADMA)         += pdc_adma.o
> diff --git a/drivers/ata/sata_exynos_phy.c b/drivers/ata/sata_exynos_phy.c
> new file mode 100644
> index 0000000..ec61db5
> --- /dev/null
> +++ b/drivers/ata/sata_exynos_phy.c
> @@ -0,0 +1,300 @@
> +/*
> + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
> + *              http://www.samsung.com
> + *
> + * EXYNOS - SATA PHY controller driver
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/module.h>
> +#include <linux/device.h>
> +#include <linux/platform_device.h>
> +#include <linux/i2c.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/ahci_platform.h>
> +#include <linux/kernel.h>
> +#include <linux/slab.h>
> +#include <linux/list.h>
> +#include <linux/io.h>
> +
> +#include <plat/cpu.h>
> +
> +#include <mach/irqs.h>
> +#include <mach/map.h>
> +#include <mach/regs-pmu.h>
> +#include <mach/regs-sata.h>
> +
> +#include "sata_phy.h"
> +
> +#define        SATA_TIME_LIMIT         1000
> +
> +static struct i2c_client *i2c_client;
> +
> +static struct i2c_driver sataphy_i2c_driver;
> +
> +struct exynos_sata_phy {
> +       void __iomem *mmio;
> +       struct resource *mem;
> +       struct clk *clk;
> +};
> +
> +static bool sata_is_reg(void __iomem *base, u32 reg, u32 checkbit, u32 status)
> +{
> +       if ((readl(base + reg) & checkbit) == status)
> +               return true;
> +       else
> +               return false;
> +}
> +
> +static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
> +                               u32 status)
> +{
> +       u16 time_limit_cnt = 0;
> +       while (!sata_is_reg(base, reg, checkbit, status)) {
> +               if (time_limit_cnt == SATA_TIME_LIMIT)
> +                       return false;
> +               udelay(1000);
> +               time_limit_cnt++;
> +       }
> +       return true;
> +}
> +
> +static int sataphy_init(struct sata_phy *phy)
> +{
> +       int ret;
> +       u32 val;
> +
> +       /* Values to be written to enable 40 bits interface */
> +       u8 buf[] = { 0x3A, 0x0B };
> +
> +       struct exynos_sata_phy *sata_phy;
> +
> +       if (!i2c_client)
> +               return -EPROBE_DEFER;
> +
> +       sata_phy = (struct exynos_sata_phy *)phy->priv_data;
> +
> +       clk_enable(sata_phy->clk);
> +
> +       writel(S5P_PMU_SATA_PHY_CONTROL_EN, EXYNOS5_SATA_PHY_CONTROL);
> +
> +       val = 0;
> +       writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
> +
> +       val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
> +       val |= 0xFF;
> +       writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
> +
> +       val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
> +       val |= LINK_RESET;
> +       writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
> +
> +       val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
> +       val |= RESET_CMN_RST_N;
> +       writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
> +
> +       val = readl(sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
> +       val &= ~PHCTRLM_REF_RATE;
> +       writel(val, sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
> +
> +       /* High speed enable for Gen3 */
> +       val = readl(sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
> +       val |= PHCTRLM_HIGH_SPEED;
> +       writel(val, sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
> +
> +       val = readl(sata_phy->mmio + EXYNOS5_SATA_CTRL0);
> +       val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
> +       writel(val, sata_phy->mmio + EXYNOS5_SATA_CTRL0);
> +
> +       writel(SATA_PHY_GENERATION3, sata_phy->mmio + EXYNOS5_SATA_MODE0);
> +
> +       ret = i2c_master_send(i2c_client, buf, sizeof(buf));
> +       if (ret < 0)
> +               return -EINVAL;
> +
> +       /* release cmu reset */
> +       val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
> +       val &= ~RESET_CMN_RST_N;
> +       writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
> +
> +       val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
> +       val |= RESET_CMN_RST_N;
> +       writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
> +
> +       if (wait_for_reg_status(sata_phy->mmio, EXYNOS5_SATA_PHSATA_STATM,
> +                               PHSTATM_PLL_LOCKED, 1)) {
> +               return 0;
> +       }
> +       return -EINVAL;
> +}
> +
> +static int sataphy_shutdown(struct sata_phy *phy)
> +{
> +
> +       struct exynos_sata_phy *sata_phy;
> +
> +       sata_phy = (struct exynos_sata_phy *)phy->priv_data;
> +
> +       clk_disable(sata_phy->clk);
> +
> +       return 0;
> +}
> +
> +static int __init sata_i2c_probe(struct i2c_client *client,
> +                         const struct i2c_device_id *i2c_id)
> +{
> +       i2c_client = client;
> +       return 0;
> +}
> +
> +static int __init sata_phy_probe(struct platform_device *pdev)
> +{
> +       struct exynos_sata_phy *sataphy;
> +       struct sata_phy *phy;
> +       struct resource *res;
> +       struct device *dev = &pdev->dev;
> +       int ret = 0;
> +
> +       phy = kzalloc(sizeof(struct sata_phy), GFP_KERNEL);
> +       if (!phy) {
> +               dev_err(&pdev->dev, "failed to allocate memory\n");
> +               ret = -ENOMEM;
> +               goto out;
> +       }
> +
> +       sataphy = kzalloc(sizeof(struct exynos_sata_phy), GFP_KERNEL);
> +       if (!sataphy) {
> +               dev_err(dev, "failed to allocate memory\n");
> +               ret = -ENOMEM;
> +               goto err0;
> +       }
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       if (!res) {
> +               dev_err(dev, "Could not find IO resource\n");
> +               ret = -EINVAL;
> +               goto err1;
> +       }
> +
> +       sataphy->mem = devm_request_mem_region(dev, res->start,
> +                                       resource_size(res), pdev->name);
> +       if (!sataphy->mem) {
> +               dev_err(dev, "Could not request IO resource\n");
> +               ret = -EINVAL;
> +               goto err1;
> +       }
> +
> +       sataphy->mmio =
> +           devm_ioremap(dev, res->start, resource_size(res));
> +       if (!sataphy->mmio) {
> +               dev_err(dev, "failed to remap IO\n");
> +               ret = -ENOMEM;
> +               goto err2;
> +       }
> +
> +       sataphy->clk = devm_clk_get(dev, "sata-phy");
> +       if (IS_ERR(sataphy->clk)) {
> +               dev_err(dev, "failed to get clk for PHY\n");
> +               ret = PTR_ERR(sataphy->clk);
> +               goto err3;
> +       }
> +
> +       phy->init = sataphy_init;
> +       phy->shutdown = sataphy_shutdown;
> +       phy->priv_data = (void *)sataphy;
> +       phy->dev = dev;
> +
> +       ret = sata_add_phy(phy, SATA_PHY_GENERATION3);
> +       if (ret < 0)
> +               goto err4;
> +
> +       ret = i2c_add_driver(&sataphy_i2c_driver);
> +       if (ret < 0)
> +               goto err5;
> +
> +       platform_set_drvdata(pdev, phy);
> +
> +       return ret;
> +
> + err5:
> +       sata_remove_phy(phy);
> +
> + err4:
> +       clk_disable(sataphy->clk);
> +       devm_clk_put(dev, sataphy->clk);
> +
> + err3:
> +       devm_iounmap(dev, sataphy->mmio);
> +
> + err2:
> +       devm_release_mem_region(dev, res->start, resource_size(res));
> +
> + err1:
> +       kfree(sataphy);
> +
> + err0:
> +       kfree(phy);
> +
> + out:
> +       return ret;
> +}
> +
> +static int sata_phy_remove(struct platform_device *pdev)
> +{
> +       struct sata_phy *phy;
> +       struct exynos_sata_phy *sataphy;
> +
> +       phy = platform_get_drvdata(pdev);
> +
> +       sataphy = (struct exynos_sata_phy *)phy->priv_data;
> +       sata_remove_phy(phy);
> +
> +       kfree(sataphy);
> +       kfree(phy);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id sata_phy_of_match[] = {
> +       { .compatible = "samsung,exynos5-sata-phy", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, sata_phy_of_match);
> +
> +static const struct i2c_device_id phy_i2c_device_match[] = {
> +       { "sata-phy", 0 },
> +};
> +
> +MODULE_DEVICE_TABLE(of, phy_i2c_device_match);
> +
> +static struct platform_driver sata_phy_driver = {
> +       .probe = sata_phy_probe,
> +       .remove = sata_phy_remove,
> +       .driver = {
> +                  .name = "sata-phy",
> +                  .owner = THIS_MODULE,
> +                  .of_match_table = sata_phy_of_match,
> +       },
> +};
> +
> +static struct i2c_driver sataphy_i2c_driver = {
> +       .driver = {
> +                  .name = "sata-phy-i2c",
> +                  .owner = THIS_MODULE,
> +                  .of_match_table = phy_i2c_device_match,
> +       },
> +       .probe = sata_i2c_probe,
> +       .id_table = phy_i2c_device_match,
> +};
> +
> +module_platform_driver(sata_phy_driver);
> +
> +MODULE_DESCRIPTION("EXYNOS SATA PHY DRIVER");
> +MODULE_AUTHOR("Vasanth Ananthan, <vasanth.a@samsung.com>");
> +MODULE_LICENSE("GPL");
> --
> 1.7.4.1
>



-- 
Regards,

Vasanth K A

[PATCH v2 1/6] ARM: EXYNOS5: Clock settings for SATA and SATA PHY

[Kukjin Kim]

Vasanth Ananthan wrote:
> 
> Hi,
> 
> Missed to include Ben, for I2C patch, including him and copying others.
> 
Vasanth, you didn't my reply? I already applied this 1st and 2nd patches.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> 
> On Tue, Oct 30, 2012 at 9:31 PM, Vasanth Ananthan
> <vasanthananthan@gmail.com> wrote:
> > This patch adds neccessary clock entries for SATA, SATA PHY and
> > I2C_SATAPHY
> >
> > Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
> > ---
> >  arch/arm/mach-exynos/clock-exynos5.c |   21 ++++++++++++++++++---
> >  1 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-
> exynos/clock-exynos5.c
> > index c44ca1e..124c54f 100644
> > --- a/arch/arm/mach-exynos/clock-exynos5.c
> > +++ b/arch/arm/mach-exynos/clock-exynos5.c
> > @@ -651,15 +651,20 @@ static struct clk exynos5_init_clocks_off[] = {
> >                 .ctrlbit        = (1 << 15),
> >         }, {
> >                 .name           = "sata",
> > -               .devname        = "ahci",
> > +               .devname        = "exynos5-sata",
> > +               .parent         = &exynos5_clk_aclk_200.clk,
> >                 .enable         = exynos5_clk_ip_fsys_ctrl,
> >                 .ctrlbit        = (1 << 6),
> >         }, {
> > -               .name           = "sata_phy",
> > +               .name           = "sata-phy",
> > +               .devname        = "exynos5-sata-phy",
> > +               .parent         = &exynos5_clk_aclk_200.clk,
> >                 .enable         = exynos5_clk_ip_fsys_ctrl,
> >                 .ctrlbit        = (1 << 24),
> >         }, {
> > -               .name           = "sata_phy_i2c",
> > +               .name           = "i2c",
> > +               .devname        = "exynos5-sata-phy-i2c",
> > +               .parent         = &exynos5_clk_aclk_200.clk,
> >                 .enable         = exynos5_clk_ip_fsys_ctrl,
> >                 .ctrlbit        = (1 << 25),
> >         }, {
> > @@ -1226,6 +1231,16 @@ static struct clksrc_clk exynos5_clksrcs[] = {
> >                 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24,
.size
> = 3 },
> >         }, {
> >                 .clk    = {
> > +                       .name           = "sclk_sata",
> > +                       .devname        = "exynos5-sata",
> > +                       .enable         = exynos5_clksrc_mask_fsys_ctrl,
> > +                       .ctrlbit        = (1 << 24),
> > +               },
> > +               .sources = &exynos5_clkset_aclk,
> > +               .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24,
.size
> = 1 },
> > +               .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift =
> 20, .size = 4 },
> > +       }, {
> > +               .clk    = {
> >                         .name           = "sclk_gscl_wrap",
> >                         .devname        = "s5p-mipi-csis.0",
> >                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
> > --
> > 1.7.4.1
> >
> 
> 
> 
> --