From: josephl@nvidia.com (Joseph Lo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: tegra: retain L2 content over CPU suspend/resume
Date: Mon, 12 Nov 2012 12:10:37 +0800 [thread overview]
Message-ID: <1352693437.19251.9.camel@jlo-ubuntu-64.nvidia.com> (raw)
In-Reply-To: <509D7BA1.506@wwwdotorg.org>
On Sat, 2012-11-10 at 05:54 +0800, Stephen Warren wrote:
> On 11/06/2012 02:32 AM, Joseph Lo wrote:
> > The L2 RAM is in different power domain from the CPU cluster. So the
> > L2 content can be retained over CPU suspend/resume. To do that, we
> > need to disable L2 after the MMU is disabled, and enable L2 before
> > the MMU is enabled. But the L2 controller is in the same power domain
> > with the CPU cluster. We need to restore it's settings and re-enable
> > it after the power be resumed.
>
> This doesn't compile:
>
> arch/arm/mach-tegra/headsmp.S: Assembler messages:
> arch/arm/mach-tegra/headsmp.S:119: Error: undefined symbol L2X0_CTRL_EN
> used as an immediate value
> arch/arm/mach-tegra/headsmp.S:119: Error: undefined symbol L2X0_CTRL_EN
> used as an immediate value
Ah, sorry for mention that.
This patch was depended on "07bd005 ARM: 7547/1: cache-l2x0: add support
for Aurora L2 cache ctrl" and only showed up after "next-20121024". The
definition of "L2X0_CTRL_EN" was been introduced in that patch.
Should I re-send a patch that based on tegra "for-next" branch that will
change L2X0_CTRL_EN to 0x1? Sorry for inconvenience.
Thanks,
Joseph
next prev parent reply other threads:[~2012-11-12 4:10 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-06 9:32 [PATCH] ARM: tegra: retain L2 content over CPU suspend/resume Joseph Lo
2012-11-09 21:54 ` Stephen Warren
2012-11-12 4:10 ` Joseph Lo [this message]
2012-11-12 16:36 ` Stephen Warren
2012-11-12 12:39 ` Peter De Schrijver
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