* [PATCH V2 1/6] ARM: tegra: add pending SGI checking API
2012-12-05 10:01 [PATCH V2 0/6] ARM: tegra20: cpuidle: add power-down state Joseph Lo
@ 2012-12-05 10:01 ` Joseph Lo
2012-12-05 22:09 ` Stephen Warren
2012-12-05 10:01 ` [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU Joseph Lo
` (6 subsequent siblings)
7 siblings, 1 reply; 27+ messages in thread
From: Joseph Lo @ 2012-12-05 10:01 UTC (permalink / raw)
To: linux-arm-kernel
The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it
include the power of GIC. That caused the SGI (Software Generated
Interrupt) been lost. Because the SGI can't wake up the CPU that in
the "powered-down" CPU idle mode. We need to check if there is any
pending SGI when go into "powered-down" CPU idle mode. This is important
especially when applying the coupled cpuidle framework into "power-down"
cpuidle dirver. Because the coupled cpuidle framework may have the
chance that misses IPI_SINGLE_FUNC handling sometimes.
For the PPI or SPI, something like the legacy peripheral interrupt. It
still can be maintained by Tegra legacy interrupt controller. If there
is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The
CPU can be woken up immediately. So we don't need to take care the same
situation for PPI or SPI.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* new in V2
---
arch/arm/mach-tegra/irq.c | 17 +++++++++++++++--
arch/arm/mach-tegra/irq.h | 22 ++++++++++++++++++++++
2 files changed, 37 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-tegra/irq.h
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index b7886f1..3d2483a 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -45,7 +45,10 @@
#define FIRST_LEGACY_IRQ 32
+#define SGI_MASK 0xFFFF
+
static int num_ictlrs;
+static void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
static void __iomem *ictlr_reg_base[] = {
IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
@@ -55,6 +58,18 @@ static void __iomem *ictlr_reg_base[] = {
IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
};
+bool tegra_pending_sgi(void)
+{
+ u32 pending_set;
+
+ pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET);
+
+ if (pending_set & SGI_MASK)
+ return true;
+
+ return false;
+}
+
static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
{
void __iomem *base;
@@ -114,9 +129,7 @@ static int tegra_retrigger(struct irq_data *d)
void __init tegra_init_irq(void)
{
int i;
- void __iomem *distbase;
- distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f;
if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) {
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h
new file mode 100644
index 0000000..5142649
--- /dev/null
+++ b/arch/arm/mach-tegra/irq.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TEGRA_IRQ_H
+#define __TEGRA_IRQ_H
+
+bool tegra_pending_sgi(void);
+
+#endif
--
1.7.0.4
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V2 1/6] ARM: tegra: add pending SGI checking API
2012-12-05 10:01 ` [PATCH V2 1/6] ARM: tegra: add pending SGI checking API Joseph Lo
@ 2012-12-05 22:09 ` Stephen Warren
2012-12-06 7:04 ` Joseph Lo
0 siblings, 1 reply; 27+ messages in thread
From: Stephen Warren @ 2012-12-05 22:09 UTC (permalink / raw)
To: linux-arm-kernel
On 12/05/2012 03:01 AM, Joseph Lo wrote:
> The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it
> include the power of GIC. That caused the SGI (Software Generated
> Interrupt) been lost. Because the SGI can't wake up the CPU that in
> the "powered-down" CPU idle mode. We need to check if there is any
> pending SGI when go into "powered-down" CPU idle mode. This is important
> especially when applying the coupled cpuidle framework into "power-down"
> cpuidle dirver. Because the coupled cpuidle framework may have the
> chance that misses IPI_SINGLE_FUNC handling sometimes.
>
> For the PPI or SPI, something like the legacy peripheral interrupt. It
> still can be maintained by Tegra legacy interrupt controller. If there
> is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The
> CPU can be woken up immediately. So we don't need to take care the same
> situation for PPI or SPI.
Is this feature something that can/should be added to the core GIC
driver, rather than something custom in the Tegra code?
Part of the reason I ask is that I'd like to avoid any more:
static void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
since that requires static page tables to be set up, whereas I'd like to
reduce, as much as possible, the set of pages Tegra maps statically.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 1/6] ARM: tegra: add pending SGI checking API
2012-12-05 22:09 ` Stephen Warren
@ 2012-12-06 7:04 ` Joseph Lo
2012-12-06 18:52 ` Stephen Warren
0 siblings, 1 reply; 27+ messages in thread
From: Joseph Lo @ 2012-12-06 7:04 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2012-12-06 at 06:09 +0800, Stephen Warren wrote:
> On 12/05/2012 03:01 AM, Joseph Lo wrote:
> > The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it
> > include the power of GIC. That caused the SGI (Software Generated
> > Interrupt) been lost. Because the SGI can't wake up the CPU that in
> > the "powered-down" CPU idle mode. We need to check if there is any
> > pending SGI when go into "powered-down" CPU idle mode. This is important
> > especially when applying the coupled cpuidle framework into "power-down"
> > cpuidle dirver. Because the coupled cpuidle framework may have the
> > chance that misses IPI_SINGLE_FUNC handling sometimes.
> >
> > For the PPI or SPI, something like the legacy peripheral interrupt. It
> > still can be maintained by Tegra legacy interrupt controller. If there
> > is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The
> > CPU can be woken up immediately. So we don't need to take care the same
> > situation for PPI or SPI.
>
> Is this feature something that can/should be added to the core GIC
> driver, rather than something custom in the Tegra code?
>
This function is SoC specific code not a generic common code even I
modify it to more generic for checking the pending irq (SGI, PPI and
SPI). Different SoC had different design about it. For ex, some SoC only
put CPU core to power saving mode not include GIC, or there is another
irq controller can handle the case when CPU go into power saving mode.
Differenc SoC had different usage here (some need to check all pending
irq, some need to check SGI only and some even no need to consider
this).
> Part of the reason I ask is that I'd like to avoid any more:
>
> static void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
>
> since that requires static page tables to be set up, whereas I'd like to
> reduce, as much as possible, the set of pages Tegra maps statically.
I can move this into the function as a temp variable.
Thanks,
Joseph
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 1/6] ARM: tegra: add pending SGI checking API
2012-12-06 7:04 ` Joseph Lo
@ 2012-12-06 18:52 ` Stephen Warren
0 siblings, 0 replies; 27+ messages in thread
From: Stephen Warren @ 2012-12-06 18:52 UTC (permalink / raw)
To: linux-arm-kernel
On 12/06/2012 12:04 AM, Joseph Lo wrote:
> On Thu, 2012-12-06 at 06:09 +0800, Stephen Warren wrote:
>> On 12/05/2012 03:01 AM, Joseph Lo wrote:
>>> The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it
>>> include the power of GIC. That caused the SGI (Software Generated
>>> Interrupt) been lost. Because the SGI can't wake up the CPU that in
>>> the "powered-down" CPU idle mode. We need to check if there is any
>>> pending SGI when go into "powered-down" CPU idle mode. This is important
>>> especially when applying the coupled cpuidle framework into "power-down"
>>> cpuidle dirver. Because the coupled cpuidle framework may have the
>>> chance that misses IPI_SINGLE_FUNC handling sometimes.
>>>
>>> For the PPI or SPI, something like the legacy peripheral interrupt. It
>>> still can be maintained by Tegra legacy interrupt controller. If there
>>> is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The
>>> CPU can be woken up immediately. So we don't need to take care the same
>>> situation for PPI or SPI.
>>
>> Is this feature something that can/should be added to the core GIC
>> driver, rather than something custom in the Tegra code?
>>
> This function is SoC specific code not a generic common code even I
> modify it to more generic for checking the pending irq (SGI, PPI and
> SPI). Different SoC had different design about it. For ex, some SoC only
> put CPU core to power saving mode not include GIC, or there is another
> irq controller can handle the case when CPU go into power saving mode.
> Differenc SoC had different usage here (some need to check all pending
> irq, some need to check SGI only and some even no need to consider
> this).
Hmmm. OK.
>> Part of the reason I ask is that I'd like to avoid any more:
>>
>> static void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
>>
>> since that requires static page tables to be set up, whereas I'd like to
>> reduce, as much as possible, the set of pages Tegra maps statically.
>
> I can move this into the function as a temp variable.
Well, the issue here is use of the IO_ADDRESS() macro at all; ioremap()
at run-time would be better, which I imagine is what the core GIC driver
does when intialized from DT. Still, I suppose there are many instance
of IO_ADDRESS() in the mach-tegra directory right now, so adding one
more won't hurt too much; we still need to do a big pass to get rid of
them sometime if possible.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2012-12-05 10:01 [PATCH V2 0/6] ARM: tegra20: cpuidle: add power-down state Joseph Lo
2012-12-05 10:01 ` [PATCH V2 1/6] ARM: tegra: add pending SGI checking API Joseph Lo
@ 2012-12-05 10:01 ` Joseph Lo
2012-12-05 10:50 ` Lorenzo Pieralisi
2012-12-05 22:18 ` Stephen Warren
2012-12-05 10:01 ` [PATCH V2 3/6] ARM: tegra20: clocks: add CPU low-power function into tegra_cpu_car_ops Joseph Lo
` (5 subsequent siblings)
7 siblings, 2 replies; 27+ messages in thread
From: Joseph Lo @ 2012-12-05 10:01 UTC (permalink / raw)
To: linux-arm-kernel
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI. The Tegra20 had a limition to
power down both CPU cores. The secondary CPU must waits for CPU0 in
powered-down state too. If the secondary CPU be woken up before CPU0
entering powered-down state, then it needs to restore its CPU states
and waits for next chance.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* no change
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 84 +++++++++++++++++++
arch/arm/mach-tegra/pm.c | 2 +
arch/arm/mach-tegra/sleep-tegra20.S | 145 +++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/sleep.h | 23 +++++
4 files changed, 254 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index d32e8b0..9d59a46 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -22,21 +22,105 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/clockchips.h>
#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/smp_plat.h>
+
+#include "pm.h"
+#include "sleep.h"
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra20_idle_lp2(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index);
+#endif
static struct cpuidle_driver tegra_idle_driver = {
.name = "tegra_idle",
.owner = THIS_MODULE,
.en_core_tk_irqen = 1,
+#ifdef CONFIG_PM_SLEEP
+ .state_count = 2,
+#else
.state_count = 1,
+#endif
.states = {
[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+#ifdef CONFIG_PM_SLEEP
+ [1] = {
+ .enter = tegra20_idle_lp2,
+ .exit_latency = 5000,
+ .target_residency = 10000,
+ .power_usage = 0,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .name = "powered-down",
+ .desc = "CPU power gated",
+ },
+#endif
},
};
static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_SMP
+static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+
+ smp_wmb();
+
+ cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
+
+ tegra20_cpu_clear_resettable();
+
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+
+ return true;
+}
+#else
+static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ return true;
+}
+#endif
+
+static int __cpuinit tegra20_idle_lp2(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
+ bool entered_lp2 = false;
+
+ local_fiq_disable();
+
+ tegra_set_cpu_in_lp2(cpu);
+ cpu_pm_enter();
+
+ if (cpu == 0)
+ cpu_do_idle();
+ else
+ entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
+
+ cpu_pm_exit();
+ tegra_clear_cpu_in_lp2(cpu);
+
+ local_fiq_enable();
+
+ smp_rmb();
+
+ return (entered_lp2) ? index : 0;
+}
+#endif
+
int __init tegra20_cpuidle_init(void)
{
int ret;
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 1b11707..db72ea9 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -173,6 +173,8 @@ bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id)
if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
last_cpu = true;
+ else if (phy_cpu_id == 1)
+ tegra20_cpu_set_resettable_soon();
spin_unlock(&tegra_lp2_lock);
return last_cpu;
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 72ce709..dfb2be5 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -21,6 +21,8 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
+#include <asm/proc-fns.h>
+#include <asm/cp15.h>
#include "sleep.h"
#include "flowctrl.h"
@@ -78,3 +80,146 @@ ENTRY(tegra20_cpu_shutdown)
mov pc, lr
ENDPROC(tegra20_cpu_shutdown)
#endif
+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_pen_lock
+ *
+ * spinlock implementation with no atomic test-and-set and no coherence
+ * using Peterson's algorithm on strongly-ordered registers
+ * used to synchronize a cpu waking up from wfi with entering lp2 on idle
+ *
+ * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]
+ * on cpu1:
+ * SCRATCH39 = r2 = flag[1]
+ * SCRATCH38 = r3 = flag[0]
+ *
+ * must be called with MMU on
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_pen_lock)
+ mov32 r3, TEGRA_PMC_VIRT
+ cpu_id r0
+ add r1, r3, #PMC_SCRATCH37
+ cmp r0, #0
+ addeq r2, r3, #PMC_SCRATCH38
+ addeq r3, r3, #PMC_SCRATCH39
+ addne r2, r3, #PMC_SCRATCH39
+ addne r3, r3, #PMC_SCRATCH38
+
+ mov r12, #1
+ str r12, [r2] @ flag[cpu] = 1
+ dsb
+ str r12, [r1] @ !turn = cpu
+1: dsb
+ ldr r12, [r3]
+ cmp r12, #1 @ flag[!cpu] == 1?
+ ldreq r12, [r1]
+ cmpeq r12, r0 @ !turn == cpu?
+ beq 1b @ while !turn == cpu && flag[!cpu] == 1
+
+ mov pc, lr @ locked
+ENDPROC(tegra_pen_lock)
+
+ENTRY(tegra_pen_unlock)
+ dsb
+ mov32 r3, TEGRA_PMC_VIRT
+ cpu_id r0
+ cmp r0, #0
+ addeq r2, r3, #PMC_SCRATCH38
+ addne r2, r3, #PMC_SCRATCH39
+ mov r12, #0
+ str r12, [r2]
+ mov pc, lr
+ENDPROC(tegra_pen_unlock)
+
+/*
+ * tegra20_cpu_clear_resettable(void)
+ *
+ * Called to clear the "resettable soon" flag in PMC_SCRATCH41 when
+ * it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra20_cpu_clear_resettable)
+ mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+ mov r12, #CPU_NOT_RESETTABLE
+ str r12, [r1]
+ mov pc, lr
+ENDPROC(tegra20_cpu_clear_resettable)
+
+/*
+ * tegra20_cpu_set_resettable_soon(void)
+ *
+ * Called to set the "resettable soon" flag in PMC_SCRATCH41 when
+ * it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra20_cpu_set_resettable_soon)
+ mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+ mov r12, #CPU_RESETTABLE_SOON
+ str r12, [r1]
+ mov pc, lr
+ENDPROC(tegra20_cpu_set_resettable_soon)
+
+/*
+ * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
+ *
+ * Enters WFI on secondary CPU by exiting coherency.
+ */
+ENTRY(tegra20_sleep_cpu_secondary_finish)
+ mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency
+
+ /* Flush and disable the L1 data cache */
+ bl tegra_disable_clean_inv_dcache
+
+ mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
+ mov r3, #CPU_RESETTABLE
+ str r3, [r0]
+
+ bl cpu_do_idle
+
+ /*
+ * cpu may be reset while in wfi, which will return through
+ * tegra_resume to cpu_resume
+ * or interrupt may wake wfi, which will return here
+ * cpu state is unchanged - MMU is on, cache is on, coherency
+ * is off, and the data cache is off
+ *
+ * r11 contains the original actlr
+ */
+
+ bl tegra_pen_lock
+
+ mov32 r3, TEGRA_PMC_VIRT
+ add r0, r3, #PMC_SCRATCH41
+ mov r3, #CPU_NOT_RESETTABLE
+ str r3, [r0]
+
+ bl tegra_pen_unlock
+
+ /* Re-enable the data cache */
+ mrc p15, 0, r10, c1, c0, 0
+ orr r10, r10, #CR_C
+ mcr p15, 0, r10, c1, c0, 0
+ isb
+
+ mcr p15, 0, r11, c1, c0, 1 @ reenable coherency
+
+ /* Invalidate the TLBs & BTAC */
+ mov r1, #0
+ mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
+ mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
+ dsb
+ isb
+
+ /* the cpu was running with coherency disabled,
+ * caches may be out of date */
+ bl v7_flush_kern_cache_louis
+
+ ldmia sp!, {r1 - r3} @ pop phys pgd, virt SP, phys resume fn
+ mov r0, #0 @ return success
+ mov sp, r2 @ sp is stored in r2 by __cpu_suspend
+ ldmfd sp!, {r4 - r11, pc}
+ENDPROC(tegra20_sleep_cpu_secondary_finish)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 9821ee7..a02f71a 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -25,6 +25,19 @@
+ IO_PPSB_VIRT)
#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
+ IO_PPSB_VIRT)
+#define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
+
+/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
+#define PMC_SCRATCH37 0x130
+#define PMC_SCRATCH38 0x134
+#define PMC_SCRATCH39 0x138
+#define PMC_SCRATCH41 0x140
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#define CPU_RESETTABLE 2
+#define CPU_RESETTABLE_SOON 1
+#define CPU_NOT_RESETTABLE 0
+#endif
#ifdef __ASSEMBLY__
/* returns the offset of the flow controller halt register for a cpu */
@@ -104,6 +117,8 @@ exit_l2_resume:
.endm
#endif /* CONFIG_CACHE_L2X0 */
#else
+void tegra_pen_lock(void);
+void tegra_pen_unlock(void);
void tegra_resume(void);
int tegra_sleep_cpu_finish(unsigned long);
@@ -115,6 +130,14 @@ static inline void tegra20_hotplug_init(void) {}
static inline void tegra30_hotplug_init(void) {}
#endif
+void tegra20_cpu_clear_resettable(void);
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void tegra20_cpu_set_resettable_soon(void);
+#else
+static inline void tegra20_cpu_set_resettable_soon(void) {}
+#endif
+
+int tegra20_sleep_cpu_secondary_finish(unsigned long);
int tegra30_sleep_cpu_secondary_finish(unsigned long);
void tegra30_tear_down_cpu(void);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2012-12-05 10:01 ` [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU Joseph Lo
@ 2012-12-05 10:50 ` Lorenzo Pieralisi
2012-12-06 8:25 ` Joseph Lo
2013-01-11 7:20 ` Joseph Lo
2012-12-05 22:18 ` Stephen Warren
1 sibling, 2 replies; 27+ messages in thread
From: Lorenzo Pieralisi @ 2012-12-05 10:50 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:
> The powered-down state of Tegra20 requires power gating both CPU cores.
> When the secondary CPU requests to enter powered-down state, it saves
> its own contexts and then enters WFI. The Tegra20 had a limition to
> power down both CPU cores. The secondary CPU must waits for CPU0 in
> powered-down state too. If the secondary CPU be woken up before CPU0
> entering powered-down state, then it needs to restore its CPU states
> and waits for next chance.
>
> Be aware of that, you may see the legacy power state "LP2" in the code
> which is exactly the same meaning of "CPU power down".
>
> Based on the work by:
> Colin Cross <ccross@android.com>
> Gary King <gking@nvidia.com>
>
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
> V2:
> * no change
> ---
> arch/arm/mach-tegra/cpuidle-tegra20.c | 84 +++++++++++++++++++
> arch/arm/mach-tegra/pm.c | 2 +
> arch/arm/mach-tegra/sleep-tegra20.S | 145 +++++++++++++++++++++++++++++++++
> arch/arm/mach-tegra/sleep.h | 23 +++++
> 4 files changed, 254 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
> index d32e8b0..9d59a46 100644
> --- a/arch/arm/mach-tegra/cpuidle-tegra20.c
> +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
> @@ -22,21 +22,105 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/cpuidle.h>
> +#include <linux/cpu_pm.h>
> +#include <linux/clockchips.h>
>
> #include <asm/cpuidle.h>
> +#include <asm/proc-fns.h>
> +#include <asm/suspend.h>
> +#include <asm/smp_plat.h>
> +
> +#include "pm.h"
> +#include "sleep.h"
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int tegra20_idle_lp2(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv,
> + int index);
> +#endif
>
> static struct cpuidle_driver tegra_idle_driver = {
> .name = "tegra_idle",
> .owner = THIS_MODULE,
> .en_core_tk_irqen = 1,
> +#ifdef CONFIG_PM_SLEEP
> + .state_count = 2,
> +#else
> .state_count = 1,
> +#endif
These hardcoded values are not nice.
> .states = {
> [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
> +#ifdef CONFIG_PM_SLEEP
> + [1] = {
> + .enter = tegra20_idle_lp2,
> + .exit_latency = 5000,
> + .target_residency = 10000,
> + .power_usage = 0,
> + .flags = CPUIDLE_FLAG_TIME_VALID,
> + .name = "powered-down",
> + .desc = "CPU power gated",
> + },
> +#endif
> },
> };
>
> static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
>
> +#ifdef CONFIG_PM_SLEEP
> +#ifdef CONFIG_SMP
> +static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv,
> + int index)
> +{
> + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
> +
> + smp_wmb();
Can you explain to me the need for this barrier ?
> +
> + cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
> +
> + tegra20_cpu_clear_resettable();
> +
> + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
> +
> + return true;
> +}
> +#else
> +static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv,
> + int index)
> +{
> + return true;
> +}
> +#endif
> +
> +static int __cpuinit tegra20_idle_lp2(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv,
> + int index)
> +{
> + u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
> + bool entered_lp2 = false;
> +
> + local_fiq_disable();
> +
> + tegra_set_cpu_in_lp2(cpu);
> + cpu_pm_enter();
> +
> + if (cpu == 0)
> + cpu_do_idle();
> + else
> + entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
> +
> + cpu_pm_exit();
> + tegra_clear_cpu_in_lp2(cpu);
> +
> + local_fiq_enable();
> +
> + smp_rmb();
> +
> + return (entered_lp2) ? index : 0;
> +}
> +#endif
> +
> int __init tegra20_cpuidle_init(void)
> {
> int ret;
> diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
> index 1b11707..db72ea9 100644
> --- a/arch/arm/mach-tegra/pm.c
> +++ b/arch/arm/mach-tegra/pm.c
> @@ -173,6 +173,8 @@ bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id)
>
> if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
> last_cpu = true;
> + else if (phy_cpu_id == 1)
> + tegra20_cpu_set_resettable_soon();
>
> spin_unlock(&tegra_lp2_lock);
> return last_cpu;
> diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
> index 72ce709..dfb2be5 100644
> --- a/arch/arm/mach-tegra/sleep-tegra20.S
> +++ b/arch/arm/mach-tegra/sleep-tegra20.S
> @@ -21,6 +21,8 @@
> #include <linux/linkage.h>
>
> #include <asm/assembler.h>
> +#include <asm/proc-fns.h>
> +#include <asm/cp15.h>
>
> #include "sleep.h"
> #include "flowctrl.h"
> @@ -78,3 +80,146 @@ ENTRY(tegra20_cpu_shutdown)
> mov pc, lr
> ENDPROC(tegra20_cpu_shutdown)
> #endif
> +
> +#ifdef CONFIG_PM_SLEEP
> +/*
> + * tegra_pen_lock
> + *
> + * spinlock implementation with no atomic test-and-set and no coherence
> + * using Peterson's algorithm on strongly-ordered registers
> + * used to synchronize a cpu waking up from wfi with entering lp2 on idle
> + *
> + * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
> + * on cpu 0:
> + * SCRATCH38 = r2 = flag[0]
> + * SCRATCH39 = r3 = flag[1]
> + * on cpu1:
> + * SCRATCH39 = r2 = flag[1]
> + * SCRATCH38 = r3 = flag[0]
> + *
> + * must be called with MMU on
> + * corrupts r0-r3, r12
> + */
> +ENTRY(tegra_pen_lock)
> + mov32 r3, TEGRA_PMC_VIRT
> + cpu_id r0
> + add r1, r3, #PMC_SCRATCH37
> + cmp r0, #0
> + addeq r2, r3, #PMC_SCRATCH38
> + addeq r3, r3, #PMC_SCRATCH39
> + addne r2, r3, #PMC_SCRATCH39
> + addne r3, r3, #PMC_SCRATCH38
> +
> + mov r12, #1
> + str r12, [r2] @ flag[cpu] = 1
> + dsb
> + str r12, [r1] @ !turn = cpu
> +1: dsb
> + ldr r12, [r3]
> + cmp r12, #1 @ flag[!cpu] == 1?
> + ldreq r12, [r1]
> + cmpeq r12, r0 @ !turn == cpu?
> + beq 1b @ while !turn == cpu && flag[!cpu] == 1
> +
> + mov pc, lr @ locked
> +ENDPROC(tegra_pen_lock)
> +
> +ENTRY(tegra_pen_unlock)
> + dsb
> + mov32 r3, TEGRA_PMC_VIRT
> + cpu_id r0
> + cmp r0, #0
> + addeq r2, r3, #PMC_SCRATCH38
> + addne r2, r3, #PMC_SCRATCH39
> + mov r12, #0
> + str r12, [r2]
> + mov pc, lr
> +ENDPROC(tegra_pen_unlock)
There is an ongoing work to make this locking scheme for MMU/coherency off
paths ARM generic, and we do not want to merge yet another platform specific
locking mechanism. I will point you to the patchset when it hits LAK.
> +
> +/*
> + * tegra20_cpu_clear_resettable(void)
> + *
> + * Called to clear the "resettable soon" flag in PMC_SCRATCH41 when
> + * it is expected that the secondary CPU will be idle soon.
> + */
> +ENTRY(tegra20_cpu_clear_resettable)
> + mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
> + mov r12, #CPU_NOT_RESETTABLE
> + str r12, [r1]
> + mov pc, lr
> +ENDPROC(tegra20_cpu_clear_resettable)
> +
> +/*
> + * tegra20_cpu_set_resettable_soon(void)
> + *
> + * Called to set the "resettable soon" flag in PMC_SCRATCH41 when
> + * it is expected that the secondary CPU will be idle soon.
> + */
> +ENTRY(tegra20_cpu_set_resettable_soon)
> + mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
> + mov r12, #CPU_RESETTABLE_SOON
> + str r12, [r1]
> + mov pc, lr
> +ENDPROC(tegra20_cpu_set_resettable_soon)
> +
> +/*
> + * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
> + *
> + * Enters WFI on secondary CPU by exiting coherency.
> + */
> +ENTRY(tegra20_sleep_cpu_secondary_finish)
> + mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency
> +
> + /* Flush and disable the L1 data cache */
> + bl tegra_disable_clean_inv_dcache
> +
> + mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
> + mov r3, #CPU_RESETTABLE
> + str r3, [r0]
> +
> + bl cpu_do_idle
> +
> + /*
> + * cpu may be reset while in wfi, which will return through
> + * tegra_resume to cpu_resume
> + * or interrupt may wake wfi, which will return here
> + * cpu state is unchanged - MMU is on, cache is on, coherency
> + * is off, and the data cache is off
> + *
> + * r11 contains the original actlr
> + */
> +
> + bl tegra_pen_lock
> +
> + mov32 r3, TEGRA_PMC_VIRT
> + add r0, r3, #PMC_SCRATCH41
> + mov r3, #CPU_NOT_RESETTABLE
> + str r3, [r0]
> +
> + bl tegra_pen_unlock
> +
> + /* Re-enable the data cache */
> + mrc p15, 0, r10, c1, c0, 0
> + orr r10, r10, #CR_C
> + mcr p15, 0, r10, c1, c0, 0
> + isb
> +
> + mcr p15, 0, r11, c1, c0, 1 @ reenable coherency
> +
> + /* Invalidate the TLBs & BTAC */
> + mov r1, #0
> + mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
> + mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
> + dsb
> + isb
> +
> + /* the cpu was running with coherency disabled,
> + * caches may be out of date */
> + bl v7_flush_kern_cache_louis
> +
> + ldmia sp!, {r1 - r3} @ pop phys pgd, virt SP, phys resume fn
> + mov r0, #0 @ return success
> + mov sp, r2 @ sp is stored in r2 by __cpu_suspend
This is not true. sp is retrieved from the r2 value popped above.
Anyway, all this code is a copy'n'paste from __cpu_suspend. Now if I got
what you want to do right, all you want to do is return to cpu_suspend
with r0 == 0.
(1) You should not rely on the register layout of __cpu_suspend since if
it changes we have to patch this code as well. Do not rely on that.
(2) Why do you want to return with r0 == 0 ? To me that's a mistery.
Is that because you want cpu_suspend to restore the page table
pointer ? Even in that case I am afraid I am against this code.
Usage of cpu_suspend must be consistent and you *must* not use it as a
plaster or rely on any specific register layout, it has to be used
for the purpose it has been designed for.
Lorenzo
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2012-12-05 10:50 ` Lorenzo Pieralisi
@ 2012-12-06 8:25 ` Joseph Lo
2012-12-06 18:56 ` Stephen Warren
2013-01-11 7:20 ` Joseph Lo
1 sibling, 1 reply; 27+ messages in thread
From: Joseph Lo @ 2012-12-06 8:25 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2012-12-05 at 18:50 +0800, Lorenzo Pieralisi wrote:
> On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:
> > static struct cpuidle_driver tegra_idle_driver = {
> > .name = "tegra_idle",
> > .owner = THIS_MODULE,
> > .en_core_tk_irqen = 1,
> > +#ifdef CONFIG_PM_SLEEP
> > + .state_count = 2,
> > +#else
> > .state_count = 1,
> > +#endif
>
> These hardcoded values are not nice.
>
OK. I will change it to runtime detection when idle driver registration.
> > .states = {
> > [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
> > +#ifdef CONFIG_PM_SLEEP
> > + [1] = {
> > + .enter = tegra20_idle_lp2,
> > + .exit_latency = 5000,
> > + .target_residency = 10000,
> > + .power_usage = 0,
> > + .flags = CPUIDLE_FLAG_TIME_VALID,
> > + .name = "powered-down",
> > + .desc = "CPU power gated",
> > + },
> > +#endif
> > },
> > };
> >
> > static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
> >
> > +#ifdef CONFIG_PM_SLEEP
> > +#ifdef CONFIG_SMP
> > +static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
> > + struct cpuidle_driver *drv,
> > + int index)
> > +{
> > + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
> > +
> > + smp_wmb();
>
> Can you explain to me the need for this barrier ?
>
Ah. The barrier was no need here. This function was been designed for
MPCore usage before. After some migrations, now it was be used for CPU1
only. Will remove it. Good catch here, thanks.
> > +
> > + cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
> > +
> > + tegra20_cpu_clear_resettable();
> > +
> > + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
> > +
> > + return true;
> > +}
> > +#ifdef CONFIG_PM_SLEEP
> > +/*
> > + * tegra_pen_lock
> > + *
> > + * spinlock implementation with no atomic test-and-set and no coherence
> > + * using Peterson's algorithm on strongly-ordered registers
> > + * used to synchronize a cpu waking up from wfi with entering lp2 on idle
> > + *
> > + * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
> > + * on cpu 0:
> > + * SCRATCH38 = r2 = flag[0]
> > + * SCRATCH39 = r3 = flag[1]
> > + * on cpu1:
> > + * SCRATCH39 = r2 = flag[1]
> > + * SCRATCH38 = r3 = flag[0]
> > + *
> > + * must be called with MMU on
> > + * corrupts r0-r3, r12
> > + */
> > +ENTRY(tegra_pen_lock)
> > + mov32 r3, TEGRA_PMC_VIRT
> > + cpu_id r0
> > + add r1, r3, #PMC_SCRATCH37
> > + cmp r0, #0
> > + addeq r2, r3, #PMC_SCRATCH38
> > + addeq r3, r3, #PMC_SCRATCH39
> > + addne r2, r3, #PMC_SCRATCH39
> > + addne r3, r3, #PMC_SCRATCH38
> > +
> > + mov r12, #1
> > + str r12, [r2] @ flag[cpu] = 1
> > + dsb
> > + str r12, [r1] @ !turn = cpu
> > +1: dsb
> > + ldr r12, [r3]
> > + cmp r12, #1 @ flag[!cpu] == 1?
> > + ldreq r12, [r1]
> > + cmpeq r12, r0 @ !turn == cpu?
> > + beq 1b @ while !turn == cpu && flag[!cpu] == 1
> > +
> > + mov pc, lr @ locked
> > +ENDPROC(tegra_pen_lock)
> > +
> > +ENTRY(tegra_pen_unlock)
> > + dsb
> > + mov32 r3, TEGRA_PMC_VIRT
> > + cpu_id r0
> > + cmp r0, #0
> > + addeq r2, r3, #PMC_SCRATCH38
> > + addne r2, r3, #PMC_SCRATCH39
> > + mov r12, #0
> > + str r12, [r2]
> > + mov pc, lr
> > +ENDPROC(tegra_pen_unlock)
>
> There is an ongoing work to make this locking scheme for MMU/coherency off
> paths ARM generic, and we do not want to merge yet another platform specific
> locking mechanism. I will point you to the patchset when it hits LAK.
>
OK. So I need to wait the common locking scheme for this patchset. Does
it possible available before K3.9? Please remind me when it show up
here. Thanks.
> > +/*
> > + * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
> > + *
> > + * Enters WFI on secondary CPU by exiting coherency.
> > + */
> > +ENTRY(tegra20_sleep_cpu_secondary_finish)
> > + mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency
> > +
> > + /* Flush and disable the L1 data cache */
> > + bl tegra_disable_clean_inv_dcache
> > +
> > + mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
> > + mov r3, #CPU_RESETTABLE
> > + str r3, [r0]
> > +
> > + bl cpu_do_idle
> > +
> > + /*
> > + * cpu may be reset while in wfi, which will return through
> > + * tegra_resume to cpu_resume
> > + * or interrupt may wake wfi, which will return here
> > + * cpu state is unchanged - MMU is on, cache is on, coherency
> > + * is off, and the data cache is off
> > + *
> > + * r11 contains the original actlr
> > + */
> > +
> > + bl tegra_pen_lock
> > +
> > + mov32 r3, TEGRA_PMC_VIRT
> > + add r0, r3, #PMC_SCRATCH41
> > + mov r3, #CPU_NOT_RESETTABLE
> > + str r3, [r0]
> > +
> > + bl tegra_pen_unlock
> > +
> > + /* Re-enable the data cache */
> > + mrc p15, 0, r10, c1, c0, 0
> > + orr r10, r10, #CR_C
> > + mcr p15, 0, r10, c1, c0, 0
> > + isb
> > +
> > + mcr p15, 0, r11, c1, c0, 1 @ reenable coherency
> > +
> > + /* Invalidate the TLBs & BTAC */
> > + mov r1, #0
> > + mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
> > + mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
> > + dsb
> > + isb
> > +
> > + /* the cpu was running with coherency disabled,
> > + * caches may be out of date */
> > + bl v7_flush_kern_cache_louis
> > +
> > + ldmia sp!, {r1 - r3} @ pop phys pgd, virt SP, phys resume fn
> > + mov r0, #0 @ return success
> > + mov sp, r2 @ sp is stored in r2 by __cpu_suspend
>
> This is not true. sp is retrieved from the r2 value popped above.
> Anyway, all this code is a copy'n'paste from __cpu_suspend. Now if I got
> what you want to do right, all you want to do is return to cpu_suspend
> with r0 == 0.
>
> (1) You should not rely on the register layout of __cpu_suspend since if
> it changes we have to patch this code as well. Do not rely on that.
> (2) Why do you want to return with r0 == 0 ? To me that's a mistery.
> Is that because you want cpu_suspend to restore the page table
> pointer ? Even in that case I am afraid I am against this code.
> Usage of cpu_suspend must be consistent and you *must* not use it as a
> plaster or rely on any specific register layout, it has to be used
> for the purpose it has been designed for.
>
Thank you for reviewing this so carefully.
I re-traced the sequence today. I think I only need to do something
below. And rely on the "cpu_suspend_abort" in "__cpu_suspend" to abort
"cpu_suspend".
ENTRY(tegra20_sleep_cpu_secondary_finish)
stmfd sp!, {r4-r11, lr}
...
ldmfd sp!, {r4-r11, pc}
ENDPROC(tegra20_sleep_cpu_secondary_finish)
Thanks,
Joseph
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2012-12-06 8:25 ` Joseph Lo
@ 2012-12-06 18:56 ` Stephen Warren
0 siblings, 0 replies; 27+ messages in thread
From: Stephen Warren @ 2012-12-06 18:56 UTC (permalink / raw)
To: linux-arm-kernel
On 12/06/2012 01:25 AM, Joseph Lo wrote:
> On Wed, 2012-12-05 at 18:50 +0800, Lorenzo Pieralisi wrote:
>> On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:
>>> static struct cpuidle_driver tegra_idle_driver = {
>>> .name = "tegra_idle",
>>> .owner = THIS_MODULE,
>>> .en_core_tk_irqen = 1,
>>> +#ifdef CONFIG_PM_SLEEP
>>> + .state_count = 2,
>>> +#else
>>> .state_count = 1,
>>> +#endif
>>
>> These hardcoded values are not nice.
>>
> OK. I will change it to runtime detection when idle driver registration.
Personally, I find doing this at compile-time much better; the
conditional definition of state_count is right next to the conditional
setup of the array whose size it defines. Assigning state_count at
run-time ense up moving the two pieces of logic apart, which seems
likely to cause more issues...
>>> .states = {
>>> [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
>>> +#ifdef CONFIG_PM_SLEEP
>>> + [1] = {
>>> + .enter = tegra20_idle_lp2,
>>> + .exit_latency = 5000,
>>> + .target_residency = 10000,
>>> + .power_usage = 0,
>>> + .flags = CPUIDLE_FLAG_TIME_VALID,
>>> + .name = "powered-down",
>>> + .desc = "CPU power gated",
>>> + },
>>> +#endif
>>> },
>>> };
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2012-12-05 10:50 ` Lorenzo Pieralisi
2012-12-06 8:25 ` Joseph Lo
@ 2013-01-11 7:20 ` Joseph Lo
2013-01-11 12:24 ` Lorenzo Pieralisi
2013-01-12 17:33 ` Nicolas Pitre
1 sibling, 2 replies; 27+ messages in thread
From: Joseph Lo @ 2013-01-11 7:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Lorenzo,
On Wed, 2012-12-05 at 18:50 +0800, Lorenzo Pieralisi wrote:
> On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:
> > The powered-down state of Tegra20 requires power gating both CPU cores.
> > When the secondary CPU requests to enter powered-down state, it saves
> > its own contexts and then enters WFI. The Tegra20 had a limition to
> > power down both CPU cores. The secondary CPU must waits for CPU0 in
> > powered-down state too. If the secondary CPU be woken up before CPU0
> > entering powered-down state, then it needs to restore its CPU states
> > and waits for next chance.
> >
> > Be aware of that, you may see the legacy power state "LP2" in the code
> > which is exactly the same meaning of "CPU power down".
> >
> > Based on the work by:
> > Colin Cross <ccross@android.com>
> > Gary King <gking@nvidia.com>
> >
> > Signed-off-by: Joseph Lo <josephl@nvidia.com>
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +/*
> > + * tegra_pen_lock
> > + *
> > + * spinlock implementation with no atomic test-and-set and no coherence
> > + * using Peterson's algorithm on strongly-ordered registers
> > + * used to synchronize a cpu waking up from wfi with entering lp2 on idle
> > + *
> > + * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
> > + * on cpu 0:
> > + * SCRATCH38 = r2 = flag[0]
> > + * SCRATCH39 = r3 = flag[1]
> > + * on cpu1:
> > + * SCRATCH39 = r2 = flag[1]
> > + * SCRATCH38 = r3 = flag[0]
> > + *
> > + * must be called with MMU on
> > + * corrupts r0-r3, r12
> > + */
> > +ENTRY(tegra_pen_lock)
> > + mov32 r3, TEGRA_PMC_VIRT
> > + cpu_id r0
> > + add r1, r3, #PMC_SCRATCH37
> > + cmp r0, #0
> > + addeq r2, r3, #PMC_SCRATCH38
> > + addeq r3, r3, #PMC_SCRATCH39
> > + addne r2, r3, #PMC_SCRATCH39
> > + addne r3, r3, #PMC_SCRATCH38
> > +
> > + mov r12, #1
> > + str r12, [r2] @ flag[cpu] = 1
> > + dsb
> > + str r12, [r1] @ !turn = cpu
> > +1: dsb
> > + ldr r12, [r3]
> > + cmp r12, #1 @ flag[!cpu] == 1?
> > + ldreq r12, [r1]
> > + cmpeq r12, r0 @ !turn == cpu?
> > + beq 1b @ while !turn == cpu && flag[!cpu] == 1
> > +
> > + mov pc, lr @ locked
> > +ENDPROC(tegra_pen_lock)
> > +
> > +ENTRY(tegra_pen_unlock)
> > + dsb
> > + mov32 r3, TEGRA_PMC_VIRT
> > + cpu_id r0
> > + cmp r0, #0
> > + addeq r2, r3, #PMC_SCRATCH38
> > + addne r2, r3, #PMC_SCRATCH39
> > + mov r12, #0
> > + str r12, [r2]
> > + mov pc, lr
> > +ENDPROC(tegra_pen_unlock)
>
> There is an ongoing work to make this locking scheme for MMU/coherency off
> paths ARM generic, and we do not want to merge yet another platform specific
> locking mechanism. I will point you to the patchset when it hits LAK.
>
You did mention there is an ARM generic locking scheme for MMU/coherency
off case before. Do you mean the patch below?
https://patchwork.kernel.org/patch/1957911/
https://patchwork.kernel.org/patch/1957901/
I gave it a review today. Looks it can't fit our usage for CPU idle
powered-down mode on Tegra20.
The generic mechanism only can be used when CPUs in non coherent world.
But our usage needs the mechanism could be used in both coherent and non
coherent case. OK. The case is we need to sync the status about the CPU1
was ready to power down. In this case, the CPU0 is still in coherent
world but the CPU1 isn't. So we need the locking scheme could be still
safe in this situation.
And the proposed scheme looks only for b.L system?
Thanks,
Joseph
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2013-01-11 7:20 ` Joseph Lo
@ 2013-01-11 12:24 ` Lorenzo Pieralisi
2013-01-15 3:00 ` Joseph Lo
2013-01-12 17:33 ` Nicolas Pitre
1 sibling, 1 reply; 27+ messages in thread
From: Lorenzo Pieralisi @ 2013-01-11 12:24 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 11, 2013 at 07:20:29AM +0000, Joseph Lo wrote:
> Hi Lorenzo,
>
> On Wed, 2012-12-05 at 18:50 +0800, Lorenzo Pieralisi wrote:
> > On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:
> > > The powered-down state of Tegra20 requires power gating both CPU cores.
> > > When the secondary CPU requests to enter powered-down state, it saves
> > > its own contexts and then enters WFI. The Tegra20 had a limition to
> > > power down both CPU cores. The secondary CPU must waits for CPU0 in
> > > powered-down state too. If the secondary CPU be woken up before CPU0
> > > entering powered-down state, then it needs to restore its CPU states
> > > and waits for next chance.
> > >
> > > Be aware of that, you may see the legacy power state "LP2" in the code
> > > which is exactly the same meaning of "CPU power down".
> > >
> > > Based on the work by:
> > > Colin Cross <ccross@android.com>
> > > Gary King <gking@nvidia.com>
> > >
> > > Signed-off-by: Joseph Lo <josephl@nvidia.com>
> > > +
> > > +#ifdef CONFIG_PM_SLEEP
> > > +/*
> > > + * tegra_pen_lock
> > > + *
> > > + * spinlock implementation with no atomic test-and-set and no coherence
> > > + * using Peterson's algorithm on strongly-ordered registers
> > > + * used to synchronize a cpu waking up from wfi with entering lp2 on idle
> > > + *
> > > + * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
> > > + * on cpu 0:
> > > + * SCRATCH38 = r2 = flag[0]
> > > + * SCRATCH39 = r3 = flag[1]
> > > + * on cpu1:
> > > + * SCRATCH39 = r2 = flag[1]
> > > + * SCRATCH38 = r3 = flag[0]
> > > + *
> > > + * must be called with MMU on
> > > + * corrupts r0-r3, r12
> > > + */
> > > +ENTRY(tegra_pen_lock)
> > > + mov32 r3, TEGRA_PMC_VIRT
> > > + cpu_id r0
> > > + add r1, r3, #PMC_SCRATCH37
> > > + cmp r0, #0
> > > + addeq r2, r3, #PMC_SCRATCH38
> > > + addeq r3, r3, #PMC_SCRATCH39
> > > + addne r2, r3, #PMC_SCRATCH39
> > > + addne r3, r3, #PMC_SCRATCH38
> > > +
> > > + mov r12, #1
> > > + str r12, [r2] @ flag[cpu] = 1
> > > + dsb
> > > + str r12, [r1] @ !turn = cpu
> > > +1: dsb
> > > + ldr r12, [r3]
> > > + cmp r12, #1 @ flag[!cpu] == 1?
> > > + ldreq r12, [r1]
> > > + cmpeq r12, r0 @ !turn == cpu?
> > > + beq 1b @ while !turn == cpu && flag[!cpu] == 1
> > > +
> > > + mov pc, lr @ locked
> > > +ENDPROC(tegra_pen_lock)
> > > +
> > > +ENTRY(tegra_pen_unlock)
> > > + dsb
> > > + mov32 r3, TEGRA_PMC_VIRT
> > > + cpu_id r0
> > > + cmp r0, #0
> > > + addeq r2, r3, #PMC_SCRATCH38
> > > + addne r2, r3, #PMC_SCRATCH39
> > > + mov r12, #0
> > > + str r12, [r2]
> > > + mov pc, lr
> > > +ENDPROC(tegra_pen_unlock)
> >
> > There is an ongoing work to make this locking scheme for MMU/coherency off
> > paths ARM generic, and we do not want to merge yet another platform specific
> > locking mechanism. I will point you to the patchset when it hits LAK.
> >
>
> You did mention there is an ARM generic locking scheme for MMU/coherency
> off case before. Do you mean the patch below?
>
> https://patchwork.kernel.org/patch/1957911/
> https://patchwork.kernel.org/patch/1957901/
Those are used for first-man election when multiple CPUs come out of
idle at once.
You should have a look at the entire series and in particular:
https://patchwork.kernel.org/patch/1957891/
https://patchwork.kernel.org/patch/1957951/
> I gave it a review today. Looks it can't fit our usage for CPU idle
> powered-down mode on Tegra20.
>
> The generic mechanism only can be used when CPUs in non coherent world.
> But our usage needs the mechanism could be used in both coherent and non
> coherent case. OK. The case is we need to sync the status about the CPU1
> was ready to power down. In this case, the CPU0 is still in coherent
> world but the CPU1 isn't. So we need the locking scheme could be still
> safe in this situation.
I know, I implemented something of that sort for an A9 based development
platform, that's why I pointed you to this new patchset.
Have a look at the series, it should do what you want.
> And the proposed scheme looks only for b.L system?
No it works also for single cluster systems. Please have a look and let
me know if you have any questions or comment on the thread so that
authors can help you understand the code.
Lorenzo
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2013-01-11 12:24 ` Lorenzo Pieralisi
@ 2013-01-15 3:00 ` Joseph Lo
2013-01-15 11:34 ` Lorenzo Pieralisi
0 siblings, 1 reply; 27+ messages in thread
From: Joseph Lo @ 2013-01-15 3:00 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 2013-01-11 at 20:24 +0800, Lorenzo Pieralisi wrote:
> On Fri, Jan 11, 2013 at 07:20:29AM +0000, Joseph Lo wrote:
> > On Wed, 2012-12-05 at 18:50 +0800, Lorenzo Pieralisi wrote:
> > > On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:
> > > > The powered-down state of Tegra20 requires power gating both CPU cores.
> > > > When the secondary CPU requests to enter powered-down state, it saves
> > > > its own contexts and then enters WFI. The Tegra20 had a limition to
> > > > power down both CPU cores. The secondary CPU must waits for CPU0 in
> > > > powered-down state too. If the secondary CPU be woken up before CPU0
> > > > entering powered-down state, then it needs to restore its CPU states
> > > > and waits for next chance.
> > > >
> > > > Be aware of that, you may see the legacy power state "LP2" in the code
> > > > which is exactly the same meaning of "CPU power down".
> > > >
> > > > Based on the work by:
> > > > Colin Cross <ccross@android.com>
> > > > Gary King <gking@nvidia.com>
> > > >
> > > > Signed-off-by: Joseph Lo <josephl@nvidia.com>
> > > > +
> > > > +#ifdef CONFIG_PM_SLEEP
> > > > +/*
> > > > + * tegra_pen_lock
> > > > + *
> > > > + * spinlock implementation with no atomic test-and-set and no coherence
> > > > + * using Peterson's algorithm on strongly-ordered registers
> > > > + * used to synchronize a cpu waking up from wfi with entering lp2 on idle
> > > > + *
> > > > + * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
> > > > + * on cpu 0:
> > > > + * SCRATCH38 = r2 = flag[0]
> > > > + * SCRATCH39 = r3 = flag[1]
> > > > + * on cpu1:
> > > > + * SCRATCH39 = r2 = flag[1]
> > > > + * SCRATCH38 = r3 = flag[0]
> > > > + *
> > > > + * must be called with MMU on
> > > > + * corrupts r0-r3, r12
> > > > + */
> > > > +ENTRY(tegra_pen_lock)
> > > > + mov32 r3, TEGRA_PMC_VIRT
> > > > + cpu_id r0
> > > > + add r1, r3, #PMC_SCRATCH37
> > > > + cmp r0, #0
> > > > + addeq r2, r3, #PMC_SCRATCH38
> > > > + addeq r3, r3, #PMC_SCRATCH39
> > > > + addne r2, r3, #PMC_SCRATCH39
> > > > + addne r3, r3, #PMC_SCRATCH38
> > > > +
> > > > + mov r12, #1
> > > > + str r12, [r2] @ flag[cpu] = 1
> > > > + dsb
> > > > + str r12, [r1] @ !turn = cpu
> > > > +1: dsb
> > > > + ldr r12, [r3]
> > > > + cmp r12, #1 @ flag[!cpu] == 1?
> > > > + ldreq r12, [r1]
> > > > + cmpeq r12, r0 @ !turn == cpu?
> > > > + beq 1b @ while !turn == cpu && flag[!cpu] == 1
> > > > +
> > > > + mov pc, lr @ locked
> > > > +ENDPROC(tegra_pen_lock)
> > > > +
> > > > +ENTRY(tegra_pen_unlock)
> > > > + dsb
> > > > + mov32 r3, TEGRA_PMC_VIRT
> > > > + cpu_id r0
> > > > + cmp r0, #0
> > > > + addeq r2, r3, #PMC_SCRATCH38
> > > > + addne r2, r3, #PMC_SCRATCH39
> > > > + mov r12, #0
> > > > + str r12, [r2]
> > > > + mov pc, lr
> > > > +ENDPROC(tegra_pen_unlock)
> > >
> > > There is an ongoing work to make this locking scheme for MMU/coherency off
> > > paths ARM generic, and we do not want to merge yet another platform specific
> > > locking mechanism. I will point you to the patchset when it hits LAK.
> > >
> >
> > You did mention there is an ARM generic locking scheme for MMU/coherency
> > off case before. Do you mean the patch below?
> >
> > https://patchwork.kernel.org/patch/1957911/
> > https://patchwork.kernel.org/patch/1957901/
>
> Those are used for first-man election when multiple CPUs come out of
> idle at once.
>
> You should have a look at the entire series and in particular:
>
> https://patchwork.kernel.org/patch/1957891/
> https://patchwork.kernel.org/patch/1957951/
>
> > I gave it a review today. Looks it can't fit our usage for CPU idle
> > powered-down mode on Tegra20.
> >
> > The generic mechanism only can be used when CPUs in non coherent world.
> > But our usage needs the mechanism could be used in both coherent and non
> > coherent case. OK. The case is we need to sync the status about the CPU1
> > was ready to power down. In this case, the CPU0 is still in coherent
> > world but the CPU1 isn't. So we need the locking scheme could be still
> > safe in this situation.
>
> I know, I implemented something of that sort for an A9 based development
> platform, that's why I pointed you to this new patchset.
>
> Have a look at the series, it should do what you want.
>
Hi Lorenzo,
May I upstream this stuff first? I can promise to you I will re-work a
common CPUs and cluster power sync wrappers (platform_power_ops) for all
Tegra series that based on the generic framework. Because we didn't have
this work in Tegra tree yet and we indeed need it for supporting cluster
power down and switching.
But it need lots of time for re-work, testing and verification. And I
have lots of patches that need the function of cpu suspend that be
introduced in this patch series to support platform suspend for Tegra.
So I am asking the permission here for upstream this series first and I
will continue the job to come out a common CPUs and cluster power sync
wrappers for Tegra that we indeed need it to support cluster power down
and switching.
Thanks,
Joseph
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2013-01-15 3:00 ` Joseph Lo
@ 2013-01-15 11:34 ` Lorenzo Pieralisi
2013-01-16 3:17 ` Joseph Lo
0 siblings, 1 reply; 27+ messages in thread
From: Lorenzo Pieralisi @ 2013-01-15 11:34 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 15, 2013 at 03:00:44AM +0000, Joseph Lo wrote:
> On Fri, 2013-01-11 at 20:24 +0800, Lorenzo Pieralisi wrote:
> > On Fri, Jan 11, 2013 at 07:20:29AM +0000, Joseph Lo wrote:
> > > On Wed, 2012-12-05 at 18:50 +0800, Lorenzo Pieralisi wrote:
> > > > On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:
> > > > > The powered-down state of Tegra20 requires power gating both CPU cores.
> > > > > When the secondary CPU requests to enter powered-down state, it saves
> > > > > its own contexts and then enters WFI. The Tegra20 had a limition to
> > > > > power down both CPU cores. The secondary CPU must waits for CPU0 in
> > > > > powered-down state too. If the secondary CPU be woken up before CPU0
> > > > > entering powered-down state, then it needs to restore its CPU states
> > > > > and waits for next chance.
> > > > >
> > > > > Be aware of that, you may see the legacy power state "LP2" in the code
> > > > > which is exactly the same meaning of "CPU power down".
> > > > >
> > > > > Based on the work by:
> > > > > Colin Cross <ccross@android.com>
> > > > > Gary King <gking@nvidia.com>
> > > > >
> > > > > Signed-off-by: Joseph Lo <josephl@nvidia.com>
> > > > > +
> > > > > +#ifdef CONFIG_PM_SLEEP
> > > > > +/*
> > > > > + * tegra_pen_lock
> > > > > + *
> > > > > + * spinlock implementation with no atomic test-and-set and no coherence
> > > > > + * using Peterson's algorithm on strongly-ordered registers
> > > > > + * used to synchronize a cpu waking up from wfi with entering lp2 on idle
> > > > > + *
> > > > > + * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
> > > > > + * on cpu 0:
> > > > > + * SCRATCH38 = r2 = flag[0]
> > > > > + * SCRATCH39 = r3 = flag[1]
> > > > > + * on cpu1:
> > > > > + * SCRATCH39 = r2 = flag[1]
> > > > > + * SCRATCH38 = r3 = flag[0]
> > > > > + *
> > > > > + * must be called with MMU on
> > > > > + * corrupts r0-r3, r12
> > > > > + */
> > > > > +ENTRY(tegra_pen_lock)
> > > > > + mov32 r3, TEGRA_PMC_VIRT
> > > > > + cpu_id r0
> > > > > + add r1, r3, #PMC_SCRATCH37
> > > > > + cmp r0, #0
> > > > > + addeq r2, r3, #PMC_SCRATCH38
> > > > > + addeq r3, r3, #PMC_SCRATCH39
> > > > > + addne r2, r3, #PMC_SCRATCH39
> > > > > + addne r3, r3, #PMC_SCRATCH38
> > > > > +
> > > > > + mov r12, #1
> > > > > + str r12, [r2] @ flag[cpu] = 1
> > > > > + dsb
> > > > > + str r12, [r1] @ !turn = cpu
> > > > > +1: dsb
> > > > > + ldr r12, [r3]
> > > > > + cmp r12, #1 @ flag[!cpu] == 1?
> > > > > + ldreq r12, [r1]
> > > > > + cmpeq r12, r0 @ !turn == cpu?
> > > > > + beq 1b @ while !turn == cpu && flag[!cpu] == 1
> > > > > +
> > > > > + mov pc, lr @ locked
> > > > > +ENDPROC(tegra_pen_lock)
> > > > > +
> > > > > +ENTRY(tegra_pen_unlock)
> > > > > + dsb
> > > > > + mov32 r3, TEGRA_PMC_VIRT
> > > > > + cpu_id r0
> > > > > + cmp r0, #0
> > > > > + addeq r2, r3, #PMC_SCRATCH38
> > > > > + addne r2, r3, #PMC_SCRATCH39
> > > > > + mov r12, #0
> > > > > + str r12, [r2]
> > > > > + mov pc, lr
> > > > > +ENDPROC(tegra_pen_unlock)
> > > >
> > > > There is an ongoing work to make this locking scheme for MMU/coherency off
> > > > paths ARM generic, and we do not want to merge yet another platform specific
> > > > locking mechanism. I will point you to the patchset when it hits LAK.
> > > >
> > >
> > > You did mention there is an ARM generic locking scheme for MMU/coherency
> > > off case before. Do you mean the patch below?
> > >
> > > https://patchwork.kernel.org/patch/1957911/
> > > https://patchwork.kernel.org/patch/1957901/
> >
> > Those are used for first-man election when multiple CPUs come out of
> > idle at once.
> >
> > You should have a look at the entire series and in particular:
> >
> > https://patchwork.kernel.org/patch/1957891/
> > https://patchwork.kernel.org/patch/1957951/
> >
> > > I gave it a review today. Looks it can't fit our usage for CPU idle
> > > powered-down mode on Tegra20.
> > >
> > > The generic mechanism only can be used when CPUs in non coherent world.
> > > But our usage needs the mechanism could be used in both coherent and non
> > > coherent case. OK. The case is we need to sync the status about the CPU1
> > > was ready to power down. In this case, the CPU0 is still in coherent
> > > world but the CPU1 isn't. So we need the locking scheme could be still
> > > safe in this situation.
> >
> > I know, I implemented something of that sort for an A9 based development
> > platform, that's why I pointed you to this new patchset.
> >
> > Have a look at the series, it should do what you want.
> >
> Hi Lorenzo,
>
> May I upstream this stuff first? I can promise to you I will re-work a
> common CPUs and cluster power sync wrappers (platform_power_ops) for all
> Tegra series that based on the generic framework. Because we didn't have
> this work in Tegra tree yet and we indeed need it for supporting cluster
> power down and switching.
>
> But it need lots of time for re-work, testing and verification. And I
> have lots of patches that need the function of cpu suspend that be
> introduced in this patch series to support platform suspend for Tegra.
>
> So I am asking the permission here for upstream this series first and I
> will continue the job to come out a common CPUs and cluster power sync
> wrappers for Tegra that we indeed need it to support cluster power down
> and switching.
I understand that and you should not ask me permission :-) since I am
not a maintainer. I just wanted to save you some effort, you will end
up rewriting the whole thing anyway IMHO and I think the power API would
have saved you time if it were there before.
Again, it is not my call, I am more than happy to review your code but
that's all I can do.
If you need help to integrate the power API please do ask questions.
Lorenzo
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2013-01-15 11:34 ` Lorenzo Pieralisi
@ 2013-01-16 3:17 ` Joseph Lo
0 siblings, 0 replies; 27+ messages in thread
From: Joseph Lo @ 2013-01-16 3:17 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 2013-01-15 at 19:34 +0800, Lorenzo Pieralisi wrote:
> On Tue, Jan 15, 2013 at 03:00:44AM +0000, Joseph Lo wrote:
> > On Fri, 2013-01-11 at 20:24 +0800, Lorenzo Pieralisi wrote:
> > > On Fri, Jan 11, 2013 at 07:20:29AM +0000, Joseph Lo wrote:
> > > > On Wed, 2012-12-05 at 18:50 +0800, Lorenzo Pieralisi wrote:
> > > > > On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:
> > > > You did mention there is an ARM generic locking scheme for MMU/coherency
> > > > off case before. Do you mean the patch below?
> > > >
> > > > https://patchwork.kernel.org/patch/1957911/
> > > > https://patchwork.kernel.org/patch/1957901/
> > >
> > > Those are used for first-man election when multiple CPUs come out of
> > > idle at once.
> > >
> > > You should have a look at the entire series and in particular:
> > >
> > > https://patchwork.kernel.org/patch/1957891/
> > > https://patchwork.kernel.org/patch/1957951/
> > >
> > > > I gave it a review today. Looks it can't fit our usage for CPU idle
> > > > powered-down mode on Tegra20.
> > > >
> > > > The generic mechanism only can be used when CPUs in non coherent world.
> > > > But our usage needs the mechanism could be used in both coherent and non
> > > > coherent case. OK. The case is we need to sync the status about the CPU1
> > > > was ready to power down. In this case, the CPU0 is still in coherent
> > > > world but the CPU1 isn't. So we need the locking scheme could be still
> > > > safe in this situation.
> > >
> > > I know, I implemented something of that sort for an A9 based development
> > > platform, that's why I pointed you to this new patchset.
> > >
> > > Have a look at the series, it should do what you want.
> > >
> > Hi Lorenzo,
> >
> > May I upstream this stuff first? I can promise to you I will re-work a
> > common CPUs and cluster power sync wrappers (platform_power_ops) for all
> > Tegra series that based on the generic framework. Because we didn't have
> > this work in Tegra tree yet and we indeed need it for supporting cluster
> > power down and switching.
> >
> > But it need lots of time for re-work, testing and verification. And I
> > have lots of patches that need the function of cpu suspend that be
> > introduced in this patch series to support platform suspend for Tegra.
> >
> > So I am asking the permission here for upstream this series first and I
> > will continue the job to come out a common CPUs and cluster power sync
> > wrappers for Tegra that we indeed need it to support cluster power down
> > and switching.
>
> I understand that and you should not ask me permission :-) since I am
> not a maintainer. I just wanted to save you some effort, you will end
> up rewriting the whole thing anyway IMHO and I think the power API would
> have saved you time if it were there before.
>
I think we are always taking care the comments from the community. And
it's really worth for us to reconsider the code design and re-use the
common framework to reduce the effort.
>
> If you need help to integrate the power API please do ask questions.
>
Thanks again.
Joseph
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2013-01-11 7:20 ` Joseph Lo
2013-01-11 12:24 ` Lorenzo Pieralisi
@ 2013-01-12 17:33 ` Nicolas Pitre
1 sibling, 0 replies; 27+ messages in thread
From: Nicolas Pitre @ 2013-01-12 17:33 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 11 Jan 2013, Joseph Lo wrote:
> Hi Lorenzo,
>
> On Wed, 2012-12-05 at 18:50 +0800, Lorenzo Pieralisi wrote:
> > On Wed, Dec 05, 2012 at 10:01:49AM +0000, Joseph Lo wrote:
> > > The powered-down state of Tegra20 requires power gating both CPU cores.
> > > When the secondary CPU requests to enter powered-down state, it saves
> > > its own contexts and then enters WFI. The Tegra20 had a limition to
> > > power down both CPU cores. The secondary CPU must waits for CPU0 in
> > > powered-down state too. If the secondary CPU be woken up before CPU0
> > > entering powered-down state, then it needs to restore its CPU states
> > > and waits for next chance.
> > >
> > > Be aware of that, you may see the legacy power state "LP2" in the code
> > > which is exactly the same meaning of "CPU power down".
> > >
> > > Based on the work by:
> > > Colin Cross <ccross@android.com>
> > > Gary King <gking@nvidia.com>
> > >
> > > Signed-off-by: Joseph Lo <josephl@nvidia.com>
> > > +
> > > +#ifdef CONFIG_PM_SLEEP
> > > +/*
> > > + * tegra_pen_lock
> > > + *
> > > + * spinlock implementation with no atomic test-and-set and no coherence
> > > + * using Peterson's algorithm on strongly-ordered registers
> > > + * used to synchronize a cpu waking up from wfi with entering lp2 on idle
> > > + *
> > > + * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
> > > + * on cpu 0:
> > > + * SCRATCH38 = r2 = flag[0]
> > > + * SCRATCH39 = r3 = flag[1]
> > > + * on cpu1:
> > > + * SCRATCH39 = r2 = flag[1]
> > > + * SCRATCH38 = r3 = flag[0]
> > > + *
> > > + * must be called with MMU on
> > > + * corrupts r0-r3, r12
> > > + */
> > > +ENTRY(tegra_pen_lock)
> > > + mov32 r3, TEGRA_PMC_VIRT
> > > + cpu_id r0
> > > + add r1, r3, #PMC_SCRATCH37
> > > + cmp r0, #0
> > > + addeq r2, r3, #PMC_SCRATCH38
> > > + addeq r3, r3, #PMC_SCRATCH39
> > > + addne r2, r3, #PMC_SCRATCH39
> > > + addne r3, r3, #PMC_SCRATCH38
> > > +
> > > + mov r12, #1
> > > + str r12, [r2] @ flag[cpu] = 1
> > > + dsb
> > > + str r12, [r1] @ !turn = cpu
> > > +1: dsb
> > > + ldr r12, [r3]
> > > + cmp r12, #1 @ flag[!cpu] == 1?
> > > + ldreq r12, [r1]
> > > + cmpeq r12, r0 @ !turn == cpu?
> > > + beq 1b @ while !turn == cpu && flag[!cpu] == 1
> > > +
> > > + mov pc, lr @ locked
> > > +ENDPROC(tegra_pen_lock)
> > > +
> > > +ENTRY(tegra_pen_unlock)
> > > + dsb
> > > + mov32 r3, TEGRA_PMC_VIRT
> > > + cpu_id r0
> > > + cmp r0, #0
> > > + addeq r2, r3, #PMC_SCRATCH38
> > > + addne r2, r3, #PMC_SCRATCH39
> > > + mov r12, #0
> > > + str r12, [r2]
> > > + mov pc, lr
> > > +ENDPROC(tegra_pen_unlock)
> >
> > There is an ongoing work to make this locking scheme for MMU/coherency off
> > paths ARM generic, and we do not want to merge yet another platform specific
> > locking mechanism. I will point you to the patchset when it hits LAK.
> >
>
> You did mention there is an ARM generic locking scheme for MMU/coherency
> off case before. Do you mean the patch below?
>
> https://patchwork.kernel.org/patch/1957911/
> https://patchwork.kernel.org/patch/1957901/
>
> I gave it a review today. Looks it can't fit our usage for CPU idle
> powered-down mode on Tegra20.
>
> The generic mechanism only can be used when CPUs in non coherent world.
> But our usage needs the mechanism could be used in both coherent and non
> coherent case. OK. The case is we need to sync the status about the CPU1
> was ready to power down. In this case, the CPU0 is still in coherent
> world but the CPU1 isn't. So we need the locking scheme could be still
> safe in this situation.
Those patches above are dealing with CPUs coming back up. If you look
at the rest of the series, especially the DCSCB one providing real usage
example, you'll see that we do have a mix of coherent and non-coherent
states that need to coordinate amongst themselves.
> And the proposed scheme looks only for b.L system?
It was initiated for b.L hence the name, but that is applicable to other
systems as well.
Nicolas
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2012-12-05 10:01 ` [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU Joseph Lo
2012-12-05 10:50 ` Lorenzo Pieralisi
@ 2012-12-05 22:18 ` Stephen Warren
2012-12-06 7:22 ` Joseph Lo
1 sibling, 1 reply; 27+ messages in thread
From: Stephen Warren @ 2012-12-05 22:18 UTC (permalink / raw)
To: linux-arm-kernel
On 12/05/2012 03:01 AM, Joseph Lo wrote:
> The powered-down state of Tegra20 requires power gating both CPU cores.
> When the secondary CPU requests to enter powered-down state, it saves
> its own contexts and then enters WFI. The Tegra20 had a limition to
> power down both CPU cores. The secondary CPU must waits for CPU0 in
> powered-down state too. If the secondary CPU be woken up before CPU0
> entering powered-down state, then it needs to restore its CPU states
> and waits for next chance.
>
> Be aware of that, you may see the legacy power state "LP2" in the code
> which is exactly the same meaning of "CPU power down".
> diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
> +static int __cpuinit tegra20_idle_lp2(struct cpuidle_device *dev,
> + return (entered_lp2) ? index : 0;
No need for the brackets there.
BTW, could you Cc Colin Cross on any future revisions of these patches;
it'd be good to get his take on them.
> diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
> +/*
> + * tegra_pen_lock
> + * on cpu 0:
> + * SCRATCH38 = r2 = flag[0]
> + * SCRATCH39 = r3 = flag[1]
It would be slightly clearer if that was written:
* r2 = flag[0] (in SCRATCH38)
* r3 = flag[1] (in SCRATCH39)
since the meaning of r2/r3 is what's being selected.
> + mov r12, #1
> + str r12, [r2] @ flag[cpu] = 1
> + dsb
> + str r12, [r1] @ !turn = cpu
Should that be "str r0, [r1]"? Otherwise, you're always writing 1 there,
not writing the CPU ID as expected.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2012-12-05 22:18 ` Stephen Warren
@ 2012-12-06 7:22 ` Joseph Lo
2012-12-06 18:59 ` Stephen Warren
0 siblings, 1 reply; 27+ messages in thread
From: Joseph Lo @ 2012-12-06 7:22 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2012-12-06 at 06:18 +0800, Stephen Warren wrote:
> On 12/05/2012 03:01 AM, Joseph Lo wrote:
> > The powered-down state of Tegra20 requires power gating both CPU cores.
> > When the secondary CPU requests to enter powered-down state, it saves
> > its own contexts and then enters WFI. The Tegra20 had a limition to
> > power down both CPU cores. The secondary CPU must waits for CPU0 in
> > powered-down state too. If the secondary CPU be woken up before CPU0
> > entering powered-down state, then it needs to restore its CPU states
> > and waits for next chance.
> >
> > Be aware of that, you may see the legacy power state "LP2" in the code
> > which is exactly the same meaning of "CPU power down".
>
> > diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
>
> > +static int __cpuinit tegra20_idle_lp2(struct cpuidle_device *dev,
>
> > + return (entered_lp2) ? index : 0;
>
> No need for the brackets there.
>
OK. Will fix.
> BTW, could you Cc Colin Cross on any future revisions of these patches;
> it'd be good to get his take on them.
>
OK. The next version will directly support coupled cpuidle. I will add
Colin into Cc.
> > diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
>
> > +/*
> > + * tegra_pen_lock
>
> > + * on cpu 0:
> > + * SCRATCH38 = r2 = flag[0]
> > + * SCRATCH39 = r3 = flag[1]
>
> It would be slightly clearer if that was written:
>
> * r2 = flag[0] (in SCRATCH38)
> * r3 = flag[1] (in SCRATCH39)
>
> since the meaning of r2/r3 is what's being selected.
>
OK. Will fix.
> > + mov r12, #1
> > + str r12, [r2] @ flag[cpu] = 1
> > + dsb
> > + str r12, [r1] @ !turn = cpu
>
> Should that be "str r0, [r1]"? Otherwise, you're always writing 1 there,
> not writing the CPU ID as expected.
The CPU_ID was not used to lock or un-lock the flag. Wriging 1 to lock
and 0 to release.
Thanks,
Joseph
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU
2012-12-06 7:22 ` Joseph Lo
@ 2012-12-06 18:59 ` Stephen Warren
0 siblings, 0 replies; 27+ messages in thread
From: Stephen Warren @ 2012-12-06 18:59 UTC (permalink / raw)
To: linux-arm-kernel
On 12/06/2012 12:22 AM, Joseph Lo wrote:
> On Thu, 2012-12-06 at 06:18 +0800, Stephen Warren wrote:
>> On 12/05/2012 03:01 AM, Joseph Lo wrote:
>>> The powered-down state of Tegra20 requires power gating both CPU cores.
>>> When the secondary CPU requests to enter powered-down state, it saves
>>> its own contexts and then enters WFI. The Tegra20 had a limition to
>>> power down both CPU cores. The secondary CPU must waits for CPU0 in
>>> powered-down state too. If the secondary CPU be woken up before CPU0
>>> entering powered-down state, then it needs to restore its CPU states
>>> and waits for next chance.
>>>
>>> Be aware of that, you may see the legacy power state "LP2" in the code
>>> which is exactly the same meaning of "CPU power down".
>>> diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
>>
>>> +/*
>>> + * tegra_pen_lock
>>
>>> + * on cpu 0:
>>> + * SCRATCH38 = r2 = flag[0]
>>> + * SCRATCH39 = r3 = flag[1]
>>
>> It would be slightly clearer if that was written:
>>
>> * r2 = flag[0] (in SCRATCH38)
>> * r3 = flag[1] (in SCRATCH39)
>>
>> since the meaning of r2/r3 is what's being selected.
>>
> OK. Will fix.
>
>>> + mov r12, #1
>>> + str r12, [r2] @ flag[cpu] = 1
So here I can see we should hard-code the value that's written
>>> + dsb
>>> + str r12, [r1] @ !turn = cpu
But here we're also writing "1" always, whereas the comment says it's
writing "cpu", and given the algorithm description, I would expect to
write "cpu" here not "1".
>> Should that be "str r0, [r1]"? Otherwise, you're always writing 1 there,
>> not writing the CPU ID as expected.
>
> The CPU_ID was not used to lock or un-lock the flag. Wriging 1 to lock
> and 0 to release.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 3/6] ARM: tegra20: clocks: add CPU low-power function into tegra_cpu_car_ops
2012-12-05 10:01 [PATCH V2 0/6] ARM: tegra20: cpuidle: add power-down state Joseph Lo
2012-12-05 10:01 ` [PATCH V2 1/6] ARM: tegra: add pending SGI checking API Joseph Lo
2012-12-05 10:01 ` [PATCH V2 2/6] ARM: tegra20: cpuidle: add powered-down state for secondary CPU Joseph Lo
@ 2012-12-05 10:01 ` Joseph Lo
2012-12-05 10:01 ` [PATCH V2 4/6] ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit Joseph Lo
` (4 subsequent siblings)
7 siblings, 0 replies; 27+ messages in thread
From: Joseph Lo @ 2012-12-05 10:01 UTC (permalink / raw)
To: linux-arm-kernel
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* refine the code sequence in "tegra20_cpu_rail_off_ready"
---
arch/arm/mach-tegra/tegra20_clocks.c | 99 ++++++++++++++++++++++++++++++++++
1 files changed, 99 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index 4eb6bc8..1780268 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -159,6 +159,31 @@
#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
#define CPU_RESET(cpu) (0x1111ul << (cpu))
+#define CLK_RESET_CCLK_BURST 0x20
+#define CLK_RESET_CCLK_DIVIDER 0x24
+#define CLK_RESET_PLLX_BASE 0xe0
+#define CLK_RESET_PLLX_MISC 0xe4
+
+#define CLK_RESET_SOURCE_CSITE 0x1d4
+
+#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
+#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
+#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
+#define CLK_RESET_CCLK_IDLE_POLICY 1
+#define CLK_RESET_CCLK_RUN_POLICY 2
+#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
+
+#ifdef CONFIG_PM_SLEEP
+static struct cpu_clk_suspend_context {
+ u32 pllx_misc;
+ u32 pllx_base;
+
+ u32 cpu_burst;
+ u32 clk_csite_src;
+ u32 cclk_divider;
+} tegra20_cpu_clk_sctx;
+#endif
+
static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
@@ -1609,12 +1634,86 @@ static void tegra20_disable_cpu_clock(u32 cpu)
reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
}
+#ifdef CONFIG_PM_SLEEP
+static bool tegra20_cpu_rail_off_ready(void)
+{
+ unsigned int cpu_rst_status;
+
+ cpu_rst_status = readl(reg_clk_base +
+ TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+
+ return !!(cpu_rst_status & 0x2);
+}
+
+static void tegra20_cpu_clock_suspend(void)
+{
+ /* switch coresite to clk_m, save off original source */
+ tegra20_cpu_clk_sctx.clk_csite_src =
+ readl(reg_clk_base + CLK_RESET_SOURCE_CSITE);
+ writel(3<<30, reg_clk_base + CLK_RESET_SOURCE_CSITE);
+
+ tegra20_cpu_clk_sctx.cpu_burst =
+ readl(reg_clk_base + CLK_RESET_CCLK_BURST);
+ tegra20_cpu_clk_sctx.pllx_base =
+ readl(reg_clk_base + CLK_RESET_PLLX_BASE);
+ tegra20_cpu_clk_sctx.pllx_misc =
+ readl(reg_clk_base + CLK_RESET_PLLX_MISC);
+ tegra20_cpu_clk_sctx.cclk_divider =
+ readl(reg_clk_base + CLK_RESET_CCLK_DIVIDER);
+}
+
+static void tegra20_cpu_clock_resume(void)
+{
+ unsigned int reg, policy;
+
+ /* Is CPU complex already running on PLLX? */
+ reg = readl(reg_clk_base + CLK_RESET_CCLK_BURST);
+ policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
+
+ if (policy == CLK_RESET_CCLK_IDLE_POLICY)
+ reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
+ else if (policy == CLK_RESET_CCLK_RUN_POLICY)
+ reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
+ else
+ BUG();
+
+ if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
+ /* restore PLLX settings if CPU is on different PLL */
+ writel(tegra20_cpu_clk_sctx.pllx_misc,
+ reg_clk_base + CLK_RESET_PLLX_MISC);
+ writel(tegra20_cpu_clk_sctx.pllx_base,
+ reg_clk_base + CLK_RESET_PLLX_BASE);
+
+ /* wait for PLL stabilization if PLLX was enabled */
+ if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
+ udelay(300);
+ }
+
+ /*
+ * Restore original burst policy setting for calls resulting from CPU
+ * LP2 in idle or system suspend.
+ */
+ writel(tegra20_cpu_clk_sctx.cclk_divider,
+ reg_clk_base + CLK_RESET_CCLK_DIVIDER);
+ writel(tegra20_cpu_clk_sctx.cpu_burst,
+ reg_clk_base + CLK_RESET_CCLK_BURST);
+
+ writel(tegra20_cpu_clk_sctx.clk_csite_src,
+ reg_clk_base + CLK_RESET_SOURCE_CSITE);
+}
+#endif
+
static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
.wait_for_reset = tegra20_wait_cpu_in_reset,
.put_in_reset = tegra20_put_cpu_in_reset,
.out_of_reset = tegra20_cpu_out_of_reset,
.enable_clock = tegra20_enable_cpu_clock,
.disable_clock = tegra20_disable_cpu_clock,
+#ifdef CONFIG_PM_SLEEP
+ .rail_off_ready = tegra20_cpu_rail_off_ready,
+ .suspend = tegra20_cpu_clock_suspend,
+ .resume = tegra20_cpu_clock_resume,
+#endif
};
void __init tegra20_cpu_car_ops_init(void)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V2 4/6] ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit
2012-12-05 10:01 [PATCH V2 0/6] ARM: tegra20: cpuidle: add power-down state Joseph Lo
` (2 preceding siblings ...)
2012-12-05 10:01 ` [PATCH V2 3/6] ARM: tegra20: clocks: add CPU low-power function into tegra_cpu_car_ops Joseph Lo
@ 2012-12-05 10:01 ` Joseph Lo
2012-12-05 10:01 ` [PATCH V2 5/6] ARM: tegra20: cpuidle: add powered-down state for CPU0 Joseph Lo
` (3 subsequent siblings)
7 siblings, 0 replies; 27+ messages in thread
From: Joseph Lo @ 2012-12-05 10:01 UTC (permalink / raw)
To: linux-arm-kernel
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* no change
---
arch/arm/mach-tegra/flowctrl.c | 38 +++++++++++++++++++++++++++++++++-----
arch/arm/mach-tegra/flowctrl.h | 4 ++++
2 files changed, 37 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index a2250dd..9c44788 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -25,6 +25,7 @@
#include "flowctrl.h"
#include "iomap.h"
+#include "fuse.h"
u8 flowctrl_offset_halt_cpu[] = {
FLOW_CTRL_HALT_CPU0_EVENTS,
@@ -75,11 +76,26 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
int i;
reg = flowctrl_read_cpu_csr(cpuid);
- reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
- reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
+ switch (tegra_chip_id) {
+ case TEGRA20:
+ /* clear wfe bitmap */
+ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
+ /* clear wfi bitmap */
+ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
+ /* pwr gating on wfe */
+ reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
+ break;
+ case TEGRA30:
+ /* clear wfe bitmap */
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
+ /* clear wfi bitmap */
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
+ /* pwr gating on wfi */
+ reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
+ break;
+ }
reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
- reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; /* pwr gating on wfi */
reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
flowctrl_write_cpu_csr(cpuid, reg);
@@ -99,8 +115,20 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
/* Disable powergating via flow controller for CPU0 */
reg = flowctrl_read_cpu_csr(cpuid);
- reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
- reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
+ switch (tegra_chip_id) {
+ case TEGRA20:
+ /* clear wfe bitmap */
+ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
+ /* clear wfi bitmap */
+ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
+ break;
+ case TEGRA30:
+ /* clear wfe bitmap */
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
+ /* clear wfi bitmap */
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
+ break;
+ }
reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 0798dec..67eab56 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -34,6 +34,10 @@
#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
#define FLOW_CTRL_CPU1_CSR 0x18
+#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
+#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
+#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0
+
#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V2 5/6] ARM: tegra20: cpuidle: add powered-down state for CPU0
2012-12-05 10:01 [PATCH V2 0/6] ARM: tegra20: cpuidle: add power-down state Joseph Lo
` (3 preceding siblings ...)
2012-12-05 10:01 ` [PATCH V2 4/6] ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit Joseph Lo
@ 2012-12-05 10:01 ` Joseph Lo
2012-12-05 10:01 ` [PATCH V2 6/6] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode Joseph Lo
` (2 subsequent siblings)
7 siblings, 0 replies; 27+ messages in thread
From: Joseph Lo @ 2012-12-05 10:01 UTC (permalink / raw)
To: linux-arm-kernel
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI for waiting CPU0 in the same state.
When the CPU0 requests powered-down state, it attempts to put the secondary
CPU into reset to prevent it from waking up. Then power down both CPUs
together and power off the cpu rail.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* refine the cpu control function that dedicate for CPU_1
* rename "tegra_cpu_pllp" to "tegra_switch_cpu_to_pllp"
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 103 +++++++++++++++++++++++++++++++-
arch/arm/mach-tegra/sleep-tegra20.S | 53 +++++++++++++++++
arch/arm/mach-tegra/sleep.S | 19 ++++++
arch/arm/mach-tegra/sleep.h | 3 +
4 files changed, 174 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 9d59a46..a83a53b 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -32,6 +32,9 @@
#include "pm.h"
#include "sleep.h"
+#include "iomap.h"
+#include "tegra_cpu_car.h"
+#include "flowctrl.h"
#ifdef CONFIG_PM_SLEEP
static int tegra20_idle_lp2(struct cpuidle_device *dev,
@@ -68,6 +71,88 @@ static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
#ifdef CONFIG_PM_SLEEP
#ifdef CONFIG_SMP
+static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+
+static int tegra20_reset_sleeping_cpu_1(void)
+{
+ int ret = 0;
+
+ tegra_pen_lock();
+
+ if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
+ tegra20_cpu_shutdown(1);
+ else
+ ret = -EINVAL;
+
+ tegra_pen_unlock();
+
+ return ret;
+}
+
+static void tegra20_wake_reset_cpu_1(void)
+{
+ tegra_pen_lock();
+
+ tegra20_cpu_clear_resettable();
+
+ /* enable cpu clock on cpu */
+ tegra_enable_cpu_clock(1);
+
+ /* take the CPU out of reset */
+ tegra_cpu_out_of_reset(1);
+
+ /* unhalt the cpu */
+ flowctrl_write_cpu_halt(1, 0);
+
+ tegra_pen_unlock();
+}
+
+static int tegra20_reset_cpu_1(void)
+{
+ if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
+ return 0;
+
+ tegra20_wake_reset_cpu_1();
+ return -EBUSY;
+}
+#else
+static inline void tegra20_wake_reset_cpu_1(void)
+{
+}
+
+static inline int tegra20_reset_cpu_1(void)
+{
+ return 0;
+}
+#endif
+
+static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ struct cpuidle_state *state = &drv->states[index];
+ u32 cpu_on_time = state->exit_latency;
+ u32 cpu_off_time = state->target_residency - state->exit_latency;
+
+ while (tegra20_cpu_is_resettable_soon())
+ cpu_relax();
+
+ if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
+ return false;
+
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+
+ tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+
+ if (cpu_online(1))
+ tegra20_wake_reset_cpu_1();
+
+ return true;
+}
+
+#ifdef CONFIG_SMP
static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
@@ -99,16 +184,22 @@ static int __cpuinit tegra20_idle_lp2(struct cpuidle_device *dev,
{
u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
bool entered_lp2 = false;
+ bool last_cpu;
local_fiq_disable();
- tegra_set_cpu_in_lp2(cpu);
+ last_cpu = tegra_set_cpu_in_lp2(cpu);
cpu_pm_enter();
- if (cpu == 0)
- cpu_do_idle();
- else
+ if (cpu == 0) {
+ if (last_cpu)
+ entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv,
+ index);
+ else
+ cpu_do_idle();
+ } else {
entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
+ }
cpu_pm_exit();
tegra_clear_cpu_in_lp2(cpu);
@@ -128,6 +219,10 @@ int __init tegra20_cpuidle_init(void)
struct cpuidle_device *dev;
struct cpuidle_driver *drv = &tegra_idle_driver;
+#ifdef CONFIG_PM_SLEEP
+ tegra_tear_down_cpu = tegra20_tear_down_cpu;
+#endif
+
ret = cpuidle_register_driver(&tegra_idle_driver);
if (ret) {
pr_err("CPUidle driver registration failed\n");
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index dfb2be5..0175ac4 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -60,6 +60,9 @@ ENDPROC(tegra20_hotplug_shutdown)
ENTRY(tegra20_cpu_shutdown)
cmp r0, #0
moveq pc, lr @ must not be called for CPU 0
+ mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+ mov r12, #CPU_RESETTABLE
+ str r12, [r1]
cpu_to_halt_reg r1, r0
ldr r3, =TEGRA_FLOW_CTRL_VIRT
@@ -163,6 +166,21 @@ ENTRY(tegra20_cpu_set_resettable_soon)
ENDPROC(tegra20_cpu_set_resettable_soon)
/*
+ * tegra20_cpu_is_resettable_soon(void)
+ *
+ * Returns true if the "resettable soon" flag in PMC_SCRATCH41 has been
+ * set because it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra20_cpu_is_resettable_soon)
+ mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
+ ldr r12, [r1]
+ cmp r12, #CPU_RESETTABLE_SOON
+ moveq r0, #1
+ movne r0, #0
+ mov pc, lr
+ENDPROC(tegra20_cpu_is_resettable_soon)
+
+/*
* tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
*
* Enters WFI on secondary CPU by exiting coherency.
@@ -222,4 +240,39 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
mov sp, r2 @ sp is stored in r2 by __cpu_suspend
ldmfd sp!, {r4 - r11, pc}
ENDPROC(tegra20_sleep_cpu_secondary_finish)
+
+/*
+ * tegra20_tear_down_cpu
+ *
+ * Switches the CPU cluster to PLL-P and enters sleep.
+ */
+ENTRY(tegra20_tear_down_cpu)
+ bl tegra_switch_cpu_to_pllp
+ b tegra20_enter_sleep
+ENDPROC(tegra20_tear_down_cpu)
+
+/*
+ * tegra20_enter_sleep
+ *
+ * uses flow controller to enter sleep state
+ * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
+ * executes from SDRAM with target state is LP2
+ */
+tegra20_enter_sleep:
+ mov32 r6, TEGRA_FLOW_CTRL_BASE
+
+ mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
+ orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
+ cpu_id r1
+ cpu_to_halt_reg r1, r1
+ str r0, [r6, r1]
+ dsb
+ ldr r0, [r6, r1] /* memory barrier */
+
+halted:
+ dsb
+ wfe /* CPU should be power gated here */
+ isb
+ b halted
+
#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 26afa7c..bbda6e9 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -34,6 +34,9 @@
#include "flowctrl.h"
#include "sleep.h"
+#define CLK_RESET_CCLK_BURST 0x20
+#define CLK_RESET_CCLK_DIVIDER 0x24
+
#ifdef CONFIG_PM_SLEEP
/*
* tegra_disable_clean_inv_dcache
@@ -108,4 +111,20 @@ ENTRY(tegra_shut_off_mmu)
mov pc, r0
ENDPROC(tegra_shut_off_mmu)
.popsection
+
+/*
+ * tegra_switch_cpu_to_pllp
+ *
+ * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp
+ */
+ENTRY(tegra_switch_cpu_to_pllp)
+ /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
+ mov32 r5, TEGRA_CLK_RESET_BASE
+ mov r0, #(2 << 28) @ burst policy = run mode
+ orr r0, r0, #(4 << 4) @ use PLLP in run mode burst
+ str r0, [r5, #CLK_RESET_CCLK_BURST]
+ mov r0, #0
+ str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
+ mov pc, lr
+ENDPROC(tegra_switch_cpu_to_pllp)
#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index a02f71a..4d2b173 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -130,6 +130,8 @@ static inline void tegra20_hotplug_init(void) {}
static inline void tegra30_hotplug_init(void) {}
#endif
+void tegra20_cpu_shutdown(int cpu);
+int tegra20_cpu_is_resettable_soon(void);
void tegra20_cpu_clear_resettable(void);
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
void tegra20_cpu_set_resettable_soon(void);
@@ -138,6 +140,7 @@ static inline void tegra20_cpu_set_resettable_soon(void) {}
#endif
int tegra20_sleep_cpu_secondary_finish(unsigned long);
+void tegra20_tear_down_cpu(void);
int tegra30_sleep_cpu_secondary_finish(unsigned long);
void tegra30_tear_down_cpu(void);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V2 6/6] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
2012-12-05 10:01 [PATCH V2 0/6] ARM: tegra20: cpuidle: add power-down state Joseph Lo
` (4 preceding siblings ...)
2012-12-05 10:01 ` [PATCH V2 5/6] ARM: tegra20: cpuidle: add powered-down state for CPU0 Joseph Lo
@ 2012-12-05 10:01 ` Joseph Lo
2012-12-05 10:01 ` Joseph Lo
2012-12-05 10:01 ` Joseph Lo
7 siblings, 0 replies; 27+ messages in thread
From: Joseph Lo @ 2012-12-05 10:01 UTC (permalink / raw)
To: linux-arm-kernel
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one
core to go into this mode before other core. The coupled cpuidle framework
can help to sync the MPCore to coupled state then go into "powered-down"
idle mode together. The driver can just assume the MPCore come into
"powered-down" mode at the same time. No need to take care if the CPU_0
goes into this mode along and only can put it into safe idle mode (WFI).
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* handling the case of SGI pending before go into "powered-down" idle mode
---
arch/arm/mach-tegra/Kconfig | 1 +
arch/arm/mach-tegra/cpuidle-tegra20.c | 48 ++++++++++++++++++++------------
2 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index e426d1b..e07241a 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -4,6 +4,7 @@ comment "NVIDIA Tegra options"
config ARCH_TEGRA_2x_SOC
bool "Enable support for Tegra20 family"
+ select ARCH_NEEDS_CPU_IDLE_COUPLED
select ARCH_REQUIRE_GPIOLIB
select ARM_ERRATA_720789
select ARM_ERRATA_742230
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index a83a53b..13e3ae4 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -33,13 +33,16 @@
#include "pm.h"
#include "sleep.h"
#include "iomap.h"
+#include "irq.h"
#include "tegra_cpu_car.h"
#include "flowctrl.h"
#ifdef CONFIG_PM_SLEEP
-static int tegra20_idle_lp2(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index);
+static atomic_t abort_flag;
+static atomic_t abort_barrier;
+static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index);
#endif
static struct cpuidle_driver tegra_idle_driver = {
@@ -55,11 +58,12 @@ static struct cpuidle_driver tegra_idle_driver = {
[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
#ifdef CONFIG_PM_SLEEP
[1] = {
- .enter = tegra20_idle_lp2,
+ .enter = tegra20_idle_lp2_coupled,
.exit_latency = 5000,
.target_residency = 10000,
.power_usage = 0,
- .flags = CPUIDLE_FLAG_TIME_VALID,
+ .flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_COUPLED,
.name = "powered-down",
.desc = "CPU power gated",
},
@@ -178,28 +182,33 @@ static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
}
#endif
-static int __cpuinit tegra20_idle_lp2(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
+static int __cpuinit tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
{
u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
bool entered_lp2 = false;
- bool last_cpu;
+
+ if (tegra_pending_sgi())
+ atomic_inc(&abort_flag);
+
+ cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+
+ if (atomic_read(&abort_flag) > 0) {
+ cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+ atomic_set(&abort_flag, 0); /* clean flag for next coming */
+ return -EINTR;
+ }
local_fiq_disable();
- last_cpu = tegra_set_cpu_in_lp2(cpu);
+ tegra_set_cpu_in_lp2(cpu);
cpu_pm_enter();
- if (cpu == 0) {
- if (last_cpu)
- entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv,
- index);
- else
- cpu_do_idle();
- } else {
+ if (cpu == 0)
+ entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
+ else
entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
- }
cpu_pm_exit();
tegra_clear_cpu_in_lp2(cpu);
@@ -232,6 +241,9 @@ int __init tegra20_cpuidle_init(void)
for_each_possible_cpu(cpu) {
dev = &per_cpu(tegra_idle_device, cpu);
dev->cpu = cpu;
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+ dev->coupled_cpus = *cpu_online_mask;
+#endif
dev->state_count = drv->state_count;
ret = cpuidle_register_device(dev);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V2 6/6] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
2012-12-05 10:01 [PATCH V2 0/6] ARM: tegra20: cpuidle: add power-down state Joseph Lo
` (5 preceding siblings ...)
2012-12-05 10:01 ` [PATCH V2 6/6] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode Joseph Lo
@ 2012-12-05 10:01 ` Joseph Lo
2012-12-05 10:10 ` Joseph Lo
2012-12-05 10:01 ` Joseph Lo
7 siblings, 1 reply; 27+ messages in thread
From: Joseph Lo @ 2012-12-05 10:01 UTC (permalink / raw)
To: linux-arm-kernel
return ret;
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 63cb643..32ecdb6 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -71,6 +71,7 @@ struct tegra_gpio_bank {
u32 oe[4];
u32 int_enb[4];
u32 int_lvl[4];
+ u32 wake_enb[4];
#endif
};
@@ -332,6 +333,9 @@ static int tegra_gpio_suspend(struct device *dev)
bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
+
+ /* Enable gpio irq for wake up source */
+ tegra_gpio_writel(bank->wake_enb[p], GPIO_INT_ENB(gpio));
}
}
local_irq_restore(flags);
@@ -341,6 +345,36 @@ static int tegra_gpio_suspend(struct device *dev)
static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+ u8 port, bit, mask;
+ int gpio = d->hwirq;
+
+ if (gpio < 0)
+ return -EIO;
+
+ port = GPIO_PORT(gpio);
+ bit = GPIO_BIT(gpio);
+ mask = BIT(bit);
+
+ if (enable)
+ bank->wake_enb[port] |= mask;
+ else
+ bank->wake_enb[port] &= ~mask;
+
+ return 0;
+}
+
+static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
+{
+ struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+ int ret;
+
+ ret = tegra_gpio_wake_enable(d, enable);
+ if (ret) {
+ pr_err("Failed gpio wake %s for irq=%d error=%d\n",
+ (enable ? "enable" : "disable"), d->irq, ret);
+ return ret;
+ }
+printk(KERN_EMERG "gpio back->irq: %d hwirq: %d irq: %d\n", bank->irq, d->hwirq, d->irq);
return irq_set_irq_wake(bank->irq, enable);
}
#endif
@@ -352,7 +386,7 @@ static struct irq_chip tegra_gpio_irq_chip = {
.irq_unmask = tegra_gpio_irq_unmask,
.irq_set_type = tegra_gpio_irq_set_type,
#ifdef CONFIG_PM_SLEEP
- .irq_set_wake = tegra_gpio_wake_enable,
+ .irq_set_wake = tegra_gpio_irq_set_wake,
#endif
};
diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c
index 79435de..0a14ec0 100644
--- a/drivers/input/keyboard/gpio_keys.c
+++ b/drivers/input/keyboard/gpio_keys.c
@@ -398,7 +398,7 @@ static irqreturn_t gpio_keys_irq_isr(int irq, void *dev_id)
BUG_ON(irq != bdata->irq);
spin_lock_irqsave(&bdata->lock, flags);
-
+printk(KERN_EMERG "key pressed irq %d\n", bdata->irq);
if (!bdata->key_pressed) {
if (bdata->button->wakeup)
pm_wakeup_event(bdata->input->dev.parent, 0);
@@ -809,8 +809,10 @@ static int gpio_keys_suspend(struct device *dev)
if (device_may_wakeup(dev)) {
for (i = 0; i < ddata->pdata->nbuttons; i++) {
struct gpio_button_data *bdata = &ddata->data[i];
- if (bdata->button->wakeup)
+ if (bdata->button->wakeup) {
+printk(KERN_EMERG "gpio-key wake irq:%d\n", bdata->irq);
enable_irq_wake(bdata->irq);
+ }
}
} else {
mutex_lock(&input->mutex);
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V2 6/6] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
2012-12-05 10:01 ` Joseph Lo
@ 2012-12-05 10:10 ` Joseph Lo
2012-12-06 11:03 ` Grant Likely
0 siblings, 1 reply; 27+ messages in thread
From: Joseph Lo @ 2012-12-05 10:10 UTC (permalink / raw)
To: linux-arm-kernel
Sorry, there is something wrong.
Please ignore this mail.
On Wed, 2012-12-05 at 18:01 +0800, Joseph Lo wrote:
> return ret;
> diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
> index 63cb643..32ecdb6 100644
> --- a/drivers/gpio/gpio-tegra.c
> +++ b/drivers/gpio/gpio-tegra.c
> @@ -71,6 +71,7 @@ struct tegra_gpio_bank {
> u32 oe[4];
> u32 int_enb[4];
> u32 int_lvl[4];
> + u32 wake_enb[4];
> #endif
> };
>
> @@ -332,6 +333,9 @@ static int tegra_gpio_suspend(struct device *dev)
> bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
> bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
> bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
> +
> + /* Enable gpio irq for wake up source */
> + tegra_gpio_writel(bank->wake_enb[p], GPIO_INT_ENB(gpio));
> }
> }
> local_irq_restore(flags);
> @@ -341,6 +345,36 @@ static int tegra_gpio_suspend(struct device *dev)
> static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
> {
> struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
> + u8 port, bit, mask;
> + int gpio = d->hwirq;
> +
> + if (gpio < 0)
> + return -EIO;
> +
> + port = GPIO_PORT(gpio);
> + bit = GPIO_BIT(gpio);
> + mask = BIT(bit);
> +
> + if (enable)
> + bank->wake_enb[port] |= mask;
> + else
> + bank->wake_enb[port] &= ~mask;
> +
> + return 0;
> +}
> +
> +static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
> +{
> + struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
> + int ret;
> +
> + ret = tegra_gpio_wake_enable(d, enable);
> + if (ret) {
> + pr_err("Failed gpio wake %s for irq=%d error=%d\n",
> + (enable ? "enable" : "disable"), d->irq, ret);
> + return ret;
> + }
> +printk(KERN_EMERG "gpio back->irq: %d hwirq: %d irq: %d\n", bank->irq, d->hwirq, d->irq);
> return irq_set_irq_wake(bank->irq, enable);
> }
> #endif
> @@ -352,7 +386,7 @@ static struct irq_chip tegra_gpio_irq_chip = {
> .irq_unmask = tegra_gpio_irq_unmask,
> .irq_set_type = tegra_gpio_irq_set_type,
> #ifdef CONFIG_PM_SLEEP
> - .irq_set_wake = tegra_gpio_wake_enable,
> + .irq_set_wake = tegra_gpio_irq_set_wake,
> #endif
> };
>
> diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c
> index 79435de..0a14ec0 100644
> --- a/drivers/input/keyboard/gpio_keys.c
> +++ b/drivers/input/keyboard/gpio_keys.c
> @@ -398,7 +398,7 @@ static irqreturn_t gpio_keys_irq_isr(int irq, void *dev_id)
> BUG_ON(irq != bdata->irq);
>
> spin_lock_irqsave(&bdata->lock, flags);
> -
> +printk(KERN_EMERG "key pressed irq %d\n", bdata->irq);
> if (!bdata->key_pressed) {
> if (bdata->button->wakeup)
> pm_wakeup_event(bdata->input->dev.parent, 0);
> @@ -809,8 +809,10 @@ static int gpio_keys_suspend(struct device *dev)
> if (device_may_wakeup(dev)) {
> for (i = 0; i < ddata->pdata->nbuttons; i++) {
> struct gpio_button_data *bdata = &ddata->data[i];
> - if (bdata->button->wakeup)
> + if (bdata->button->wakeup) {
> +printk(KERN_EMERG "gpio-key wake irq:%d\n", bdata->irq);
> enable_irq_wake(bdata->irq);
> + }
> }
> } else {
> mutex_lock(&input->mutex);
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V2 6/6] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
2012-12-05 10:01 [PATCH V2 0/6] ARM: tegra20: cpuidle: add power-down state Joseph Lo
` (6 preceding siblings ...)
2012-12-05 10:01 ` Joseph Lo
@ 2012-12-05 10:01 ` Joseph Lo
2012-12-05 10:11 ` Joseph Lo
7 siblings, 1 reply; 27+ messages in thread
From: Joseph Lo @ 2012-12-05 10:01 UTC (permalink / raw)
To: linux-arm-kernel
config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
+ select ARCH_NEEDS_CPU_IDLE_COUPLED
select ARCH_REQUIRE_GPIOLIB
select ARM_ERRATA_743622
select ARM_ERRATA_751472
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 5e8cbf5..f880350 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -23,6 +23,7 @@
#include <linux/module.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
+#include <linux/cpumask.h>
#include <linux/clockchips.h>
#include <asm/cpuidle.h>
@@ -30,14 +31,18 @@
#include <asm/suspend.h>
#include <asm/smp_plat.h>
+#include "irq.h"
#include "pm.h"
#include "sleep.h"
#include "tegra_cpu_car.h"
#ifdef CONFIG_PM_SLEEP
-static int tegra30_idle_lp2(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index);
+static bool abort_flag;
+static atomic_t abort_barrier;
+static cpumask_t cpus_out_lp2;
+static int tegra30_idle_lp2_coupled(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index);
#endif
static struct cpuidle_driver tegra_idle_driver = {
@@ -53,11 +58,12 @@ static struct cpuidle_driver tegra_idle_driver = {
[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
#ifdef CONFIG_PM_SLEEP
[1] = {
- .enter = tegra30_idle_lp2,
+ .enter = tegra30_idle_lp2_coupled,
.exit_latency = 2000,
.target_residency = 2200,
.power_usage = 0,
- .flags = CPUIDLE_FLAG_TIME_VALID,
+ .flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_COUPLED,
.name = "powered-down",
.desc = "CPU power gated",
},
@@ -79,8 +85,8 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
/* All CPUs entering LP2 is not working.
* Don't let CPU0 enter LP2 when any secondary CPU is online.
*/
- if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
- cpu_do_idle();
+ if (num_online_cpus() > 1 && !tegra_cpu_rail_off_ready()) {
+// cpu_do_idle();
return false;
}
@@ -94,6 +100,13 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
}
#ifdef CONFIG_SMP
+static void tegra30_wake_up_secondary_cpus(u32 cpu)
+{
+// if (!cpumask_test_cpu(cpu, &cpus_out_lp2))
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+// gic_raise_softirq(cpumask_of(cpu), 0);
+}
+
static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
@@ -113,6 +126,11 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
return true;
}
#else
+static inline void tegra30_wake_up_secondary_cpus(u32 cpu)
+{
+ return;
+}
+
static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
@@ -121,36 +139,56 @@ static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
}
#endif
-static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
+static int __cpuinit tegra30_idle_lp2_coupled(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
{
u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
bool entered_lp2 = false;
- bool last_cpu;
+int i;
+ abort_flag = tegra_pending_irq();
+ cpumask_clear(&cpus_out_lp2);
+ cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+//printk(KERN_EMERG "cpu %d in\n", cpu);
+ if (abort_flag)
+ return -EINTR;
local_fiq_disable();
- last_cpu = tegra_set_cpu_in_lp2(cpu);
+ tegra_set_cpu_in_lp2(cpu);
cpu_pm_enter();
if (cpu == 0) {
- if (last_cpu)
- entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
- index);
- else
- cpu_do_idle();
+ while (num_online_cpus() > 1 && !tegra_cpu_rail_off_ready()) {
+ cpu_relax();
+
+// if (!cpumask_empty(&cpus_out_lp2))
+// goto out;
+ }
+ entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index);
+
+out:
+// if (!entered_lp2) {
+// int i;
+ for_each_online_cpu(i)
+ if (i != cpu)
+ tegra30_wake_up_secondary_cpus(i);
+// }
} else {
entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
+ cpumask_set_cpu(cpu, &cpus_out_lp2);
}
+
cpu_pm_exit();
tegra_clear_cpu_in_lp2(cpu);
-
+//
+//
local_fiq_enable();
smp_rmb();
-
+//printk(KERN_EMERG "cpu %d out\n", cpu);
+cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
return (entered_lp2) ? index : 0;
}
#endif
@@ -175,6 +213,9 @@ int __init tegra30_cpuidle_init(void)
for_each_possible_cpu(cpu) {
dev = &per_cpu(tegra_idle_device, cpu);
dev->cpu = cpu;
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+ dev->coupled_cpus = *cpu_online_mask;
+#endif
dev->state_count = drv->state_count;
ret = cpuidle_register_device(dev);
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V2 6/6] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
2012-12-05 10:01 ` Joseph Lo
@ 2012-12-05 10:11 ` Joseph Lo
0 siblings, 0 replies; 27+ messages in thread
From: Joseph Lo @ 2012-12-05 10:11 UTC (permalink / raw)
To: linux-arm-kernel
Sorry, there is something wrong.
Please ignore this mail.
On Wed, 2012-12-05 at 18:01 +0800, Joseph Lo wrote:
> config ARCH_TEGRA_3x_SOC
> bool "Enable support for Tegra30 family"
> + select ARCH_NEEDS_CPU_IDLE_COUPLED
> select ARCH_REQUIRE_GPIOLIB
> select ARM_ERRATA_743622
> select ARM_ERRATA_751472
> diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
> index 5e8cbf5..f880350 100644
> --- a/arch/arm/mach-tegra/cpuidle-tegra30.c
> +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
> @@ -23,6 +23,7 @@
> #include <linux/module.h>
> #include <linux/cpuidle.h>
> #include <linux/cpu_pm.h>
> +#include <linux/cpumask.h>
> #include <linux/clockchips.h>
>
> #include <asm/cpuidle.h>
> @@ -30,14 +31,18 @@
> #include <asm/suspend.h>
> #include <asm/smp_plat.h>
>
> +#include "irq.h"
> #include "pm.h"
> #include "sleep.h"
> #include "tegra_cpu_car.h"
>
> #ifdef CONFIG_PM_SLEEP
> -static int tegra30_idle_lp2(struct cpuidle_device *dev,
> - struct cpuidle_driver *drv,
> - int index);
> +static bool abort_flag;
> +static atomic_t abort_barrier;
> +static cpumask_t cpus_out_lp2;
> +static int tegra30_idle_lp2_coupled(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv,
> + int index);
> #endif
>
> static struct cpuidle_driver tegra_idle_driver = {
> @@ -53,11 +58,12 @@ static struct cpuidle_driver tegra_idle_driver = {
> [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
> #ifdef CONFIG_PM_SLEEP
> [1] = {
> - .enter = tegra30_idle_lp2,
> + .enter = tegra30_idle_lp2_coupled,
> .exit_latency = 2000,
> .target_residency = 2200,
> .power_usage = 0,
> - .flags = CPUIDLE_FLAG_TIME_VALID,
> + .flags = CPUIDLE_FLAG_TIME_VALID |
> + CPUIDLE_FLAG_COUPLED,
> .name = "powered-down",
> .desc = "CPU power gated",
> },
> @@ -79,8 +85,8 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
> /* All CPUs entering LP2 is not working.
> * Don't let CPU0 enter LP2 when any secondary CPU is online.
> */
> - if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
> - cpu_do_idle();
> + if (num_online_cpus() > 1 && !tegra_cpu_rail_off_ready()) {
> +// cpu_do_idle();
> return false;
> }
>
> @@ -94,6 +100,13 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
> }
>
> #ifdef CONFIG_SMP
> +static void tegra30_wake_up_secondary_cpus(u32 cpu)
> +{
> +// if (!cpumask_test_cpu(cpu, &cpus_out_lp2))
> + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
> +// gic_raise_softirq(cpumask_of(cpu), 0);
> +}
> +
> static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
> struct cpuidle_driver *drv,
> int index)
> @@ -113,6 +126,11 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
> return true;
> }
> #else
> +static inline void tegra30_wake_up_secondary_cpus(u32 cpu)
> +{
> + return;
> +}
> +
> static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
> struct cpuidle_driver *drv,
> int index)
> @@ -121,36 +139,56 @@ static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
> }
> #endif
>
> -static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
> - struct cpuidle_driver *drv,
> - int index)
> +static int __cpuinit tegra30_idle_lp2_coupled(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv,
> + int index)
> {
> u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
> bool entered_lp2 = false;
> - bool last_cpu;
> +int i;
> + abort_flag = tegra_pending_irq();
> + cpumask_clear(&cpus_out_lp2);
> + cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
> +//printk(KERN_EMERG "cpu %d in\n", cpu);
> + if (abort_flag)
> + return -EINTR;
>
> local_fiq_disable();
>
> - last_cpu = tegra_set_cpu_in_lp2(cpu);
> + tegra_set_cpu_in_lp2(cpu);
> cpu_pm_enter();
>
> if (cpu == 0) {
> - if (last_cpu)
> - entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
> - index);
> - else
> - cpu_do_idle();
> + while (num_online_cpus() > 1 && !tegra_cpu_rail_off_ready()) {
> + cpu_relax();
> +
> +// if (!cpumask_empty(&cpus_out_lp2))
> +// goto out;
> + }
> + entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index);
> +
> +out:
> +// if (!entered_lp2) {
> +// int i;
> + for_each_online_cpu(i)
> + if (i != cpu)
> + tegra30_wake_up_secondary_cpus(i);
> +// }
> } else {
> entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
> + cpumask_set_cpu(cpu, &cpus_out_lp2);
> }
>
> +
> cpu_pm_exit();
> tegra_clear_cpu_in_lp2(cpu);
> -
> +//
> +//
> local_fiq_enable();
>
> smp_rmb();
> -
> +//printk(KERN_EMERG "cpu %d out\n", cpu);
> +cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
> return (entered_lp2) ? index : 0;
> }
> #endif
> @@ -175,6 +213,9 @@ int __init tegra30_cpuidle_init(void)
> for_each_possible_cpu(cpu) {
> dev = &per_cpu(tegra_idle_device, cpu);
> dev->cpu = cpu;
> +#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
> + dev->coupled_cpus = *cpu_online_mask;
> +#endif
>
> dev->state_count = drv->state_count;
> ret = cpuidle_register_device(dev);
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 27+ messages in thread