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From: nicolas.pitre@linaro.org (Nicolas Pitre)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 12/16] ARM: vexpress/dcscb: do not hardcode number of CPUs per cluster
Date: Thu, 24 Jan 2013 01:27:55 -0500	[thread overview]
Message-ID: <1359008879-9015-13-git-send-email-nicolas.pitre@linaro.org> (raw)
In-Reply-To: <1359008879-9015-1-git-send-email-nicolas.pitre@linaro.org>

If 4 CPUs are assumed, the A15x1-A7x1 model configuration would never
shut down the initial cluster as the 0xf reset bit mask will never be
observed.  Let's construct this mask based on the provided information
in the DCSCB config register for the number of CPUs per cluster.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
---
 arch/arm/mach-vexpress/dcscb.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index cde9d3a8d2..e61ccce3c5 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -46,10 +46,12 @@ static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 
 static void __iomem *dcscb_base;
 static int dcscb_use_count[4][2];
+static int dcscb_cluster_cpu_mask[2];
 
 static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
 {
 	unsigned int rst_hold, cpumask = (1 << cpu);
+	unsigned int cluster_mask = dcscb_cluster_cpu_mask[cluster];
 
 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
 	if (cpu >= 4 || cluster >= 2)
@@ -68,7 +70,7 @@ static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
 		if (rst_hold & (1 << 8)) {
 			/* remove cluster reset and add individual CPU's reset */
 			rst_hold &= ~(1 << 8);
-			rst_hold |= 0xf;
+			rst_hold |= cluster_mask;
 		}
 		rst_hold &= ~(cpumask | (cpumask << 4));
 		writel(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
@@ -92,13 +94,14 @@ static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
 
 static void dcscb_power_down(void)
 {
-	unsigned int mpidr, cpu, cluster, rst_hold, cpumask;
+	unsigned int mpidr, cpu, cluster, rst_hold, cpumask, cluster_mask;
 	bool last_man = false, skip_wfi = false;
 
 	mpidr = read_cpuid_mpidr();
 	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 	cpumask = (1 << cpu);
+	cluster_mask = dcscb_cluster_cpu_mask[cluster];
 
 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
 	BUG_ON(cpu >= 4 || cluster >= 2);
@@ -108,7 +111,7 @@ static void dcscb_power_down(void)
 	if (dcscb_use_count[cpu][cluster] == 0) {
 		rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
 		rst_hold |= cpumask;
-		if (((rst_hold | (rst_hold >> 4)) & 0xf) == 0xf) {
+		if (((rst_hold | (rst_hold >> 4)) & cluster_mask) == cluster_mask) {
 			rst_hold |= (1 << 8);
 			last_man = true;
 		}
@@ -178,12 +181,15 @@ static void __init dcscb_usage_count_init(void)
 
 static int __init dcscb_init(void)
 {
+	unsigned int cfg;
 	int ret;
 
 	dcscb_base = ioremap(DCSCB_PHYS_BASE, 0x1000);
 	if (!dcscb_base)
 		return -ENOMEM;
-
+	cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
+	dcscb_cluster_cpu_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
+	dcscb_cluster_cpu_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
 	dcscb_usage_count_init();
 
 	ret = bL_platform_power_register(&dcscb_power_ops);
-- 
1.8.0

  parent reply	other threads:[~2013-01-24  6:27 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-01-24  6:27 [PATCH v2 00/16] low-level CPU and cluster power management Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 01/16] ARM: introduce common set_auxcr/get_auxcr functions Nicolas Pitre
2013-01-28 14:39   ` Will Deacon
2013-01-28 15:23     ` Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 02/16] ARM: b.L: secondary kernel entry code Nicolas Pitre
2013-01-28 14:46   ` Will Deacon
2013-01-28 15:07     ` Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 03/16] ARM: b.L: introduce the CPU/cluster power API Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 04/16] ARM: b.L: introduce helpers for platform coherency exit/setup Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 05/16] ARM: b.L: Add baremetal voting mutexes Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 06/16] ARM: bL_head.S: vlock-based first man election Nicolas Pitre
2013-01-28 17:18   ` Will Deacon
2013-01-28 17:58     ` Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 07/16] ARM: b.L: generic SMP secondary bringup and hotplug support Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 08/16] ARM: bL_platsmp.c: close the kernel entry gate before hot-unplugging a CPU Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 09/16] ARM: vexpress: Select the correct SMP operations at run-time Nicolas Pitre
2013-01-24 11:56   ` Jon Medhurst (Tixy)
2013-01-24  6:27 ` [PATCH v2 10/16] ARM: vexpress: introduce DCSCB support Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 11/16] ARM: vexpress/dcscb: add CPU use counts to the power up/down API implementation Nicolas Pitre
2013-01-24  6:27 ` Nicolas Pitre [this message]
2013-01-24  6:27 ` [PATCH v2 13/16] drivers/bus: add ARM CCI support Nicolas Pitre
2013-01-24 21:05   ` saeed bishara
2013-01-24  6:27 ` [PATCH v2 14/16] ARM: CCI: ensure powerdown-time data is flushed from cache Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 15/16] ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI Nicolas Pitre
2013-01-24  6:27 ` [PATCH v2 16/16] ARM: vexpress/dcscb: probe via device tree Nicolas Pitre

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