* [PATCH 0/2] RM9200 EBI write/read interface
@ 2013-02-09 15:54 Joachim Eastwood
2013-02-09 15:54 ` [PATCH 1/2] ARM: at91: create ebi read/write interface for RM9200 Joachim Eastwood
2013-02-09 15:54 ` [PATCH 2/2] ARM: at91: move at91_ramc.h and clean up includes Joachim Eastwood
0 siblings, 2 replies; 5+ messages in thread
From: Joachim Eastwood @ 2013-02-09 15:54 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This patch introduces a EBI (External Bus Interface) read/write
interface for RM9200. This allow to use the real base address
for the SDRAMC on RM9200 and share SDRAMC headers for RM9200
and SAM9.
In the process at91_ramc can now be made private to mach-at91
since the at91_cf driver will use at91_ebi instead.
The ultimate goal is to create a EBI driver for RM9200. This
will make it possible to setup EBI and SMC for external chips.
My board has octal USART which needs SMC to be setup correctly
and this is not currently possible when using DT. Boards with
NOR and NAND flash where SMC is not setup by bootloader will
also benefit from such a driver.
I'm working this EBI driver and its DT bindings right now but
would like some comments on this before I proceed.
Joachim Eastwood (2):
ARM: at91: create ebi read/write interface for RM9200
ARM: at91: move at91_ramc.h and clean up includes
arch/arm/boot/dts/at91rm9200.dtsi | 4 +-
arch/arm/mach-at91/at91_ramc.h | 31 +++++++++++
arch/arm/mach-at91/at91rm9200.c | 3 +-
arch/arm/mach-at91/at91rm9200_devices.c | 14 ++---
arch/arm/mach-at91/at91sam9_alt_reset.S | 2 +-
arch/arm/mach-at91/at91sam9g45_reset.S | 2 +-
arch/arm/mach-at91/board-cpuat91.c | 2 -
arch/arm/mach-at91/board-eco920.c | 6 +--
arch/arm/mach-at91/board-kb9202.c | 2 -
arch/arm/mach-at91/board-picotux200.c | 3 --
arch/arm/mach-at91/board-rm9200dk.c | 2 -
arch/arm/mach-at91/board-rm9200ek.c | 2 -
arch/arm/mach-at91/board-yl-9200.c | 4 +-
arch/arm/mach-at91/generic.h | 3 ++
arch/arm/mach-at91/include/mach/at91_ebi.h | 20 +++++++
arch/arm/mach-at91/include/mach/at91_ramc.h | 32 -----------
arch/arm/mach-at91/include/mach/at91rm9200.h | 1 +
.../arm/mach-at91/include/mach/at91rm9200_sdramc.h | 63 ----------------------
arch/arm/mach-at91/include/mach/at91sam9_sdramc.h | 2 +
arch/arm/mach-at91/pm.c | 2 +-
arch/arm/mach-at91/pm.h | 9 ++--
arch/arm/mach-at91/pm_slowclock.S | 2 +-
arch/arm/mach-at91/setup.c | 10 ++++
drivers/pcmcia/at91_cf.c | 6 +--
24 files changed, 94 insertions(+), 133 deletions(-)
create mode 100644 arch/arm/mach-at91/at91_ramc.h
create mode 100644 arch/arm/mach-at91/include/mach/at91_ebi.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91_ramc.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
--
1.8.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] ARM: at91: create ebi read/write interface for RM9200
2013-02-09 15:54 [PATCH 0/2] RM9200 EBI write/read interface Joachim Eastwood
@ 2013-02-09 15:54 ` Joachim Eastwood
2013-02-11 16:49 ` Jean-Christophe PLAGNIOL-VILLARD
2013-02-09 15:54 ` [PATCH 2/2] ARM: at91: move at91_ramc.h and clean up includes Joachim Eastwood
1 sibling, 1 reply; 5+ messages in thread
From: Joachim Eastwood @ 2013-02-09 15:54 UTC (permalink / raw)
To: linux-arm-kernel
Introduce ebi read/write functions on AT91RM9200 to make
it possible to have a common SDRAMC header and driver.
SDRAMC register layout is more or less the same on RM9200
and SAM926x. The only difference is the header file for
RM9200 uses a different offset on SDRAMC registers. The
offset used is actually for RM9200 MC.
By using the real base for SDRAMC on RM9200 header files
can be shared. With this change there are also no users
of ramc outside mach-at91.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
---
arch/arm/boot/dts/at91rm9200.dtsi | 4 +-
arch/arm/mach-at91/at91rm9200.c | 3 +-
arch/arm/mach-at91/at91rm9200_devices.c | 14 ++---
arch/arm/mach-at91/board-eco920.c | 6 +--
arch/arm/mach-at91/board-yl-9200.c | 4 +-
arch/arm/mach-at91/generic.h | 3 ++
arch/arm/mach-at91/include/mach/at91_ebi.h | 20 +++++++
arch/arm/mach-at91/include/mach/at91_ramc.h | 1 -
arch/arm/mach-at91/include/mach/at91rm9200.h | 1 +
.../arm/mach-at91/include/mach/at91rm9200_sdramc.h | 63 ----------------------
arch/arm/mach-at91/include/mach/at91sam9_sdramc.h | 2 +
arch/arm/mach-at91/pm.c | 2 +-
arch/arm/mach-at91/pm.h | 7 ++-
arch/arm/mach-at91/setup.c | 10 ++++
drivers/pcmcia/at91_cf.c | 6 +--
15 files changed, 59 insertions(+), 87 deletions(-)
create mode 100644 arch/arm/mach-at91/include/mach/at91_ebi.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 5d3ed5a..48dd97f 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -64,9 +64,9 @@
atmel,external-irqs = <25 26 27 28 29 30 31>;
};
- ramc0: ramc at ffffff00 {
+ ramc0: ramc at ffffff90 {
compatible = "atmel,at91rm9200-sdramc";
- reg = <0xffffff00 0x100>;
+ reg = <0xffffff90 0x30>;
};
pmc: pmc at fffffc00 {
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 36b05fc..c4c22d1 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -325,7 +325,8 @@ static void __init at91rm9200_map_io(void)
static void __init at91rm9200_ioremap_registers(void)
{
at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
- at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
+ at91_ioremap_ebi(AT91RM9200_BASE_MC, 144);
+ at91_ioremap_ramc(0, AT91RM9200_BASE_SDRAMC, 48);
}
static void __init at91rm9200_initialize(void)
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 3ebc979..a298707 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -20,7 +20,7 @@
#include <mach/at91rm9200.h>
#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach/at91_ebi.h>
#include "board.h"
#include "generic.h"
@@ -242,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
data->chipselect = 4; /* can only use EBI ChipSelect 4 */
/* CF takes over CS4, CS5, CS6 */
- csa = at91_ramc_read(0, AT91_EBI_CSA);
- at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
+ csa = at91_ebi_read(AT91_EBI_CSA);
+ at91_ebi_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
/*
* Static memory controller timing adjustments.
* REVISIT: these timings are in terms of MCK cycles, so
* when MCK changes (cpufreq etc) so must these values...
*/
- at91_ramc_write(0, AT91_SMC_CSR(4),
+ at91_ebi_write(AT91_SMC_CSR(4),
AT91_SMC_ACSS_STD
| AT91_SMC_DBW_16
| AT91_SMC_BAT
@@ -424,11 +424,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
return;
/* enable the address range of CS3 */
- csa = at91_ramc_read(0, AT91_EBI_CSA);
- at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
+ csa = at91_ebi_read(AT91_EBI_CSA);
+ at91_ebi_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
/* set the bus interface characteristics */
- at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
+ at91_ebi_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
| AT91_SMC_NWS_(5)
| AT91_SMC_TDF_(1)
| AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 77de410..fbe9f7b 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -25,7 +25,7 @@
#include <asm/mach/map.h>
#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach/at91_ebi.h>
#include <mach/cpu.h>
#include "at91_aic.h"
@@ -123,7 +123,7 @@ static void __init eco920_board_init(void)
at91_add_device_mci(0, &eco920_mci0_data);
platform_device_register(&eco920_flash);
- at91_ramc_write(0, AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
+ at91_ebi_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
| AT91_SMC_RWSETUP_(1)
| AT91_SMC_DBW_8
| AT91_SMC_WSEN
@@ -135,7 +135,7 @@ static void __init eco920_board_init(void)
at91_set_deglitch(AT91_PIN_PA23, 1);
/* Initialization of the Static Memory Controller for Chip Select 3 */
- at91_ramc_write(0, AT91_SMC_CSR(3),
+ at91_ebi_write(AT91_SMC_CSR(3),
AT91_SMC_DBW_16 | /* 16 bit */
AT91_SMC_WSEN |
AT91_SMC_NWS_(5) | /* wait states */
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index be08377..541ce1d 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -44,7 +44,7 @@
#include <mach/hardware.h>
#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach/at91_ebi.h>
#include <mach/cpu.h>
#include "at91_aic.h"
@@ -377,7 +377,7 @@ static void yl9200_init_video(void)
at91_set_A_periph(AT91_PIN_PC6, 0);
/* Initialization of the Static Memory Controller for Chip Select 2 */
- at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
+ at91_ebi_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
| AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
| AT91_SMC_TDF_(0x100) /* float time */
);
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..3cced6b 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -69,6 +69,9 @@ extern void at91_ioremap_shdwc(u32 base_addr);
/* Matrix */
extern void at91_ioremap_matrix(u32 base_addr);
+/* EBI */
+extern void at91_ioremap_ebi(u32 addr, u32 size);
+
/* Ram Controler */
extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
diff --git a/arch/arm/mach-at91/include/mach/at91_ebi.h b/arch/arm/mach-at91/include/mach/at91_ebi.h
new file mode 100644
index 0000000..4d400c0
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ebi.h
@@ -0,0 +1,20 @@
+/*
+ * Header file for the Atmel EBI Controller
+ *
+ * Copyright (C) 2012 Joachim Eastwood <manabian@gmail.com>
+ *
+ * Under GPLv2 only
+ */
+
+#ifndef __AT91_EBI_H__
+#define __AT91_EBI_H__
+
+extern void __iomem *at91_ebi_base;
+
+#define at91_ebi_read(field) \
+ __raw_readl(at91_ebi_base + field)
+
+#define at91_ebi_write(field, value) \
+ __raw_writel(value, at91_ebi_base + field)
+
+#endif /* __AT91_EBI_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
index d8aeb27..038041d 100644
--- a/arch/arm/mach-at91/include/mach/at91_ramc.h
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -25,7 +25,6 @@ extern void __iomem *at91_ramc_base[];
#define AT91_MEMCTRL_SDRAMC 1
#define AT91_MEMCTRL_DDRSDR 2
-#include <mach/at91rm9200_sdramc.h>
#include <mach/at91sam9_ddrsdr.h>
#include <mach/at91sam9_sdramc.h>
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index e67317c..cca1b96 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -87,6 +87,7 @@
#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
+#define AT91RM9200_BASE_SDRAMC 0xffffff90 /* SDRAM Controller */
/*
* Internal Memory.
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
deleted file mode 100644
index aa047f45..0000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Memory Controllers (SDRAMC only) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_SDRAMC_H
-#define AT91RM9200_SDRAMC_H
-
-/* SDRAM Controller registers */
-#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
-#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
-#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
-#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
-#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
-#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
-#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
-#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
-#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
-#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
-
-#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
-#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
-
-#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
-#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
-#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
-#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
-#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
-#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
-#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
-#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
-#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
-#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
-#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
-#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
-#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
-#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
-#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
-#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
-#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
-#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
-#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
-#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
-#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
-
-#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
-#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
-#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
-#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
-#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
-#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 3d085a9..e45aff7 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -57,6 +57,8 @@
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
+#define AT91_SDRAMC_SRR 0x0c /* SDRAM Controller Self Refresh Register AT91RM9200 only */
+
#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_SDRAMC_LPCB_DISABLE 0
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index adb6db8..5ba38e5 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -316,7 +316,7 @@ static int __init at91_pm_init(void)
/* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
if (cpu_is_at91rm9200())
- at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
+ at91_ramc_write(0, AT91_SDRAMC_LPR, 0);
suspend_set_ops(&at91_pm_ops);
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 38f467c..c5dd8dc 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -12,7 +12,6 @@
#define __ARCH_ARM_MACH_AT91_PM
#include <mach/at91_ramc.h>
-#include <mach/at91rm9200_sdramc.h>
/*
* The AT91RM9200 goes into self-refresh mode with this command, and will
@@ -26,7 +25,7 @@
static inline void at91rm9200_standby(void)
{
- u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
+ u32 lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
asm volatile(
"b 1f\n\t"
@@ -37,8 +36,8 @@ static inline void at91rm9200_standby(void)
" mcr p15, 0, %0, c7, c0, 4\n\t"
" str %5, [%1, %2]"
:
- : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
- "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
+ : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_SDRAMC_LPR),
+ "r" (1), "r" (AT91_SDRAMC_SRR),
"r" (lpr));
}
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 4b67847..10d5b2f 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -54,6 +54,16 @@ void __init at91_init_interrupts(unsigned int *priority)
at91_gpio_irq_setup();
}
+void __iomem *at91_ebi_base;
+EXPORT_SYMBOL_GPL(at91_ebi_base);
+
+void __init at91_ioremap_ebi(u32 addr, u32 size)
+{
+ at91_ebi_base = ioremap(addr, size);
+ if (!at91_ebi_base)
+ panic("Impossible to ioremap ebi. 0x%x\n", addr);
+}
+
void __iomem *at91_ramc_base[2];
EXPORT_SYMBOL_GPL(at91_ramc_base);
diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c
index 01463c7..d9d696f 100644
--- a/drivers/pcmcia/at91_cf.c
+++ b/drivers/pcmcia/at91_cf.c
@@ -26,7 +26,7 @@
#include <asm/sizes.h>
#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach/at91_ebi.h>
/*
@@ -157,7 +157,7 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
/*
* Use 16 bit accesses unless/until we need 8-bit i/o space.
*/
- csr = at91_ramc_read(0, AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
+ csr = at91_ebi_read(AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
/*
* NOTE: this CF controller ignores IOIS16, so we can't really do
@@ -176,7 +176,7 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
csr |= AT91_SMC_DBW_16;
pr_debug("%s: 16bit i/o bus\n", driver_name);
}
- at91_ramc_write(0, AT91_SMC_CSR(cf->board->chipselect), csr);
+ at91_ebi_write(AT91_SMC_CSR(cf->board->chipselect), csr);
io->start = cf->socket.io_offset;
io->stop = io->start + SZ_2K - 1;
--
1.8.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] ARM: at91: move at91_ramc.h and clean up includes
2013-02-09 15:54 [PATCH 0/2] RM9200 EBI write/read interface Joachim Eastwood
2013-02-09 15:54 ` [PATCH 1/2] ARM: at91: create ebi read/write interface for RM9200 Joachim Eastwood
@ 2013-02-09 15:54 ` Joachim Eastwood
1 sibling, 0 replies; 5+ messages in thread
From: Joachim Eastwood @ 2013-02-09 15:54 UTC (permalink / raw)
To: linux-arm-kernel
Now that the ebi interface isn't handled by ramc, make
ramc private to mach-at91.
And while at it clean up some unnecessary ramc includes
in the RM9200 board files.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
---
arch/arm/mach-at91/at91_ramc.h | 31 +++++++++++++++++++++++++++++
arch/arm/mach-at91/at91sam9_alt_reset.S | 2 +-
arch/arm/mach-at91/at91sam9g45_reset.S | 2 +-
arch/arm/mach-at91/board-cpuat91.c | 2 --
arch/arm/mach-at91/board-kb9202.c | 2 --
arch/arm/mach-at91/board-picotux200.c | 3 ---
arch/arm/mach-at91/board-rm9200dk.c | 2 --
arch/arm/mach-at91/board-rm9200ek.c | 2 --
arch/arm/mach-at91/include/mach/at91_ramc.h | 31 -----------------------------
arch/arm/mach-at91/pm.h | 2 +-
arch/arm/mach-at91/pm_slowclock.S | 2 +-
11 files changed, 35 insertions(+), 46 deletions(-)
create mode 100644 arch/arm/mach-at91/at91_ramc.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91_ramc.h
diff --git a/arch/arm/mach-at91/at91_ramc.h b/arch/arm/mach-at91/at91_ramc.h
new file mode 100644
index 0000000..038041d
--- /dev/null
+++ b/arch/arm/mach-at91/at91_ramc.h
@@ -0,0 +1,31 @@
+/*
+ * Header file for the Atmel RAM Controller
+ *
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+
+#ifndef __AT91_RAMC_H__
+#define __AT91_RAMC_H__
+
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_ramc_base[];
+
+#define at91_ramc_read(id, field) \
+ __raw_readl(at91_ramc_base[id] + field)
+
+#define at91_ramc_write(id, field, value) \
+ __raw_writel(value, at91_ramc_base[id] + field)
+#else
+.extern at91_ramc_base
+#endif
+
+#define AT91_MEMCTRL_MC 0
+#define AT91_MEMCTRL_SDRAMC 1
+#define AT91_MEMCTRL_DDRSDR 2
+
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91sam9_sdramc.h>
+
+#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index f039538..7430f3c 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -15,7 +15,7 @@
#include <linux/linkage.h>
#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
+#include "at91_ramc.h"
#include "at91_rstc.h"
.arm
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 721a1a3..d021154 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -12,7 +12,7 @@
#include <linux/linkage.h>
#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
+#include "at91_ramc.h"
#include "at91_rstc.h"
.arm
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 42f1353..89a9ea0 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -36,8 +36,6 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
#include <mach/cpu.h>
#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 0c519d9..4d4ef55 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -36,8 +36,6 @@
#include <asm/mach/irq.h>
#include <mach/cpu.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
#include "at91_aic.h"
#include "board.h"
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab2b2ec..69a8bce 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -37,9 +37,6 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 690541b..dce4c77 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -39,8 +39,6 @@
#include <asm/mach/irq.h>
#include <mach/hardware.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
#include "at91_aic.h"
#include "board.h"
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 8b17dad..1369bf6 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -39,8 +39,6 @@
#include <asm/mach/irq.h>
#include <mach/hardware.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
#include "at91_aic.h"
#include "board.h"
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
deleted file mode 100644
index 038041d..0000000
--- a/arch/arm/mach-at91/include/mach/at91_ramc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Header file for the Atmel RAM Controller
- *
- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * Under GPLv2 only
- */
-
-#ifndef __AT91_RAMC_H__
-#define __AT91_RAMC_H__
-
-#ifndef __ASSEMBLY__
-extern void __iomem *at91_ramc_base[];
-
-#define at91_ramc_read(id, field) \
- __raw_readl(at91_ramc_base[id] + field)
-
-#define at91_ramc_write(id, field, value) \
- __raw_writel(value, at91_ramc_base[id] + field)
-#else
-.extern at91_ramc_base
-#endif
-
-#define AT91_MEMCTRL_MC 0
-#define AT91_MEMCTRL_SDRAMC 1
-#define AT91_MEMCTRL_DDRSDR 2
-
-#include <mach/at91sam9_ddrsdr.h>
-#include <mach/at91sam9_sdramc.h>
-
-#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index c5dd8dc..8f3a4f7 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -11,7 +11,7 @@
#ifndef __ARCH_ARM_MACH_AT91_PM
#define __ARCH_ARM_MACH_AT91_PM
-#include <mach/at91_ramc.h>
+#include "at91_ramc.h"
/*
* The AT91RM9200 goes into self-refresh mode with this command, and will
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 098c28d..ac49fd4 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -15,7 +15,7 @@
#include <linux/linkage.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
-#include <mach/at91_ramc.h>
+#include "at91_ramc.h"
#ifdef CONFIG_SOC_AT91SAM9263
--
1.8.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 1/2] ARM: at91: create ebi read/write interface for RM9200
2013-02-09 15:54 ` [PATCH 1/2] ARM: at91: create ebi read/write interface for RM9200 Joachim Eastwood
@ 2013-02-11 16:49 ` Jean-Christophe PLAGNIOL-VILLARD
2013-02-11 17:17 ` Joachim Eastwood
0 siblings, 1 reply; 5+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-02-11 16:49 UTC (permalink / raw)
To: linux-arm-kernel
On 16:54 Sat 09 Feb , Joachim Eastwood wrote:
> Introduce ebi read/write functions on AT91RM9200 to make
> it possible to have a common SDRAMC header and driver.
>
> SDRAMC register layout is more or less the same on RM9200
> and SAM926x. The only difference is the header file for
> RM9200 uses a different offset on SDRAMC registers. The
> offset used is actually for RM9200 MC.
>
> By using the real base for SDRAMC on RM9200 header files
> can be shared. With this change there are also no users
> of ramc outside mach-at91.
nack the idea is wrong on rm9200 we have sdramc that do ram controler + EBI
and the EBI is completly soc dependant
and you have 2 ebi on 9263 and 9g45 so the no
Best Regards,
J.
>
> Signed-off-by: Joachim Eastwood <manabian@gmail.com>
> ---
> arch/arm/boot/dts/at91rm9200.dtsi | 4 +-
> arch/arm/mach-at91/at91rm9200.c | 3 +-
> arch/arm/mach-at91/at91rm9200_devices.c | 14 ++---
> arch/arm/mach-at91/board-eco920.c | 6 +--
> arch/arm/mach-at91/board-yl-9200.c | 4 +-
> arch/arm/mach-at91/generic.h | 3 ++
> arch/arm/mach-at91/include/mach/at91_ebi.h | 20 +++++++
> arch/arm/mach-at91/include/mach/at91_ramc.h | 1 -
> arch/arm/mach-at91/include/mach/at91rm9200.h | 1 +
> .../arm/mach-at91/include/mach/at91rm9200_sdramc.h | 63 ----------------------
> arch/arm/mach-at91/include/mach/at91sam9_sdramc.h | 2 +
> arch/arm/mach-at91/pm.c | 2 +-
> arch/arm/mach-at91/pm.h | 7 ++-
> arch/arm/mach-at91/setup.c | 10 ++++
> drivers/pcmcia/at91_cf.c | 6 +--
> 15 files changed, 59 insertions(+), 87 deletions(-)
> create mode 100644 arch/arm/mach-at91/include/mach/at91_ebi.h
> delete mode 100644 arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
>
> diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
> index 5d3ed5a..48dd97f 100644
> --- a/arch/arm/boot/dts/at91rm9200.dtsi
> +++ b/arch/arm/boot/dts/at91rm9200.dtsi
> @@ -64,9 +64,9 @@
> atmel,external-irqs = <25 26 27 28 29 30 31>;
> };
>
> - ramc0: ramc at ffffff00 {
> + ramc0: ramc at ffffff90 {
> compatible = "atmel,at91rm9200-sdramc";
> - reg = <0xffffff00 0x100>;
> + reg = <0xffffff90 0x30>;
> };
>
> pmc: pmc at fffffc00 {
> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
> index 36b05fc..c4c22d1 100644
> --- a/arch/arm/mach-at91/at91rm9200.c
> +++ b/arch/arm/mach-at91/at91rm9200.c
> @@ -325,7 +325,8 @@ static void __init at91rm9200_map_io(void)
> static void __init at91rm9200_ioremap_registers(void)
> {
> at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
> - at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
> + at91_ioremap_ebi(AT91RM9200_BASE_MC, 144);
> + at91_ioremap_ramc(0, AT91RM9200_BASE_SDRAMC, 48);
> }
>
> static void __init at91rm9200_initialize(void)
> diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
> index 3ebc979..a298707 100644
> --- a/arch/arm/mach-at91/at91rm9200_devices.c
> +++ b/arch/arm/mach-at91/at91rm9200_devices.c
> @@ -20,7 +20,7 @@
>
> #include <mach/at91rm9200.h>
> #include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> +#include <mach/at91_ebi.h>
>
> #include "board.h"
> #include "generic.h"
> @@ -242,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
> data->chipselect = 4; /* can only use EBI ChipSelect 4 */
>
> /* CF takes over CS4, CS5, CS6 */
> - csa = at91_ramc_read(0, AT91_EBI_CSA);
> - at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
> + csa = at91_ebi_read(AT91_EBI_CSA);
> + at91_ebi_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
>
> /*
> * Static memory controller timing adjustments.
> * REVISIT: these timings are in terms of MCK cycles, so
> * when MCK changes (cpufreq etc) so must these values...
> */
> - at91_ramc_write(0, AT91_SMC_CSR(4),
> + at91_ebi_write(AT91_SMC_CSR(4),
> AT91_SMC_ACSS_STD
> | AT91_SMC_DBW_16
> | AT91_SMC_BAT
> @@ -424,11 +424,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
> return;
>
> /* enable the address range of CS3 */
> - csa = at91_ramc_read(0, AT91_EBI_CSA);
> - at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
> + csa = at91_ebi_read(AT91_EBI_CSA);
> + at91_ebi_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
>
> /* set the bus interface characteristics */
> - at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
> + at91_ebi_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
> | AT91_SMC_NWS_(5)
> | AT91_SMC_TDF_(1)
> | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
> diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
> index 77de410..fbe9f7b 100644
> --- a/arch/arm/mach-at91/board-eco920.c
> +++ b/arch/arm/mach-at91/board-eco920.c
> @@ -25,7 +25,7 @@
> #include <asm/mach/map.h>
>
> #include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> +#include <mach/at91_ebi.h>
> #include <mach/cpu.h>
>
> #include "at91_aic.h"
> @@ -123,7 +123,7 @@ static void __init eco920_board_init(void)
> at91_add_device_mci(0, &eco920_mci0_data);
> platform_device_register(&eco920_flash);
>
> - at91_ramc_write(0, AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
> + at91_ebi_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
> | AT91_SMC_RWSETUP_(1)
> | AT91_SMC_DBW_8
> | AT91_SMC_WSEN
> @@ -135,7 +135,7 @@ static void __init eco920_board_init(void)
> at91_set_deglitch(AT91_PIN_PA23, 1);
>
> /* Initialization of the Static Memory Controller for Chip Select 3 */
> - at91_ramc_write(0, AT91_SMC_CSR(3),
> + at91_ebi_write(AT91_SMC_CSR(3),
> AT91_SMC_DBW_16 | /* 16 bit */
> AT91_SMC_WSEN |
> AT91_SMC_NWS_(5) | /* wait states */
> diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
> index be08377..541ce1d 100644
> --- a/arch/arm/mach-at91/board-yl-9200.c
> +++ b/arch/arm/mach-at91/board-yl-9200.c
> @@ -44,7 +44,7 @@
>
> #include <mach/hardware.h>
> #include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> +#include <mach/at91_ebi.h>
> #include <mach/cpu.h>
>
> #include "at91_aic.h"
> @@ -377,7 +377,7 @@ static void yl9200_init_video(void)
> at91_set_A_periph(AT91_PIN_PC6, 0);
>
> /* Initialization of the Static Memory Controller for Chip Select 2 */
> - at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
> + at91_ebi_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
> | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
> | AT91_SMC_TDF_(0x100) /* float time */
> );
> diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
> index 78ab065..3cced6b 100644
> --- a/arch/arm/mach-at91/generic.h
> +++ b/arch/arm/mach-at91/generic.h
> @@ -69,6 +69,9 @@ extern void at91_ioremap_shdwc(u32 base_addr);
> /* Matrix */
> extern void at91_ioremap_matrix(u32 base_addr);
>
> +/* EBI */
> +extern void at91_ioremap_ebi(u32 addr, u32 size);
> +
> /* Ram Controler */
> extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
>
> diff --git a/arch/arm/mach-at91/include/mach/at91_ebi.h b/arch/arm/mach-at91/include/mach/at91_ebi.h
> new file mode 100644
> index 0000000..4d400c0
> --- /dev/null
> +++ b/arch/arm/mach-at91/include/mach/at91_ebi.h
> @@ -0,0 +1,20 @@
> +/*
> + * Header file for the Atmel EBI Controller
> + *
> + * Copyright (C) 2012 Joachim Eastwood <manabian@gmail.com>
> + *
> + * Under GPLv2 only
> + */
> +
> +#ifndef __AT91_EBI_H__
> +#define __AT91_EBI_H__
> +
> +extern void __iomem *at91_ebi_base;
> +
> +#define at91_ebi_read(field) \
> + __raw_readl(at91_ebi_base + field)
> +
> +#define at91_ebi_write(field, value) \
> + __raw_writel(value, at91_ebi_base + field)
> +
> +#endif /* __AT91_EBI_H__ */
> diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
> index d8aeb27..038041d 100644
> --- a/arch/arm/mach-at91/include/mach/at91_ramc.h
> +++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
> @@ -25,7 +25,6 @@ extern void __iomem *at91_ramc_base[];
> #define AT91_MEMCTRL_SDRAMC 1
> #define AT91_MEMCTRL_DDRSDR 2
>
> -#include <mach/at91rm9200_sdramc.h>
> #include <mach/at91sam9_ddrsdr.h>
> #include <mach/at91sam9_sdramc.h>
>
> diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
> index e67317c..cca1b96 100644
> --- a/arch/arm/mach-at91/include/mach/at91rm9200.h
> +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
> @@ -87,6 +87,7 @@
> #define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
> #define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
> #define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
> +#define AT91RM9200_BASE_SDRAMC 0xffffff90 /* SDRAM Controller */
>
> /*
> * Internal Memory.
> diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
> deleted file mode 100644
> index aa047f45..0000000
> --- a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
> +++ /dev/null
> @@ -1,63 +0,0 @@
> -/*
> - * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
> - *
> - * Copyright (C) 2005 Ivan Kokshaysky
> - * Copyright (C) SAN People
> - *
> - * Memory Controllers (SDRAMC only) - System peripherals registers.
> - * Based on AT91RM9200 datasheet revision E.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - */
> -
> -#ifndef AT91RM9200_SDRAMC_H
> -#define AT91RM9200_SDRAMC_H
> -
> -/* SDRAM Controller registers */
> -#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
> -#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
> -#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
> -#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
> -#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
> -#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
> -#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
> -#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
> -#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
> -#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
> -
> -#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
> -#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
> -
> -#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
> -#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
> -#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
> -#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
> -#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
> -#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
> -#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
> -#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
> -#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
> -#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
> -#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
> -#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
> -#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
> -#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
> -#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
> -#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
> -#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
> -#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
> -#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
> -#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
> -#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
> -
> -#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
> -#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
> -#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
> -#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
> -#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
> -#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
> -
> -#endif
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> index 3d085a9..e45aff7 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
> @@ -57,6 +57,8 @@
> #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
> #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
>
> +#define AT91_SDRAMC_SRR 0x0c /* SDRAM Controller Self Refresh Register AT91RM9200 only */
> +
> #define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
> #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
> #define AT91_SDRAMC_LPCB_DISABLE 0
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index adb6db8..5ba38e5 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -316,7 +316,7 @@ static int __init at91_pm_init(void)
>
> /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
> if (cpu_is_at91rm9200())
> - at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
> + at91_ramc_write(0, AT91_SDRAMC_LPR, 0);
>
> suspend_set_ops(&at91_pm_ops);
>
> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
> index 38f467c..c5dd8dc 100644
> --- a/arch/arm/mach-at91/pm.h
> +++ b/arch/arm/mach-at91/pm.h
> @@ -12,7 +12,6 @@
> #define __ARCH_ARM_MACH_AT91_PM
>
> #include <mach/at91_ramc.h>
> -#include <mach/at91rm9200_sdramc.h>
>
> /*
> * The AT91RM9200 goes into self-refresh mode with this command, and will
> @@ -26,7 +25,7 @@
>
> static inline void at91rm9200_standby(void)
> {
> - u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
> + u32 lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
>
> asm volatile(
> "b 1f\n\t"
> @@ -37,8 +36,8 @@ static inline void at91rm9200_standby(void)
> " mcr p15, 0, %0, c7, c0, 4\n\t"
> " str %5, [%1, %2]"
> :
> - : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
> - "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
> + : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_SDRAMC_LPR),
> + "r" (1), "r" (AT91_SDRAMC_SRR),
> "r" (lpr));
> }
>
> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> index 4b67847..10d5b2f 100644
> --- a/arch/arm/mach-at91/setup.c
> +++ b/arch/arm/mach-at91/setup.c
> @@ -54,6 +54,16 @@ void __init at91_init_interrupts(unsigned int *priority)
> at91_gpio_irq_setup();
> }
>
> +void __iomem *at91_ebi_base;
> +EXPORT_SYMBOL_GPL(at91_ebi_base);
> +
> +void __init at91_ioremap_ebi(u32 addr, u32 size)
> +{
> + at91_ebi_base = ioremap(addr, size);
> + if (!at91_ebi_base)
> + panic("Impossible to ioremap ebi. 0x%x\n", addr);
> +}
> +
> void __iomem *at91_ramc_base[2];
> EXPORT_SYMBOL_GPL(at91_ramc_base);
>
> diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c
> index 01463c7..d9d696f 100644
> --- a/drivers/pcmcia/at91_cf.c
> +++ b/drivers/pcmcia/at91_cf.c
> @@ -26,7 +26,7 @@
> #include <asm/sizes.h>
>
> #include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> +#include <mach/at91_ebi.h>
>
>
> /*
> @@ -157,7 +157,7 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
> /*
> * Use 16 bit accesses unless/until we need 8-bit i/o space.
> */
> - csr = at91_ramc_read(0, AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
> + csr = at91_ebi_read(AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
>
> /*
> * NOTE: this CF controller ignores IOIS16, so we can't really do
> @@ -176,7 +176,7 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
> csr |= AT91_SMC_DBW_16;
> pr_debug("%s: 16bit i/o bus\n", driver_name);
> }
> - at91_ramc_write(0, AT91_SMC_CSR(cf->board->chipselect), csr);
> + at91_ebi_write(AT91_SMC_CSR(cf->board->chipselect), csr);
>
> io->start = cf->socket.io_offset;
> io->stop = io->start + SZ_2K - 1;
> --
> 1.8.0
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] ARM: at91: create ebi read/write interface for RM9200
2013-02-11 16:49 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2013-02-11 17:17 ` Joachim Eastwood
0 siblings, 0 replies; 5+ messages in thread
From: Joachim Eastwood @ 2013-02-11 17:17 UTC (permalink / raw)
To: linux-arm-kernel
On 11 February 2013 17:49, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj@jcrosoft.com> wrote:
> On 16:54 Sat 09 Feb , Joachim Eastwood wrote:
>> Introduce ebi read/write functions on AT91RM9200 to make
>> it possible to have a common SDRAMC header and driver.
>>
>> SDRAMC register layout is more or less the same on RM9200
>> and SAM926x. The only difference is the header file for
>> RM9200 uses a different offset on SDRAMC registers. The
>> offset used is actually for RM9200 MC.
>>
>> By using the real base for SDRAMC on RM9200 header files
>> can be shared. With this change there are also no users
>> of ramc outside mach-at91.
>
> nack the idea is wrong on rm9200 we have sdramc that do ram controler + EBI
>
> and the EBI is completly soc dependant
>
> and you have 2 ebi on 9263 and 9g45 so the no
Well, the at91_ebi_read/write functions in this patch was only meant
for RM9200. Guess I should have called it at91rm9200_ebi_read/write or
something.
Anyway; my goal is to create an EBI driver for AT91RM9200 which will
use DT to setup EBI/SMC for devices hooked up to EBI. This driver will
live in drivers/bus. The sdramc "driver" can continue to live in
mach-at91 but the handling of EBI and SMC will move into a proper
driver.
Do you a better approach?
The two patches I posted was only a clean up to prepare for a proper
driver living in drivers/bus. I'll try to finish up the rest of the
series so you see the whole picture.
regards
Joachim Eastwood
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2013-02-11 17:17 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-02-09 15:54 [PATCH 0/2] RM9200 EBI write/read interface Joachim Eastwood
2013-02-09 15:54 ` [PATCH 1/2] ARM: at91: create ebi read/write interface for RM9200 Joachim Eastwood
2013-02-11 16:49 ` Jean-Christophe PLAGNIOL-VILLARD
2013-02-11 17:17 ` Joachim Eastwood
2013-02-09 15:54 ` [PATCH 2/2] ARM: at91: move at91_ramc.h and clean up includes Joachim Eastwood
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