From mboxrd@z Thu Jan 1 00:00:00 1970 From: haojian.zhuang@linaro.org (Haojian Zhuang) Date: Wed, 20 Feb 2013 00:22:24 +0800 Subject: [PATCH v4 07/11] document: devicetree: add properties in mrvl gpio In-Reply-To: <1361290948-16669-1-git-send-email-haojian.zhuang@linaro.org> References: <1361290948-16669-1-git-send-email-haojian.zhuang@linaro.org> Message-ID: <1361290948-16669-8-git-send-email-haojian.zhuang@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Append new properties for mrvl gpio. They're in below. marvell,gpio-ed-mask marvell,gpio-inverted & marvell,nr_gpios. Signed-off-by: Haojian Zhuang --- Documentation/devicetree/bindings/gpio/mrvl-gpio.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt index e137874..8cd5252 100644 --- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt @@ -14,6 +14,13 @@ Required properties: interrupt source. - gpio-controller : Marks the device node as a gpio controller. - #gpio-cells : Should be one. It is the pin number. +- marvell,nr-gpios : Should be the number of total gpio pins. + +Optional properties: +- marvell,gpio-ed-mask : It means that there's gpio edge mask register. + It only exists in mmp family SoC. +- marvell,gpio-inverted : It means that some gpio pins are inverted. + It only exists in PXA26x SoC. Example: @@ -26,6 +33,8 @@ Example: #gpio-cells = <1>; interrupt-controller; #interrupt-cells = <1>; + marvell,gpio-ed-mask; + marvell,nr-gpios = <128>; }; * Marvell Orion GPIO Controller -- 1.7.10.4