[PATCH V2 0/5] ARM: DT: tegra114: Add DT entry for different controller

[PATCH V2 0/5] ARM: DT: tegra114: Add DT entry for different controller

[Laxman Dewangan]

This patch series add DT entry for APB DMA, I2C, UART, KBC and SPI.

This patch series is generated on top of CCF work for T114 done by Peter
and hence it should be applied on top of T114 CCF patches.

Changes from V1:
- Add reeason why APBDMA is not compatible with older driver
  in description.
- Remove UARTB car id correction. Make the compatible with tegra114 and
  older chip.
- Add compatible for kbc as nvidia,tegra114-kbc and nvidia,tegra20-kbc.

Laxman Dewangan (5):
  ARM: DT: tegra114: add APB DMA controller DT entry
  ARM: DT: tegra114: Add i2c controller DT entry
  ARM: DT: tegra114:add aliases and DMA requestor for serial controller
  ARM: DT: tegra114: add KBC controller DT entry
  ARM: DT: tegra114: Add spi controller DT entry

 arch/arm/boot/dts/tegra114.dtsi |  200 ++++++++++++++++++++++++++++++++++++++-
 1 files changed, 196 insertions(+), 4 deletions(-)

[PATCH V2 1/5] ARM: DT: tegra114: add APB DMA controller DT entry

[Laxman Dewangan]

NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".

Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA
controller driver as in T114, the global pause also clock gate the
DMA register and hence it iw not possible to write the DMA register
with global pause.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- Add reeason why APBDMA is not compatible with older driver
  in description.

 arch/arm/boot/dts/tegra114.dtsi |   38 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 0eec49f..b73b8a6 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -38,6 +38,44 @@
 		reg = <0x6000c004 0x14c>;
 	};
 
+	apbdma: dma {
+		compatible = "nvidia,tegra114-apbdma";
+		reg = <0x6000a000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+		clocks = <&tegra_car 34>;
+	};
+
 	gpio: gpio {
 		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
-- 
1.7.1.1

[PATCH V2 1/5] ARM: DT: tegra114: add APB DMA controller DT entry

[Thierry Reding]

On Sat, Mar 09, 2013 at 11:41:14PM +0530, Laxman Dewangan wrote:
> NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
> APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".
> 
> Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA
> controller driver as in T114, the global pause also clock gate the

"clockgates"? "clock-gates"?

> DMA register and hence it iw not possible to write the DMA register

"it is not"

Thierry
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[PATCH V2 2/5] ARM: DT: tegra114: Add i2c controller DT entry

[Laxman Dewangan]

NVIDIA's Tegra114 has 5 i2c controllers. These controllers have
additional feature/configurations to make it functional over
Tegra30's i2c controller driver.

Add DT entry for i2c controllers and make it compatible with
"nvidia,tegra114-i2c".

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- None

 arch/arm/boot/dts/tegra114.dtsi |   55 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index b73b8a6..14afbc8 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -135,6 +135,61 @@
 		clocks = <&tegra_car 65>;
 	};
 
+	i2c at 7000c000 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c000 0x100>;
+		interrupts = <0 38 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 12>;
+		clock-names = "div-clk";
+	};
+
+	i2c at 7000c400 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c400 0x100>;
+		interrupts = <0 84 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 54>;
+		clock-names = "div-clk";
+	};
+
+	i2c at 7000c500 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c500 0x100>;
+		interrupts = <0 92 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 67>;
+		clock-names = "div-clk";
+	};
+
+	i2c at 7000c700 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c700 0x100>;
+		interrupts = <0 120 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 103>;
+		clock-names = "div-clk";
+	};
+
+	i2c at 7000d000 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000d000 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 47>;
+		clock-names = "div-clk";
+	};
+
 	sdhci at 78000000 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000000 0x200>;
-- 
1.7.1.1

[PATCH V2 2/5] ARM: DT: tegra114: Add i2c controller DT entry

[Thierry Reding]

On Sat, Mar 09, 2013 at 11:41:15PM +0530, Laxman Dewangan wrote:
> NVIDIA's Tegra114 has 5 i2c controllers. These controllers have
> additional feature/configurations to make it functional over
> Tegra30's i2c controller driver.
> 
> Add DT entry for i2c controllers and make it compatible with
> "nvidia,tegra114-i2c".

Both the subject and description should probably use I2C instead of i2c.
Also I don't understand what "make it functional over" means. Perhaps,
since the entries aren't marked compatible with nvidia,tegra30-i2c you
meant to say that they are incompatible with Tegra30?

Thierry
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[PATCH V2 2/5] ARM: DT: tegra114: Add i2c controller DT entry

[Stephen Warren]

On 03/10/2013 04:39 PM, Thierry Reding wrote:
> On Sat, Mar 09, 2013 at 11:41:15PM +0530, Laxman Dewangan wrote:
>> NVIDIA's Tegra114 has 5 i2c controllers. These controllers have 
>> additional feature/configurations to make it functional over 
>> Tegra30's i2c controller driver.
>> 
>> Add DT entry for i2c controllers and make it compatible with 
>> "nvidia,tegra114-i2c".
> 
> Both the subject and description should probably use I2C instead of
> i2c. Also I don't understand what "make it functional over" means.
> Perhaps, since the entries aren't marked compatible with
> nvidia,tegra30-i2c you meant to say that they are incompatible with
> Tegra30?

The second sentence Laxman wrote above should probably say:

These controllers have a modified clocking structure that make them
incompatible with previous hardware.

[PATCH V2 2/5] ARM: DT: tegra114: Add i2c controller DT entry

[Stephen Warren]

On 03/09/2013 11:11 AM, Laxman Dewangan wrote:
> NVIDIA's Tegra114 has 5 i2c controllers. These controllers have
> additional feature/configurations to make it functional over
> Tegra30's i2c controller driver.
> 
> Add DT entry for i2c controllers and make it compatible with
> "nvidia,tegra114-i2c".

Hmm. We're missing a binding document for the Tegra I2C module! Can you
please submit a separate patch to add one. When you do, since the
Tegra114 nodes need just a "div-clk" clock, and the Tegra20/30 nodes
need both div-clk and fast-clk, please be sure to mention this in the
document. Thanks.

[PATCH V2 3/5] ARM: DT: tegra114:add aliases and DMA requestor for serial controller

[Laxman Dewangan]

Add APB DMA requestor and serial aliases for serial controller.
There will be two serial driver i.e. 8250 based simple serial driver
and APB DMA based serial driver for higher baudrate and performace.

The simple serial driver get enabled with compatible "nvidia,tegra114-uart",
"nvidia,tegra20-uart" and APB DMA based driver will get enabled with
compatible "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- Remove UARTB car id correction. Make the compatible with tegra114 and
  tegra30 for hsuart and tegra20 for simple uart driver.

 arch/arm/boot/dts/tegra114.dtsi |   27 +++++++++++++++++++++++----
 1 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 14afbc8..300082d 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -4,6 +4,13 @@
 	compatible = "nvidia,tegra114";
 	interrupt-parent = <&gic>;
 
+	aliases {
+		serial0 = &uarta;
+		serial1 = &uartb;
+		serial2 = &uartc;
+		serial3 = &uartd;
+	};
+
 	gic: interrupt-controller {
 		compatible = "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
@@ -99,38 +106,50 @@
 		       0x70003000 0x40c>;	/* Mux registers */
 	};
 
-	serial at 70006000 {
+	/*
+	 * There are two serial driver i.e. 8250 based simple serial
+	 * driver and APB DMA based serial driver for higher baudrate
+	 * and performace. To enable the 8250 based driver, the compatible
+	 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
+	 * the APB DMA based serial driver, the comptible is
+	 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
+	 */
+	uarta: serial at 70006000 {
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <0 36 0x04>;
+		nvidia,dma-request-selector = <&apbdma 8>;
 		status = "disabled";
 		clocks = <&tegra_car 6>;
 	};
 
-	serial at 70006040 {
+	uartb: serial at 70006040 {
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <0 37 0x04>;
+		nvidia,dma-request-selector = <&apbdma 9>;
 		status = "disabled";
 		clocks = <&tegra_car 192>;
 	};
 
-	serial at 70006200 {
+	uartc: serial at 70006200 {
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <0 46 0x04>;
+		nvidia,dma-request-selector = <&apbdma 10>;
 		status = "disabled";
 		clocks = <&tegra_car 55>;
 	};
 
-	serial at 70006300 {
+	uartd: serial at 70006300 {
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <0 90 0x04>;
+		nvidia,dma-request-selector = <&apbdma 19>;
 		status = "disabled";
 		clocks = <&tegra_car 65>;
 	};
-- 
1.7.1.1

[PATCH V2 3/5] ARM: DT: tegra114:add aliases and DMA requestor for serial controller

[Thierry Reding]

On Sat, Mar 09, 2013 at 11:41:16PM +0530, Laxman Dewangan wrote:
[...]
> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
[...]
> @@ -99,38 +106,50 @@
>  		       0x70003000 0x40c>;	/* Mux registers */
>  	};
>  
> -	serial at 70006000 {
> +	/*
> +	 * There are two serial driver i.e. 8250 based simple serial
> +	 * driver and APB DMA based serial driver for higher baudrate
> +	 * and performace. To enable the 8250 based driver, the compatible
> +	 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
> +	 * the APB DMA based serial driver, the comptible is
> +	 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
> +	 */
> +	uarta: serial at 70006000 {

I'm not sure if this is a good place for this comment. Perhaps it should
go into the binding documentation?

Thierry
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[PATCH V2 3/5] ARM: DT: tegra114:add aliases and DMA requestor for serial controller

[Stephen Warren]

On 03/10/2013 04:42 PM, Thierry Reding wrote:
> On Sat, Mar 09, 2013 at 11:41:16PM +0530, Laxman Dewangan wrote: 
> [...]
>> diff --git a/arch/arm/boot/dts/tegra114.dtsi 
>> b/arch/arm/boot/dts/tegra114.dtsi
> [...]
>> @@ -99,38 +106,50 @@ 0x70003000 0x40c>;	/* Mux registers */ };
>> 
>> -	serial at 70006000 { +	/* +	 * There are two serial driver i.e. 
>> 8250 based simple serial +	 * driver and APB DMA based serial 
>> driver for higher baudrate +	 * and performace. To enable the 
>> 8250 based driver, the compatible +	 * is
>> "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable +	 *
>> the APB DMA based serial driver, the comptible is +	 *
>> "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". +	 */ +	uarta:
>> serial at 70006000 {
> 
> I'm not sure if this is a good place for this comment. Perhaps it 
> should go into the binding documentation?

It is at least consistent with previous tegra20/30.dtsi. The two
compatible values are separate bindings, so a clue here re: which one
to go look at isn't a bad idea, although I agree that having each
binding document mention the other one would also be good.

[PATCH V2 3/5] ARM: DT: tegra114:add aliases and DMA requestor for serial controller

[Stephen Warren]

On 03/09/2013 11:11 AM, Laxman Dewangan wrote:
> Add APB DMA requestor and serial aliases for serial controller.
> There will be two serial driver i.e. 8250 based simple serial driver
> and APB DMA based serial driver for higher baudrate and performace.
> 
> The simple serial driver get enabled with compatible "nvidia,tegra114-uart",
> "nvidia,tegra20-uart" and APB DMA based driver will get enabled with
> compatible "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
> Changes from V1:
> - Remove UARTB car id correction. Make the compatible with tegra114 and
>   tegra30 for hsuart and tegra20 for simple uart driver.

Why the difference for the two drivers? Either the HW is compatible with
all 3 of 114/30/20 (in which case you only need list 114/20 in the
compatible value), or it's not compatible with either 30/20, since we
already know that 30/20 are compatible with each-other (in which case
you should only list 114 in the compatible property).

[PATCH V2 4/5] ARM: DT: tegra114: add KBC controller DT entry

[Laxman Dewangan]

NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
supports 11x8 type of matrix. The number of rows and columns
are configurable.

Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc",
"nvidia,tegra20-kbc".

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- Add compatible for kbc as nvidia,tegra114-kbc and nvidia,tegra20-kbc.

 arch/arm/boot/dts/tegra114.dtsi |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 300082d..21ff340 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -248,6 +248,14 @@
 		clocks = <&tegra_car 4>;
 	};
 
+	kbc {
+		compatible = "nvidia,tegra114-kbc", "nvidia,tegra20-kbc";
+		reg = <0x7000e200 0x100>;
+		interrupts = <0 85 0x04>;
+		clocks = <&tegra_car 36>;
+		status = "disabled";
+	};
+
 	pmc {
 		compatible = "nvidia,tegra114-pmc";
 		reg = <0x7000e400 0x400>;
-- 
1.7.1.1

[PATCH V2 4/5] ARM: DT: tegra114: add KBC controller DT entry

[Stephen Warren]

On 03/09/2013 11:11 AM, Laxman Dewangan wrote:
> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
> supports 11x8 type of matrix. The number of rows and columns
> are configurable.
> 
> Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc",
> "nvidia,tegra20-kbc".

I thought the HW really wasn't compatible with Tegra20 due to the
reduced number of rows/columns/pins supported?

[PATCH V2 4/5] ARM: DT: tegra114: add KBC controller DT entry

[Laxman Dewangan]

On Monday 11 March 2013 11:13 PM, Stephen Warren wrote:
> On 03/09/2013 11:11 AM, Laxman Dewangan wrote:
>> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
>> supports 11x8 type of matrix. The number of rows and columns
>> are configurable.
>>
>> Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc",
>> "nvidia,tegra20-kbc".
> I thought the HW really wasn't compatible with Tegra20 due to the
> reduced number of rows/columns/pins supported?

Hw controller is really compatible. Only thing is that there is no 
physical pins on SoC for KBC-ROW11 to KBC-ROW15.
Because, there is no physical pins for ROW11 to ROW15, we asked to 
remove programming/reference this rows from  TRM of T114 to consistent 
with SoCs.

[PATCH V2 4/5] ARM: DT: tegra114: add KBC controller DT entry

[Stephen Warren]

On 03/11/2013 11:59 AM, Laxman Dewangan wrote:
> On Monday 11 March 2013 11:13 PM, Stephen Warren wrote:
>> On 03/09/2013 11:11 AM, Laxman Dewangan wrote:
>>> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
>>> supports 11x8 type of matrix. The number of rows and columns
>>> are configurable.
>>>
>>> Add DT entry for KBC controller with compatibility as
>>> "nvidia,tegra114-kbc",
>>> "nvidia,tegra20-kbc".
>> I thought the HW really wasn't compatible with Tegra20 due to the
>> reduced number of rows/columns/pins supported?
> 
> Hw controller is really compatible. Only thing is that there is no
> physical pins on SoC for KBC-ROW11 to KBC-ROW15.
> Because, there is no physical pins for ROW11 to ROW15, we asked to
> remove programming/reference this rows from  TRM of T114 to consistent
> with SoCs.

I think that makes the HW incompatible. If you only have knowledge of
Tegra20/30, you can assume that there are more rows/pins/columns than
there actually are. Applying those same validation restrictions on
Tegra114 will yield validation that isn't strict enough; invalid values
could be accepted.

[PATCH V2 5/5] ARM: DT: tegra114: Add spi controller DT entry

[Laxman Dewangan]

NVIDIA's Tegra114 has 6 spi controllers. These controllers are
redesign on T114 with different register interface.

Add DT entry for spi controllers and make it compatible with
"nvidia,tegra114-spi".

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- None

 arch/arm/boot/dts/tegra114.dtsi |   72 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 72 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 21ff340..47ad1b8 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -209,6 +209,78 @@
 		clock-names = "div-clk";
 	};
 
+	spi at 7000d400 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 41>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
+	spi at 7000d600 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 44>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
+	spi at 7000d800 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d480 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 46>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
+	spi at 7000da00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 68>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
+	spi at 7000dc00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 104>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
+	spi at 7000de00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 105>;
+		clock-names = "spi";
+		status = "disabled";
+	};
+
 	sdhci at 78000000 {
 		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 		reg = <0x78000000 0x200>;
-- 
1.7.1.1

[PATCH V2 5/5] ARM: DT: tegra114: Add spi controller DT entry

[Thierry Reding]

On Sat, Mar 09, 2013 at 11:41:18PM +0530, Laxman Dewangan wrote:
> NVIDIA's Tegra114 has 6 spi controllers. These controllers are
> redesign on T114 with different register interface.
> 
> Add DT entry for spi controllers and make it compatible with
> "nvidia,tegra114-spi".

Similarly, SPI is an abbreviation and should be in all uppercase
letters. I can't really comment on the rest since there's no TRM
available publicly to check against.

Thierry
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[PATCH V2 0/5] ARM: DT: tegra114: Add DT entry for different controller

[Stephen Warren]

On 03/09/2013 11:11 AM, Laxman Dewangan wrote:
> This patch series add DT entry for APB DMA, I2C, UART, KBC and SPI.
> 
> This patch series is generated on top of CCF work for T114 done by Peter
> and hence it should be applied on top of T114 CCF patches.
> 
> Changes from V1:
> - Add reeason why APBDMA is not compatible with older driver
>   in description.
> - Remove UARTB car id correction. Make the compatible with tegra114 and
>   older chip.
> - Add compatible for kbc as nvidia,tegra114-kbc and nvidia,tegra20-kbc.
> 
> Laxman Dewangan (5):
>   ARM: DT: tegra114: add APB DMA controller DT entry
>   ARM: DT: tegra114: Add i2c controller DT entry
>   ARM: DT: tegra114:add aliases and DMA requestor for serial controller
>   ARM: DT: tegra114: add KBC controller DT entry
>   ARM: DT: tegra114: Add spi controller DT entry

What branch is this series based on? I tried to apply these for testing,
but git am failed to apply it to Tegra's for-3.10/dt, and Tegra's
for-next, and my local work branch, and next-20130307.

Can you please rebase onto Tegra's for-3.10/dt. Thanks.

[PATCH V2 0/5] ARM: DT: tegra114: Add DT entry for different controller

[Laxman Dewangan]

On Tuesday 12 March 2013 03:45 AM, Stephen Warren wrote:
> On 03/09/2013 11:11 AM, Laxman Dewangan wrote:
>> This patch series add DT entry for APB DMA, I2C, UART, KBC and SPI.
>>
>> This patch series is generated on top of CCF work for T114 done by Peter
>> and hence it should be applied on top of T114 CCF patches.
>>
>> Changes from V1:
>> - Add reeason why APBDMA is not compatible with older driver
>>    in description.
>> - Remove UARTB car id correction. Make the compatible with tegra114 and
>>    older chip.
>> - Add compatible for kbc as nvidia,tegra114-kbc and nvidia,tegra20-kbc.
>>
>> Laxman Dewangan (5):
>>    ARM: DT: tegra114: add APB DMA controller DT entry
>>    ARM: DT: tegra114: Add i2c controller DT entry
>>    ARM: DT: tegra114:add aliases and DMA requestor for serial controller
>>    ARM: DT: tegra114: add KBC controller DT entry
>>    ARM: DT: tegra114: Add spi controller DT entry
> What branch is this series based on? I tried to apply these for testing,
> but git am failed to apply it to Tegra's for-3.10/dt, and Tegra's
> for-next, and my local work branch, and next-20130307.
>
> Can you please rebase onto Tegra's for-3.10/dt. Thanks.

I created the patch as:
- linux next 20130307
- Then add all clock changes from Peter's
git://nv-tegra.nvidia.com/user/pdeschrijver/linux.git

- Then I generated the DT entry on top of this which has clock reference.

In your 3.10/DT, there is no change for Peter's clock change and 
possibly this is the reason.


If I base my change on your 3.10/DT then:
- Do I need to add the clock entry for all modules also?

[PATCH V2 0/5] ARM: DT: tegra114: Add DT entry for different controller

[Stephen Warren]

On 03/12/2013 04:11 AM, Laxman Dewangan wrote:
> On Tuesday 12 March 2013 03:45 AM, Stephen Warren wrote:
>> On 03/09/2013 11:11 AM, Laxman Dewangan wrote:
>>> This patch series add DT entry for APB DMA, I2C, UART, KBC and SPI.
>>>
>>> This patch series is generated on top of CCF work for T114 done by Peter
>>> and hence it should be applied on top of T114 CCF patches.
>>>
>>> Changes from V1:
>>> - Add reeason why APBDMA is not compatible with older driver
>>>    in description.
>>> - Remove UARTB car id correction. Make the compatible with tegra114 and
>>>    older chip.
>>> - Add compatible for kbc as nvidia,tegra114-kbc and nvidia,tegra20-kbc.
>>>
>>> Laxman Dewangan (5):
>>>    ARM: DT: tegra114: add APB DMA controller DT entry
>>>    ARM: DT: tegra114: Add i2c controller DT entry
>>>    ARM: DT: tegra114:add aliases and DMA requestor for serial controller
>>>    ARM: DT: tegra114: add KBC controller DT entry
>>>    ARM: DT: tegra114: Add spi controller DT entry
>> What branch is this series based on? I tried to apply these for testing,
>> but git am failed to apply it to Tegra's for-3.10/dt, and Tegra's
>> for-next, and my local work branch, and next-20130307.
>>
>> Can you please rebase onto Tegra's for-3.10/dt. Thanks.
> 
> I created the patch as:
> - linux next 20130307
> - Then add all clock changes from Peter's
> git://nv-tegra.nvidia.com/user/pdeschrijver/linux.git
> 
> - Then I generated the DT entry on top of this which has clock reference.
> 
> In your 3.10/DT, there is no change for Peter's clock change and
> possibly this is the reason.

Yes, that's probably the problem. Please base on the current for-3.10/dt
branch directly.

> If I base my change on your 3.10/DT then:
> - Do I need to add the clock entry for all modules also?

Yes, please add complete nodes.