[PATCH 0/3] ARM: EXYNOS: cpuidle: Several fixes in exynos cpuidle/PM

[PATCH 0/3] ARM: EXYNOS: cpuidle: Several fixes in exynos cpuidle/PM

[Amit Daniel Kachhap]

This patch series contains a couple of fixes in cpuidle/PM due to
1) clock migration in driver folder.
2) exynos5440 platform which does not support cpuidle C1 state.
3) Compilations error when generic PM options are enabled.

All these patches are based on Samsung maintainer's for-next tree.
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git for-next

Amit Daniel Kachhap (3):
  ARM: EXYNOS: Move arm core power down clock to exynos5250 common
    clock
  ARM: SAMSUNG: Add SAMSUNG_PM config option to select pm
  ARM: EXYNOS: cpuidle: Allow C1 state only in supported SOC's.

 arch/arm/mach-exynos/Makefile           |    2 +-
 arch/arm/mach-exynos/common.c           |    2 +-
 arch/arm/mach-exynos/common.h           |    1 -
 arch/arm/mach-exynos/cpuidle.c          |   40 +++--------------------------
 arch/arm/plat-samsung/Kconfig           |    7 +++++
 arch/arm/plat-samsung/Makefile          |    3 +-
 arch/arm/plat-samsung/include/plat/pm.h |    8 +++---
 drivers/clk/samsung/clk-exynos5250.c    |   42 +++++++++++++++++++++++++++++++
 8 files changed, 60 insertions(+), 45 deletions(-)

[PATCH 1/3] ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock

[Amit Daniel Kachhap]

Now with common clock support added for exynos5250 it is necessary to move
this code to exynos5250 common clock driver as clock registers should be
handled there. This change is tested in exynos5250 based arndale platform.

Cc: Abhilash Kesavan <a.kesavan@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
---
 arch/arm/mach-exynos/cpuidle.c       |   35 ----------------------------
 drivers/clk/samsung/clk-exynos5250.c |   42 ++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 35 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index e2689d1..6929c77 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -160,46 +160,11 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
 		return exynos4_enter_core0_aftr(dev, drv, new_index);
 }
 
-static void __init exynos5_core_down_clk(void)
-{
-	unsigned int tmp;
-
-	/*
-	 * Enable arm clock down (in idle) and set arm divider
-	 * ratios in WFI/WFE state.
-	 */
-	tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
-	      PWR_CTRL1_CORE1_DOWN_RATIO | \
-	      PWR_CTRL1_DIV2_DOWN_EN	 | \
-	      PWR_CTRL1_DIV1_DOWN_EN	 | \
-	      PWR_CTRL1_USE_CORE1_WFE	 | \
-	      PWR_CTRL1_USE_CORE0_WFE	 | \
-	      PWR_CTRL1_USE_CORE1_WFI	 | \
-	      PWR_CTRL1_USE_CORE0_WFI;
-	__raw_writel(tmp, EXYNOS5_PWR_CTRL1);
-
-	/*
-	 * Enable arm clock up (on exiting idle). Set arm divider
-	 * ratios when not in idle along with the standby duration
-	 * ratios.
-	 */
-	tmp = PWR_CTRL2_DIV2_UP_EN	 | \
-	      PWR_CTRL2_DIV1_UP_EN	 | \
-	      PWR_CTRL2_DUR_STANDBY2_VAL | \
-	      PWR_CTRL2_DUR_STANDBY1_VAL | \
-	      PWR_CTRL2_CORE2_UP_RATIO	 | \
-	      PWR_CTRL2_CORE1_UP_RATIO;
-	__raw_writel(tmp, EXYNOS5_PWR_CTRL2);
-}
-
 static int __init exynos4_init_cpuidle(void)
 {
 	int cpu_id, ret;
 	struct cpuidle_device *device;
 
-	if (soc_is_exynos5250())
-		exynos5_core_down_clk();
-
 	ret = cpuidle_register_driver(&exynos4_idle_driver);
 	if (ret) {
 		printk(KERN_ERR "CPUidle failed to register driver\n");
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 1152125..b653863 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -22,6 +22,8 @@
 
 #define SRC_CPU			0x200
 #define DIV_CPU0		0x500
+#define PWR_CTRL1		0x1020
+#define PWR_CTRL2		0x1024
 #define SRC_CORE1		0x4204
 #define SRC_TOP0		0x10210
 #define SRC_TOP2		0x10218
@@ -63,6 +65,23 @@
 #define SRC_CDREX		0x20200
 #define PLL_DIV2_SEL		0x20a24
 
+/*Below definitions are used for PWR_CTRL settings*/
+#define PWR_CTRL1_CORE2_DOWN_RATIO		(7 << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO		(7 << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN			(1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN			(1 << 8)
+#define PWR_CTRL1_USE_CORE1_WFE			(1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE			(1 << 4)
+#define PWR_CTRL1_USE_CORE1_WFI			(1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI			(1 << 0)
+
+#define PWR_CTRL2_DIV2_UP_EN			(1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN			(1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2_VAL		(1 << 16)
+#define PWR_CTRL2_DUR_STANDBY1_VAL		(1 << 8)
+#define PWR_CTRL2_CORE2_UP_RATIO		(1 << 4)
+#define PWR_CTRL2_CORE1_UP_RATIO		(1 << 0)
+
 /*
  * Let each supported clock get a unique id. This id is used to lookup the clock
  * for device tree based platforms. The clocks are categorized into three
@@ -110,6 +129,8 @@ enum exynos5250_clks {
 static __initdata unsigned long exynos5250_clk_regs[] = {
 	SRC_CPU,
 	DIV_CPU0,
+	PWR_CTRL1,
+	PWR_CTRL2,
 	SRC_CORE1,
 	SRC_TOP0,
 	SRC_TOP2,
@@ -467,6 +488,7 @@ void __init exynos5250_clk_init(struct device_node *np)
 {
 	void __iomem *reg_base;
 	struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+	unsigned int tmp;
 
 	if (np) {
 		reg_base = of_iomap(np, 0);
@@ -508,6 +530,26 @@ void __init exynos5250_clk_init(struct device_node *np)
 	samsung_clk_register_gate(exynos5250_gate_clks,
 			ARRAY_SIZE(exynos5250_gate_clks));
 
+	/*
+	 * Enable arm clock down (in idle) and set arm divider
+	 * ratios in WFI/WFE state.
+	 */
+	tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
+		PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
+		PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
+		PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
+	__raw_writel(tmp, reg_base + PWR_CTRL1);
+
+	/*
+	 * Enable arm clock up (on exiting idle). Set arm divider
+	 * ratios when not in idle along with the standby duration
+	 * ratios.
+	 */
+	tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
+		PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
+		PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
+	__raw_writel(tmp, reg_base + PWR_CTRL2);
+
 	pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
 			_get_rate("armclk"));
 }
-- 
1.7.1

[RESEND PATCH 1/3] ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock

[Amit Daniel Kachhap]

Now with common clock support added for exynos5250 it is necessary to move
this code to exynos5250 common clock driver as clock registers should be
handled there. This change is tested in exynos5250 based arndale platform.

Cc: Abhilash Kesavan <a.kesavan@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
---
Re-based against linux for-next branch.
 
 arch/arm/mach-exynos/cpuidle.c       |   35 ----------------------------
 drivers/clk/samsung/clk-exynos5250.c |   42 ++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 35 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 17a18ff..4667907 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -159,46 +159,11 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
 		return exynos4_enter_core0_aftr(dev, drv, new_index);
 }
 
-static void __init exynos5_core_down_clk(void)
-{
-	unsigned int tmp;
-
-	/*
-	 * Enable arm clock down (in idle) and set arm divider
-	 * ratios in WFI/WFE state.
-	 */
-	tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
-	      PWR_CTRL1_CORE1_DOWN_RATIO | \
-	      PWR_CTRL1_DIV2_DOWN_EN	 | \
-	      PWR_CTRL1_DIV1_DOWN_EN	 | \
-	      PWR_CTRL1_USE_CORE1_WFE	 | \
-	      PWR_CTRL1_USE_CORE0_WFE	 | \
-	      PWR_CTRL1_USE_CORE1_WFI	 | \
-	      PWR_CTRL1_USE_CORE0_WFI;
-	__raw_writel(tmp, EXYNOS5_PWR_CTRL1);
-
-	/*
-	 * Enable arm clock up (on exiting idle). Set arm divider
-	 * ratios when not in idle along with the standby duration
-	 * ratios.
-	 */
-	tmp = PWR_CTRL2_DIV2_UP_EN	 | \
-	      PWR_CTRL2_DIV1_UP_EN	 | \
-	      PWR_CTRL2_DUR_STANDBY2_VAL | \
-	      PWR_CTRL2_DUR_STANDBY1_VAL | \
-	      PWR_CTRL2_CORE2_UP_RATIO	 | \
-	      PWR_CTRL2_CORE1_UP_RATIO;
-	__raw_writel(tmp, EXYNOS5_PWR_CTRL2);
-}
-
 static int __init exynos4_init_cpuidle(void)
 {
 	int cpu_id, ret;
 	struct cpuidle_device *device;
 
-	if (soc_is_exynos5250())
-		exynos5_core_down_clk();
-
 	ret = cpuidle_register_driver(&exynos4_idle_driver);
 	if (ret) {
 		printk(KERN_ERR "CPUidle failed to register driver\n");
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..89f51e9 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -21,6 +21,8 @@
 
 #define SRC_CPU			0x200
 #define DIV_CPU0		0x500
+#define PWR_CTRL1		0x1020
+#define PWR_CTRL2		0x1024
 #define SRC_CORE1		0x4204
 #define SRC_TOP0		0x10210
 #define SRC_TOP2		0x10218
@@ -63,6 +65,23 @@
 #define PLL_DIV2_SEL		0x20a24
 #define GATE_IP_DISP1		0x10928
 
+/*Below definitions are used for PWR_CTRL settings*/
+#define PWR_CTRL1_CORE2_DOWN_RATIO		(7 << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO		(7 << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN			(1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN			(1 << 8)
+#define PWR_CTRL1_USE_CORE1_WFE			(1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE			(1 << 4)
+#define PWR_CTRL1_USE_CORE1_WFI			(1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI			(1 << 0)
+
+#define PWR_CTRL2_DIV2_UP_EN			(1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN			(1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2_VAL		(1 << 16)
+#define PWR_CTRL2_DUR_STANDBY1_VAL		(1 << 8)
+#define PWR_CTRL2_CORE2_UP_RATIO		(1 << 4)
+#define PWR_CTRL2_CORE1_UP_RATIO		(1 << 0)
+
 /*
  * Let each supported clock get a unique id. This id is used to lookup the clock
  * for device tree based platforms. The clocks are categorized into three
@@ -110,6 +129,8 @@ enum exynos5250_clks {
 static __initdata unsigned long exynos5250_clk_regs[] = {
 	SRC_CPU,
 	DIV_CPU0,
+	PWR_CTRL1,
+	PWR_CTRL2,
 	SRC_CORE1,
 	SRC_TOP0,
 	SRC_TOP2,
@@ -474,6 +495,7 @@ void __init exynos5250_clk_init(struct device_node *np)
 {
 	void __iomem *reg_base;
 	struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+	unsigned int tmp;
 
 	if (np) {
 		reg_base = of_iomap(np, 0);
@@ -516,6 +538,26 @@ void __init exynos5250_clk_init(struct device_node *np)
 	samsung_clk_register_gate(exynos5250_gate_clks,
 			ARRAY_SIZE(exynos5250_gate_clks));
 
+	/*
+	 * Enable arm clock down (in idle) and set arm divider
+	 * ratios in WFI/WFE state.
+	 */
+	tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
+		PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
+		PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
+		PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
+	__raw_writel(tmp, reg_base + PWR_CTRL1);
+
+	/*
+	 * Enable arm clock up (on exiting idle). Set arm divider
+	 * ratios when not in idle along with the standby duration
+	 * ratios.
+	 */
+	tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
+		PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
+		PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
+	__raw_writel(tmp, reg_base + PWR_CTRL2);
+
 	pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
 			_get_rate("armclk"));
 }
-- 
1.7.1

[RESEND PATCH 1/3] ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock

[amit daniel kachhap]

Hi Mike,

If possible please ack this patch or merge this via your tree.

Thanks,
Amit Daniel

On Thu, Jun 6, 2013 at 12:27 PM, Amit Daniel Kachhap
<amit.daniel@samsung.com> wrote:
> Now with common clock support added for exynos5250 it is necessary to move
> this code to exynos5250 common clock driver as clock registers should be
> handled there. This change is tested in exynos5250 based arndale platform.
>
> Cc: Abhilash Kesavan <a.kesavan@samsung.com>
> Cc: Thomas Abraham <thomas.abraham@linaro.org>
> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> ---
> Re-based against linux for-next branch.
>
>  arch/arm/mach-exynos/cpuidle.c       |   35 ----------------------------
>  drivers/clk/samsung/clk-exynos5250.c |   42 ++++++++++++++++++++++++++++++++++
>  2 files changed, 42 insertions(+), 35 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
> index 17a18ff..4667907 100644
> --- a/arch/arm/mach-exynos/cpuidle.c
> +++ b/arch/arm/mach-exynos/cpuidle.c
> @@ -159,46 +159,11 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
>                 return exynos4_enter_core0_aftr(dev, drv, new_index);
>  }
>
> -static void __init exynos5_core_down_clk(void)
> -{
> -       unsigned int tmp;
> -
> -       /*
> -        * Enable arm clock down (in idle) and set arm divider
> -        * ratios in WFI/WFE state.
> -        */
> -       tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
> -             PWR_CTRL1_CORE1_DOWN_RATIO | \
> -             PWR_CTRL1_DIV2_DOWN_EN     | \
> -             PWR_CTRL1_DIV1_DOWN_EN     | \
> -             PWR_CTRL1_USE_CORE1_WFE    | \
> -             PWR_CTRL1_USE_CORE0_WFE    | \
> -             PWR_CTRL1_USE_CORE1_WFI    | \
> -             PWR_CTRL1_USE_CORE0_WFI;
> -       __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
> -
> -       /*
> -        * Enable arm clock up (on exiting idle). Set arm divider
> -        * ratios when not in idle along with the standby duration
> -        * ratios.
> -        */
> -       tmp = PWR_CTRL2_DIV2_UP_EN       | \
> -             PWR_CTRL2_DIV1_UP_EN       | \
> -             PWR_CTRL2_DUR_STANDBY2_VAL | \
> -             PWR_CTRL2_DUR_STANDBY1_VAL | \
> -             PWR_CTRL2_CORE2_UP_RATIO   | \
> -             PWR_CTRL2_CORE1_UP_RATIO;
> -       __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
> -}
> -
>  static int __init exynos4_init_cpuidle(void)
>  {
>         int cpu_id, ret;
>         struct cpuidle_device *device;
>
> -       if (soc_is_exynos5250())
> -               exynos5_core_down_clk();
> -
>         ret = cpuidle_register_driver(&exynos4_idle_driver);
>         if (ret) {
>                 printk(KERN_ERR "CPUidle failed to register driver\n");
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index 5c97e75..89f51e9 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -21,6 +21,8 @@
>
>  #define SRC_CPU                        0x200
>  #define DIV_CPU0               0x500
> +#define PWR_CTRL1              0x1020
> +#define PWR_CTRL2              0x1024
>  #define SRC_CORE1              0x4204
>  #define SRC_TOP0               0x10210
>  #define SRC_TOP2               0x10218
> @@ -63,6 +65,23 @@
>  #define PLL_DIV2_SEL           0x20a24
>  #define GATE_IP_DISP1          0x10928
>
> +/*Below definitions are used for PWR_CTRL settings*/
> +#define PWR_CTRL1_CORE2_DOWN_RATIO             (7 << 28)
> +#define PWR_CTRL1_CORE1_DOWN_RATIO             (7 << 16)
> +#define PWR_CTRL1_DIV2_DOWN_EN                 (1 << 9)
> +#define PWR_CTRL1_DIV1_DOWN_EN                 (1 << 8)
> +#define PWR_CTRL1_USE_CORE1_WFE                        (1 << 5)
> +#define PWR_CTRL1_USE_CORE0_WFE                        (1 << 4)
> +#define PWR_CTRL1_USE_CORE1_WFI                        (1 << 1)
> +#define PWR_CTRL1_USE_CORE0_WFI                        (1 << 0)
> +
> +#define PWR_CTRL2_DIV2_UP_EN                   (1 << 25)
> +#define PWR_CTRL2_DIV1_UP_EN                   (1 << 24)
> +#define PWR_CTRL2_DUR_STANDBY2_VAL             (1 << 16)
> +#define PWR_CTRL2_DUR_STANDBY1_VAL             (1 << 8)
> +#define PWR_CTRL2_CORE2_UP_RATIO               (1 << 4)
> +#define PWR_CTRL2_CORE1_UP_RATIO               (1 << 0)
> +
>  /*
>   * Let each supported clock get a unique id. This id is used to lookup the clock
>   * for device tree based platforms. The clocks are categorized into three
> @@ -110,6 +129,8 @@ enum exynos5250_clks {
>  static __initdata unsigned long exynos5250_clk_regs[] = {
>         SRC_CPU,
>         DIV_CPU0,
> +       PWR_CTRL1,
> +       PWR_CTRL2,
>         SRC_CORE1,
>         SRC_TOP0,
>         SRC_TOP2,
> @@ -474,6 +495,7 @@ void __init exynos5250_clk_init(struct device_node *np)
>  {
>         void __iomem *reg_base;
>         struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
> +       unsigned int tmp;
>
>         if (np) {
>                 reg_base = of_iomap(np, 0);
> @@ -516,6 +538,26 @@ void __init exynos5250_clk_init(struct device_node *np)
>         samsung_clk_register_gate(exynos5250_gate_clks,
>                         ARRAY_SIZE(exynos5250_gate_clks));
>
> +       /*
> +        * Enable arm clock down (in idle) and set arm divider
> +        * ratios in WFI/WFE state.
> +        */
> +       tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
> +               PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
> +               PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
> +               PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
> +       __raw_writel(tmp, reg_base + PWR_CTRL1);
> +
> +       /*
> +        * Enable arm clock up (on exiting idle). Set arm divider
> +        * ratios when not in idle along with the standby duration
> +        * ratios.
> +        */
> +       tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
> +               PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
> +               PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
> +       __raw_writel(tmp, reg_base + PWR_CTRL2);
> +
>         pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
>                         _get_rate("armclk"));
>  }
> --
> 1.7.1
>
> --
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[RESEND PATCH 1/3] ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock

[Kukjin Kim]

amit daniel kachhap wrote:
> 
> Hi Mike,
> 
> If possible please ack this patch or merge this via your tree.
> 
> Thanks,
> Amit Daniel
> 
> On Thu, Jun 6, 2013 at 12:27 PM, Amit Daniel Kachhap
> <amit.daniel@samsung.com> wrote:
> > Now with common clock support added for exynos5250 it is necessary to
> move
> > this code to exynos5250 common clock driver as clock registers should be
> > handled there. This change is tested in exynos5250 based arndale
> platform.
> >
> > Cc: Abhilash Kesavan <a.kesavan@samsung.com>
> > Cc: Thomas Abraham <thomas.abraham@linaro.org>
> > Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>

Acked-by: Kukjin Kim <kgene.kim@samsung.com>

Mike, if you have any concerns on this, please let me know.

Thanks,
Kukjin

> > ---
> > Re-based against linux for-next branch.
> >
> >  arch/arm/mach-exynos/cpuidle.c       |   35
----------------------------
> >  drivers/clk/samsung/clk-exynos5250.c |   42
> ++++++++++++++++++++++++++++++++++
> >  2 files changed, 42 insertions(+), 35 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-
> exynos/cpuidle.c
> > index 17a18ff..4667907 100644
> > --- a/arch/arm/mach-exynos/cpuidle.c
> > +++ b/arch/arm/mach-exynos/cpuidle.c
> > @@ -159,46 +159,11 @@ static int exynos4_enter_lowpower(struct
> cpuidle_device *dev,
> >                 return exynos4_enter_core0_aftr(dev, drv, new_index);
> >  }
> >
> > -static void __init exynos5_core_down_clk(void)
> > -{
> > -       unsigned int tmp;
> > -
> > -       /*
> > -        * Enable arm clock down (in idle) and set arm divider
> > -        * ratios in WFI/WFE state.
> > -        */
> > -       tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
> > -             PWR_CTRL1_CORE1_DOWN_RATIO | \
> > -             PWR_CTRL1_DIV2_DOWN_EN     | \
> > -             PWR_CTRL1_DIV1_DOWN_EN     | \
> > -             PWR_CTRL1_USE_CORE1_WFE    | \
> > -             PWR_CTRL1_USE_CORE0_WFE    | \
> > -             PWR_CTRL1_USE_CORE1_WFI    | \
> > -             PWR_CTRL1_USE_CORE0_WFI;
> > -       __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
> > -
> > -       /*
> > -        * Enable arm clock up (on exiting idle). Set arm divider
> > -        * ratios when not in idle along with the standby duration
> > -        * ratios.
> > -        */
> > -       tmp = PWR_CTRL2_DIV2_UP_EN       | \
> > -             PWR_CTRL2_DIV1_UP_EN       | \
> > -             PWR_CTRL2_DUR_STANDBY2_VAL | \
> > -             PWR_CTRL2_DUR_STANDBY1_VAL | \
> > -             PWR_CTRL2_CORE2_UP_RATIO   | \
> > -             PWR_CTRL2_CORE1_UP_RATIO;
> > -       __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
> > -}
> > -
> >  static int __init exynos4_init_cpuidle(void)
> >  {
> >         int cpu_id, ret;
> >         struct cpuidle_device *device;
> >
> > -       if (soc_is_exynos5250())
> > -               exynos5_core_down_clk();
> > -
> >         ret = cpuidle_register_driver(&exynos4_idle_driver);
> >         if (ret) {
> >                 printk(KERN_ERR "CPUidle failed to register driver\n");
> > diff --git a/drivers/clk/samsung/clk-exynos5250.c
> b/drivers/clk/samsung/clk-exynos5250.c
> > index 5c97e75..89f51e9 100644
> > --- a/drivers/clk/samsung/clk-exynos5250.c
> > +++ b/drivers/clk/samsung/clk-exynos5250.c
> > @@ -21,6 +21,8 @@
> >
> >  #define SRC_CPU                        0x200
> >  #define DIV_CPU0               0x500
> > +#define PWR_CTRL1              0x1020
> > +#define PWR_CTRL2              0x1024
> >  #define SRC_CORE1              0x4204
> >  #define SRC_TOP0               0x10210
> >  #define SRC_TOP2               0x10218
> > @@ -63,6 +65,23 @@
> >  #define PLL_DIV2_SEL           0x20a24
> >  #define GATE_IP_DISP1          0x10928
> >
> > +/*Below definitions are used for PWR_CTRL settings*/
> > +#define PWR_CTRL1_CORE2_DOWN_RATIO             (7 << 28)
> > +#define PWR_CTRL1_CORE1_DOWN_RATIO             (7 << 16)
> > +#define PWR_CTRL1_DIV2_DOWN_EN                 (1 << 9)
> > +#define PWR_CTRL1_DIV1_DOWN_EN                 (1 << 8)
> > +#define PWR_CTRL1_USE_CORE1_WFE                        (1 << 5)
> > +#define PWR_CTRL1_USE_CORE0_WFE                        (1 << 4)
> > +#define PWR_CTRL1_USE_CORE1_WFI                        (1 << 1)
> > +#define PWR_CTRL1_USE_CORE0_WFI                        (1 << 0)
> > +
> > +#define PWR_CTRL2_DIV2_UP_EN                   (1 << 25)
> > +#define PWR_CTRL2_DIV1_UP_EN                   (1 << 24)
> > +#define PWR_CTRL2_DUR_STANDBY2_VAL             (1 << 16)
> > +#define PWR_CTRL2_DUR_STANDBY1_VAL             (1 << 8)
> > +#define PWR_CTRL2_CORE2_UP_RATIO               (1 << 4)
> > +#define PWR_CTRL2_CORE1_UP_RATIO               (1 << 0)
> > +
> >  /*
> >   * Let each supported clock get a unique id. This id is used to lookup
> the clock
> >   * for device tree based platforms. The clocks are categorized into
> three
> > @@ -110,6 +129,8 @@ enum exynos5250_clks {
> >  static __initdata unsigned long exynos5250_clk_regs[] = {
> >         SRC_CPU,
> >         DIV_CPU0,
> > +       PWR_CTRL1,
> > +       PWR_CTRL2,
> >         SRC_CORE1,
> >         SRC_TOP0,
> >         SRC_TOP2,
> > @@ -474,6 +495,7 @@ void __init exynos5250_clk_init(struct device_node
> *np)
> >  {
> >         void __iomem *reg_base;
> >         struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
> > +       unsigned int tmp;
> >
> >         if (np) {
> >                 reg_base = of_iomap(np, 0);
> > @@ -516,6 +538,26 @@ void __init exynos5250_clk_init(struct device_node
> *np)
> >         samsung_clk_register_gate(exynos5250_gate_clks,
> >                         ARRAY_SIZE(exynos5250_gate_clks));
> >
> > +       /*
> > +        * Enable arm clock down (in idle) and set arm divider
> > +        * ratios in WFI/WFE state.
> > +        */
> > +       tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
> > +               PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
> > +               PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
> > +               PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
> > +       __raw_writel(tmp, reg_base + PWR_CTRL1);
> > +
> > +       /*
> > +        * Enable arm clock up (on exiting idle). Set arm divider
> > +        * ratios when not in idle along with the standby duration
> > +        * ratios.
> > +        */
> > +       tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
> > +               PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL
|
> > +               PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
> > +       __raw_writel(tmp, reg_base + PWR_CTRL2);
> > +
> >         pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
> >                         _get_rate("armclk"));
> >  }
> > --
> > 1.7.1
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-samsung-
> soc" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html

[RESEND PATCH 1/3] ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock

[Kukjin Kim]

Amit Daniel Kachhap wrote:
> 
> Now with common clock support added for exynos5250 it is necessary to move
> this code to exynos5250 common clock driver as clock registers should be
> handled there. This change is tested in exynos5250 based arndale platform.
> 
> Cc: Abhilash Kesavan <a.kesavan@samsung.com>
> Cc: Thomas Abraham <thomas.abraham@linaro.org>
> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>

Hmm...I'm not sure it's better to handle the ARM core power down clock in
common clock but the clock registers should be handled in one part, clock.

Acked-by: Kukjin Kim <kgene.kim@samsugn.com>

Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this
moment, so this patch will not create any conflict between samsung and clk.

Thanks,
- Kukjin

[RESEND PATCH 1/3] ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock

[amit daniel kachhap]

Hi Mike,

Please merge this patch as it is pending since last merge window.

Thanks,
Amit

On Thu, Jun 13, 2013 at 5:56 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Amit Daniel Kachhap wrote:
>>
>> Now with common clock support added for exynos5250 it is necessary to move
>> this code to exynos5250 common clock driver as clock registers should be
>> handled there. This change is tested in exynos5250 based arndale platform.
>>
>> Cc: Abhilash Kesavan <a.kesavan@samsung.com>
>> Cc: Thomas Abraham <thomas.abraham@linaro.org>
>> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
>
> Hmm...I'm not sure it's better to handle the ARM core power down clock in
> common clock but the clock registers should be handled in one part, clock.
>
> Acked-by: Kukjin Kim <kgene.kim@samsugn.com>
>
> Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this
> moment, so this patch will not create any conflict between samsung and clk.
>
> Thanks,
> - Kukjin
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

On Thu, Jun 13, 2013 at 5:56 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Amit Daniel Kachhap wrote:
>>
>> Now with common clock support added for exynos5250 it is necessary to move
>> this code to exynos5250 common clock driver as clock registers should be
>> handled there. This change is tested in exynos5250 based arndale platform.
>>
>> Cc: Abhilash Kesavan <a.kesavan@samsung.com>
>> Cc: Thomas Abraham <thomas.abraham@linaro.org>
>> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
>
> Hmm...I'm not sure it's better to handle the ARM core power down clock in
> common clock but the clock registers should be handled in one part, clock.
>
> Acked-by: Kukjin Kim <kgene.kim@samsugn.com>
>
> Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this
> moment, so this patch will not create any conflict between samsung and clk.
>
> Thanks,
> - Kukjin
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[RESEND PATCH 1/3] ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock

[Bartlomiej Zolnierkiewicz]

Hi,

Mike:

Could you please apply this patch? It is few months overdue..

Amit:

This patch no longer applies to -next. Could you please refresh and resend it?

You can add:

	Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

while at it.

Thanks.

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

On Friday, August 16, 2013 10:22:44 AM amit daniel kachhap wrote:
> Hi Mike,
> 
> Please merge this patch as it is pending since last merge window.
> 
> Thanks,
> Amit
> 
> On Thu, Jun 13, 2013 at 5:56 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> > Amit Daniel Kachhap wrote:
> >>
> >> Now with common clock support added for exynos5250 it is necessary to move
> >> this code to exynos5250 common clock driver as clock registers should be
> >> handled there. This change is tested in exynos5250 based arndale platform.
> >>
> >> Cc: Abhilash Kesavan <a.kesavan@samsung.com>
> >> Cc: Thomas Abraham <thomas.abraham@linaro.org>
> >> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> >
> > Hmm...I'm not sure it's better to handle the ARM core power down clock in
> > common clock but the clock registers should be handled in one part, clock.
> >
> > Acked-by: Kukjin Kim <kgene.kim@samsugn.com>
> >
> > Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this
> > moment, so this patch will not create any conflict between samsung and clk.
> >
> > Thanks,
> > - Kukjin

[RESEND PATCH 1/3] ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock

[Amit Kachhap]

Hi Bartlomeij,

Yes these patches have missed 2 merge windows and still not merged.

Mike:
I am re-basing these patches on linux-next. Please merge them.

Regards,
Amit

On Wed, Oct 9, 2013 at 3:18 PM, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
>
> Hi,
>
> Mike:
>
> Could you please apply this patch? It is few months overdue..
>
> Amit:
>
> This patch no longer applies to -next. Could you please refresh and resend it?
>
> You can add:
>
>         Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>
> while at it.
>
> Thanks.
>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>
> On Friday, August 16, 2013 10:22:44 AM amit daniel kachhap wrote:
>> Hi Mike,
>>
>> Please merge this patch as it is pending since last merge window.
>>
>> Thanks,
>> Amit
>>
>> On Thu, Jun 13, 2013 at 5:56 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> > Amit Daniel Kachhap wrote:
>> >>
>> >> Now with common clock support added for exynos5250 it is necessary to move
>> >> this code to exynos5250 common clock driver as clock registers should be
>> >> handled there. This change is tested in exynos5250 based arndale platform.
>> >>
>> >> Cc: Abhilash Kesavan <a.kesavan@samsung.com>
>> >> Cc: Thomas Abraham <thomas.abraham@linaro.org>
>> >> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
>> >
>> > Hmm...I'm not sure it's better to handle the ARM core power down clock in
>> > common clock but the clock registers should be handled in one part, clock.
>> >
>> > Acked-by: Kukjin Kim <kgene.kim@samsugn.com>
>> >
>> > Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this
>> > moment, so this patch will not create any conflict between samsung and clk.
>> >
>> > Thanks,
>> > - Kukjin
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


On Wed, Oct 9, 2013 at 3:18 PM, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
>
> Hi,
>
> Mike:
>
> Could you please apply this patch? It is few months overdue..
>
> Amit:
>
> This patch no longer applies to -next. Could you please refresh and resend it?
>
> You can add:
>
>         Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>
> while at it.
>
> Thanks.
>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>
> On Friday, August 16, 2013 10:22:44 AM amit daniel kachhap wrote:
>> Hi Mike,
>>
>> Please merge this patch as it is pending since last merge window.
>>
>> Thanks,
>> Amit
>>
>> On Thu, Jun 13, 2013 at 5:56 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> > Amit Daniel Kachhap wrote:
>> >>
>> >> Now with common clock support added for exynos5250 it is necessary to move
>> >> this code to exynos5250 common clock driver as clock registers should be
>> >> handled there. This change is tested in exynos5250 based arndale platform.
>> >>
>> >> Cc: Abhilash Kesavan <a.kesavan@samsung.com>
>> >> Cc: Thomas Abraham <thomas.abraham@linaro.org>
>> >> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
>> >
>> > Hmm...I'm not sure it's better to handle the ARM core power down clock in
>> > common clock but the clock registers should be handled in one part, clock.
>> >
>> > Acked-by: Kukjin Kim <kgene.kim@samsugn.com>
>> >
>> > Mike, the mach-exynos/cpuidle.c is not touched in samsung tree at this
>> > moment, so this patch will not create any conflict between samsung and clk.
>> >
>> > Thanks,
>> > - Kukjin
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 2/3] ARM: SAMSUNG: Add SAMSUNG_PM config option to select pm

[Amit Daniel Kachhap]

This patch enables the selection of samsung pm related stuffs
when SAMSUNG_PM config is enabled and not just when generic PM
config is enabled. Power management for s3c64XX and s3c24XX
is enabled by default and for other platform depends on S5P_PM.
This patch also fixes the following compilation error's when compiling
a platform like exynos5440 which does not select pm stuffs.

arch/arm/mach-exynos/built-in.o: In function `__virt_to_phys':
linux/arch/arm/include/asm/memory.h:175: undefined reference to `s3c_cpu_resume'
linux/arch/arm/include/asm/memory.h:175: undefined reference to `s3c_cpu_resume'
linux/arch/arm/include/asm/memory.h:175: undefined reference to `s3c_cpu_resume'
linux/arch/arm/include/asm/memory.h:175: undefined reference to `s3c_cpu_resume'
arch/arm/mach-exynos/built-in.o: In function `exynos5_init_irq':
linux/arch/arm/mach-exynos/common.c:492: undefined reference to `s3c_irq_wake'
linux/arch/arm/mach-exynos/common.c:492: undefined reference to `s3c_irq_wake'
arch/arm/mach-exynos/built-in.o: In function `exynos4_init_irq':
linux/arch/arm/mach-exynos/common.c:476: undefined reference to `s3c_irq_wake'
linux/arch/arm/mach-exynos/common.c:476: undefined reference to `s3c_irq_wake'
arch/arm/plat-samsung/built-in.o: In function `s3c_irqext_wake':
linux/arch/arm/plat-samsung/pm.c:144: undefined reference to `s3c_irqwake_eintallow'
linux/arch/arm/plat-samsung/pm.c:144: undefined reference to `s3c_irqwake_eintallow'
arch/arm/plat-samsung/built-in.o: In function `s3c_pm_enter':
linux/arch/arm/plat-samsung/pm.c:263: undefined reference to `s3c_irqwake_intallow'
linux/arch/arm/plat-samsung/pm.c:263: undefined reference to `s3c_irqwake_intallow'
linux/arch/arm/plat-samsung/pm.c:264: undefined reference to `s3c_irqwake_eintallow'
linux/arch/arm/plat-samsung/pm.c:264: undefined reference to `s3c_irqwake_eintallow'
linux/arch/arm/plat-samsung/pm.c:275: undefined reference to `s3c_pm_save_core'
linux/arch/arm/plat-samsung/pm.c:279: undefined reference to `s3c_pm_configure_extint'
linux/arch/arm/plat-samsung/pm.c:310: undefined reference to `s3c_pm_restore_core'
make: *** [vmlinux] Error 1

Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
---
 arch/arm/mach-exynos/Makefile           |    2 +-
 arch/arm/mach-exynos/common.c           |    2 +-
 arch/arm/mach-exynos/common.h           |    1 -
 arch/arm/mach-exynos/cpuidle.c          |    1 +
 arch/arm/plat-samsung/Kconfig           |    7 +++++++
 arch/arm/plat-samsung/Makefile          |    3 +--
 arch/arm/plat-samsung/include/plat/pm.h |    8 ++++----
 7 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index b09b027..2a431fc 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -14,7 +14,7 @@ obj-				:=
 
 obj-$(CONFIG_ARCH_EXYNOS)	+= common.o
 
-obj-$(CONFIG_PM)		+= pm.o
+obj-$(CONFIG_S5P_PM)		+= pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5b3c2b2..5e3ccda 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -764,7 +764,7 @@ static struct irq_chip exynos_irq_eint = {
 	.irq_mask_ack	= exynos_irq_eint_maskack,
 	.irq_ack	= exynos_irq_eint_ack,
 	.irq_set_type	= exynos_irq_eint_set_type,
-#ifdef CONFIG_PM
+#ifdef CONFIG_S5P_PM
 	.irq_set_wake	= s3c_irqext_wake,
 #endif
 };
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index fcfc64c..c6062dd 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -95,6 +95,5 @@ struct exynos_pmu_conf {
 };
 
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
-extern void s3c_cpu_resume(void);
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 6929c77..4fc1f4f 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -25,6 +25,7 @@
 #include <mach/regs-pmu.h>
 
 #include <plat/cpu.h>
+#include <plat/pm.h>
 
 #include "common.h"
 
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 6cb19c6..66427af 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -31,6 +31,13 @@ config PLAT_S5P
 	help
 	  Base platform code for Samsung's S5P series SoC.
 
+config SAMSUNG_PM
+	bool
+	depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM)
+	default y
+	help
+	  Base platform power management code for samsung code
+
 if PLAT_SAMSUNG
 
 # boot configurations
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index a23c460..1c406b3 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -51,8 +51,7 @@ obj-$(CONFIG_SAMSUNG_DMADEV)	+= dma-ops.o
 
 # PM support
 
-obj-$(CONFIG_PM)		+= pm.o
-obj-$(CONFIG_PM)		+= pm-gpio.o
+obj-$(CONFIG_SAMSUNG_PM)	+= pm.o pm-gpio.o
 obj-$(CONFIG_SAMSUNG_PM_CHECK)	+= pm-check.o
 
 obj-$(CONFIG_SAMSUNG_WAKEMASK)	+= wakeup-mask.o
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index f6fcade..46e2c82 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -19,7 +19,7 @@
 
 struct device;
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_SAMSUNG_PM
 
 extern __init int s3c_pm_init(void);
 extern __init int s3c64xx_pm_init(void);
@@ -58,8 +58,6 @@ extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
 
 /* from sleep.S */
 
-extern void s3c_cpu_resume(void);
-
 extern int s3c2410_cpu_suspend(unsigned long);
 
 /* sleep save info */
@@ -106,12 +104,14 @@ extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
 extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
 extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_SAMSUNG_PM
 extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
 extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
+extern void s3c_cpu_resume(void);
 #else
 #define s3c_irq_wake NULL
 #define s3c_irqext_wake NULL
+#define s3c_cpu_resume NULL
 #endif
 
 /* PM debug functions */
-- 
1.7.1

[PATCH 3/3] ARM: EXYNOS: cpuidle: Allow C1 state only in supported SOC's.

[Amit Daniel Kachhap]

This patch registers the basic C0 state for all exynos SOC's but
limits the C1(AFTR -Arm off top running) state in only the supported
SOC's(ie. EXYNOS 4210, 4212, 4412 and 5250).

Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
---
 arch/arm/mach-exynos/cpuidle.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 4fc1f4f..459979a 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -177,7 +177,9 @@ static int __init exynos4_init_cpuidle(void)
 		device->cpu = cpu_id;
 
 		/* Support IDLE only */
-		if (cpu_id != 0)
+		if (!(soc_is_exynos4210() || soc_is_exynos4212() ||
+			soc_is_exynos4412() || soc_is_exynos5250()) ||
+			cpu_id != 0)
 			device->state_count = 1;
 
 		ret = cpuidle_register_device(device);
-- 
1.7.1