[PATCH 0/5] add SPI/NOR for imx6q{dl}-sabreauto boards

[PATCH 0/5] add SPI/NOR for imx6q{dl}-sabreauto boards

[Huang Shijie]

this patch set add the SPI/NOR support for imx6q-sabreauto/imx6dl-sabreauto
boards.

Tested on both boards.

Huang Shijie (5):
  ARM: dts: imx6q: add a new device node for ecspi1
  ARM: dts: imx6dl: add a pinctrl for eCSPI1
  ARM: dts: imx6dl: add a gpio for hog
  ARM: dts: imx6q: add a gpio for hog
  ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards

 arch/arm/boot/dts/imx6dl-sabreauto.dts   |    1 +
 arch/arm/boot/dts/imx6dl.dtsi            |   10 +++++++++
 arch/arm/boot/dts/imx6q-sabreauto.dts    |    1 +
 arch/arm/boot/dts/imx6q.dtsi             |   11 ++++++++++
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   32 ++++++++++++++++++++++++++++++
 5 files changed, 55 insertions(+), 0 deletions(-)

[PATCH 1/5] ARM: dts: imx6q: add a new device node for ecspi1

[Huang Shijie]

Signed-off-by: Huang Shijie <b32955@freescale.com>
---
 arch/arm/boot/dts/imx6q.dtsi |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ed11bcf..5601026 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -59,6 +59,17 @@
 	soc {
 		aips-bus at 02000000 { /* AIPS1 */
 			spba-bus at 02000000 {
+				ecspi1: ecspi at 02008000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+					reg = <0x02008000 0x4000>;
+					interrupts = <0 31 0x04>;
+					clocks = <&clks 112>, <&clks 112>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
 				ecspi5: ecspi at 02018000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
-- 
1.7.1

[PATCH 1/5] ARM: dts: imx6q: add a new device node for ecspi1

[Huang Shijie]

? 2013?05?09? 11:28, Huang Shijie ??:
> Signed-off-by: Huang Shijie <b32955@freescale.com>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |   11 +++++++++++
>  1 files changed, 11 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index ed11bcf..5601026 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -59,6 +59,17 @@
>  	soc {
>  		aips-bus at 02000000 { /* AIPS1 */
>  			spba-bus at 02000000 {
> +				ecspi1: ecspi at 02008000 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> +					reg = <0x02008000 0x4000>;
> +					interrupts = <0 31 0x04>;
> +					clocks = <&clks 112>, <&clks 112>;
> +					clock-names = "ipg", "per";
> +					status = "disabled";
> +				};
> +
>  				ecspi5: ecspi at 02018000 {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
Please ignore this single patch.

the eCSPI1 has been added in the imx6qdl.dtsi.

so this patch is redundant.

thanks
Huang Shijie

[PATCH 2/5] ARM: dts: imx6dl: add a pinctrl for eCSPI1

[Huang Shijie]

Signed-off-by: Huang Shijie <b32955@freescale.com>
---
 arch/arm/boot/dts/imx6dl.dtsi |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 24544ed..4b13454 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -35,6 +35,16 @@
 				compatible = "fsl,imx6dl-iomuxc";
 				reg = <0x020e0000 0x4000>;
 
+				ecspi1 {
+					pinctrl_ecspi1_1: ecspi1grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+							MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+							MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+						>;
+					};
+				};
+
 				enet {
 					pinctrl_enet_1: enetgrp-1 {
 						fsl,pins = <
-- 
1.7.1

[PATCH 3/5] ARM: dts: imx6dl: add a gpio for hog

[Huang Shijie]

The SPI/NOR needs this gpio for CS.
So add this gpio in the hog pinctrl.

Signed-off-by: Huang Shijie <b32955@freescale.com>
---
 arch/arm/boot/dts/imx6dl-sabreauto.dts |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 7adcec3..60f3038 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -25,6 +25,7 @@
 			fsl,pins = <
 				MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6DL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
+				MX6DL_PAD_EIM_D19__GPIO3_IO19 	0x80000000
 			>;
 		};
 	};
-- 
1.7.1

[PATCH 4/5] ARM: dts: imx6q: add a gpio for hog

[Huang Shijie]

The SPI/NOR needs this gpio for CS.
So add this gpio in the hog pinctrl.

Signed-off-by: Huang Shijie <b32955@freescale.com>
---
 arch/arm/boot/dts/imx6q-sabreauto.dts |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 49d6f28..9fb3e99 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -29,6 +29,7 @@
 			fsl,pins = <
 				MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 				MX6Q_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
+				MX6Q_PAD_EIM_D19__GPIO3_IO19   0x80000000
 			>;
 		};
 	};
-- 
1.7.1

[PATCH 5/5] ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards

[Huang Shijie]

Since the SPI/NOR has pin conflict with the WEIM NOR,
we disable the spi/nor by default.

Signed-off-by: Huang Shijie <b32955@freescale.com>
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   32 ++++++++++++++++++++++++++++++
 1 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 7b561fb..b6b9e56 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -16,6 +16,38 @@
 	};
 };
 
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio3 19 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1_1>;
+	status = "disabled";
+
+	flash: m25p80 at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+
+		partition at 0 {
+			label = "U-Boot";
+			reg = <0x0 0x40000>;
+		};
+
+		partition at 40000 {
+			label = "U-Boot-ENV";
+			reg = <0x40000 0x10000>;
+			read-only;
+		};
+
+		partition at 50000 {
+			label = "Kernel";
+			reg = <0x50000 0x3b0000>;
+		};
+	};
+};
+
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet_2>;
-- 
1.7.1

[PATCH 5/5] ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards

[Shawn Guo]

On Thu, May 09, 2013 at 11:29:03AM +0800, Huang Shijie wrote:
> Since the SPI/NOR has pin conflict with the WEIM NOR,
> we disable the spi/nor by default.
> 
> Signed-off-by: Huang Shijie <b32955@freescale.com>
> ---
>  arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   32 ++++++++++++++++++++++++++++++
>  1 files changed, 32 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> index 7b561fb..b6b9e56 100644
> --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> @@ -16,6 +16,38 @@
>  	};
>  };
>  
> +&ecspi1 {
> +	fsl,spi-num-chipselects = <1>;
> +	cs-gpios = <&gpio3 19 0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ecspi1_1>;
> +	status = "disabled";

I added a comment to it as below, and applied patch #2~5.

	status = "disabled"; /* pin conflict with WEIM NOR */

Shawn

[PATCH 5/5] ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards

[Sascha Hauer]

On Thu, May 09, 2013 at 11:29:03AM +0800, Huang Shijie wrote:
> Since the SPI/NOR has pin conflict with the WEIM NOR,
> we disable the spi/nor by default.
> 
> Signed-off-by: Huang Shijie <b32955@freescale.com>
> ---
>  arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   32 ++++++++++++++++++++++++++++++
>  1 files changed, 32 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> index 7b561fb..b6b9e56 100644
> --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> @@ -16,6 +16,38 @@
>  	};
>  };
>  
> +&ecspi1 {
> +	fsl,spi-num-chipselects = <1>;
> +	cs-gpios = <&gpio3 19 0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ecspi1_1>;
> +	status = "disabled";
> +
> +	flash: m25p80 at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "st,m25p32";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +
> +		partition at 0 {
> +			label = "U-Boot";
> +			reg = <0x0 0x40000>;
> +		};
> +
> +		partition at 40000 {
> +			label = "U-Boot-ENV";
> +			reg = <0x40000 0x10000>;
> +			read-only;
> +		};
> +
> +		partition at 50000 {
> +			label = "Kernel";
> +			reg = <0x50000 0x3b0000>;
> +		};

I really object to enforcing partition layouts in the devicetree. That's
clearly usecase specific and should be filled by the bootloader. Having
no partitions normally is not harmful, but having the wrong layout just
because we start a mainline devicetree really can be harmful.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 5/5] ARM: dts: add SPI/NOR for mx6q{dl}-sabreauto boards

[Shawn Guo]

On Sun, May 12, 2013 at 04:43:39PM +0200, Sascha Hauer wrote:
> On Thu, May 09, 2013 at 11:29:03AM +0800, Huang Shijie wrote:
> > Since the SPI/NOR has pin conflict with the WEIM NOR,
> > we disable the spi/nor by default.
> > 
> > Signed-off-by: Huang Shijie <b32955@freescale.com>
> > ---
> >  arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |   32 ++++++++++++++++++++++++++++++
> >  1 files changed, 32 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> > index 7b561fb..b6b9e56 100644
> > --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> > +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
> > @@ -16,6 +16,38 @@
> >  	};
> >  };
> >  
> > +&ecspi1 {
> > +	fsl,spi-num-chipselects = <1>;
> > +	cs-gpios = <&gpio3 19 0>;
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_ecspi1_1>;
> > +	status = "disabled";
> > +
> > +	flash: m25p80 at 0 {
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		compatible = "st,m25p32";
> > +		spi-max-frequency = <20000000>;
> > +		reg = <0>;
> > +
> > +		partition at 0 {
> > +			label = "U-Boot";
> > +			reg = <0x0 0x40000>;
> > +		};
> > +
> > +		partition at 40000 {
> > +			label = "U-Boot-ENV";
> > +			reg = <0x40000 0x10000>;
> > +			read-only;
> > +		};
> > +
> > +		partition at 50000 {
> > +			label = "Kernel";
> > +			reg = <0x50000 0x3b0000>;
> > +		};
> 
> I really object to enforcing partition layouts in the devicetree. That's
> clearly usecase specific and should be filled by the bootloader. Having
> no partitions normally is not harmful, but having the wrong layout just
> because we start a mainline devicetree really can be harmful.

Ah, yes.  I recall the discussion you had with people a couple of weeks
ago.  I agreed with your opinion.  Just fixed it up with partition
layouts removed.

Shawn