[PATCH 00/21] ARM: ux500: Enable Clock look-up from Device Tree

[PATCH 00/21] ARM: ux500: Enable Clock look-up from Device Tree

[Lee Jones]

Nice and simple implementation using standard Clk APIs.

 arch/arm/boot/dts/dbx5x0.dtsi    |   94 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 arch/arm/boot/dts/snowball.dts   |    3 ++-
 arch/arm/mach-ux500/cpu-db8500.c |   36 +--------------------------
 drivers/clk/ux500/u8500_clk.c    |  154 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 4 files changed, 249 insertions(+), 38 deletions(-)

[PATCH 01/21] ARM: ux500: Supply the PRCMU Clock node

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index fd5794a..6c445d5 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -243,7 +243,13 @@
 				interrupts = <21 0x4>, <22 0x4>;
 				interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 				status = "disabled";
-			 };
+			};
+
+			clk: prcmu-clock {
+				compatible = "stericsson,u8500-clk";
+
+				#clock-cells = <1>;
+			};
 
 			db8500-prcmu-regulators {
 				compatible = "stericsson,db8500-prcmu-regulator";
-- 
1.7.10.4

[PATCH 02/21] ARM: ux500: Supply the Ethernet clock lookup to Snowball's DT

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/snowball.dts |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index db5db24..cb37851 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -137,12 +137,13 @@
 				vdd33a-supply = <&en_3v3_reg>;
 				vddvario-supply = <&db8500_vape_reg>;
 
-
 				reg-shift = <1>;
 				reg-io-width = <2>;
 				smsc,force-internal-phy;
 				smsc,irq-active-high;
 				smsc,irq-push-pull;
+
+				clocks = <&clk 64>;
 			};
 		};
 
-- 
1.7.10.4

[PATCH 03/21] ARM: ux500: Supply the TWD Timer clock lookup to the DBX500 DT

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 6c445d5..6eec1cd 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -45,6 +45,8 @@
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xa0410600 0x20>;
 			interrupts = <1 13 0x304>;
+
+			clocks = <&clk 39>;
 		};
 
 		rtc at 80154000 {
-- 
1.7.10.4

[PATCH 04/21] ARM: ux500: Supply the RTC clock lookup to the DBX500 DT

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 6eec1cd..fe7cb84 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -53,6 +53,9 @@
 			compatible = "arm,rtc-pl031", "arm,primecell";
 			reg = <0x80154000 0x1000>;
 			interrupts = <0 18 0x4>;
+
+			clocks = <&clk 3>;
+			clock-names = "apb_pclk";
 		};
 
 		gpio0: gpio at 8012e000 {
-- 
1.7.10.4

[PATCH 05/21] ARM: ux500: Supply the GPIO clocks lookup to the DBX500 DT

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index fe7cb84..fa3fd41 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -69,6 +69,8 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-bank = <0>;
+
+			clocks = <&clk 49>;
 		};
 
 		gpio1: gpio at 8012e080 {
@@ -82,6 +84,8 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-bank = <1>;
+
+			clocks = <&clk 49>;
 		};
 
 		gpio2: gpio at 8000e000 {
@@ -95,6 +99,8 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-bank = <2>;
+
+			clocks = <&clk 72>;
 		};
 
 		gpio3: gpio at 8000e080 {
@@ -108,6 +114,8 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-bank = <3>;
+
+			clocks = <&clk 72>;
 		};
 
 		gpio4: gpio at 8000e100 {
@@ -121,6 +129,8 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-bank = <4>;
+
+			clocks = <&clk 72>;
 		};
 
 		gpio5: gpio at 8000e180 {
@@ -134,6 +144,8 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-bank = <5>;
+
+			clocks = <&clk 72>;
 		};
 
 		gpio6: gpio at 8011e000 {
@@ -147,6 +159,8 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-bank = <6>;
+
+			clocks = <&clk 63>;
 		};
 
 		gpio7: gpio at 8011e080 {
@@ -160,6 +174,8 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-bank = <7>;
+
+			clocks = <&clk 63>;
 		};
 
 		gpio8: gpio at a03fe000 {
@@ -173,6 +189,8 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-bank = <8>;
+
+			clocks = <&clk 74>;
 		};
 
 		pinctrl {
-- 
1.7.10.4

[PATCH 06/21] ARM: ux500: Supply the USB clock lookup to the DBX500 DT

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index fa3fd41..c5acbc9 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -232,6 +232,8 @@
 				    "iep_6_14", "oep_6_14",
 				    "iep_7_15", "oep_7_15",
 				    "iep_8",    "oep_8";
+
+			clocks = <&clk 73>;
 		};
 
 		dma: dma-controller at 801C0000 {
-- 
1.7.10.4

[PATCH 07/21] ARM: ux500: Supply the DMA clock lookup to the DBX500 DT

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index c5acbc9..3acc528 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -244,6 +244,8 @@
 
 			#dma-cells = <3>;
 			memcpy-channels = <56 57 58 59 60>;
+
+			clocks = <&clk 24>;
 		};
 
 		prcmu: prcmu at 80157000 {
-- 
1.7.10.4

[PATCH 08/21] ARM: ux500: Supply the I2C clocks lookup to the DBX500 DT

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 3acc528..659865d 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -559,6 +559,8 @@
 			v-i2c-supply = <&db8500_vape_reg>;
 
 			clock-frequency = <400000>;
+			clocks = <&clk 100>, <&clk 67>;
+			clock-names = "nmk-i2c.0", "apb_pclk";
 		};
 
 		i2c at 80122000 {
@@ -572,6 +574,9 @@
 			v-i2c-supply = <&db8500_vape_reg>;
 
 			clock-frequency = <400000>;
+
+			clocks = <&clk 85>, <&clk 42>;
+			clock-names = "nmk-i2c.1", "apb_pclk";
 		};
 
 		i2c at 80128000 {
@@ -585,6 +590,9 @@
 			v-i2c-supply = <&db8500_vape_reg>;
 
 			clock-frequency = <400000>;
+
+			clocks = <&clk 89>, <&clk 46>;
+			clock-names = "nmk-i2c.2", "apb_pclk";
 		};
 
 		i2c at 80110000 {
@@ -598,6 +606,9 @@
 			v-i2c-supply = <&db8500_vape_reg>;
 
 			clock-frequency = <400000>;
+
+			clocks = <&clk 93>, <&clk 52>;
+			clock-names = "nmk-i2c.3", "apb_pclk";
 		};
 
 		i2c at 8012a000 {
@@ -611,6 +622,9 @@
 			v-i2c-supply = <&db8500_vape_reg>;
 
 			clock-frequency = <400000>;
+
+			clocks = <&clk 91>, <&clk 50>;
+			clock-names = "nmk-i2c.4", "apb_pclk";
 		};
 
 		ssp at 80002000 {
-- 
1.7.10.4

[PATCH 08/21] ARM: ux500: Supply the I2C clocks lookup to the DBX500 DT

[Arnd Bergmann]

On Monday 03 June 2013 14:42:32 Lee Jones wrote:
> @@ -559,6 +559,8 @@
>                         v-i2c-supply = <&db8500_vape_reg>;
>  
>                         clock-frequency = <400000>;
> +                       clocks = <&clk 100>, <&clk 67>;
> +                       clock-names = "nmk-i2c.0", "apb_pclk";
>                 };
>  
>                 i2c at 80122000 {
> @@ -572,6 +574,9 @@
>                         v-i2c-supply = <&db8500_vape_reg>;
>  
>                         clock-frequency = <400000>;
> +
> +                       clocks = <&clk 85>, <&clk 42>;
> +                       clock-names = "nmk-i2c.1", "apb_pclk";
>                 };

Same comment actually as for the uart patch, also SDI and MSP
have the same problem.

	Arnd

[PATCH 08/21] ARM: ux500: Supply the I2C clocks lookup to the DBX500 DT

[Lee Jones]

On Mon, 03 Jun 2013, Arnd Bergmann wrote:

> On Monday 03 June 2013 14:42:32 Lee Jones wrote:
> > @@ -559,6 +559,8 @@
> >                         v-i2c-supply = <&db8500_vape_reg>;
> >  
> >                         clock-frequency = <400000>;
> > +                       clocks = <&clk 100>, <&clk 67>;
> > +                       clock-names = "nmk-i2c.0", "apb_pclk";
> >                 };
> >  
> >                 i2c at 80122000 {
> > @@ -572,6 +574,9 @@
> >                         v-i2c-supply = <&db8500_vape_reg>;
> >  
> >                         clock-frequency = <400000>;
> > +
> > +                       clocks = <&clk 85>, <&clk 42>;
> > +                       clock-names = "nmk-i2c.1", "apb_pclk";
> >                 };
> 
> Same comment actually as for the uart patch, also SDI and MSP
> have the same problem.

I was only using the names in the same manor as the API does, to fetch
the 'clocks =' index. Do you mean that I should be using 'uartclk',
'i2cclk', 'sdmmcclk' and 'msp1clk' instead?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH 08/21] ARM: ux500: Supply the I2C clocks lookup to the DBX500 DT

[Arnd Bergmann]

On Monday 03 June 2013 15:27:55 Lee Jones wrote:
> On Mon, 03 Jun 2013, Arnd Bergmann wrote:
> 
> > On Monday 03 June 2013 14:42:32 Lee Jones wrote:
> > > @@ -559,6 +559,8 @@
> > >                         v-i2c-supply = <&db8500_vape_reg>;
> > >  
> > >                         clock-frequency = <400000>;
> > > +                       clocks = <&clk 100>, <&clk 67>;
> > > +                       clock-names = "nmk-i2c.0", "apb_pclk";
> > >                 };
> > >  
> > >                 i2c at 80122000 {
> > > @@ -572,6 +574,9 @@
> > >                         v-i2c-supply = <&db8500_vape_reg>;
> > >  
> > >                         clock-frequency = <400000>;
> > > +
> > > +                       clocks = <&clk 85>, <&clk 42>;
> > > +                       clock-names = "nmk-i2c.1", "apb_pclk";
> > >                 };
> > 
> > Same comment actually as for the uart patch, also SDI and MSP
> > have the same problem.
> 
> I was only using the names in the same manor as the API does, to fetch
> the 'clocks =' index. Do you mean that I should be using 'uartclk',
> 'i2cclk', 'sdmmcclk' and 'msp1clk' instead?

Yes, that would be better. I suppose you can actually leave out the
'clk' part and just call them 'i2c', 'sdmmc', 'msp' and 'uart',
but you should check if any of the driver already specify the
clock names in their DT bindings.

	Arnd

[PATCH 09/21] ARM: ux500: Supply the UART clocks lookup to the DBX500 DT

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 659865d..f2fe7d9 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -650,6 +650,9 @@
 			       <&dma 13 0 0x0>; /* Logical - MemToDev */
 			dma-names = "rx", "tx";
 
+			clocks = <&clk 83>, <&clk 40>;
+			clock-names = "uart0", "apb_pclk";
+
 			status = "disabled";
 		};
 
@@ -662,6 +665,9 @@
 			       <&dma 12 0 0x0>; /* Logical - MemToDev */
 			dma-names = "rx", "tx";
 
+			clocks = <&clk 84>, <&clk 41>;
+			clock-names = "uart1", "apb_pclk";
+
 			status = "disabled";
 		};
 
@@ -674,6 +680,9 @@
 			       <&dma 11 0 0x0>; /* Logical - MemToDev */
 			dma-names = "rx", "tx";
 
+			clocks = <&clk 103>, <&clk 70>;
+			clock-names = "uart2", "apb_pclk";
+
 			status = "disabled";
 		};
 
@@ -686,6 +695,9 @@
 			       <&dma 29 0 0x0>; /* Logical - MemToDev */
 			dma-names = "rx", "tx";
 
+			clocks = <&clk 88>, <&clk 45>;
+			clock-names = "uart3", "apb_pclk";
+
 			status = "disabled";
 		};
 
-- 
1.7.10.4

[PATCH 09/21] ARM: ux500: Supply the UART clocks lookup to the DBX500 DT

[Arnd Bergmann]

On Monday 03 June 2013 14:42:33 Lee Jones wrote:
> @@ -650,6 +650,9 @@
>                                <&dma 13 0 0x0>; /* Logical - MemToDev */
>                         dma-names = "rx", "tx";
>  
> +                       clocks = <&clk 83>, <&clk 40>;
> +                       clock-names = "uart0", "apb_pclk";
> +
>                         status = "disabled";
>                 };
>  
> @@ -662,6 +665,9 @@
>                                <&dma 12 0 0x0>; /* Logical - MemToDev */
>                         dma-names = "rx", "tx";
>  
> +                       clocks = <&clk 84>, <&clk 41>;
> +                       clock-names = "uart1", "apb_pclk";
> +
>                         status = "disabled";
>                 };
>  

This seems wrong: why would one of them have a clock named "uart0"
and the other one call it "uart1"? The clock name should be defined
in the binding and specific to the driver using it, not a string that
indicates where it is connected to.

	Arnd

[PATCH 10/21] ARM: ux500: Supply the SDI (MMC) clocks lookup to the DBX500 DT

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index f2fe7d9..e5a5e9f 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -710,6 +710,9 @@
 			       <&dma 32 0 0x0>; /* Logical - MemToDev */
 			dma-names = "rx", "tx";
 
+			clocks = <&clk 96>, <&clk 58>;
+			clock-names = "sdi1", "apb_pclk";
+
 			status = "disabled";
 		};
 
@@ -722,6 +725,9 @@
 			       <&dma 28 0 0x0>; /* Logical - MemToDev */
 			dma-names = "rx", "tx";
 
+			clocks = <&clk 101>, <&clk 68>;
+			clock-names = "sdi2", "apb_pclk";
+
 			status = "disabled";
 		};
 
@@ -729,6 +735,10 @@
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80119000 0x1000>;
 			interrupts = <0 59 0x4>;
+
+			clocks = <&clk 97>, <&clk 59>;
+			clock-names = "sdi3", "apb_pclk";
+
 			status = "disabled";
 		};
 
@@ -741,6 +751,9 @@
 			       <&dma 42 0 0x0>; /* Logical - MemToDev */
 			dma-names = "rx", "tx";
 
+			clocks = <&clk 94>, <&clk 56>;
+			clock-names = "sdi4", "apb_pclk";
+
 			status = "disabled";
 		};
 
@@ -748,6 +761,10 @@
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80008000 0x1000>;
 			interrupts = <0 100 0x4>;
+
+			clocks = <&clk 104>, <&clk 71>;
+			clock-names = "sdi5", "apb_pclk";
+
 			status = "disabled";
 		};
 
-- 
1.7.10.4

[PATCH 11/21] ARM: ux500: Supply the MSP (Audio) clocks lookup to the DBX500 DT

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index e5a5e9f..4701e75 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -773,6 +773,10 @@
 			reg = <0x80123000 0x1000>;
 			interrupts = <0 31 0x4>;
 			v-ape-supply = <&db8500_vape_reg>;
+
+			clocks = <&clk 86>, <&clk 43>;
+			clock-names = "msp0", "apb_pclk";
+
 			status = "disabled";
 		};
 
@@ -781,6 +785,10 @@
 			reg = <0x80124000 0x1000>;
 			interrupts = <0 62 0x4>;
 			v-ape-supply = <&db8500_vape_reg>;
+
+			clocks = <&clk 87>, <&clk 44>;
+			clock-names = "msp1", "apb_pclk";
+
 			status = "disabled";
 		};
 
@@ -790,6 +798,10 @@
 			reg = <0x80117000 0x1000>;
 			interrupts = <0 98 0x4>;
 			v-ape-supply = <&db8500_vape_reg>;
+
+			clocks = <&clk 95>, <&clk 57>;
+			clock-names = "msp2", "apb_pclk";
+
 			status = "disabled";
 		};
 
@@ -798,6 +810,10 @@
 			reg = <0x80125000 0x1000>;
 			interrupts = <0 62 0x4>;
 			v-ape-supply = <&db8500_vape_reg>;
+
+			clocks = <&clk 92>, <&clk 51>;
+			clock-names = "msp3", "apb_pclk";
+
 			status = "disabled";
 		};
 
-- 
1.7.10.4

[PATCH 12/21] ARM: ux500: Remove AUXDATA relating to GPIO clock-name bindings

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    9 ---------
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 3b77e36..53187fc 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -228,15 +228,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  NULL),
-	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
-	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
-	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
-	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
-	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
-	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
-	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
-	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
-	OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
-- 
1.7.10.4

[PATCH 13/21] ARM: ux500: Remove AUXDATA relating to UART clock-name bindings

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 53187fc..8cdbd20 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -221,9 +221,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires DMA bindings. */
 	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 	/* Requires clock name bindings. */
-	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
-	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
-	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  NULL),
 	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  NULL),
-- 
1.7.10.4

[PATCH 14/21] ARM: ux500: Remove AUXDATA relating to SDI (MMC) clock-name bindings

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 8cdbd20..ad4250f 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -221,10 +221,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires DMA bindings. */
 	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 	/* Requires clock name bindings. */
-	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  NULL),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  NULL),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  NULL),
-	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  NULL),
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
-- 
1.7.10.4

[PATCH 15/21] ARM: ux500: Remove AUXDATA relating to I2C clock-name bindings

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index ad4250f..d57667c 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -221,11 +221,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires DMA bindings. */
 	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 	/* Requires clock name bindings. */
-	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
-	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
-	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
-	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
-	OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
 	OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL),
 	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 			&db8500_prcmu_pdata),
-- 
1.7.10.4

[PATCH 16/21] ARM: ux500: Remove AUXDATA relating to MSP (Audio) clock-name bindings

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    9 ---------
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index d57667c..87406d8 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -228,15 +228,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires device name bindings. */
 	OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
 		"pinctrl-db8500", NULL),
-	/* Requires clock name and DMA bindings. */
-	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
-		"ux500-msp-i2s.0", &msp0_platform_data),
-	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
-		"ux500-msp-i2s.1", &msp1_platform_data),
-	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
-		"ux500-msp-i2s.2", &msp2_platform_data),
-	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
-		"ux500-msp-i2s.3", &msp3_platform_data),
 	/* Requires clock name bindings and channel address lookup table. */
 	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
 	{},
-- 
1.7.10.4

[PATCH 17/21] ARM: ux500: Remove AUXDATA relating to USB clock-name bindings

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 87406d8..a137813 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -221,7 +221,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires DMA bindings. */
 	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 	/* Requires clock name bindings. */
-	OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL),
 	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 			&db8500_prcmu_pdata),
 	OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
-- 
1.7.10.4

[PATCH 18/21] ARM: ux500: Remove AUXDATA relating to Ethernet clock-name bindings

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index a137813..e93548b 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -223,7 +223,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires clock name bindings. */
 	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 			&db8500_prcmu_pdata),
-	OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
 	/* Requires device name bindings. */
 	OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
 		"pinctrl-db8500", NULL),
-- 
1.7.10.4

[PATCH 19/21] ARM: ux500: Remove AUXDATA relating to DMA clock-name bindings

[Lee Jones]

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index e93548b..ddea9c7 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -226,8 +226,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires device name bindings. */
 	OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
 		"pinctrl-db8500", NULL),
-	/* Requires clock name bindings and channel address lookup table. */
-	OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
 	{},
 };
 
-- 
1.7.10.4

[PATCH 20/21] ARM: ux500: Reclassify PRCMU AUXDATA entry

[Lee Jones]

We still need to utilise the AUXDATA system for the PRCMU to pass
through platform data which can not be DT:ed i.e. regulator initialisation
values. All we're doing in this patch is changing the comment header to be
more accurate.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 arch/arm/mach-ux500/cpu-db8500.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index ddea9c7..5f9b089 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -220,7 +220,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
 	/* Requires DMA bindings. */
 	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
-	/* Requires clock name bindings. */
+	/* Requires non-DT:able platform data. */
 	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 			&db8500_prcmu_pdata),
 	/* Requires device name bindings. */
-- 
1.7.10.4

[PATCH 21/21] clk: ux500: Supply provider look-up functionality to support Device Tree

[Lee Jones]

In this patch we're populating a clk_data array, one clock per element to
act as a clk look-up using indexes supplied from Device Tree.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/clk/ux500/u8500_clk.c |  154 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 153 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 80069c3..9b4d8d9 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -7,6 +7,7 @@
  * License terms: GNU General Public License (GPL) version 2
  */
 
+#include <linux/of.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
@@ -14,25 +15,66 @@
 #include <linux/platform_data/clk-ux500.h>
 #include "clk.h"
 
+/*
+ * Important:
+ * Only add clocks to the end. Do not remove or change the order of the clocks.
+ */
+enum u8500_clk {
+	soc0_pll      = 0,   soc1_pll, ddr_pll, rtc_pl031, mali,
+	uart          = 5,   msp2clk, msp1clk, i2c, slim,
+	per1          = 10,  per2, per3, per5, per6,
+	per7          = 15,  lcd, bml, hdmi, apeat,
+	apetrace      = 20,  dsilink, ipi2, dsialt, dma,
+	b2r2          = 25,  tv, ssp, rngclk, uicc,
+	mtu           = 30,  sdmmc, dsihs2, dsihs0, dsihs1,
+	dsilp0        = 35,  dsilp1, dsilp2, armss, smp_twd,
+	uart0         = 40,  uart1, nmk_i2c1, msp0, msp1,
+	sdi0          = 45,  nmk_i2c2, spi3, slimbus0, gpioblock0,
+	nmk_i2c4      = 50,  msp3, nmk_i2c3, spi2, spi1,
+	pwl           = 55,  sdi4, msp2, sdi1, sdi3,
+	spi0          = 60,  hsir_hclk, hsit_hclk, gpioblock1, fsmc,
+	ssp0          = 65,  ssp1, nmk_i2c0, sdi2, ske,
+	uart2         = 70,  sdi5, gpioblock2, musb, gpioblock3,
+	rng           = 75,  crypt, hash0, pka, hash1,
+	cfgreg        = 80,  mtu0, mtu1, per1_uart0, per1_uart1,
+	per1_nmk_i2c1 = 85,  per1_msp0, per1_msp1, per1_sdi0, per1_nmk_i2c2,
+	per1_slimbus0 = 90,  per1_nmk_i2c4, per1_msp3, per2_nmk_i2c3, per2_sdi4,
+	per2_msp2     = 95,  per2_sdi1, per2_sdi3, per3_ssp0, per3_ssp1,
+	per3_nmk_i2c0 = 100, per3_sdi2, per3_ske, per3_uart2, per3_sdi5,
+	per6_rng      = 105, /* New clks go here. */ CLK_MAX,
+};
+
+struct clk *clks[CLK_MAX];
+
+const static struct of_device_id u8500_clk_of_match[] = {
+	{ .compatible = "stericsson,u8500-clk", },
+	{ },
+};
+
 void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 		    u32 clkrst5_base, u32 clkrst6_base)
 {
 	struct prcmu_fw_version *fw_version;
 	const char *sgaclk_parent = NULL;
+	static struct clk_onecell_data clk_data;
+	struct device_node *np = NULL;
 	struct clk *clk;
 
 	/* Clock sources */
 	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
 				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
 	clk_register_clkdev(clk, "soc0_pll", NULL);
+	clks[soc0_pll] = clk;
 
 	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
 				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
 	clk_register_clkdev(clk, "soc1_pll", NULL);
+	clks[soc1_pll] = clk;
 
 	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
 				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
 	clk_register_clkdev(clk, "ddr_pll", NULL);
+	clks[ddr_pll] = clk;
 
 	/* FIXME: Add sys, ulp and int clocks here. */
 
@@ -41,6 +83,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 				32768);
 	clk_register_clkdev(clk, "clk32k", NULL);
 	clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
+	clks[rtc_pl031] = clk;
 
 	/* PRCMU clocks */
 	fw_version = prcmu_get_fw_version();
@@ -63,47 +106,61 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 		clk = clk_reg_prcmu_gate("sgclk", NULL,
 					PRCMU_SGACLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "mali");
+	clks[mali] = clk;
 
 	clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "UART");
+	clks[uart] = clk;
 
 	clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "MSP02");
+	clks[msp2clk] = clk;
 
 	clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "MSP1");
+	clks[msp1clk] = clk;
 
 	clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "I2C");
+	clks[i2c] = clk;
 
 	clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "slim");
+	clks[slim] = clk;
 
 	clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "PERIPH1");
+	clks[per1] = clk;
 
 	clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "PERIPH2");
+	clks[per2] = clk;
 
 	clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "PERIPH3");
+	clks[per3] = clk;
 
 	clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "PERIPH5");
+	clks[per5] = clk;
 
 	clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "PERIPH6");
+	clks[per6] = clk;
 
 	clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "PERIPH7");
+	clks[per7] = clk;
 
 	clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
 				CLK_IS_ROOT|CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "lcd");
 	clk_register_clkdev(clk, "lcd", "mcde");
+	clks[lcd] = clk;
 
 	clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "bml");
+	clks[bml] = clk;
 
 	clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
 				CLK_IS_ROOT|CLK_SET_RATE_GATE);
@@ -115,13 +172,16 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 				CLK_IS_ROOT|CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "hdmi");
 	clk_register_clkdev(clk, "hdmi", "mcde");
+	clks[hdmi] = clk;
 
 	clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "apeat");
+	clks[apeat] = clk;
 
 	clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
 				CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "apetrace");
+	clks[apetrace] = clk;
 
 	clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "mcde");
@@ -129,84 +189,102 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 	clk_register_clkdev(clk, "dsisys", "dsilink.0");
 	clk_register_clkdev(clk, "dsisys", "dsilink.1");
 	clk_register_clkdev(clk, "dsisys", "dsilink.2");
+	clks[dsilink] = clk;
 
 	clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
 				CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "ipi2");
+	clks[ipi2] = clk;
 
 	clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
 				CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "dsialt");
+	clks[dsialt] = clk;
 
 	clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "dma40.0");
+	clks[dma] = clk;
 
 	clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "b2r2");
 	clk_register_clkdev(clk, NULL, "b2r2_core");
 	clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
+	clks[b2r2] = clk;
 
 	clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
 				CLK_IS_ROOT|CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "tv");
 	clk_register_clkdev(clk, "tv", "mcde");
+	clks[tv] = clk;
 
 	clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "SSP");
+	clks[ssp] = clk;
 
 	clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "rngclk");
+	clks[rngclk] = clk;
 
 	clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "uicc");
+	clks[uicc] = clk;
 
 	clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
 	clk_register_clkdev(clk, NULL, "mtu0");
 	clk_register_clkdev(clk, NULL, "mtu1");
+	clks[mtu] = clk;
 
 	clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
 					100000000,
 					CLK_IS_ROOT|CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "sdmmc");
+	clks[sdmmc] = clk;
 
 	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
 				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, "dsihs2", "mcde");
 	clk_register_clkdev(clk, "dsihs2", "dsilink.2");
-
+	clks[dsihs2] = clk;
 
 	clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
 				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, "dsihs0", "mcde");
 	clk_register_clkdev(clk, "dsihs0", "dsilink.0");
+	clks[dsihs0] = clk;
 
 	clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
 				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, "dsihs1", "mcde");
 	clk_register_clkdev(clk, "dsihs1", "dsilink.1");
+	clks[dsihs1] = clk;
 
 	clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
 				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, "dsilp0", "dsilink.0");
 	clk_register_clkdev(clk, "dsilp0", "mcde");
+	clks[dsilp0] = clk;
 
 	clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
 				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, "dsilp1", "dsilink.1");
 	clk_register_clkdev(clk, "dsilp1", "mcde");
+	clks[dsilp1] = clk;
 
 	clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
 				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, "dsilp2", "dsilink.2");
 	clk_register_clkdev(clk, "dsilp2", "mcde");
+	clks[dsilp2] = clk;
 
 	clk = clk_reg_prcmu_scalable_rate("armss", NULL,
 				PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
 	clk_register_clkdev(clk, "armss", NULL);
+	clks[armss] = clk;
 
 	clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
 				CLK_IGNORE_UNUSED, 1, 2);
 	clk_register_clkdev(clk, NULL, "smp_twd");
+	clks[smp_twd] = clk;
 
 	/*
 	 * FIXME: Add special handled PRCMU clocks here:
@@ -218,106 +296,130 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
 				BIT(0), 0);
 	clk_register_clkdev(clk, "apb_pclk", "uart0");
+	clks[uart0] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
 				BIT(1), 0);
 	clk_register_clkdev(clk, "apb_pclk", "uart1");
+	clks[uart1] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
 				BIT(2), 0);
 	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
+	clks[nmk_i2c1] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
 				BIT(3), 0);
 	clk_register_clkdev(clk, "apb_pclk", "msp0");
 	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");
+	clks[msp0] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
 				BIT(4), 0);
 	clk_register_clkdev(clk, "apb_pclk", "msp1");
 	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");
+	clks[msp1] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
 				BIT(5), 0);
 	clk_register_clkdev(clk, "apb_pclk", "sdi0");
+	clks[sdi0] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
 				BIT(6), 0);
 	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
+	clks[nmk_i2c2] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
 				BIT(7), 0);
 	clk_register_clkdev(clk, NULL, "spi3");
+	clks[spi3] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
 				BIT(8), 0);
 	clk_register_clkdev(clk, "apb_pclk", "slimbus0");
+	clks[slimbus0] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
 				BIT(9), 0);
 	clk_register_clkdev(clk, NULL, "gpio.0");
 	clk_register_clkdev(clk, NULL, "gpio.1");
 	clk_register_clkdev(clk, NULL, "gpioblock0");
+	clks[gpioblock0] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
 				BIT(10), 0);
 	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
+	clks[nmk_i2c4] = clk;
 
 	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
 				BIT(11), 0);
 	clk_register_clkdev(clk, "apb_pclk", "msp3");
 	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");
+	clks[msp3] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
 				BIT(0), 0);
 	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
+	clks[nmk_i2c3] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
 				BIT(1), 0);
 	clk_register_clkdev(clk, NULL, "spi2");
+	clks[spi2] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
 				BIT(2), 0);
 	clk_register_clkdev(clk, NULL, "spi1");
+	clks[spi1] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
 				BIT(3), 0);
 	clk_register_clkdev(clk, NULL, "pwl");
+	clks[pwl] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
 				BIT(4), 0);
 	clk_register_clkdev(clk, "apb_pclk", "sdi4");
+	clks[sdi4] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
 				BIT(5), 0);
 	clk_register_clkdev(clk, "apb_pclk", "msp2");
 	clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");
+	clks[msp2] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
 				BIT(6), 0);
 	clk_register_clkdev(clk, "apb_pclk", "sdi1");
+	clks[sdi1] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
 				BIT(7), 0);
 	clk_register_clkdev(clk, "apb_pclk", "sdi3");
+	clks[sdi3] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
 				BIT(8), 0);
 	clk_register_clkdev(clk, NULL, "spi0");
+	clks[spi0] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
 				BIT(9), 0);
 	clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
+	clks[hsir_hclk] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
 				BIT(10), 0);
 	clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
+	clks[hsit_hclk] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
 				BIT(11), 0);
 	clk_register_clkdev(clk, NULL, "gpio.6");
 	clk_register_clkdev(clk, NULL, "gpio.7");
 	clk_register_clkdev(clk, NULL, "gpioblock1");
+	clks[gpioblock1] = clk;
 
 	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
 				BIT(12), 0);
@@ -326,35 +428,43 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 				BIT(0), 0);
 	clk_register_clkdev(clk, "fsmc", NULL);
 	clk_register_clkdev(clk, NULL, "smsc911x.0");
+	clks[fsmc] = clk;
 
 	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
 				BIT(1), 0);
 	clk_register_clkdev(clk, "apb_pclk", "ssp0");
+	clks[ssp0] = clk;
 
 	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
 				BIT(2), 0);
 	clk_register_clkdev(clk, "apb_pclk", "ssp1");
+	clks[ssp1] = clk;
 
 	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
 				BIT(3), 0);
 	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
+	clks[nmk_i2c0] = clk;
 
 	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
 				BIT(4), 0);
 	clk_register_clkdev(clk, "apb_pclk", "sdi2");
+	clks[sdi2] = clk;
 
 	clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
 				BIT(5), 0);
 	clk_register_clkdev(clk, "apb_pclk", "ske");
 	clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
+	clks[ske] = clk;
 
 	clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
 				BIT(6), 0);
 	clk_register_clkdev(clk, "apb_pclk", "uart2");
+	clks[uart2] = clk;
 
 	clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
 				BIT(7), 0);
 	clk_register_clkdev(clk, "apb_pclk", "sdi5");
+	clks[sdi5] = clk;
 
 	clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
 				BIT(8), 0);
@@ -363,48 +473,59 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 	clk_register_clkdev(clk, NULL, "gpio.4");
 	clk_register_clkdev(clk, NULL, "gpio.5");
 	clk_register_clkdev(clk, NULL, "gpioblock2");
+	clks[gpioblock2] = clk;
 
 	clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
 				BIT(0), 0);
 	clk_register_clkdev(clk, "usb", "musb-ux500.0");
+	clks[musb] = clk;
 
 	clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
 				BIT(1), 0);
 	clk_register_clkdev(clk, NULL, "gpio.8");
 	clk_register_clkdev(clk, NULL, "gpioblock3");
+	clks[gpioblock3] = clk;
 
 	clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
 				BIT(0), 0);
 	clk_register_clkdev(clk, "apb_pclk", "rng");
+	clks[rng] = clk;
 
 	clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
 				BIT(1), 0);
 	clk_register_clkdev(clk, NULL, "cryp0");
 	clk_register_clkdev(clk, NULL, "cryp1");
+	clks[crypt] = clk;
 
 	clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
 				BIT(2), 0);
 	clk_register_clkdev(clk, NULL, "hash0");
+	clks[hash0] = clk;
 
 	clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
 				BIT(3), 0);
 	clk_register_clkdev(clk, NULL, "pka");
+	clks[pka] = clk;
 
 	clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
 				BIT(4), 0);
 	clk_register_clkdev(clk, NULL, "hash1");
+	clks[hash1] = clk;
 
 	clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
 				BIT(5), 0);
 	clk_register_clkdev(clk, NULL, "cfgreg");
+	clks[cfgreg] = clk;
 
 	clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
 				BIT(6), 0);
 	clk_register_clkdev(clk, "apb_pclk", "mtu0");
+	clks[mtu0] = clk;
 
 	clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
 				BIT(7), 0);
 	clk_register_clkdev(clk, "apb_pclk", "mtu1");
+	clks[mtu1] = clk;
 
 	/* PRCC K-clocks
 	 *
@@ -418,67 +539,82 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 	clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
 			clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "uart0");
+	clks[per1_uart0] = clk;
 
 	clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
 			clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "uart1");
+	clks[per1_uart1] = clk;
 
 	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 			clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "nmk-i2c.1");
+	clks[per1_nmk_i2c1] = clk;
 
 	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 			clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "msp0");
 	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");
+	clks[per1_msp0] = clk;
 
 	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 			clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "msp1");
 	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");
+	clks[per1_msp1] = clk;
 
 	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
 			clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "sdi0");
+	clks[per1_sdi0] = clk;
 
 	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 			clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "nmk-i2c.2");
+	clks[per1_nmk_i2c2] = clk;
 
 	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 			clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "slimbus0");
+	clks[per1_slimbus0] = clk;
 
 	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 			clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "nmk-i2c.4");
+	clks[per1_nmk_i2c4] = clk;
 
 	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 			clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "msp3");
 	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");
+	clks[per1_msp3] = clk;
 
 	/* Periph2 */
 	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 			clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "nmk-i2c.3");
+	clks[per2_nmk_i2c3] = clk;
 
 	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
 			clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "sdi4");
+	clks[per2_sdi4] = clk;
 
 	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 			clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "msp2");
 	clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");
+	clks[per2_msp2] = clk;
 
 	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
 			clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "sdi1");
+	clks[per2_sdi1] = clk;
 
 	clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
 			clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "sdi3");
+	clks[per2_sdi3] = clk;
 
 	/* Note that rate is received from parent. */
 	clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
@@ -492,34 +628,50 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 			clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "ssp0");
+	clks[per3_ssp0] = clk;
 
 	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 			clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "ssp1");
+	clks[per3_ssp1] = clk;
 
 	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 			clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "nmk-i2c.0");
+	clks[per3_nmk_i2c0] = clk;
 
 	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
 			clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "sdi2");
+	clks[per3_sdi2] = clk;
 
 	clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
 			clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "ske");
 	clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
+	clks[per3_ske] = clk;
 
 	clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
 			clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "uart2");
+	clks[per3_uart2] = clk;
 
 	clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
 			clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "sdi5");
+	clks[per3_sdi5] = clk;
 
 	/* Periph6 */
 	clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
 			clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
 	clk_register_clkdev(clk, NULL, "rng");
+	clks[per6_rng] = clk;
+
+	if (of_have_populated_dt())
+		np = of_find_matching_node(NULL, u8500_clk_of_match);
+	if (np) {
+		clk_data.clks = clks;
+		clk_data.clk_num = CLK_MAX;
+		of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+	}
 }
-- 
1.7.10.4

[PATCH 21/21] clk: ux500: Supply provider look-up functionality to support Device Tree

[Arnd Bergmann]

On Monday 03 June 2013 14:42:45 Lee Jones wrote:
> In this patch we're populating a clk_data array, one clock per element to
> act as a clk look-up using indexes supplied from Device Tree.

This is the first time I actually take a closer look at clock bindings.
It feels odd to have a single index when you have multiple clock
providers in hardware.

> +struct clk *clks[CLK_MAX];
> +
> +const static struct of_device_id u8500_clk_of_match[] = {
> +	{ .compatible = "stericsson,u8500-clk", },
> +	{ },
> +};

>From the code in drivers/clk/ux500, I would have expected two separate
clock nodes: the prcmu and the prcc, each with their own number
space.

>  void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
>  		    u32 clkrst5_base, u32 clkrst6_base)
>  {
>  	struct prcmu_fw_version *fw_version;
>  	const char *sgaclk_parent = NULL;
> +	static struct clk_onecell_data clk_data;
> +	struct device_node *np = NULL;
>  	struct clk *clk;
>  
>  	/* Clock sources */
>  	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
>  				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
>  	clk_register_clkdev(clk, "soc0_pll", NULL);
> +	clks[soc0_pll] = clk;
>  
>  	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
>  				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
>  	clk_register_clkdev(clk, "soc1_pll", NULL);
> +	clks[soc1_pll] = clk;
>  
>  	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
>  				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
>  	clk_register_clkdev(clk, "ddr_pll", NULL);
> +	clks[ddr_pll] = clk;

It seems the actual numbers for the PCRMU clocks are defined
in drivers/mfd/dbx500-prcmu-regs.h, at PRCM_ACLK_MGT through
PRCM_MSP1CLK_MGT, where each clock has its own register.

> @@ -218,106 +296,130 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
>  	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
>  				BIT(0), 0);
>  	clk_register_clkdev(clk, "apb_pclk", "uart0");
> +	clks[uart0] = clk;
>  
>  	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
>  				BIT(1), 0);
>  	clk_register_clkdev(clk, "apb_pclk", "uart1");
> +	clks[uart1] = clk;
>  
>  	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
>  				BIT(2), 0);
>  	clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
> +	clks[nmk_i2c1] = clk;

The prcc clocks are inherently numbered, there is a set of six
registers with 8 bits each, so the number you use can simply
be the index from 0 to 48, or use #clock-cells=<2> and pass both.
Using the same numbers as the hardware in the binding is much less
ambiguous than making up your own number space that you have to
then document in the binding and update every time a new chip
gets released.

	Arnd

[PATCH 21/21] clk: ux500: Supply provider look-up functionality to support Device Tree

[Linus Walleij]

On Mon, Jun 3, 2013 at 3:42 PM, Lee Jones <lee.jones@linaro.org> wrote:

> In this patch we're populating a clk_data array, one clock per element to
> act as a clk look-up using indexes supplied from Device Tree.
>
> Cc: Mike Turquette <mturquette@linaro.org>
> Signed-off-by: Lee Jones <lee.jones@linaro.org>

This needs to be patch 1/21 because otherwise the rest of the
stuff is non-bisectable right? It's being broken the first time
you remove auxdata and not fixed until this patch.

The whole thing is very different from other DT clock things
I've seen, usually you add a compatible node for each
clock type, and a node for each physical gate. But there
may be several ways to skin this cat...

Make sure to include devicetree-discuss in the series for
an OS-neutral review opportunity.

Yours,
Linus Walleij

[PATCH 21/21] clk: ux500: Supply provider look-up functionality to support Device Tree

[Arnd Bergmann]

On Tuesday 04 June 2013, Linus Walleij wrote:
> The whole thing is very different from other DT clock things
> I've seen, usually you add a compatible node for each
> clock type, and a node for each physical gate. But there
> may be several ways to skin this cat...
> 

Based on the IRC discussion we had, I would think that the "prcc" clocks
would best be represented using multiple clock-cells since you can describe
them easily a tuple of register index, bit number some way to distinguish
the two types.

The "prcmu" clocks are harder, and we probably need either a more verbose
representation using one node per clock there, or have a single node
for the entire prcmu and not bother to describe them in DT but hardcode
everything in the source. The current patch does the latter, which is
easier now but means we cannot simplify the code much in the future
when we remove ATAGS boot support.

I hope Mike can give some better insight to what his preferences are.

	Arnd

[PATCH 21/21] clk: ux500: Supply provider look-up functionality to support Device Tree

[Lee Jones]

On Tue, 04 Jun 2013, Arnd Bergmann wrote:

> On Tuesday 04 June 2013, Linus Walleij wrote:
> > The whole thing is very different from other DT clock things
> > I've seen, usually you add a compatible node for each
> > clock type, and a node for each physical gate. But there
> > may be several ways to skin this cat...
> > 
> 
> Based on the IRC discussion we had, I would think that the "prcc" clocks
> would best be represented using multiple clock-cells since you can describe
> them easily a tuple of register index, bit number some way to distinguish
> the two types.
> 
> The "prcmu" clocks are harder, and we probably need either a more verbose
> representation using one node per clock there, or have a single node
> for the entire prcmu and not bother to describe them in DT but hardcode
> everything in the source. The current patch does the latter, which is
> easier now but means we cannot simplify the code much in the future
> when we remove ATAGS boot support.

As already discussed, in the PRCMU case I'm going to make 'enum
prcmu_clock {' look like register PRCM_YYCLKEN0_MGT_SET as described
by the design specification, and use that as our indexer.

> I hope Mike can give some better insight to what his preferences are.
> 
> 	Arnd

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH 21/21] clk: ux500: Supply provider look-up functionality to support Device Tree

[Mike Turquette]

Quoting Arnd Bergmann (2013-06-04 13:52:03)
> On Tuesday 04 June 2013, Linus Walleij wrote:
> > The whole thing is very different from other DT clock things
> > I've seen, usually you add a compatible node for each
> > clock type, and a node for each physical gate. But there
> > may be several ways to skin this cat...
> > 
> 
> Based on the IRC discussion we had, I would think that the "prcc" clocks
> would best be represented using multiple clock-cells since you can describe
> them easily a tuple of register index, bit number some way to distinguish
> the two types.
> 
> The "prcmu" clocks are harder, and we probably need either a more verbose
> representation using one node per clock there, or have a single node
> for the entire prcmu and not bother to describe them in DT but hardcode
> everything in the source. The current patch does the latter, which is
> easier now but means we cannot simplify the code much in the future
> when we remove ATAGS boot support.
> 
> I hope Mike can give some better insight to what his preferences are.

I'm still learning about DT so my inputs should be weighed, measured and
then promptly thrown out. With that said I recently published an RFC to
convert the OMAP4 PRCM clocks to DT and my approach was a single node
per clock.

The register mapping for those clocks is mostly orderly, but not so
orderly that a neat and tidy tuple would suffice.  Also the recent MMP
clock series represents many of the clocks as single nodes.

I am not opposed to this design choice and it removes more data from C
files.  Some concerns were brought up about impacts to boot time but no
one has quantified that yet.

Regards,
Mike

> 
>         Arnd

[PATCH 21/21] clk: ux500: Supply provider look-up functionality to support Device Tree

[Grant Likely]

On Tue, 4 Jun 2013 12:57:06 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Mon, Jun 3, 2013 at 3:42 PM, Lee Jones <lee.jones@linaro.org> wrote:
> 
> > In this patch we're populating a clk_data array, one clock per element to
> > act as a clk look-up using indexes supplied from Device Tree.
> >
> > Cc: Mike Turquette <mturquette@linaro.org>
> > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> 
> This needs to be patch 1/21 because otherwise the rest of the
> stuff is non-bisectable right? It's being broken the first time
> you remove auxdata and not fixed until this patch.
> 
> The whole thing is very different from other DT clock things
> I've seen, usually you add a compatible node for each
> clock type, and a node for each physical gate. But there
> may be several ways to skin this cat...

The design choice made here is perfectly fine by me. There has never
been a requirement to expose every clock as a separate node, and for
SoCs with complex clock control blocks I can certainly appreciate not
wanting to expose how the internal clocks interact out to the device
tree, especially if only the leaf clocks ever get reverenced by device
drivers. As long as there is a driver there that understands the binding
and hands out the correct clock when asked, then this design is great.

g.

[PATCH 00/21] ARM: ux500: Enable Clock look-up from Device Tree

[Ulf Hansson]

On 3 June 2013 15:42, Lee Jones <lee.jones@linaro.org> wrote:
> Nice and simple implementation using standard Clk APIs.
Hi Lee,

I may be a bit tired, but I am having a bit hard to follow the steps
taken in this patch set. :-)

I should of course tell you why:
1. You start out by adding DT definitions in the DT files, should that
not be done as the final step, after the DT support has been added in
ux500 clk driver?
2. Moreover, I think it would be enough to group the definitions
patches into one patch or at least significant fewer. Same feeling
about the patches were you remove the AUXDATA, this would simplify the
review for me.
3. The rest will be commented per patch.

Kind regards
Ulf Hansson

>
>  arch/arm/boot/dts/dbx5x0.dtsi    |   94 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
>  arch/arm/boot/dts/snowball.dts   |    3 ++-
>  arch/arm/mach-ux500/cpu-db8500.c |   36 +--------------------------
>  drivers/clk/ux500/u8500_clk.c    |  154 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
>  4 files changed, 249 insertions(+), 38 deletions(-)
>
>

[PATCH 00/21] ARM: ux500: Enable Clock look-up from Device Tree

[Lee Jones]

> > Nice and simple implementation using standard Clk APIs.
> Hi Lee,
> 
> I may be a bit tired, but I am having a bit hard to follow the steps
> taken in this patch set. :-)
> 
> I should of course tell you why:
> 1. You start out by adding DT definitions in the DT files, should that
> not be done as the final step, after the DT support has been added in
> ux500 clk driver?

No, let me tell you why. ;)

a) The DT definitions will be going in via a separate tree, so it
doesn't really matter where they are placed in _this_ patchset. and b)
they will remain completely dormant until they are backed up with
driver bindings, so there is no harm in putting them in first.

> 2. Moreover, I think it would be enough to group the definitions
> patches into one patch or at least significant fewer. Same feeling
> about the patches were you remove the AUXDATA, this would simplify the
> review for me.

It's generally accepted that lots of lines of code split over a
greater number of patches (so long as they are in consistent groups of
functionality) are easier to review and thus have a greater chance of
acceptance. It also makes things like reverting easier and bisecting
more precise (rather than finding a big patch using bisect, then
having to complete a manual mini-bisect to find the offending change.

Arnd provides the maths for calculating the ease of upstreaming a
patch, which he calls 'weight' (NB: this is from memory, it might be a
little off):

(patch_weight * patch_weight) * patch_count = delta_weight

So if we had a 100 lines split over 2 patches, it would be:

(50 * 50) * 2 = 5000

Whereas if we split those lines over 4 patches we would see:

(25 * 25) * 4 = 1000

Thus, by this convention it would (generally) considered to be twice
as difficult to upstream - at least that's the theory. There is a more
extravagant formula for calculating how difficult it would be to
upstream an entire tree of delta if a) all patches were contained on a
single branch compared to b) if patches were split into topic branches.

Something like:

((patch_weight * patch_weight) * patch_count)  *
 (patch_weight * patch_weight) * patch_count)) *
  branch_count = delta_weight

So following on from the example above and placing 100 lines over 2
patches on 1 branch you would get:

(((25 * 25) * 4) * (25 * 25) * 4) * 1 = 6250000

Whereas if you spread the patches over two branches you'd have:

(((25 * 25) * 2) * (25 * 25) * 2) * 2 = 3125000

Obviously the branch number comparison works better with the larger
numbers you'd expect to find in a typical downstream BSP, but you get
the idea.

</tangent> ... whoops, sorry! :)

> 3. The rest will be commented per patch.
> 
> Kind regards
> Ulf Hansson
> 
> >
> >  arch/arm/boot/dts/dbx5x0.dtsi    |   94 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
> >  arch/arm/boot/dts/snowball.dts   |    3 ++-
> >  arch/arm/mach-ux500/cpu-db8500.c |   36 +--------------------------
> >  drivers/clk/ux500/u8500_clk.c    |  154 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
> >  4 files changed, 249 insertions(+), 38 deletions(-)
> >
> >

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH 00/21] ARM: ux500: Enable Clock look-up from Device Tree

[Ulf Hansson]

On 11 June 2013 12:01, Lee Jones <lee.jones@linaro.org> wrote:
>> > Nice and simple implementation using standard Clk APIs.
>> Hi Lee,
>>
>> I may be a bit tired, but I am having a bit hard to follow the steps
>> taken in this patch set. :-)
>>
>> I should of course tell you why:
>> 1. You start out by adding DT definitions in the DT files, should that
>> not be done as the final step, after the DT support has been added in
>> ux500 clk driver?
>
> No, let me tell you why. ;)
>
> a) The DT definitions will be going in via a separate tree, so it
> doesn't really matter where they are placed in _this_ patchset. and b)
> they will remain completely dormant until they are backed up with
> driver bindings, so there is no harm in putting them in first.

Okay, was not aware of that those were to be merged on it's own.

>
>> 2. Moreover, I think it would be enough to group the definitions
>> patches into one patch or at least significant fewer. Same feeling
>> about the patches were you remove the AUXDATA, this would simplify the
>> review for me.
>
> It's generally accepted that lots of lines of code split over a
> greater number of patches (so long as they are in consistent groups of
> functionality) are easier to review and thus have a greater chance of
> acceptance. It also makes things like reverting easier and bisecting
> more precise (rather than finding a big patch using bisect, then
> having to complete a manual mini-bisect to find the offending change.
>
> Arnd provides the maths for calculating the ease of upstreaming a
> patch, which he calls 'weight' (NB: this is from memory, it might be a
> little off):
>
> (patch_weight * patch_weight) * patch_count = delta_weight
>
> So if we had a 100 lines split over 2 patches, it would be:
>
> (50 * 50) * 2 = 5000
>
> Whereas if we split those lines over 4 patches we would see:
>
> (25 * 25) * 4 = 1000
>
> Thus, by this convention it would (generally) considered to be twice
> as difficult to upstream - at least that's the theory. There is a more
> extravagant formula for calculating how difficult it would be to
> upstream an entire tree of delta if a) all patches were contained on a
> single branch compared to b) if patches were split into topic branches.
>
> Something like:
>
> ((patch_weight * patch_weight) * patch_count)  *
>  (patch_weight * patch_weight) * patch_count)) *
>   branch_count = delta_weight
>
> So following on from the example above and placing 100 lines over 2
> patches on 1 branch you would get:
>
> (((25 * 25) * 4) * (25 * 25) * 4) * 1 = 6250000
>
> Whereas if you spread the patches over two branches you'd have:
>
> (((25 * 25) * 2) * (25 * 25) * 2) * 2 = 3125000
>
> Obviously the branch number comparison works better with the larger
> numbers you'd expect to find in a typical downstream BSP, but you get
> the idea.
>
> </tangent> ... whoops, sorry! :)

Hehe, I stopped reading long before this line. Go ahead, keep them as
is then! :-)

>
>> 3. The rest will be commented per patch.
>>
>> Kind regards
>> Ulf Hansson
>>
>> >
>> >  arch/arm/boot/dts/dbx5x0.dtsi    |   94 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
>> >  arch/arm/boot/dts/snowball.dts   |    3 ++-
>> >  arch/arm/mach-ux500/cpu-db8500.c |   36 +--------------------------
>> >  drivers/clk/ux500/u8500_clk.c    |  154 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
>> >  4 files changed, 249 insertions(+), 38 deletions(-)
>> >
>> >
>
> --
> Lee Jones
> Linaro ST-Ericsson Landing Team Lead
> Linaro.org ? Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog