From mboxrd@z Thu Jan 1 00:00:00 1970 From: chander.kashyap@linaro.org (Chander Kashyap) Date: Thu, 6 Jun 2013 16:31:15 +0530 Subject: [PATCH 01/13] ARM: Exynos: initialize l2x0 cache controller only for cortex-a9 based SoCs Message-ID: <1370516488-25860-1-git-send-email-chander.kashyap@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Only cortex-a9 based Exynos SoCs have l2x0 cache controller. Hence instead of checking for every SoC with soc_is_xxx, just check for cpu part number and initialize the cache controller for cortex-a9 based SoCs. Signed-off-by: Chander Kashyap --- arch/arm/mach-exynos/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 8ce2db4..bad000e 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -520,7 +521,7 @@ static int __init exynos4_l2x0_cache_init(void) { int ret; - if (soc_is_exynos5250() || soc_is_exynos5440()) + if (read_cpuid_part_number() != ARM_CPU_PART_CORTEX_A9) return 0; ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); -- 1.7.9.5