* [PATCH 0/6] Add support for Allwinner A10s SoCs
@ 2013-06-09 16:36 Maxime Ripard
2013-06-09 16:36 ` [PATCH 1/6] ARM: sunxi: Add Allwinner A10s machine compatible Maxime Ripard
` (6 more replies)
0 siblings, 7 replies; 16+ messages in thread
From: Maxime Ripard @ 2013-06-09 16:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi everyone,
This patch serie reworks a bit the pinctrl driver and adds the necessary
bits needed to support the Allwinner A10s SoC.
This SoC is a bit in between the A10 and A13. Notable differences with
the A13 is the addition of an HDMI controller and of the EMAC.
For the time being (ie until we find a proper datasheet for this SoCs),
the clock definition is taken from the A10 one.
This patches depends on the "Add external interrupt support for Allwinner SoCs"
patch serie.
Thanks,
Maxime
Maxime Ripard (6):
ARM: sunxi: Add Allwinner A10s machine compatible
pinctrl: sunxi: Move the pins definitions to a separate header
pinctrl: sunxi: Add Allwinner A10s pins
ARM: sunxi: dt: Add Allwinner A10s DTSI
ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree
ARM: multi_v7: Enable Allwinner EMAC in multi_v7_defconfig
Documentation/arm/sunxi/README | 4 +
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 75 +
arch/arm/boot/dts/sun5i-a10s.dtsi | 286 +++
arch/arm/configs/multi_v7_defconfig | 2 +
arch/arm/mach-sunxi/sunxi.c | 1 +
drivers/pinctrl/pinctrl-sunxi-pins.h | 2023 ++++++++++++++++++++++
drivers/pinctrl/pinctrl-sunxi.c | 1362 +--------------
7 files changed, 2393 insertions(+), 1360 deletions(-)
create mode 100644 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
create mode 100644 arch/arm/boot/dts/sun5i-a10s.dtsi
create mode 100644 drivers/pinctrl/pinctrl-sunxi-pins.h
--
1.8.3
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 1/6] ARM: sunxi: Add Allwinner A10s machine compatible 2013-06-09 16:36 [PATCH 0/6] Add support for Allwinner A10s SoCs Maxime Ripard @ 2013-06-09 16:36 ` Maxime Ripard 2013-06-09 16:36 ` [PATCH 3/6] pinctrl: sunxi: Add Allwinner A10s pins Maxime Ripard ` (5 subsequent siblings) 6 siblings, 0 replies; 16+ messages in thread From: Maxime Ripard @ 2013-06-09 16:36 UTC (permalink / raw) To: linux-arm-kernel The A10s is a SoC member of the Allwinner sun5i family. It is basically an A13 with an EMAC and an HDMI controller. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- Documentation/arm/sunxi/README | 4 ++++ arch/arm/mach-sunxi/sunxi.c | 1 + 2 files changed, 5 insertions(+) diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README index d9a372d..e3f93fb 100644 --- a/Documentation/arm/sunxi/README +++ b/Documentation/arm/sunxi/README @@ -17,6 +17,10 @@ SunXi family + User Manual http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf + - Allwinner A10s (sun5i) + + Datasheet + http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf + - Allwinner A13 (sun5i) + Datasheet http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 08937a3..a42d874 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -109,6 +109,7 @@ static void __init sunxi_dt_init(void) static const char * const sunxi_board_dt_compat[] = { "allwinner,sun4i-a10", + "allwinner,sun5i-a10s", "allwinner,sun5i-a13", NULL, }; -- 1.8.3 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/6] pinctrl: sunxi: Add Allwinner A10s pins 2013-06-09 16:36 [PATCH 0/6] Add support for Allwinner A10s SoCs Maxime Ripard 2013-06-09 16:36 ` [PATCH 1/6] ARM: sunxi: Add Allwinner A10s machine compatible Maxime Ripard @ 2013-06-09 16:36 ` Maxime Ripard 2013-06-16 11:04 ` Linus Walleij 2013-06-09 16:36 ` [PATCH 4/6] ARM: sunxi: dt: Add Allwinner A10s DTSI Maxime Ripard ` (4 subsequent siblings) 6 siblings, 1 reply; 16+ messages in thread From: Maxime Ripard @ 2013-06-09 16:36 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- drivers/pinctrl/pinctrl-sunxi-pins.h | 645 +++++++++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-sunxi.c | 1 + 2 files changed, 646 insertions(+) diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h index 92c6b14..2eeae0c 100644 --- a/drivers/pinctrl/pinctrl-sunxi-pins.h +++ b/drivers/pinctrl/pinctrl-sunxi-pins.h @@ -1004,6 +1004,646 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ }; +static const struct sunxi_desc_pin sun5i_a10s_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ + SUNXI_FUNCTION(0x3, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ + SUNXI_FUNCTION(0x3, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ + SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ + SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ + SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ + SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ + SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ + SUNXI_FUNCTION(0x3, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart1"), /* RING */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ + SUNXI_FUNCTION(0x3, "uart1"), /* TX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ + SUNXI_FUNCTION(0x3, "uart1"), /* RX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ + SUNXI_FUNCTION(0x3, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ + SUNXI_FUNCTION(0x3, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ + SUNXI_FUNCTION(0x3, "uart2")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */ + SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir0"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ + SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ + SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DO */ + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DI */ + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NWP */ + SUNXI_FUNCTION(0x4, "uart3")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */ + SUNXI_FUNCTION(0x4, "uart3")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */ + SUNXI_FUNCTION(0x3, "uart2"), /* TX */ + SUNXI_FUNCTION(0x4, "uart3")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ + SUNXI_FUNCTION(0x3, "uart2"), /* RX */ + SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "uart2")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart2")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "emac")), /* ECRS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "emac")), /* ECOL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "emac")), /* EMDC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x3, "csi0"), /* PCK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ + SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x3, "csi0"), /* CK */ + SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ + SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ + SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ + SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ + SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* CLK */ + SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* SIGN */ + SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x2, "gps"), /* MAG */ + SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* DO */ + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x5, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION(0x5, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION(0x5, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ + SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */ + SUNXI_FUNCTION(0x5, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ +}; + static const struct sunxi_desc_pin sun5i_a13_pins[] = { /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, @@ -1370,6 +2010,11 @@ static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { .npins = ARRAY_SIZE(sun4i_a10_pins), }; +static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = { + .pins = sun5i_a10s_pins, + .npins = ARRAY_SIZE(sun5i_a10s_pins), +}; + static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { .pins = sun5i_a13_pins, .npins = ARRAY_SIZE(sun5i_a13_pins), diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c index d6af459..0a34219 100644 --- a/drivers/pinctrl/pinctrl-sunxi.c +++ b/drivers/pinctrl/pinctrl-sunxi.c @@ -629,6 +629,7 @@ static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) static struct of_device_id sunxi_pinctrl_match[] = { { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data }, + { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data }, { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data }, {} }; -- 1.8.3 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/6] pinctrl: sunxi: Add Allwinner A10s pins 2013-06-09 16:36 ` [PATCH 3/6] pinctrl: sunxi: Add Allwinner A10s pins Maxime Ripard @ 2013-06-16 11:04 ` Linus Walleij 0 siblings, 0 replies; 16+ messages in thread From: Linus Walleij @ 2013-06-16 11:04 UTC (permalink / raw) To: linux-arm-kernel On Sun, Jun 9, 2013 at 6:36 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Patch applied. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/6] ARM: sunxi: dt: Add Allwinner A10s DTSI 2013-06-09 16:36 [PATCH 0/6] Add support for Allwinner A10s SoCs Maxime Ripard 2013-06-09 16:36 ` [PATCH 1/6] ARM: sunxi: Add Allwinner A10s machine compatible Maxime Ripard 2013-06-09 16:36 ` [PATCH 3/6] pinctrl: sunxi: Add Allwinner A10s pins Maxime Ripard @ 2013-06-09 16:36 ` Maxime Ripard 2013-06-09 21:36 ` Arnd Bergmann 2013-06-09 16:36 ` [PATCH 5/6] ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree Maxime Ripard ` (3 subsequent siblings) 6 siblings, 1 reply; 16+ messages in thread From: Maxime Ripard @ 2013-06-09 16:36 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- arch/arm/boot/dts/sun5i-a10s.dtsi | 286 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 286 insertions(+) create mode 100644 arch/arm/boot/dts/sun5i-a10s.dtsi diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi new file mode 100644 index 0000000..2307ce8 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -0,0 +1,286 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&intc>; + + cpus { + cpu at 0 { + compatible = "arm,cortex-a8"; + }; + }; + + memory { + reg = <0x40000000 0x20000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + osc24M: osc24M at 01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-osc-clk"; + reg = <0x01c20050 0x4>; + clock-frequency = <24000000>; + }; + + osc32k: osc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + pll1: pll1 at 01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + }; + + /* dummy is 200M */ + cpu: cpu at 01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + }; + + axi: axi at 01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + }; + + axi_gates: axi_gates at 01c2005c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-axi-gates-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&axi>; + clock-output-names = "axi_dram"; + }; + + ahb: ahb at 01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>; + }; + + ahb_gates: ahb_gates at 01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-output-names = "ahb_usb0", "ahb_ehci0", + "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", + "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", + "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", + "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", + "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", + "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", + "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", + "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", + "ahb_de_fe1", "ahb_mp", "ahb_mali400"; + }; + + apb0: apb0 at 01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + }; + + apb0_gates: apb0_gates at 01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-apb0-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-output-names = "apb0_codec", "apb0_spdif", + "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", + "apb0_ir1", "apb0_keypad"; + }; + + /* dummy is pll62 */ + apb1_mux: apb1_mux at 01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb1-mux-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&dummy>, <&osc32k>; + }; + + apb1: apb1 at 01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&apb1_mux>; + }; + + apb1_gates: apb1_gates at 01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-apb1-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_i2c0", "apb1_i2c1", + "apb1_i2c2", "apb1_can", "apb1_scr", + "apb1_ps20", "apb1_ps21", "apb1_uart0", + "apb1_uart1", "apb1_uart2", "apb1_uart3", + "apb1_uart4", "apb1_uart5", "apb1_uart6", + "apb1_uart7"; + }; + }; + + soc at 01c20000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01c20000 0x300000>; + ranges; + + emac: ethernet at 01c0b000 { + compatible = "allwinner,sun4i-emac"; + reg = <0x01c0b000 0x1000>; + interrupts = <55>; + clocks = <&ahb_gates 17>; + status = "disabled"; + }; + + mdio at 01c0b080 { + compatible = "allwinner,sun4i-mdio"; + reg = <0x01c0b080 0x14>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller at 01c20400 { + compatible = "allwinner,sun4i-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl at 01c20800 { + compatible = "allwinner,sun5i-a10s-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <28>; + clocks = <&apb0_gates 5>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + + uart0_pins_a: uart0 at 0 { + allwinner,pins = "PB19", "PB20"; + allwinner,function = "uart0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart2_pins_a: uart2 at 0 { + allwinner,pins = "PC18", "PC19"; + allwinner,function = "uart2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart3_pins_a: uart3 at 0 { + allwinner,pins = "PG9", "PG10"; + allwinner,function = "uart3"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + emac_pins_a: emac0 at 0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "emac"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + timer at 01c20c00 { + compatible = "allwinner,sun4i-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <22>; + clocks = <&osc24M>; + }; + + wdt: watchdog at 01c20c90 { + compatible = "allwinner,sun4i-wdt"; + reg = <0x01c20c90 0x10>; + }; + + uart0: serial at 01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 16>; + status = "disabled"; + }; + + uart1: serial at 01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 17>; + status = "disabled"; + }; + + uart2: serial at 01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 18>; + status = "disabled"; + }; + + uart3: serial at 01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 19>; + status = "disabled"; + }; + }; +}; -- 1.8.3 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/6] ARM: sunxi: dt: Add Allwinner A10s DTSI 2013-06-09 16:36 ` [PATCH 4/6] ARM: sunxi: dt: Add Allwinner A10s DTSI Maxime Ripard @ 2013-06-09 21:36 ` Arnd Bergmann 2013-06-10 10:34 ` Maxime Ripard 0 siblings, 1 reply; 16+ messages in thread From: Arnd Bergmann @ 2013-06-09 21:36 UTC (permalink / raw) To: linux-arm-kernel On Sunday 09 June 2013 18:36:05 Maxime Ripard wrote: > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > arch/arm/boot/dts/sun5i-a10s.dtsi | 286 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 286 insertions(+) > create mode 100644 arch/arm/boot/dts/sun5i-a10s.dtsi Would it make sense to split out the parts that are common with A13 into a separate sun5i.dtsi file? Arnd ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/6] ARM: sunxi: dt: Add Allwinner A10s DTSI 2013-06-09 21:36 ` Arnd Bergmann @ 2013-06-10 10:34 ` Maxime Ripard 2013-06-10 14:58 ` Arnd Bergmann 0 siblings, 1 reply; 16+ messages in thread From: Maxime Ripard @ 2013-06-10 10:34 UTC (permalink / raw) To: linux-arm-kernel Hi Arnd, On Sun, Jun 09, 2013 at 11:36:24PM +0200, Arnd Bergmann wrote: > On Sunday 09 June 2013 18:36:05 Maxime Ripard wrote: > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > --- > > arch/arm/boot/dts/sun5i-a10s.dtsi | 286 ++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 286 insertions(+) > > create mode 100644 arch/arm/boot/dts/sun5i-a10s.dtsi > > Would it make sense to split out the parts that are common with A13 into > a separate sun5i.dtsi file? I don't have the documentation at the moment, so I'm not exactly sure at which extent it's similar to the A13. Yet for the moment, the two dtsi are very different (different clock definitions, different muxings, etc.), so , I'm not quite sure about wether it would make stuff smaller. Of course, if we find they actually share a lot, we can definitely make a common sun5i DTSI later. But if you prefer to have it right now, I can always send a v2 :) Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/6] ARM: sunxi: dt: Add Allwinner A10s DTSI 2013-06-10 10:34 ` Maxime Ripard @ 2013-06-10 14:58 ` Arnd Bergmann 0 siblings, 0 replies; 16+ messages in thread From: Arnd Bergmann @ 2013-06-10 14:58 UTC (permalink / raw) To: linux-arm-kernel On Monday 10 June 2013, Maxime Ripard wrote: > I don't have the documentation at the moment, so I'm not exactly sure at > which extent it's similar to the A13. Yet for the moment, the two dtsi > are very different (different clock definitions, different muxings, > etc.), so , I'm not quite sure about wether it would make stuff smaller. > > Of course, if we find they actually share a lot, we can definitely make > a common sun5i DTSI later. > > But if you prefer to have it right now, I can always send a v2 :) I thought it was actually the same silicon in a different package with fewer pins, but if the files look very different right now, just leave them separately. Arnd ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/6] ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree 2013-06-09 16:36 [PATCH 0/6] Add support for Allwinner A10s SoCs Maxime Ripard ` (2 preceding siblings ...) 2013-06-09 16:36 ` [PATCH 4/6] ARM: sunxi: dt: Add Allwinner A10s DTSI Maxime Ripard @ 2013-06-09 16:36 ` Maxime Ripard 2013-06-14 18:09 ` [linux-sunxi] " Emilio López 2013-06-09 16:36 ` [PATCH 6/6] ARM: multi_v7: Enable Allwinner EMAC in multi_v7_defconfig Maxime Ripard ` (2 subsequent siblings) 6 siblings, 1 reply; 16+ messages in thread From: Maxime Ripard @ 2013-06-09 16:36 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 75 ++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts new file mode 100644 index 0000000..73ad65e --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -0,0 +1,75 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun5i-a10s.dtsi" + +/ { + model = "Olimex A10s-Olinuxino Micro"; + compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; + + soc at 01c20000 { + emac: ethernet at 01c0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; + }; + + mdio at 01c0b080 { + status = "okay"; + + phy1: ethernet-phy at 1 { + reg = <1>; + }; + }; + + pinctrl at 01c20800 { + led_pins_olinuxino: led_pins at 0 { + allwinner,pins = "PE3"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + }; + + uart0: serial at 01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + uart2: serial at 01c28800 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; + }; + + uart3: serial at 01c28c00 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxino>; + + power { + gpios = <&pio 4 3 0>; + default-state = "on"; + }; + }; +}; -- 1.8.3 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [linux-sunxi] [PATCH 5/6] ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree 2013-06-09 16:36 ` [PATCH 5/6] ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree Maxime Ripard @ 2013-06-14 18:09 ` Emilio López 2013-06-17 8:38 ` Maxime Ripard 0 siblings, 1 reply; 16+ messages in thread From: Emilio López @ 2013-06-14 18:09 UTC (permalink / raw) To: linux-arm-kernel Hi Maxime, El 09/06/13 13:36, Maxime Ripard escribi?: > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 75 ++++++++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts Please add this on the sunxi target in arch/arm/boot/dts/Makefile so it gets built on make dtbs. (snip) > + leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&led_pins_olinuxino>; > + > + power { > + gpios = <&pio 4 3 0>; > + default-state = "on"; > + }; Also, as discussed on IRC, I think it would be wise to change the name on the LED node. The schematics have a 'power' led already that is hard-wired to 3.3v, and this led node that you are declaring is referred as 'led1' there. I suppose 'green' would be a suitable name to keep consistency with other sunxi boards (namely cubieboard). Other than that, my OLinuXino worked just fine after applying this patchset, so Tested-by: Emilio L?pez <emilio@elopez.com.ar> Thanks! Emilio ^ permalink raw reply [flat|nested] 16+ messages in thread
* [linux-sunxi] [PATCH 5/6] ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree 2013-06-14 18:09 ` [linux-sunxi] " Emilio López @ 2013-06-17 8:38 ` Maxime Ripard 0 siblings, 0 replies; 16+ messages in thread From: Maxime Ripard @ 2013-06-17 8:38 UTC (permalink / raw) To: linux-arm-kernel Hi Emilio, On Fri, Jun 14, 2013 at 03:09:49PM -0300, Emilio L?pez wrote: > Hi Maxime, > > El 09/06/13 13:36, Maxime Ripard escribi?: > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > --- > > arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 75 ++++++++++++++++++++++++ > > 1 file changed, 75 insertions(+) > > create mode 100644 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts > > Please add this on the sunxi target in arch/arm/boot/dts/Makefile so it > gets built on make dtbs. > > (snip) > > > + leds { > > + compatible = "gpio-leds"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&led_pins_olinuxino>; > > + > > + power { > > + gpios = <&pio 4 3 0>; > > + default-state = "on"; > > + }; > > Also, as discussed on IRC, I think it would be wise to change the name > on the LED node. The schematics have a 'power' led already that is > hard-wired to 3.3v, and this led node that you are declaring is referred > as 'led1' there. I suppose 'green' would be a suitable name to keep > consistency with other sunxi boards (namely cubieboard). > > Other than that, my OLinuXino worked just fine after applying this > patchset, so > > Tested-by: Emilio L?pez <emilio@elopez.com.ar> Thanks for your comments and the test. I'll send a v2. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 6/6] ARM: multi_v7: Enable Allwinner EMAC in multi_v7_defconfig 2013-06-09 16:36 [PATCH 0/6] Add support for Allwinner A10s SoCs Maxime Ripard ` (3 preceding siblings ...) 2013-06-09 16:36 ` [PATCH 5/6] ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree Maxime Ripard @ 2013-06-09 16:36 ` Maxime Ripard 2013-06-15 13:14 ` [PATCH 0/6] Add support for Allwinner A10s SoCs Maxime Ripard [not found] ` <1370795767-9769-3-git-send-email-maxime.ripard@free-electrons.com> 6 siblings, 0 replies; 16+ messages in thread From: Maxime Ripard @ 2013-06-09 16:36 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- arch/arm/configs/multi_v7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 2e67a27..4aa6401 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -31,10 +31,12 @@ CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_AHCI_PLATFORM=y CONFIG_NETDEVICES=y +CONFIG_SUN4I_EMAC=y CONFIG_NET_CALXEDA_XGMAC=y CONFIG_SMSC911X=y CONFIG_STMMAC_ETH=y CONFIG_SERIO_AMBAKMI=y +CONFIG_MDIO_SUN4I=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y -- 1.8.3 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 0/6] Add support for Allwinner A10s SoCs 2013-06-09 16:36 [PATCH 0/6] Add support for Allwinner A10s SoCs Maxime Ripard ` (4 preceding siblings ...) 2013-06-09 16:36 ` [PATCH 6/6] ARM: multi_v7: Enable Allwinner EMAC in multi_v7_defconfig Maxime Ripard @ 2013-06-15 13:14 ` Maxime Ripard [not found] ` <1370795767-9769-3-git-send-email-maxime.ripard@free-electrons.com> 6 siblings, 0 replies; 16+ messages in thread From: Maxime Ripard @ 2013-06-15 13:14 UTC (permalink / raw) To: linux-arm-kernel Hi Linus, On Sun, Jun 09, 2013 at 06:36:01PM +0200, Maxime Ripard wrote: > Hi everyone, > > This patch serie reworks a bit the pinctrl driver and adds the necessary > bits needed to support the Allwinner A10s SoC. > > This SoC is a bit in between the A10 and A13. Notable differences with > the A13 is the addition of an HDMI controller and of the EMAC. > > For the time being (ie until we find a proper datasheet for this SoCs), > the clock definition is taken from the A10 one. > > This patches depends on the "Add external interrupt support for Allwinner SoCs" > patch serie. Do you have any comments on the two patches on the pinctrl driver? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <1370795767-9769-3-git-send-email-maxime.ripard@free-electrons.com>]
* [PATCH 2/6] pinctrl: sunxi: Move the pins definitions to a separate header [not found] ` <1370795767-9769-3-git-send-email-maxime.ripard@free-electrons.com> @ 2013-06-16 11:03 ` Linus Walleij 2013-06-17 8:41 ` Maxime Ripard 0 siblings, 1 reply; 16+ messages in thread From: Linus Walleij @ 2013-06-16 11:03 UTC (permalink / raw) To: linux-arm-kernel On Sun, Jun 9, 2013 at 6:36 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > It will allow us to have a cleaner separation between the data needed by > the driver to work, and the core logic of the driver in itself, and will > allow having too much noise in the core driver in the future. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Patch applied. Since you will anyway have to bring the ARM SoC branch on top of the pinctrl tree, I might as well apply this to my tree. If everything else fails, you'll have a nice development base in v3.11 with this in place, right? Yours, Linus Walleij ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/6] pinctrl: sunxi: Move the pins definitions to a separate header 2013-06-16 11:03 ` [PATCH 2/6] pinctrl: sunxi: Move the pins definitions to a separate header Linus Walleij @ 2013-06-17 8:41 ` Maxime Ripard 2013-06-17 16:11 ` Linus Walleij 0 siblings, 1 reply; 16+ messages in thread From: Maxime Ripard @ 2013-06-17 8:41 UTC (permalink / raw) To: linux-arm-kernel Hi Linus, On Sun, Jun 16, 2013 at 01:03:09PM +0200, Linus Walleij wrote: > On Sun, Jun 9, 2013 at 6:36 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > > It will allow us to have a cleaner separation between the data needed by > > the driver to work, and the core logic of the driver in itself, and will > > allow having too much noise in the core driver in the future. > > > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > Patch applied. > > Since you will anyway have to bring the ARM SoC branch on > top of the pinctrl tree, I might as well apply this to my tree. Thanks for merging this. I applied the other patches except for the 5th one that Emilio commented on. > If everything else fails, you'll have a nice development base > in v3.11 with this in place, right? Yes, As far as I can see, we should have a pretty complete support for the GPIO/muxing/IRQ on the "old" allwinner SoCs (sun4i and sun5i) now. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/6] pinctrl: sunxi: Move the pins definitions to a separate header 2013-06-17 8:41 ` Maxime Ripard @ 2013-06-17 16:11 ` Linus Walleij 0 siblings, 0 replies; 16+ messages in thread From: Linus Walleij @ 2013-06-17 16:11 UTC (permalink / raw) To: linux-arm-kernel On Mon, Jun 17, 2013 at 10:41 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Yes, As far as I can see, we should have a pretty complete support for > the GPIO/muxing/IRQ on the "old" allwinner SoCs (sun4i and sun5i) now. Lucky you! My Android tablet is an Ainol Hero 2 using Actions Semiconductor ATM7029. They don't even publish their kernel sources nor datasheet so no chance of supporting that thing. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2013-06-17 16:11 UTC | newest]
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2013-06-09 16:36 [PATCH 0/6] Add support for Allwinner A10s SoCs Maxime Ripard
2013-06-09 16:36 ` [PATCH 1/6] ARM: sunxi: Add Allwinner A10s machine compatible Maxime Ripard
2013-06-09 16:36 ` [PATCH 3/6] pinctrl: sunxi: Add Allwinner A10s pins Maxime Ripard
2013-06-16 11:04 ` Linus Walleij
2013-06-09 16:36 ` [PATCH 4/6] ARM: sunxi: dt: Add Allwinner A10s DTSI Maxime Ripard
2013-06-09 21:36 ` Arnd Bergmann
2013-06-10 10:34 ` Maxime Ripard
2013-06-10 14:58 ` Arnd Bergmann
2013-06-09 16:36 ` [PATCH 5/6] ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree Maxime Ripard
2013-06-14 18:09 ` [linux-sunxi] " Emilio López
2013-06-17 8:38 ` Maxime Ripard
2013-06-09 16:36 ` [PATCH 6/6] ARM: multi_v7: Enable Allwinner EMAC in multi_v7_defconfig Maxime Ripard
2013-06-15 13:14 ` [PATCH 0/6] Add support for Allwinner A10s SoCs Maxime Ripard
[not found] ` <1370795767-9769-3-git-send-email-maxime.ripard@free-electrons.com>
2013-06-16 11:03 ` [PATCH 2/6] pinctrl: sunxi: Move the pins definitions to a separate header Linus Walleij
2013-06-17 8:41 ` Maxime Ripard
2013-06-17 16:11 ` Linus Walleij
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