From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 03/12] ARM: tlb: don't bother with barriers for branch predictor maintenance
Date: Thu, 20 Jun 2013 15:21:17 +0100 [thread overview]
Message-ID: <1371738086-6707-4-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1371738086-6707-1-git-send-email-will.deacon@arm.com>
Branch predictor maintenance is only required when we are either
changing the kernel's view of memory (switching tables completely) or
dealing with ASID rollover.
Both of these use-cases require subsequent TLB invalidation, which has
the relevant barrier instructions to ensure completion and visibility
of the maintenance, so this patch removes the instruction barrier from
[local_]flush_bp_all.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/include/asm/tlbflush.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 91b2922..45e3aea 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -527,6 +527,10 @@ static inline void __flush_tlb_kernel_page(unsigned long kaddr)
}
}
+/*
+ * Branch predictor maintenance is paired with full TLB invalidation, so
+ * there is no need for any barriers here.
+ */
static inline void local_flush_bp_all(void)
{
const int zero = 0;
@@ -536,9 +540,6 @@ static inline void local_flush_bp_all(void)
asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
else if (tlb_flag(TLB_V6_BP))
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
-
- if (tlb_flag(TLB_BARRIER))
- isb();
}
#ifdef CONFIG_ARM_ERRATA_798181
--
1.8.2.2
next prev parent reply other threads:[~2013-06-20 14:21 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-20 14:21 [PATCH v2 00/12] Make use of v7 barrier variants in Linux Will Deacon
2013-06-20 14:21 ` [PATCH v2 01/12] ARM: mm: remove redundant dsb() prior to range TLB invalidation Will Deacon
2013-06-20 14:21 ` [PATCH v2 02/12] ARM: tlb: don't perform inner-shareable invalidation for local TLB ops Will Deacon
2013-06-20 14:21 ` Will Deacon [this message]
2013-06-20 14:21 ` [PATCH v2 04/12] ARM: tlb: don't perform inner-shareable invalidation for local BP ops Will Deacon
2013-06-20 14:21 ` [PATCH v2 05/12] ARM: barrier: allow options to be passed to memory barrier instructions Will Deacon
2013-06-21 8:37 ` Ming Lei
2013-06-21 8:51 ` Will Deacon
2013-06-21 8:53 ` Ming Lei
2013-06-20 14:21 ` [PATCH v2 06/12] ARM: tlb: reduce scope of barrier domains for TLB invalidation Will Deacon
2013-06-20 14:21 ` [PATCH v2 07/12] ARM: mm: use inner-shareable barriers for TLB and user cache operations Will Deacon
2013-06-20 14:21 ` [PATCH v2 08/12] ARM: spinlock: use inner-shareable dsb variant prior to sev instruction Will Deacon
2013-06-20 14:21 ` [PATCH v2 09/12] ARM: kvm: use inner-shareable barriers after TLB flushing Will Deacon
2013-06-20 14:21 ` [PATCH v2 10/12] ARM: mcpm: use -st dsb option prior to sev instructions Will Deacon
2013-06-20 14:21 ` [PATCH v2 11/12] ARM: l2x0: use -st dsb option for ordering writel_relaxed with unlock Will Deacon
2013-06-20 14:21 ` [PATCH v2 12/12] ARM: cacheflush: use -ishst dsb variant for ensuring flush completion Will Deacon
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