From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 05/12] ARM: barrier: allow options to be passed to memory barrier instructions
Date: Thu, 20 Jun 2013 15:21:19 +0100 [thread overview]
Message-ID: <1371738086-6707-6-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1371738086-6707-1-git-send-email-will.deacon@arm.com>
On ARMv7, the memory barrier instructions take an optional `option'
field which can be used to constrain the effects of a memory barrier
based on shareability and access type.
This patch allows the caller to pass these options if required, and
updates the smp_*() barriers to request inner-shareable barriers,
affecting only stores for the _wmb variant. wmb() is also changed to
use the -st version of dsb.
Reported-by: Albin Tonnerre <albin.tonnerre@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/include/asm/assembler.h | 4 ++--
arch/arm/include/asm/barrier.h | 32 ++++++++++++++++----------------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 05ee9ee..863b280 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -212,9 +212,9 @@
#ifdef CONFIG_SMP
#if __LINUX_ARM_ARCH__ >= 7
.ifeqs "\mode","arm"
- ALT_SMP(dmb)
+ ALT_SMP(dmb ish)
.else
- ALT_SMP(W(dmb))
+ ALT_SMP(W(dmb) ish)
.endif
#elif __LINUX_ARM_ARCH__ == 6
ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 8dcd9c7..60f15e2 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -14,27 +14,27 @@
#endif
#if __LINUX_ARM_ARCH__ >= 7
-#define isb() __asm__ __volatile__ ("isb" : : : "memory")
-#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
-#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
+#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
+#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
-#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
: : "r" (0) : "memory")
-#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
: : "r" (0) : "memory")
#elif defined(CONFIG_CPU_FA526)
-#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
: : "r" (0) : "memory")
-#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
#else
-#define isb() __asm__ __volatile__ ("" : : : "memory")
-#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+#define isb(x) __asm__ __volatile__ ("" : : : "memory")
+#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
#endif
#ifdef CONFIG_ARCH_HAS_BARRIERS
@@ -42,7 +42,7 @@
#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
#define mb() do { dsb(); outer_sync(); } while (0)
#define rmb() dsb()
-#define wmb() mb()
+#define wmb() do { dsb(st); outer_sync(); } while (0)
#else
#define mb() barrier()
#define rmb() barrier()
@@ -54,9 +54,9 @@
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#else
-#define smp_mb() dmb()
-#define smp_rmb() dmb()
-#define smp_wmb() dmb()
+#define smp_mb() dmb(ish)
+#define smp_rmb() smp_mb()
+#define smp_wmb() dmb(ishst)
#endif
#define read_barrier_depends() do { } while(0)
--
1.8.2.2
next prev parent reply other threads:[~2013-06-20 14:21 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-20 14:21 [PATCH v2 00/12] Make use of v7 barrier variants in Linux Will Deacon
2013-06-20 14:21 ` [PATCH v2 01/12] ARM: mm: remove redundant dsb() prior to range TLB invalidation Will Deacon
2013-06-20 14:21 ` [PATCH v2 02/12] ARM: tlb: don't perform inner-shareable invalidation for local TLB ops Will Deacon
2013-06-20 14:21 ` [PATCH v2 03/12] ARM: tlb: don't bother with barriers for branch predictor maintenance Will Deacon
2013-06-20 14:21 ` [PATCH v2 04/12] ARM: tlb: don't perform inner-shareable invalidation for local BP ops Will Deacon
2013-06-20 14:21 ` Will Deacon [this message]
2013-06-21 8:37 ` [PATCH v2 05/12] ARM: barrier: allow options to be passed to memory barrier instructions Ming Lei
2013-06-21 8:51 ` Will Deacon
2013-06-21 8:53 ` Ming Lei
2013-06-20 14:21 ` [PATCH v2 06/12] ARM: tlb: reduce scope of barrier domains for TLB invalidation Will Deacon
2013-06-20 14:21 ` [PATCH v2 07/12] ARM: mm: use inner-shareable barriers for TLB and user cache operations Will Deacon
2013-06-20 14:21 ` [PATCH v2 08/12] ARM: spinlock: use inner-shareable dsb variant prior to sev instruction Will Deacon
2013-06-20 14:21 ` [PATCH v2 09/12] ARM: kvm: use inner-shareable barriers after TLB flushing Will Deacon
2013-06-20 14:21 ` [PATCH v2 10/12] ARM: mcpm: use -st dsb option prior to sev instructions Will Deacon
2013-06-20 14:21 ` [PATCH v2 11/12] ARM: l2x0: use -st dsb option for ordering writel_relaxed with unlock Will Deacon
2013-06-20 14:21 ` [PATCH v2 12/12] ARM: cacheflush: use -ishst dsb variant for ensuring flush completion Will Deacon
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