From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
To: Chen-Yu Tsai <wenst@chromium.org>
Cc: "AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Dong Aisheng" <aisheng.dong@nxp.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"Yassine Oudjana" <y.oudjana@protonmail.com>,
"Laura Nao" <laura.nao@collabora.com>,
"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
"Chia-I Wu" <olvaffe@gmail.com>,
kernel@collabora.com, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH v2 4/5] clk: mediatek: Refactor pllfh registration to pass device
Date: Fri, 10 Oct 2025 22:06:31 +0200 [thread overview]
Message-ID: <13720474.O9o76ZdvQC@workhorse> (raw)
In-Reply-To: <CAGXv+5Hpndq09cbudofSvkNE6w+tHb85VCqDb3P920S8vwonHQ@mail.gmail.com>
On Thursday, 9 October 2025 09:33:22 Central European Summer Time Chen-Yu Tsai wrote:
> On Thu, Oct 9, 2025 at 12:06 AM Nicolas Frattaroli
> <nicolas.frattaroli@collabora.com> wrote:
> >
> > After refactoring all of PLL to pass the device, it's now fairly easy to
> > refactor pllfh and its users, as pllfh registration wraps PLL
> > registration.
> >
> > Do this refactor and move all of the pllfh users to pass the device as
> > well.
> >
> > Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> > ---
> > drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +-
> > drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
> > drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +-
> > drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +-
> > drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +-
> > drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++-----
> > drivers/clk/mediatek/clk-pllfh.h | 2 +-
> > 7 files changed, 20 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
> > index 91665d7f125efde4941cc4de881c5b503a935529..123d5d7fea8554676364dc56f5c023e43325d516 100644
> > --- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
> > +++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
> > @@ -152,7 +152,7 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
> > return -ENOMEM;
> >
> > fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
> > - ret = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
> > + ret = mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls),
> > pllfhs, ARRAY_SIZE(pllfhs), clk_data);
> > if (ret)
> > goto free_clk_data;
> > diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
> > index 95385bb67d5511eda3a851f81986e67eaf81e5fb..d7d416172ab35bc027ae67c163c1dc20dee857b6 100644
> > --- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
> > +++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
> > @@ -140,13 +140,13 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_apmixed);
> > static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
> > {
> > const u8 *fhctl_node = "mediatek,mt8173-fhctl";
> > - struct device_node *node = pdev->dev.of_node;
> > struct clk_hw_onecell_data *clk_data;
> > + struct device *dev = &pdev->dev;
> > void __iomem *base;
> > struct clk_hw *hw;
> > int r;
> >
> > - base = of_iomap(node, 0);
> > + base = of_iomap(dev->of_node, 0);
> > if (!base)
> > return -ENOMEM;
> >
> > @@ -157,25 +157,25 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
> > }
> >
> > fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
> > - r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
> > - pllfhs, ARRAY_SIZE(pllfhs), clk_data);
> > + r = mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls), pllfhs,
> > + ARRAY_SIZE(pllfhs), clk_data);
> > if (r)
> > goto free_clk_data;
> >
> > hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_REF2USB);
> > if (IS_ERR(hw)) {
> > r = PTR_ERR(hw);
> > - dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r);
> > + dev_err(dev, "Failed to register ref2usb_tx: %d\n", r);
> > goto unregister_plls;
> > }
> > clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
> >
> > - hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0,
> > + hw = devm_clk_hw_register_divider(dev, "hdmi_ref", "tvdpll_594m", 0,
> > base + REGOFF_HDMI_REF, 16, 3,
> > CLK_DIVIDER_POWER_OF_TWO, NULL);
> > clk_data->hws[CLK_APMIXED_HDMI_REF] = hw;
> >
> > - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> > + r = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_data);
> > if (r)
> > goto unregister_ref2usb;
> >
> > diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
> > index 4b2b16578232d986f78deed4778c5fab7f460184..d35dd2632e43ab535b32b8b99f8d75de02d56fe2 100644
> > --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
> > +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
> > @@ -151,7 +151,7 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
> >
> > fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
> >
> > - r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
> > + r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
> > pllfhs, ARRAY_SIZE(pllfhs), clk_data);
> > if (r)
> > goto free_apmixed_data;
> > diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
> > index 0b66a27e4d5ac68f09dc6a4197fd84ef82342df9..b0563a285bd666d492a7fa940733aad1ab1a0bae 100644
> > --- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
> > +++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
> > @@ -162,7 +162,7 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
> >
> > fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
> >
> > - r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
> > + r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
> > pllfhs, ARRAY_SIZE(pllfhs), clk_data);
> > if (r)
> > goto free_clk_data;
> > diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> > index 282a3137dc89419a6d0b574fd549cee941687900..44917ab034c56f01ef02d1957f17eb0655438d75 100644
> > --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> > +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> > @@ -181,7 +181,7 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
> >
> > fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
> >
> > - r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
> > + r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
> > pllfhs, ARRAY_SIZE(pllfhs), clk_data);
> > if (r)
> > goto free_apmixed_data;
> > diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c
> > index 62bfe4a480f14a0a742fb094aff0e6d1a79fe0c3..8ad11023d91127e88900bc6bcabbaeafb1e00664 100644
> > --- a/drivers/clk/mediatek/clk-pllfh.c
> > +++ b/drivers/clk/mediatek/clk-pllfh.c
> > @@ -10,6 +10,7 @@
> > #include <linux/slab.h>
> > #include <linux/clkdev.h>
> > #include <linux/delay.h>
> > +#include <linux/device.h>
>
> This shouldn't be needed, as you aren't using any of the APIs.
>
> A forward declaration of |struct device| in the header should suffice.
> It should be added anyway, since the header defines data structures that
> have a |struct device *| field.
>
>
> ChenYu
>
drivers/clk/mediatek/clk-pllfh.c:208:21: error: incomplete definition of type 'struct device'
208 | base = of_iomap(dev->of_node, 0);
| ~~~^
Alas, it is needed, otherwise we can't get the of_node. dev_of_node
is also defined in device.h, so it works out to the same difference.
Kind regards,
Nicolas Frattaroli
next prev parent reply other threads:[~2025-10-10 20:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-08 16:05 [PATCH v2 0/5] MediaTek PLL Refactors and Fixes Nicolas Frattaroli
2025-10-08 16:05 ` [PATCH v2 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc Nicolas Frattaroli
2025-10-09 7:07 ` Chen-Yu Tsai
2025-10-09 8:01 ` AngeloGioacchino Del Regno
2025-10-08 16:05 ` [PATCH v2 2/5] clk: mediatek: Refactor pll registration to pass device Nicolas Frattaroli
2025-10-09 7:09 ` Chen-Yu Tsai
2025-10-09 7:19 ` Chen-Yu Tsai
2025-10-09 8:09 ` AngeloGioacchino Del Regno
2025-10-09 8:18 ` Chen-Yu Tsai
2025-10-09 8:52 ` AngeloGioacchino Del Regno
2025-10-10 20:11 ` Nicolas Frattaroli
2025-10-08 16:05 ` [PATCH v2 3/5] clk: mediatek: Pass device to clk_hw_register for PLLs Nicolas Frattaroli
2025-10-09 8:11 ` AngeloGioacchino Del Regno
2025-10-09 8:32 ` Chen-Yu Tsai
2025-10-08 16:05 ` [PATCH v2 4/5] clk: mediatek: Refactor pllfh registration to pass device Nicolas Frattaroli
2025-10-09 7:33 ` Chen-Yu Tsai
2025-10-10 20:06 ` Nicolas Frattaroli [this message]
2025-10-09 8:12 ` AngeloGioacchino Del Regno
2025-10-08 16:05 ` [PATCH v2 5/5] clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks Nicolas Frattaroli
2025-10-09 8:22 ` AngeloGioacchino Del Regno
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