From: ben.dooks@codethink.co.uk (Ben Dooks)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 09/10] mvebu: support running big-endian
Date: Mon, 1 Jul 2013 12:04:07 +0100 [thread overview]
Message-ID: <1372676648-9254-10-git-send-email-ben.dooks@codethink.co.uk> (raw)
In-Reply-To: <1372676648-9254-1-git-send-email-ben.dooks@codethink.co.uk>
Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
arch/arm/mach-mvebu/Kconfig | 1 +
arch/arm/mach-mvebu/coherency_ll.S | 3 +++
arch/arm/mach-mvebu/headsmp.S | 4 ++++
3 files changed, 8 insertions(+)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 80a8bca..317cdb8 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,5 +1,6 @@
config ARCH_MVEBU
bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+ select ARCH_SUPPORTS_BIG_ENDIAN
select CLKSRC_MMIO
select COMMON_CLK
select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 5476669..ee7598f 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -20,6 +20,8 @@
#define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
+#include <asm/assembler.h>
+
.text
/*
* r0: Coherency fabric base register address
@@ -29,6 +31,7 @@ ENTRY(ll_set_cpu_coherent)
/* Create bit by cpu index */
mov r3, #(1 << 24)
lsl r1, r3, r1
+ARM_BE8(rev r1, r1)
/* Add CPU to SMP group - Atomic */
add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index a06e0ed..a4f995d 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -21,6 +21,8 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
+
/*
* At this stage the secondary CPUs don't have acces yet to the MMU, so
* we have to provide physical addresses
@@ -36,6 +38,8 @@
*/
ENTRY(armada_xp_secondary_startup)
+ ARM_BE8(setend be ) @ go BE8 if booted LE
+
/* Read CPU id */
mrc p15, 0, r1, c0, c0, 5
and r1, r1, #0xF
--
1.7.10.4
next prev parent reply other threads:[~2013-07-01 11:04 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-01 11:03 v3.10 - big endian core support Ben Dooks
2013-07-01 11:03 ` [PATCH 01/10] ARM: fix ARCH_IXP4xx usage of ARCH_SUPPORTS_BIG_ENDIAN Ben Dooks
2013-07-01 11:04 ` [PATCH 02/10] ARM: asm: Add ARM_BE8() assembly helper Ben Dooks
2013-07-01 11:04 ` [PATCH 03/10] ARM: fixup_pv_table bug when CPU_ENDIAN_BE8 Ben Dooks
2013-07-01 11:04 ` [PATCH 04/10] ARM: set BE8 if LE in head code Ben Dooks
2013-07-01 11:04 ` [PATCH 05/10] ARM: pl01x debug code endian fix Ben Dooks
2013-07-01 11:04 ` [PATCH 06/10] ARM: twd: data " Ben Dooks
2013-07-01 11:04 ` [PATCH 07/10] ARM: smp_scu: data endian fixes Ben Dooks
2013-07-01 11:04 ` [PATCH 08/10] highbank: enable big-endian Ben Dooks
2013-07-01 11:04 ` Ben Dooks [this message]
2013-07-01 11:04 ` [PATCH 10/10] vexpress: add big endian support Ben Dooks
2013-07-01 14:33 ` v3.10 - big endian core support Thomas Petazzoni
2013-07-01 15:20 ` Ben Dooks
2013-07-08 5:39 ` jgq516 at gmail.com
2013-07-08 8:49 ` Will Deacon
2013-07-08 9:51 ` jgq516 at gmail.com
2013-07-08 11:02 ` Will Deacon
2013-07-08 17:03 ` Will Deacon
2013-07-09 1:18 ` jgq516 at gmail.com
2013-07-09 3:34 ` jgq516 at gmail.com
2013-07-09 7:45 ` Will Deacon
2013-07-09 9:55 ` jgq516 at gmail.com
2013-07-09 10:04 ` jgq516 at gmail.com
2013-07-09 15:36 ` Thomas Petazzoni
2013-07-08 9:58 ` Ben Dooks
2013-07-08 10:03 ` jgq516 at gmail.com
2013-07-08 11:10 ` Ben Dooks
2013-07-09 9:53 ` jgq516 at gmail.com
2013-07-09 9:59 ` Ben Dooks
-- strict thread matches above, loose matches on Subject: below --
2013-06-19 12:36 Initial big-endian support series Ben Dooks
2013-06-19 12:36 ` [PATCH 09/10] mvebu: support running big-endian Ben Dooks
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