From: josephl@nvidia.com (Joseph Lo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V2 01/11] ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9
Date: Wed, 3 Jul 2013 17:50:37 +0800 [thread overview]
Message-ID: <1372845047-25147-2-git-send-email-josephl@nvidia.com> (raw)
In-Reply-To: <1372845047-25147-1-git-send-email-josephl@nvidia.com>
The v7_invalidate_l1 was used for the L1 cache that come out from reset
in a undefined state. This is no need for Cortex-A15. We do it for A9
only.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
V2:
* take care the v7_invalidate_l1 in tegra_secondary_startup also
---
arch/arm/mach-tegra/headsmp.S | 3 ++-
arch/arm/mach-tegra/reset-handler.S | 7 +++++--
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 045c16f..2072e73 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -6,6 +6,7 @@
.section ".text.head", "ax"
ENTRY(tegra_secondary_startup)
- bl v7_invalidate_l1
+ check_cpu_part_num 0xc09, r8, r9
+ bleq v7_invalidate_l1
b secondary_startup
ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 39dc9e7..75285a3 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -40,9 +40,11 @@
* re-enabling sdram.
*
* r6: SoC ID
+ * r8: CPU part number
*/
ENTRY(tegra_resume)
- bl v7_invalidate_l1
+ check_cpu_part_num 0xc09, r8, r9
+ bleq v7_invalidate_l1
cpu_id r0
tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
@@ -70,7 +72,8 @@ no_cpu0_chk:
str r1, [r2]
1:
- check_cpu_part_num 0xc09, r8, r9
+ mov32 r9, 0xc09
+ cmp r8, r9
bne not_ca9
#ifdef CONFIG_HAVE_ARM_SCU
/* enable SCU */
--
1.8.3.2
next prev parent reply other threads:[~2013-07-03 9:50 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-03 9:50 [PATCH V2 00/11] ARM: tegra114: add support for system suspend Joseph Lo
2013-07-03 9:50 ` Joseph Lo [this message]
2013-07-03 9:50 ` [PATCH V2 02/11] ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL Joseph Lo
2013-07-03 9:50 ` [PATCH V2 03/11] ARM: tegra114: set up the correct L2 data RAM latency for Cortex-A15 Joseph Lo
2013-07-03 9:50 ` [PATCH V2 04/11] ARM: tegra114: add low level support code for cluster power down Joseph Lo
2013-07-03 9:50 ` [PATCH V2 05/11] ARM: tegra114: shut off the CPU rail when the last CPU in suspend Joseph Lo
2013-07-03 9:50 ` [PATCH V2 06/11] ARM: tegra114: hook tegra_tear_down_cpu function Joseph Lo
2013-07-03 9:50 ` [PATCH V2 07/11] ARM: tegra114: flowctrl: add support for cpu_suspend_enter/exit Joseph Lo
2013-07-03 9:50 ` [PATCH V2 08/11] clk: tegra114: add suspend/resume function for tegra_cpu_car_ops Joseph Lo
2013-07-03 9:50 ` [PATCH V2 09/11] ARM: tegra: remove the limitation that Tegra114 can't support suspend Joseph Lo
2013-07-03 9:50 ` [PATCH V2 10/11] ARM: dts: tegra114: dalmore: add GPIO power key support Joseph Lo
2013-07-09 17:03 ` Stephen Warren
2013-07-10 1:06 ` Joseph Lo
2013-07-03 9:50 ` [PATCH V2 11/11] ARM: dts: tegra114: dalmore: add PM configurations for PMC Joseph Lo
2013-07-19 16:54 ` [PATCH V2 00/11] ARM: tegra114: add support for system suspend Stephen Warren
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