From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv3 10/10] clocksource: sun4i: Fix bug when switching from periodic to oneshot modes
Date: Fri, 5 Jul 2013 21:34:37 +0200 [thread overview]
Message-ID: <1373052877-29366-11-git-send-email-maxime.ripard@free-electrons.com> (raw)
In-Reply-To: <1373052877-29366-1-git-send-email-maxime.ripard@free-electrons.com>
The interval was firing at was set up at probe time, and only changed in
the set_next_event, and never changed back, which is not really what is
expected.
When enabling the periodic mode, now set an interval to tick every
jiffy.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/clocksource/sun4i_timer.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
index 581e903..2b7cc31 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -38,6 +38,7 @@
#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
static void __iomem *timer_base;
+static u32 ticks_per_jiffy;
/*
* When we disable a timer, we need to wait at least for 2 cycles of
@@ -74,7 +75,8 @@ static void sun4i_clkevt_time_start(u8 timer, bool periodic)
else
val |= TIMER_CTL_ONESHOT;
- writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
+ writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
+ timer_base + TIMER_CTL_REG(timer));
}
static void sun4i_clkevt_mode(enum clock_event_mode mode,
@@ -83,6 +85,7 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode,
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
sun4i_clkevt_time_stop(0);
+ sun4i_clkevt_time_setup(0, ticks_per_jiffy);
sun4i_clkevt_time_start(0, true);
break;
case CLOCK_EVT_MODE_ONESHOT:
@@ -170,7 +173,9 @@ static void __init sun4i_timer_init(struct device_node *node)
writel(clk_get_rate(clk) / HZ,
timer_base + TIMER_INTVAL_REG(0));
- writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M) | TIMER_CTL_RELOAD,
+ ticks_per_jiffy = DIV_ROUND_UP(clk_get_rate(clk), HZ);
+
+ writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
timer_base + TIMER_CTL_REG(0));
ret = setup_irq(irq, &sun4i_timer_irq);
--
1.8.3.2
prev parent reply other threads:[~2013-07-05 19:34 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-05 19:34 [PATCHv3 00/10] clocksource: sunxi: Timer fixes and cleanup Maxime Ripard
2013-07-05 19:34 ` [PATCHv3 01/10] clocksource: sun4i: Use the BIT macros where possible Maxime Ripard
2013-07-05 19:34 ` [PATCHv3 02/10] clocksource: sun4i: Wrap macros arguments in parenthesis Maxime Ripard
2013-07-05 19:34 ` [PATCHv3 03/10] clocksource: sun4i: rename AUTORELOAD define to RELOAD Maxime Ripard
2013-07-05 19:34 ` [PATCHv3 04/10] clocksource: sun4i: Add clocksource and sched clock drivers Maxime Ripard
2013-07-05 19:34 ` [PATCHv3 05/10] clocksource: sun4i: Don't forget to enable the clock we use Maxime Ripard
2013-07-05 19:34 ` [PATCHv3 06/10] clocksource: sun4i: Fix the next event code Maxime Ripard
2013-07-05 19:34 ` [PATCHv3 07/10] clocksource: sun4i: Factor out some timer code Maxime Ripard
2013-07-05 19:34 ` [PATCHv3 08/10] clocksource: sun4i: Remove TIMER_SCAL variable Maxime Ripard
2013-07-05 20:48 ` Thomas Gleixner
2013-07-05 22:12 ` Maxime Ripard
2013-07-05 19:34 ` [PATCHv3 09/10] clocksource: sun4i: Cleanup parent clock setup Maxime Ripard
2013-07-05 19:34 ` Maxime Ripard [this message]
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