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From: josephl@nvidia.com (Joseph Lo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/8] ARM: tegra: config the polarity of the request of sys clock
Date: Mon, 5 Aug 2013 16:42:05 +0800	[thread overview]
Message-ID: <1375692125.1731.45.camel@jlo-ubuntu-64.nvidia.com> (raw)
In-Reply-To: <51FC1579.50100@wwwdotorg.org>

On Sat, 2013-08-03 at 04:24 +0800, Stephen Warren wrote:
> On 08/02/2013 01:48 AM, Joseph Lo wrote:
> > On Tue, 2013-07-30 at 06:47 +0800, Stephen Warren wrote:
> >> On 07/26/2013 03:15 AM, Joseph Lo wrote:
> >>> When suspending to LP1 mode, the SYSCLK will be clock gated. And different
> >>> board may have different polarity of the request of SYSCLK, this patch
> >>> configure the polarity from the DT for the board.
> >>
> >>> diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
> >>
> >>> @@ -238,6 +240,20 @@ void tegra_pmc_suspend_init(void)
> >>>  	reg = tegra_pmc_readl(PMC_CTRL);
> >>>  	reg |= TEGRA_POWER_CPU_PWRREQ_OE;
> >>>  	tegra_pmc_writel(reg, PMC_CTRL);
> >>> +
> >>> +	reg = tegra_pmc_readl(PMC_CTRL);
> >>> +
> >>> +	if (!pmc_pm_data.sysclkreq_high)
> >>> +		reg |= TEGRA_POWER_SYSCLK_POLARITY;
> >>> +	else
> >>> +		reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
> >>> +
> >>> +	/* configure the output inverts while the request is tristated */
> >>> +	tegra_pmc_writel(reg, PMC_CTRL);
> >>
> >> I think s/inverts/polarity/ in that comment would make a lot more sense.
> >>
> > Yes, thanks.
> > 
> >> Must _OE be disabled for the code to work correctly? If so, should the
> >> code explicitly clear _OE first, since who knows what state it was
> >> originally in? Can't we just set the new polarity and enable _OE in a
> >> single register write?
> >>
> > The SYSCLK is super clock that was connected to COP subsystem. It can't
> > be disabled when system is running. The boot loader had initialized it
> > and brought it to kernel. We follow the HW description in DT of the
> > polarity of SCLK to re-configure and re-init again. Then the PMC can
> > clock gate it when system go into suspend state.
> 
> So it sounds like the bootloader has already configured the clock to a
> certain polarity. If so, why do we need to reconfigure it again?
> 
> Or, is this code not duplicating something the bootloader must have
> done, but simply informing some HW in the PMC that's receiving SYSCLK
> how the clock is configured elsewhere?

I can't always guarantee the bootloader does the stuffs that kernel
needs. For this reason, it's better to do what the kernel needs in the
kernel.

  reply	other threads:[~2013-08-05  8:42 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-26  9:15 [PATCH 0/8] ARM: tegra: support LP1 suspend mode Joseph Lo
2013-07-26  9:15 ` [PATCH 1/8] ARM: tegra: add common resume handling code for LP1 resuming Joseph Lo
2013-07-29 22:38   ` Stephen Warren
2013-07-26  9:15 ` [PATCH 2/8] ARM: tegra: config the polarity of the request of sys clock Joseph Lo
2013-07-29 22:47   ` Stephen Warren
2013-08-02  7:48     ` Joseph Lo
2013-08-02 20:24       ` Stephen Warren
2013-08-05  8:42         ` Joseph Lo [this message]
2013-07-26  9:15 ` [PATCH 3/8] clk: tegra114: add LP1 suspend/resume support Joseph Lo
2013-07-29 22:51   ` Stephen Warren
2013-08-02  8:09     ` Joseph Lo
2013-08-02 20:32       ` Stephen Warren
2013-08-05  8:02         ` Joseph Lo
2013-08-05 17:00           ` Stephen Warren
2013-08-05 17:39             ` Stephen Warren
2013-08-06  9:10               ` Joseph Lo
2013-08-06 18:37                 ` Stephen Warren
2013-08-07  9:12                   ` Joseph Lo
2013-08-07 16:46                     ` Stephen Warren
2013-08-08  2:23                       ` Joseph Lo
2013-08-08 19:54                         ` Stephen Warren
2013-08-09  9:23                           ` Joseph Lo
2013-08-06  9:19             ` Joseph Lo
2013-07-26  9:15 ` [PATCH 4/8] ARM: tegra: add common LP1 suspend support Joseph Lo
2013-07-29 23:13   ` Stephen Warren
2013-08-02  9:27     ` Joseph Lo
2013-08-02 20:40       ` Stephen Warren
2013-08-05  8:07         ` Joseph Lo
2013-07-26  9:15 ` [PATCH 5/8] ARM: tegra30: add " Joseph Lo
2013-07-29 23:45   ` Stephen Warren
2013-08-05  6:46     ` Joseph Lo
2013-07-26  9:15 ` [PATCH 6/8] ARM: tegra20: " Joseph Lo
2013-07-26  9:15 ` [PATCH 7/8] ARM: tegra114: " Joseph Lo
2013-07-29 23:53   ` Stephen Warren
2013-08-05  6:51     ` Joseph Lo
2013-07-26  9:15 ` [PATCH 8/8] ARM: dts: tegra: enable LP1 suspend mode Joseph Lo
2013-07-27 16:12 ` [PATCH 0/8] ARM: tegra: support " Marc Dietrich
2013-07-27 16:20   ` Dmitry Osipenko
2013-07-27 18:09     ` Marc Dietrich
2013-07-27 18:26       ` Dmitry Osipenko
2013-07-27 18:29         ` Dmitry Osipenko
2013-07-27 19:03         ` Marc Dietrich
2013-07-27 19:11           ` Dmitry Osipenko
2013-07-30  9:49   ` Joseph Lo

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