* [PATCH 1/5] ARM: vexpress/dcscb: fix cache disabling sequences
2013-08-06 18:54 [PATCH 0/5] ARM: vexpress: TC2 MCPC/SPC again, the complete series Pawel Moll
@ 2013-08-06 18:54 ` Pawel Moll
2013-08-06 18:54 ` [PATCH 2/5] ARM: vexpress/TC2: add Serial Power Controller (SPC) support Pawel Moll
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Pawel Moll @ 2013-08-06 18:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Nicolas Pitre <nicolas.pitre@linaro.org>
Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the
cache when the CTRL.C bit is cleared. Let's ensure there is no memory
access within the disable and flush cache sequence, including to the
stack.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
---
arch/arm/mach-vexpress/dcscb.c | 58 +++++++++++++++++++++++++++---------------
1 file changed, 37 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 16d57a8..85fffa7 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -136,14 +136,29 @@ static void dcscb_power_down(void)
/*
* Flush all cache levels for this cluster.
*
- * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
- * a preliminary flush here for those CPUs. At least, that's
- * the theory -- without the extra flush, Linux explodes on
- * RTSM (to be investigated).
+ * To do so we do:
+ * - Clear the SCTLR.C bit to prevent further cache allocations
+ * - Flush the whole cache
+ * - Clear the ACTLR "SMP" bit to disable local coherency
+ *
+ * Let's do it in the safest possible way i.e. with
+ * no memory access within the following sequence
+ * including to the stack.
*/
- flush_cache_all();
- set_cr(get_cr() & ~CR_C);
- flush_cache_all();
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
+ "bic r0, r0, #"__stringify(CR_C)" \n\t"
+ "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
+ "isb \n\t"
+ "bl v7_flush_dcache_all \n\t"
+ "clrex \n\t"
+ "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
+ "bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
+ "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
+ "isb \n\t"
+ "dsb "
+ : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+ "r9","r10","r11","lr","memory");
/*
* This is a harmless no-op. On platforms with a real
@@ -152,9 +167,6 @@ static void dcscb_power_down(void)
*/
outer_flush_all();
- /* Disable local coherency by clearing the ACTLR "SMP" bit: */
- set_auxcr(get_auxcr() & ~(1 << 6));
-
/*
* Disable cluster-level coherency by masking
* incoming snoops and DVM messages:
@@ -167,18 +179,22 @@ static void dcscb_power_down(void)
/*
* Flush the local CPU cache.
- *
- * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
- * a preliminary flush here for those CPUs. At least, that's
- * the theory -- without the extra flush, Linux explodes on
- * RTSM (to be investigated).
+ * Let's do it in the safest possible way as above.
*/
- flush_cache_louis();
- set_cr(get_cr() & ~CR_C);
- flush_cache_louis();
-
- /* Disable local coherency by clearing the ACTLR "SMP" bit: */
- set_auxcr(get_auxcr() & ~(1 << 6));
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
+ "bic r0, r0, #"__stringify(CR_C)" \n\t"
+ "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
+ "isb \n\t"
+ "bl v7_flush_dcache_louis \n\t"
+ "clrex \n\t"
+ "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
+ "bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
+ "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
+ "isb \n\t"
+ "dsb "
+ : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+ "r9","r10","r11","lr","memory");
}
__mcpm_cpu_down(cpu, cluster);
--
1.8.1.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/5] ARM: vexpress/TC2: add Serial Power Controller (SPC) support
2013-08-06 18:54 [PATCH 0/5] ARM: vexpress: TC2 MCPC/SPC again, the complete series Pawel Moll
2013-08-06 18:54 ` [PATCH 1/5] ARM: vexpress/dcscb: fix cache disabling sequences Pawel Moll
@ 2013-08-06 18:54 ` Pawel Moll
2013-08-06 18:58 ` Pawel Moll
2013-08-06 18:54 ` [PATCH 3/5] ARM: vexpress: Add SCC & SPC to V2P-CA15_A7's device tree Pawel Moll
` (2 subsequent siblings)
4 siblings, 1 reply; 7+ messages in thread
From: Pawel Moll @ 2013-08-06 18:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
The TC2 versatile express core tile integrates a logic block that provides
the interface between the dual cluster test-chip and the M3 microcontroller
that carries out power management. The logic block, called Serial Power
Controller (SPC), contains several memory mapped registers to control among
other things low-power states, wake-up irqs and per-CPU jump addresses
registers.
This patch provides a driver that enables run-time control of features
implemented by the SPC power management control logic with an API to
be used by different subsystem drivers on top.
The SPC control logic is required to be programmed very early in the boot
process to reset secondary CPUs on the TC2 testchip, set-up jump addresses
and wake-up IRQs for power management. Hence, waiting for core changes to
be made in the device core code to enable early registration of platform
devices, the driver puts in place an early init scheme that allows kernel
drivers to initialize the SPC driver directly from the components requiring
it, if their initialization routine is called before this driver init
function during the boot process.
Device tree bindings documentation for the SPC component is also provided.
Cc: Olof Johansson <olof@lixom.net>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
[ np: moved from drivers/mfd/ to drivers/platform/vexpress/ ]
Signed-off-by: Nicolas Pitre <nico@linaro.org>
[ PM: moved again to arch/arm/mach-vexpress, requested by Olof ]
[ PM: removed generic compatible value and useless printk, from Olof ]
[ PM: removed SPC_BASE so the driver only uses SPC registers ]
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
.../devicetree/bindings/arm/vexpress-spc.txt | 30 +++
arch/arm/mach-vexpress/spc.c | 246 +++++++++++++++++++++
arch/arm/mach-vexpress/spc.h | 25 +++
drivers/platform/Kconfig | 1 -
4 files changed, 301 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress-spc.txt
create mode 100644 arch/arm/mach-vexpress/spc.c
create mode 100644 arch/arm/mach-vexpress/spc.h
diff --git a/Documentation/devicetree/bindings/arm/vexpress-spc.txt b/Documentation/devicetree/bindings/arm/vexpress-spc.txt
new file mode 100644
index 0000000..c2e0e6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress-spc.txt
@@ -0,0 +1,30 @@
+* ARM Versatile Express Serial Power Controller device tree bindings
+
+Latest ARM development boards implement a power management interface (serial
+power controller - SPC) that is capable of managing power states transitions,
+wake-up IRQs and resume addresses for ARM multiprocessor testchips.
+The serial controller can be programmed through a memory mapped interface
+that enables communication between firmware running on the microcontroller
+managing power states and the application processors.
+
+The SPC DT bindings are defined as follows:
+
+- spc node
+
+ - compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be
+ "arm,vexpress-spc,v2p-ca15_a7", "arm,vexpress-spc"
+ - reg:
+ Usage: required
+ Value type: <prop-encode-array>
+ Definition: A standard property that specifies the base address
+ and the size of the SPC address space
+
+Example:
+
+spc at 7fff0b00 {
+ compatible = "arm,vexpress-spc,v2p-ca15_a7", "arm,vexpress-spc";
+ reg = <0x7fff0b00 0x100>;
+};
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
new file mode 100644
index 0000000..bd6d4f2
--- /dev/null
+++ b/arch/arm/mach-vexpress/spc.c
@@ -0,0 +1,246 @@
+/*
+ * Versatile Express Serial Power Controller (SPC) support
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
+ * Achin Gupta <achin.gupta@arm.com>
+ * Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/vexpress.h>
+
+#include <asm/cacheflush.h>
+
+#define SPCLOG "vexpress-spc: "
+
+/* SCC conf registers */
+#define A15_CONF 0x400
+#define SYS_INFO 0x700
+
+/* SPC wake-up IRQs status and mask */
+#define WAKE_INT_MASK 0x24
+#define WAKE_INT_RAW 0x28
+#define WAKE_INT_STAT 0x2c
+/* SPC power down registers */
+#define A15_PWRDN_EN 0x30
+#define A7_PWRDN_EN 0x34
+/* SPC per-CPU mailboxes */
+#define A15_BX_ADDR0 0x68
+#define A7_BX_ADDR0 0x78
+
+/* wake-up interrupt masks */
+#define GBL_WAKEUP_INT_MSK (0x3 << 10)
+
+/* TC2 static dual-cluster configuration */
+#define MAX_CLUSTERS 2
+
+struct ve_spc_drvdata {
+ void __iomem *baseaddr;
+ /*
+ * A15s cluster identifier
+ * It corresponds to A15 processors MPIDR[15:8] bitfield
+ */
+ u32 a15_clusid;
+};
+
+static struct ve_spc_drvdata *info;
+
+static inline bool cluster_is_a15(u32 cluster)
+{
+ return cluster == info->a15_clusid;
+}
+
+/**
+ * ve_spc_global_wakeup_irq()
+ *
+ * Function to set/clear global wakeup IRQs. Not protected by locking since
+ * it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @set: if true, global wake-up IRQs are set, if false they are cleared
+ */
+void ve_spc_global_wakeup_irq(bool set)
+{
+ u32 reg;
+
+ reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
+
+ if (set)
+ reg |= GBL_WAKEUP_INT_MSK;
+ else
+ reg &= ~GBL_WAKEUP_INT_MSK;
+
+ writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
+}
+
+/**
+ * ve_spc_cpu_wakeup_irq()
+ *
+ * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
+ * it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @cpu: mpidr[7:0] bitfield describing cpu affinity level
+ * @set: if true, wake-up IRQs are set, if false they are cleared
+ */
+void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
+{
+ u32 mask, reg;
+
+ if (cluster >= MAX_CLUSTERS)
+ return;
+
+ mask = 1 << cpu;
+
+ if (!cluster_is_a15(cluster))
+ mask <<= 4;
+
+ reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
+
+ if (set)
+ reg |= mask;
+ else
+ reg &= ~mask;
+
+ writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
+}
+
+/**
+ * ve_spc_set_resume_addr() - set the jump address used for warm boot
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @cpu: mpidr[7:0] bitfield describing cpu affinity level
+ * @addr: physical resume address
+ */
+void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
+{
+ void __iomem *baseaddr;
+
+ if (cluster >= MAX_CLUSTERS)
+ return;
+
+ if (cluster_is_a15(cluster))
+ baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
+ else
+ baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
+
+ writel_relaxed(addr, baseaddr);
+}
+
+/**
+ * ve_spc_get_nr_cpus() - get number of cpus in a cluster
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ *
+ * Return: > 0 number of cpus in the cluster
+ * or 0 if cluster number invalid
+ */
+u32 ve_spc_get_nr_cpus(u32 cluster)
+{
+ u32 val;
+
+ if (cluster >= MAX_CLUSTERS)
+ return 0;
+
+ val = readl_relaxed(info->baseaddr + SYS_INFO);
+ val = cluster_is_a15(cluster) ? (val >> 16) : (val >> 20);
+ return val & 0xf;
+}
+
+/**
+ * ve_spc_powerdown()
+ *
+ * Function to enable/disable cluster powerdown. Not protected by locking
+ * since it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @enable: if true enables powerdown, if false disables it
+ */
+void ve_spc_powerdown(u32 cluster, bool enable)
+{
+ u32 pwdrn_reg;
+
+ if (cluster >= MAX_CLUSTERS)
+ return;
+
+ pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
+ writel_relaxed(enable, info->baseaddr + pwdrn_reg);
+}
+
+static int __init ve_spc_probe(void)
+{
+ int ret;
+ struct device_node *dn;
+
+ dn = of_find_compatible_node(NULL, NULL,
+ "arm,vexpress-scc,v2p-ca15_a7");
+
+ if (!dn)
+ return -ENODEV;
+
+ info = kzalloc(sizeof(*info), GFP_KERNEL);
+ if (!info) {
+ pr_err(SPCLOG "unable to allocate mem\n");
+ return -ENOMEM;
+ }
+
+ info->baseaddr = of_iomap(dn, 0);
+ if (!info->baseaddr) {
+ pr_err(SPCLOG "unable to ioremap memory\n");
+ ret = -ENXIO;
+ goto mem_free;
+ }
+
+ info->a15_clusid = readl_relaxed(info->baseaddr + A15_CONF) & 0xf;
+
+ /*
+ * Multi-cluster systems may need this data when non-coherent, during
+ * cluster power-up/power-down. Make sure driver info reaches main
+ * memory.
+ */
+ sync_cache_w(info);
+ sync_cache_w(&info);
+
+ return 0;
+
+mem_free:
+ kfree(info);
+ return ret;
+}
+
+/**
+ * ve_spc_init()
+ *
+ * Function exported to manage pre early_initcall initialization.
+ * SPC code is needed very early in the boot process to bring CPUs out of
+ * reset and initialize power management back-end so an init interface is
+ * provided to platform code to allow early initialization. The init
+ * interface can be removed as soon as the DT layer and platform bus allow
+ * platform device creation and probing before SMP boot.
+ */
+int __init ve_spc_init(void)
+{
+ static int ve_spc_init_status __initdata = -EAGAIN;
+
+ if (ve_spc_init_status == -EAGAIN)
+ ve_spc_init_status = ve_spc_probe();
+
+ return ve_spc_init_status;
+}
diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-vexpress/spc.h
new file mode 100644
index 0000000..f6b87fc
--- /dev/null
+++ b/arch/arm/mach-vexpress/spc.h
@@ -0,0 +1,25 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+
+
+#ifndef __SPC_H_
+#define __SPC_H_
+
+int __init ve_spc_init(void);
+void ve_spc_global_wakeup_irq(bool set);
+void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set);
+void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr);
+u32 ve_spc_get_nr_cpus(u32 cluster);
+void ve_spc_powerdown(u32 cluster, bool enable);
+
+#endif
diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig
index 69616ae..57811ea 100644
--- a/drivers/platform/Kconfig
+++ b/drivers/platform/Kconfig
@@ -4,4 +4,3 @@ endif
if GOLDFISH
source "drivers/platform/goldfish/Kconfig"
endif
-
--
1.8.1.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/5] ARM: vexpress: Add SCC & SPC to V2P-CA15_A7's device tree
2013-08-06 18:54 [PATCH 0/5] ARM: vexpress: TC2 MCPC/SPC again, the complete series Pawel Moll
2013-08-06 18:54 ` [PATCH 1/5] ARM: vexpress/dcscb: fix cache disabling sequences Pawel Moll
2013-08-06 18:54 ` [PATCH 2/5] ARM: vexpress/TC2: add Serial Power Controller (SPC) support Pawel Moll
@ 2013-08-06 18:54 ` Pawel Moll
2013-08-06 18:54 ` [PATCH 4/5] ARM: vexpress/TC2: basic PM support Pawel Moll
2013-08-06 18:54 ` [PATCH 5/5] ARM: vexpress/TC2: implement PM suspend method Pawel Moll
4 siblings, 0 replies; 7+ messages in thread
From: Pawel Moll @ 2013-08-06 18:54 UTC (permalink / raw)
To: linux-arm-kernel
SCC is a set of random system control registers. One of
the functionality provided is an interface to power
management features (SPC).
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index d2803be..004025d 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -125,6 +125,17 @@
clock-names = "apb_pclk";
};
+ scc at 7fff0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x7fff0000 0x1000>;
+
+ spc at b00 {
+ compatible = "arm,vexpress-spc,v2p-ca15_a7", "arm,vexpress-spc";
+ reg = <0xb00 0x100>;
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
--
1.8.1.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 4/5] ARM: vexpress/TC2: basic PM support
2013-08-06 18:54 [PATCH 0/5] ARM: vexpress: TC2 MCPC/SPC again, the complete series Pawel Moll
` (2 preceding siblings ...)
2013-08-06 18:54 ` [PATCH 3/5] ARM: vexpress: Add SCC & SPC to V2P-CA15_A7's device tree Pawel Moll
@ 2013-08-06 18:54 ` Pawel Moll
2013-08-06 18:54 ` [PATCH 5/5] ARM: vexpress/TC2: implement PM suspend method Pawel Moll
4 siblings, 0 replies; 7+ messages in thread
From: Pawel Moll @ 2013-08-06 18:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Nicolas Pitre <nico@linaro.org>
This is the MCPM backend for the Virtual Express A15x2 A7x3 CoreTile
aka TC2. This provides cluster management for SMP secondary boot and
CPU hotplug.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[PM: including local "spc.h" as required by changes in SPC driver]
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/mach-vexpress/Kconfig | 8 ++
arch/arm/mach-vexpress/Makefile | 1 +
arch/arm/mach-vexpress/tc2_pm.c | 288 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 297 insertions(+)
create mode 100644 arch/arm/mach-vexpress/tc2_pm.c
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index b8bbabe..c700e62 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -66,4 +66,12 @@ config ARCH_VEXPRESS_DCSCB
This is needed to provide CPU and cluster power management
on RTSM implementing big.LITTLE.
+config ARCH_VEXPRESS_TC2_PM
+ bool "Versatile Express TC2 power management"
+ depends on MCPM
+ select ARM_CCI
+ help
+ Support for CPU and cluster power management on Versatile Express
+ with a TC2 (A15x2 A7x3) big.LITTLE core tile.
+
endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 48ba89a..36ea824 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -7,5 +7,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
obj-y := v2m.o
obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o
+obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o spc.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
new file mode 100644
index 0000000..1d4de8e
--- /dev/null
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -0,0 +1,288 @@
+/*
+ * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
+ *
+ * Created by: Nicolas Pitre, October 2012
+ * Copyright: (C) 2012-2013 Linaro Limited
+ *
+ * Some portions of this file were originally written by Achin Gupta
+ * Copyright: (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+
+#include <asm/mcpm.h>
+#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+
+#include <linux/arm-cci.h>
+
+#include "spc.h"
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+#define TC2_CLUSTERS 2
+#define TC2_MAX_CPUS_PER_CLUSTER 3
+
+/* Keep per-cpu usage count to cope with unordered up/down requests */
+static int tc2_pm_use_count[TC2_MAX_CPUS_PER_CLUSTER][TC2_CLUSTERS];
+
+#define tc2_cluster_unused(cluster) \
+ (!tc2_pm_use_count[0][cluster] && \
+ !tc2_pm_use_count[1][cluster] && \
+ !tc2_pm_use_count[2][cluster])
+
+static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
+{
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ if (cluster >= TC2_CLUSTERS || cpu >= ve_spc_get_nr_cpus(cluster))
+ return -EINVAL;
+
+ /*
+ * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+ * variant exists, we need to disable IRQs manually here.
+ */
+ local_irq_disable();
+ arch_spin_lock(&tc2_pm_lock);
+
+ if (tc2_cluster_unused(cluster))
+ ve_spc_powerdown(cluster, false);
+
+ tc2_pm_use_count[cpu][cluster]++;
+ if (tc2_pm_use_count[cpu][cluster] == 1) {
+ ve_spc_set_resume_addr(cluster, cpu,
+ virt_to_phys(mcpm_entry_point));
+ ve_spc_cpu_wakeup_irq(cluster, cpu, true);
+ } else if (tc2_pm_use_count[cpu][cluster] != 2) {
+ /*
+ * The only possible values are:
+ * 0 = CPU down
+ * 1 = CPU (still) up
+ * 2 = CPU requested to be up before it had a chance
+ * to actually make itself down.
+ * Any other value is a bug.
+ */
+ BUG();
+ }
+
+ arch_spin_unlock(&tc2_pm_lock);
+ local_irq_enable();
+
+ return 0;
+}
+
+static void tc2_pm_power_down(void)
+{
+ unsigned int mpidr, cpu, cluster;
+ bool last_man = false, skip_wfi = false;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
+
+ __mcpm_cpu_going_down(cpu, cluster);
+
+ arch_spin_lock(&tc2_pm_lock);
+ BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+ tc2_pm_use_count[cpu][cluster]--;
+ if (tc2_pm_use_count[cpu][cluster] == 0) {
+ ve_spc_cpu_wakeup_irq(cluster, cpu, true);
+ if (tc2_cluster_unused(cluster)) {
+ ve_spc_powerdown(cluster, true);
+ ve_spc_global_wakeup_irq(true);
+ last_man = true;
+ }
+ } else if (tc2_pm_use_count[cpu][cluster] == 1) {
+ /*
+ * A power_up request went ahead of us.
+ * Even if we do not want to shut this CPU down,
+ * the caller expects a certain state as if the WFI
+ * was aborted. So let's continue with cache cleaning.
+ */
+ skip_wfi = true;
+ } else
+ BUG();
+
+ if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+ arch_spin_unlock(&tc2_pm_lock);
+
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+ /*
+ * On the Cortex-A15 we need to disable
+ * L2 prefetching before flushing the cache.
+ */
+ asm volatile(
+ "mcr p15, 1, %0, c15, c0, 3 \n\t"
+ "isb \n\t"
+ "dsb "
+ : : "r" (0x400) );
+ }
+
+ /*
+ * We need to disable and flush the whole (L1 and L2) cache.
+ * Let's do it in the safest possible way i.e. with
+ * no memory access within the following sequence
+ * including the stack.
+ */
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
+ "bic r0, r0, #"__stringify(CR_C)" \n\t"
+ "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
+ "isb \n\t"
+ "bl v7_flush_dcache_all \n\t"
+ "clrex \n\t"
+ "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
+ "bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
+ "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
+ "isb \n\t"
+ "dsb "
+ : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+ "r9","r10","r11","lr","memory");
+
+ cci_disable_port_by_cpu(mpidr);
+
+ __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+ } else {
+ /*
+ * If last man then undo any setup done previously.
+ */
+ if (last_man) {
+ ve_spc_powerdown(cluster, false);
+ ve_spc_global_wakeup_irq(false);
+ }
+
+ arch_spin_unlock(&tc2_pm_lock);
+
+ /*
+ * We need to disable and flush only the L1 cache.
+ * Let's do it in the safest possible way as above.
+ */
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
+ "bic r0, r0, #"__stringify(CR_C)" \n\t"
+ "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
+ "isb \n\t"
+ "bl v7_flush_dcache_louis \n\t"
+ "clrex \n\t"
+ "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
+ "bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
+ "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
+ "isb \n\t"
+ "dsb "
+ : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+ "r9","r10","r11","lr","memory");
+ }
+
+ __mcpm_cpu_down(cpu, cluster);
+
+ /* Now we are prepared for power-down, do it: */
+ if (!skip_wfi)
+ wfi();
+
+ /* Not dead@this point? Let our caller cope. */
+}
+
+static void tc2_pm_powered_up(void)
+{
+ unsigned int mpidr, cpu, cluster;
+ unsigned long flags;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
+
+ local_irq_save(flags);
+ arch_spin_lock(&tc2_pm_lock);
+
+ if (tc2_cluster_unused(cluster)) {
+ ve_spc_powerdown(cluster, false);
+ ve_spc_global_wakeup_irq(false);
+ }
+
+ if (!tc2_pm_use_count[cpu][cluster])
+ tc2_pm_use_count[cpu][cluster] = 1;
+
+ ve_spc_cpu_wakeup_irq(cluster, cpu, false);
+ ve_spc_set_resume_addr(cluster, cpu, 0);
+
+ arch_spin_unlock(&tc2_pm_lock);
+ local_irq_restore(flags);
+}
+
+static const struct mcpm_platform_ops tc2_pm_power_ops = {
+ .power_up = tc2_pm_power_up,
+ .power_down = tc2_pm_power_down,
+ .powered_up = tc2_pm_powered_up,
+};
+
+static bool __init tc2_pm_usage_count_init(void)
+{
+ unsigned int mpidr, cpu, cluster;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ if (cluster >= TC2_CLUSTERS || cpu >= ve_spc_get_nr_cpus(cluster)) {
+ pr_err("%s: boot CPU is out of bound!\n", __func__);
+ return false;
+ }
+ tc2_pm_use_count[cpu][cluster] = 1;
+ return true;
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
+{
+ asm volatile (" \n"
+" cmp r0, #1 \n"
+" bxne lr \n"
+" b cci_enable_port_for_self ");
+}
+
+static int __init tc2_pm_init(void)
+{
+ int ret;
+
+ ret = ve_spc_init();
+ if (ret)
+ return ret;
+
+ if (!cci_probed())
+ return -ENODEV;
+
+ if (!tc2_pm_usage_count_init())
+ return -EINVAL;
+
+ ret = mcpm_platform_register(&tc2_pm_power_ops);
+ if (!ret) {
+ mcpm_sync_init(tc2_pm_power_up_setup);
+ pr_info("TC2 power management initialized\n");
+ }
+ return ret;
+}
+
+early_initcall(tc2_pm_init);
--
1.8.1.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 5/5] ARM: vexpress/TC2: implement PM suspend method
2013-08-06 18:54 [PATCH 0/5] ARM: vexpress: TC2 MCPC/SPC again, the complete series Pawel Moll
` (3 preceding siblings ...)
2013-08-06 18:54 ` [PATCH 4/5] ARM: vexpress/TC2: basic PM support Pawel Moll
@ 2013-08-06 18:54 ` Pawel Moll
4 siblings, 0 replies; 7+ messages in thread
From: Pawel Moll @ 2013-08-06 18:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Nicolas Pitre <nico@linaro.org>
Similar to power_down(), except that for a suspend, the firmware
mailbox address has to be set prior entering low power mode.
The residency argument is not used yet, so the last man always shuts
down the cluster for now.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/mach-vexpress/tc2_pm.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
index 1d4de8e..79cf4bc 100644
--- a/arch/arm/mach-vexpress/tc2_pm.c
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -85,7 +85,7 @@ static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
return 0;
}
-static void tc2_pm_power_down(void)
+static void tc2_pm_down(u64 residency)
{
unsigned int mpidr, cpu, cluster;
bool last_man = false, skip_wfi = false;
@@ -199,6 +199,22 @@ static void tc2_pm_power_down(void)
/* Not dead at this point? Let our caller cope. */
}
+static void tc2_pm_power_down(void)
+{
+ tc2_pm_down(0);
+}
+
+static void tc2_pm_suspend(u64 residency)
+{
+ unsigned int mpidr, cpu, cluster;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
+ tc2_pm_down(residency);
+}
+
static void tc2_pm_powered_up(void)
{
unsigned int mpidr, cpu, cluster;
@@ -232,6 +248,7 @@ static void tc2_pm_powered_up(void)
static const struct mcpm_platform_ops tc2_pm_power_ops = {
.power_up = tc2_pm_power_up,
.power_down = tc2_pm_power_down,
+ .suspend = tc2_pm_suspend,
.powered_up = tc2_pm_powered_up,
};
--
1.8.1.2
^ permalink raw reply related [flat|nested] 7+ messages in thread