From: joelf@ti.com (Joel Fernandes)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 08/14] crypto: omap-aes: PIO mode: Add IRQ handler and walk SGs
Date: Sat, 17 Aug 2013 21:42:29 -0500 [thread overview]
Message-ID: <1376793755-30478-9-git-send-email-joelf@ti.com> (raw)
In-Reply-To: <1376793755-30478-1-git-send-email-joelf@ti.com>
We add an IRQ handler that implements a state-machine for PIO-mode and data
structures for walking the scatter-gather list. The IRQ handler is called in
succession both when data is available to read or next data can be sent for
processing. This process continues till the entire in/out SG lists have been
walked. Once the SG-list has been completely walked, the IRQ handler schedules
the done_task tasklet.
Also add a useful macro that is used through out the IRQ code for a common
pattern of calculating how much an SG list has been walked. This improves code
readability and avoids checkpatch errors.
Signed-off-by: Joel Fernandes <joelf@ti.com>
---
drivers/crypto/omap-aes.c | 90 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/drivers/crypto/omap-aes.c b/drivers/crypto/omap-aes.c
index 9a964e8..889dc99 100644
--- a/drivers/crypto/omap-aes.c
+++ b/drivers/crypto/omap-aes.c
@@ -39,6 +39,8 @@
#define DST_MAXBURST 4
#define DMA_MIN (DST_MAXBURST * sizeof(u32))
+#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
+
/* OMAP TRM gives bitfields as start:end, where start is the higher bit
number. For example 7:0 */
#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
@@ -91,6 +93,8 @@
#define FLAGS_FAST BIT(5)
#define FLAGS_BUSY BIT(6)
+#define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2)
+
struct omap_aes_ctx {
struct omap_aes_dev *dd;
@@ -156,6 +160,8 @@ struct omap_aes_dev {
size_t total;
struct scatterlist *in_sg;
struct scatterlist *out_sg;
+ struct scatter_walk in_walk;
+ struct scatter_walk out_walk;
int dma_in;
struct dma_chan *dma_lch_in;
int dma_out;
@@ -852,6 +858,90 @@ static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
.minor_shift = 0,
};
+static irqreturn_t omap_aes_irq(int irq, void *dev_id)
+{
+ struct omap_aes_dev *dd = dev_id;
+ u32 status, i;
+ u32 *src, *dst;
+
+ status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
+ if (status & AES_REG_IRQ_DATA_IN) {
+ omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
+
+ BUG_ON(!dd->in_sg);
+
+ BUG_ON(_calc_walked(in) > dd->in_sg->length);
+
+ src = sg_virt(dd->in_sg) + _calc_walked(in);
+
+ for (i = 0; i < AES_BLOCK_WORDS; i++) {
+ omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
+
+ scatterwalk_advance(&dd->in_walk, 4);
+ if (dd->in_sg->length == _calc_walked(in)) {
+ dd->in_sg = scatterwalk_sg_next(dd->in_sg);
+ if (dd->in_sg) {
+ scatterwalk_start(&dd->in_walk,
+ dd->in_sg);
+ src = sg_virt(dd->in_sg) +
+ _calc_walked(in);
+ }
+ } else {
+ src++;
+ }
+ }
+
+ /* Clear IRQ status */
+ status &= ~AES_REG_IRQ_DATA_IN;
+ omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
+
+ /* Enable DATA_OUT interrupt */
+ omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
+
+ } else if (status & AES_REG_IRQ_DATA_OUT) {
+ omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
+
+ BUG_ON(!dd->out_sg);
+
+ BUG_ON(_calc_walked(out) > dd->out_sg->length);
+
+ dst = sg_virt(dd->out_sg) + _calc_walked(out);
+
+ for (i = 0; i < AES_BLOCK_WORDS; i++) {
+ *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
+ scatterwalk_advance(&dd->out_walk, 4);
+ if (dd->out_sg->length == _calc_walked(out)) {
+ dd->out_sg = scatterwalk_sg_next(dd->out_sg);
+ if (dd->out_sg) {
+ scatterwalk_start(&dd->out_walk,
+ dd->out_sg);
+ dst = sg_virt(dd->out_sg) +
+ _calc_walked(out);
+ }
+ } else {
+ dst++;
+ }
+ }
+
+ dd->total -= AES_BLOCK_SIZE;
+
+ BUG_ON(dd->total < 0);
+
+ /* Clear IRQ status */
+ status &= ~AES_REG_IRQ_DATA_OUT;
+ omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
+
+ if (!dd->total)
+ /* All bytes read! */
+ tasklet_schedule(&dd->done_task);
+ else
+ /* Enable DATA_IN interrupt for next block */
+ omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
+ }
+
+ return IRQ_HANDLED;
+}
+
static const struct of_device_id omap_aes_of_match[] = {
{
.compatible = "ti,omap2-aes",
--
1.7.9.5
next prev parent reply other threads:[~2013-08-18 2:42 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-18 2:42 [PATCH v2 00/14] crypto: omap-aes: Improve DMA, add PIO mode and support for AM437x Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 01/14] crypto: scatterwalk: Add support for calculating number of SG elements Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 02/14] crypto: omap-aes: Add useful debug macros Joel Fernandes
2013-08-18 4:22 ` Joe Perches
2013-08-18 5:56 ` Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 03/14] crypto: omap-aes: Populate number of SG elements Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 04/14] crypto: omap-aes: Simplify DMA usage by using direct SGs Joel Fernandes
2013-08-20 12:57 ` Lokesh Vutla
2013-08-21 0:54 ` Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 05/14] crypto: omap-aes: Sync SG before DMA operation Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 06/14] crypto: omap-aes: Remove previously used intermediate buffers Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 07/14] crypto: omap-aes: Add IRQ info and helper macros Joel Fernandes
2013-08-18 2:42 ` Joel Fernandes [this message]
2013-08-18 2:42 ` [PATCH v2 09/14] crypto: omap-aes: PIO mode: platform data for OMAP4/AM437x and trigger Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 10/14] crypto: omap-aes: Switch to PIO mode during probe Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 11/14] crypto: omap-aes: Add support for cases of unaligned lengths Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 12/14] crypto: omap-aes: Convert kzalloc to devm_kzalloc Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 13/14] crypto: omap-aes: Convert request_irq to devm_request_irq Joel Fernandes
2013-08-18 2:42 ` [PATCH v2 14/14] crypto: omap-aes: Kconfig: Add build support for AM437x Joel Fernandes
2013-08-21 11:50 ` [PATCH v2 00/14] crypto: omap-aes: Improve DMA, add PIO mode and " Herbert Xu
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