[PATCHv3 1/4] arm: dts: Add clock entries for timers in SOCFPGA

[PATCHv3 1/4] arm: dts: Add clock entries for timers in SOCFPGA

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Set the correct clock entries for the the timers, and also clean up
the timer entries for SOCFPGA by removing timer<n> in the timer entry.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
CC: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
CC: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
CC: Jamie Iles <jamie@jamieiles.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: devicetree at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/boot/dts/socfpga.dtsi         |   16 ++++++++--------
 arch/arm/boot/dts/socfpga_cyclone5.dts |    8 ++++----
 arch/arm/boot/dts/socfpga_vt.dts       |    8 ++++----
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 9706767..9957bae 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -26,10 +26,6 @@
 		ethernet1 = &gmac1;
 		serial0 = &uart0;
 		serial1 = &uart1;
-		timer0 = &timer0;
-		timer1 = &timer1;
-		timer2 = &timer2;
-		timer3 = &timer3;
 	};
 
 	cpus {
@@ -486,28 +482,32 @@
 			interrupts = <1 13 0xf04>;
 		};
 
-		timer0: timer0 at ffc08000 {
+		timer at ffc08000 {
 			compatible = "snps,dw-apb-timer-sp";
 			interrupts = <0 167 4>;
 			reg = <0xffc08000 0x1000>;
+			clocks = <&osc>;
 		};
 
-		timer1: timer1 at ffc09000 {
+		timer at ffc09000 {
 			compatible = "snps,dw-apb-timer-sp";
 			interrupts = <0 168 4>;
 			reg = <0xffc09000 0x1000>;
+			clocks = <&osc>;
 		};
 
-		timer2: timer2 at ffd00000 {
+		timer at ffd00000 {
 			compatible = "snps,dw-apb-timer-osc";
 			interrupts = <0 169 4>;
 			reg = <0xffd00000 0x1000>;
+			clocks = <&l4_sp_clk>;
 		};
 
-		timer3: timer3 at ffd01000 {
+		timer at ffd01000 {
 			compatible = "snps,dw-apb-timer-osc";
 			interrupts = <0 170 4>;
 			reg = <0xffd01000 0x1000>;
+			clocks = <&l4_sp_clk>;
 		};
 
 		uart0: serial0 at ffc02000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 698dde9..c1af01c 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -67,19 +67,19 @@
 			};
 		};
 
-		timer0 at ffc08000 {
+		timer at ffc08000 {
 			clock-frequency = <100000000>;
 		};
 
-		timer1 at ffc09000 {
+		timer at ffc09000 {
 			clock-frequency = <100000000>;
 		};
 
-		timer2 at ffd00000 {
+		timer at ffd00000 {
 			clock-frequency = <25000000>;
 		};
 
-		timer3 at ffd01000 {
+		timer at ffd01000 {
 			clock-frequency = <25000000>;
 		};
 
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 6f23121..72ff14c 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -57,19 +57,19 @@
 			};
 		};
 
-		timer0 at ffc08000 {
+		timer at ffc08000 {
 			clock-frequency = <7000000>;
 		};
 
-		timer1 at ffc09000 {
+		timer at ffc09000 {
 			clock-frequency = <7000000>;
 		};
 
-		timer2 at ffd00000 {
+		timer at ffd00000 {
 			clock-frequency = <7000000>;
 		};
 
-		timer3 at ffd01000 {
+		timer at ffd01000 {
 			clock-frequency = <7000000>;
 		};
 
-- 
1.7.9.5

[PATCHv3 2/4] arm: dts: Change dw-apb-timer-osc and dw-apb-timer-sp to just dw-apb-timer

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

"dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the
DW APB timer, just fed by different clocks. Thus, deprecate both
"dw-apb-timer-osc" and "dw-apb-timer-sp" in lieu of "dw-apb-timer".

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
CC: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
CC: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
CC: Jamie Iles <jamie@jamieiles.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: devicetree at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org

v3:
- Split out a separate that cleans up the timer entries and clock information.
- Clearly states which binding is deprecated in the bindingd doc.

v2:
- Deprecate the "dw-apb-timer-osc" and "dw-apb-timer-sp" but maintain
  backwards compatibility in the driver.
---
 Documentation/devicetree/bindings/rtc/dw-apb.txt |   34 +++++++---------------
 arch/arm/boot/dts/socfpga.dtsi                   |    8 ++---
 2 files changed, 15 insertions(+), 27 deletions(-)

diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt
index eb2327b..c703d51 100644
--- a/Documentation/devicetree/bindings/rtc/dw-apb.txt
+++ b/Documentation/devicetree/bindings/rtc/dw-apb.txt
@@ -1,7 +1,10 @@
 * Designware APB timer
 
 Required properties:
-- compatible: "snps,dw-apb-timer-sp" or "snps,dw-apb-timer-osc"
+- compatible: One of:
+ 	"snps,dw-apb-timer"
+	"snps,dw-apb-timer-sp" <DEPRECATED>
+	"snps,dw-apb-timer-osc" <DEPRECATED>
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: IRQ line for the timer.
@@ -20,25 +23,10 @@ systems may use one.
 
 
 Example:
-
-		timer1: timer at ffc09000 {
-				compatible = "snps,dw-apb-timer-sp";
-				interrupts = <0 168 4>;
-				clock-frequency = <200000000>;
-				reg = <0xffc09000 0x1000>;
-			};
-
-		timer2: timer at ffd00000 {
-				compatible = "snps,dw-apb-timer-osc";
-				interrupts = <0 169 4>;
-				clock-frequency = <200000000>;
-				reg = <0xffd00000 0x1000>;
-			};
-
-		timer3: timer at ffe00000 {
-				compatible = "snps,dw-apb-timer-osc";
-				interrupts = <0 170 4>;
-				reg = <0xffe00000 0x1000>;
-				clocks = <&timer_clk>, <&timer_pclk>;
-				clock-names = "timer", "pclk";
-			};
+	timer at ffe00000 {
+		compatible = "snps,dw-apb-timer";
+		interrupts = <0 170 4>;
+		reg = <0xffe00000 0x1000>;
+		clocks = <&timer_clk>, <&timer_pclk>;
+		clock-names = "timer", "pclk";
+	};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 9957bae..03845cb 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -483,28 +483,28 @@
 		};
 
 		timer at ffc08000 {
-			compatible = "snps,dw-apb-timer-sp";
+			compatible = "snps,dw-apb-timer";
 			interrupts = <0 167 4>;
 			reg = <0xffc08000 0x1000>;
 			clocks = <&osc>;
 		};
 
 		timer at ffc09000 {
-			compatible = "snps,dw-apb-timer-sp";
+			compatible = "snps,dw-apb-timer";
 			interrupts = <0 168 4>;
 			reg = <0xffc09000 0x1000>;
 			clocks = <&osc>;
 		};
 
 		timer at ffd00000 {
-			compatible = "snps,dw-apb-timer-osc";
+			compatible = "snps,dw-apb-timer";
 			interrupts = <0 169 4>;
 			reg = <0xffd00000 0x1000>;
 			clocks = <&l4_sp_clk>;
 		};
 
 		timer at ffd01000 {
-			compatible = "snps,dw-apb-timer-osc";
+			compatible = "snps,dw-apb-timer";
 			interrupts = <0 170 4>;
 			reg = <0xffd01000 0x1000>;
 			clocks = <&l4_sp_clk>;
-- 
1.7.9.5

[PATCHv3 3/4] clocksource: dw_apb_timer: Move timer defines to header file.

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

Move all dw_apb_timer defines to include/linux/dw_apb_timer.h.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
CC: Rob Herring <rob.herring@calxeda.com>
CC: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
CC: Jamie Iles <jamie@jamieiles.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Pavel Machek <pavel@denx.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel at lists.infradead.org
---
 include/linux/dw_apb_timer.h |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
index 1f79b20..1d2b949 100644
--- a/include/linux/dw_apb_timer.h
+++ b/include/linux/dw_apb_timer.h
@@ -19,6 +19,25 @@
 
 #define APBTMRS_REG_SIZE       0x14
 
+#define APBT_MIN_PERIOD                 4
+#define APBT_MIN_DELTA_USEC             200
+
+#define APBTMR_N_LOAD_COUNT             0x00
+#define APBTMR_N_CURRENT_VALUE          0x04
+#define APBTMR_N_CONTROL                0x08
+#define APBTMR_N_EOI                    0x0c
+#define APBTMR_N_INT_STATUS             0x10
+
+#define APBTMRS_INT_STATUS              0xa0
+#define APBTMRS_EOI                     0xa4
+#define APBTMRS_RAW_INT_STATUS          0xa8
+#define APBTMRS_COMP_VERSION            0xac
+
+#define APBTMR_CONTROL_ENABLE           (1 << 0)
+/* 1: periodic, 0:free running. */
+#define APBTMR_CONTROL_MODE_PERIODIC    (1 << 1)
+#define APBTMR_CONTROL_INT              (1 << 2)
+
 struct dw_apb_timer {
 	void __iomem				*base;
 	unsigned long				freq;
-- 
1.7.9.5

[PATCHv3 4/4] clocksource: dw_apb_timer_of: Fix read_sched_clock

[dinguyen at altera.com]

From: Dinh Nguyen <dinguyen@altera.com>

The read_sched_clock should return the ~value because the clock is a
countdown implementation. read_sched_clock() should be the same as
__apbt_read_clocksource().

If a separate timer for the sched_clock exist, then read_sched_clock()
will return an incorrect value. The (sched_io_base + 0x4) needs to be in
the function for both cases.

Maintain backwards compatibility for "dw-apb-timer-sp" and
"dw-apb-timer-osc".

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Jamie Iles <jamie@jamieiles.com>
CC: Rob Herring <rob.herring@calxeda.com>
CC: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
CC: Jamie Iles <jamie@jamieiles.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Pavel Machek <pavel@denx.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel at lists.infradead.org

v3:
- Use APBTMR_N_CURRENT_VALUE define in read_sched_clock()

v2:
- Maintain backwards compatibility for "dw-apb-timer-sp" and
  "dw-apb-timer-osc".
---
 drivers/clocksource/dw_apb_timer_of.c |    9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index 4cbae4f..01c1238 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -102,18 +102,17 @@ static void add_clocksource(struct device_node *source_timer)
 	 * timer is found. sched_io_base then points to the current_value
 	 * register of the clocksource timer.
 	 */
-	sched_io_base = iobase + 0x04;
+	sched_io_base = iobase;
 	sched_rate = rate;
 }
 
 static u32 read_sched_clock(void)
 {
-	return __raw_readl(sched_io_base);
+	return ~__raw_readl(sched_io_base + APBTMR_N_CURRENT_VALUE);
 }
 
 static const struct of_device_id sptimer_ids[] __initconst = {
 	{ .compatible = "picochip,pc3x2-rtc" },
-	{ .compatible = "snps,dw-apb-timer-sp" },
 	{ /* Sentinel */ },
 };
 
@@ -153,4 +152,6 @@ static void __init dw_apb_timer_init(struct device_node *timer)
 	num_called++;
 }
 CLOCKSOURCE_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
-CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer-osc", dw_apb_timer_init);
+CLOCKSOURCE_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init);
+CLOCKSOURCE_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init);
+CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init);
-- 
1.7.9.5

[PATCHv3 1/4] arm: dts: Add clock entries for timers in SOCFPGA

[Pavel Machek]

On Wed 2013-08-21 15:53:44, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Set the correct clock entries for the the timers, and also clean up
> the timer entries for SOCFPGA by removing timer<n> in the timer entry.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> CC: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Ian Campbell <ian.campbell@citrix.com>
> CC: Arnd Bergmann <arnd@arndb.de>
> Cc: Olof Johansson <olof@lixom.net>
> CC: Jamie Iles <jamie@jamieiles.com>
> Cc: John Stultz <john.stultz@linaro.org>
> Cc: Heiko Stuebner <heiko@sntech.de>


Reviewed-by: Pavel Machek <pavel@denx.de>

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv3 3/4] clocksource: dw_apb_timer: Move timer defines to header file.

[Pavel Machek]

Hi!

On Wed 2013-08-21 15:53:46, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Move all dw_apb_timer defines to include/linux/dw_apb_timer.h.

That makes sense. But the changelog says "move" while the patch only
adds them to second place, which can not be right.

Is there public git tree with the patches somewhere?

Thanks,
								Pavel

> ---
>  include/linux/dw_apb_timer.h |   19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
> index 1f79b20..1d2b949 100644
> --- a/include/linux/dw_apb_timer.h
> +++ b/include/linux/dw_apb_timer.h
> @@ -19,6 +19,25 @@
>  
>  #define APBTMRS_REG_SIZE       0x14
>  
> +#define APBT_MIN_PERIOD                 4
> +#define APBT_MIN_DELTA_USEC             200
> +
> +#define APBTMR_N_LOAD_COUNT             0x00
> +#define APBTMR_N_CURRENT_VALUE          0x04
> +#define APBTMR_N_CONTROL                0x08
> +#define APBTMR_N_EOI                    0x0c
> +#define APBTMR_N_INT_STATUS             0x10
> +
> +#define APBTMRS_INT_STATUS              0xa0
> +#define APBTMRS_EOI                     0xa4
> +#define APBTMRS_RAW_INT_STATUS          0xa8
> +#define APBTMRS_COMP_VERSION            0xac
> +
> +#define APBTMR_CONTROL_ENABLE           (1 << 0)
> +/* 1: periodic, 0:free running. */
> +#define APBTMR_CONTROL_MODE_PERIODIC    (1 << 1)
> +#define APBTMR_CONTROL_INT              (1 << 2)
> +
>  struct dw_apb_timer {
>  	void __iomem				*base;
>  	unsigned long				freq;

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[PATCHv3 3/4] clocksource: dw_apb_timer: Move timer defines to header file.

[Dinh Nguyen]

On Thu, 2013-08-22 at 13:01 +0200, ZY - pavel wrote:
> Hi!
> 
> On Wed 2013-08-21 15:53:46, dinguyen at altera.com wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > Move all dw_apb_timer defines to include/linux/dw_apb_timer.h.
> 
> That makes sense. But the changelog says "move" while the patch only
> adds them to second place, which can not be right.

Oops, must not have saved on one of my shells. Thanks for the review.
Will post a v4 asap.

> 
> Is there public git tree with the patches somewhere?

git://git.rocketboards.org/linux-socfpga-next.git

Dinh
> 
> Thanks,
> 								Pavel
> 
> > ---
> >  include/linux/dw_apb_timer.h |   19 +++++++++++++++++++
> >  1 file changed, 19 insertions(+)
> > 
> > diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
> > index 1f79b20..1d2b949 100644
> > --- a/include/linux/dw_apb_timer.h
> > +++ b/include/linux/dw_apb_timer.h
> > @@ -19,6 +19,25 @@
> >  
> >  #define APBTMRS_REG_SIZE       0x14
> >  
> > +#define APBT_MIN_PERIOD                 4
> > +#define APBT_MIN_DELTA_USEC             200
> > +
> > +#define APBTMR_N_LOAD_COUNT             0x00
> > +#define APBTMR_N_CURRENT_VALUE          0x04
> > +#define APBTMR_N_CONTROL                0x08
> > +#define APBTMR_N_EOI                    0x0c
> > +#define APBTMR_N_INT_STATUS             0x10
> > +
> > +#define APBTMRS_INT_STATUS              0xa0
> > +#define APBTMRS_EOI                     0xa4
> > +#define APBTMRS_RAW_INT_STATUS          0xa8
> > +#define APBTMRS_COMP_VERSION            0xac
> > +
> > +#define APBTMR_CONTROL_ENABLE           (1 << 0)
> > +/* 1: periodic, 0:free running. */
> > +#define APBTMR_CONTROL_MODE_PERIODIC    (1 << 1)
> > +#define APBTMR_CONTROL_INT              (1 << 2)
> > +
> >  struct dw_apb_timer {
> >  	void __iomem				*base;
> >  	unsigned long				freq;
> 

[PATCHv3 1/4] arm: dts: Add clock entries for timers in SOCFPGA

[Steffen Trumtrar]

Hi!

On Wed, Aug 21, 2013 at 03:53:44PM -0500, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Set the correct clock entries for the the timers, and also clean up
> the timer entries for SOCFPGA by removing timer<n> in the timer entry.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> CC: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Ian Campbell <ian.campbell@citrix.com>
> CC: Arnd Bergmann <arnd@arndb.de>
> Cc: Olof Johansson <olof@lixom.net>
> CC: Jamie Iles <jamie@jamieiles.com>
> Cc: John Stultz <john.stultz@linaro.org>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: devicetree at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> ---
>  arch/arm/boot/dts/socfpga.dtsi         |   16 ++++++++--------
>  arch/arm/boot/dts/socfpga_cyclone5.dts |    8 ++++----
>  arch/arm/boot/dts/socfpga_vt.dts       |    8 ++++----
>  3 files changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 9706767..9957bae 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -26,10 +26,6 @@
>  		ethernet1 = &gmac1;
>  		serial0 = &uart0;
>  		serial1 = &uart1;
> -		timer0 = &timer0;
> -		timer1 = &timer1;
> -		timer2 = &timer2;
> -		timer3 = &timer3;
>  	};
>

Yes. Do that.

>  	cpus {
> @@ -486,28 +482,32 @@
>  			interrupts = <1 13 0xf04>;
>  		};
>  
> -		timer0: timer0 at ffc08000 {
> +		timer at ffc08000 {

No. Why? Than I can not write something like

&timer0 {
	clock-frequency = <100000000>;
};

and would have to reference the whole tree ala

/ {
	soc {
		timer at ffc08000 {
			clock-frequency = <100000000>;
		};
	};
};

in a boardspecific or SoC specific file (see below).

> diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
> index 698dde9..c1af01c 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
>  
> diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
> index 6f23121..72ff14c 100644
> --- a/arch/arm/boot/dts/socfpga_vt.dts
> +++ b/arch/arm/boot/dts/socfpga_vt.dts

Leads me to a question about terminology: Is the cyclone5 an actual board?
AFAIK it is. And the Cyclone 5 FPGA is also called socfpga? Is that correct?
But then, seeing that, in an other patch, you add two different sysmgr addresses to
the socfpga_vt and socfpga_cyclone5, there are different socfpgas?

I want to write a devicetree for the SoCkit. It has a Cyclone 5 on it.
So naturally I would now go and include the socfpga_cyclone5.dtsi, with all the
cyclone5 stuff and just add my board specific stuff in a socfpga_sockit.dts.
But there is no socfpga_cyclone5.dtsi, just the socfpga_cyclone5.dts, which itself
seems to be a board...

So, how should we reorder the current dts (as I tested with current mainline, the
support is completely broken out of the box, but works fine with your patches that
are floating around, there should be no users as of now)?

Something like:

socfpga.dtsi
 -> socfpga_cyclone5.dtsi
 --> socfpga_cyclone5_devboard.dts (?)
 --> socfpga_sockit.dts
 -> socfpga_???.dtsi
 --> socfpga_vt.dts

?

Thanks and regards,
Steffen

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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[PATCHv3 1/4] arm: dts: Add clock entries for timers in SOCFPGA

[Dinh Nguyen]

Hi Steffen,

On Wed, 2013-08-28 at 17:31 +0200, Steffen Trumtrar wrote:
> Hi!
> 
> On Wed, Aug 21, 2013 at 03:53:44PM -0500, dinguyen at altera.com wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > Set the correct clock entries for the the timers, and also clean up
> > the timer entries for SOCFPGA by removing timer<n> in the timer entry.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > CC: Rob Herring <rob.herring@calxeda.com>
> > Cc: Pawel Moll <pawel.moll@arm.com>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Stephen Warren <swarren@wwwdotorg.org>
> > Cc: Ian Campbell <ian.campbell@citrix.com>
> > CC: Arnd Bergmann <arnd@arndb.de>
> > Cc: Olof Johansson <olof@lixom.net>
> > CC: Jamie Iles <jamie@jamieiles.com>
> > Cc: John Stultz <john.stultz@linaro.org>
> > Cc: Heiko Stuebner <heiko@sntech.de>
> > Cc: Pavel Machek <pavel@denx.de>
> > Cc: devicetree at vger.kernel.org
> > Cc: linux-arm-kernel at lists.infradead.org
> > ---
> >  arch/arm/boot/dts/socfpga.dtsi         |   16 ++++++++--------
> >  arch/arm/boot/dts/socfpga_cyclone5.dts |    8 ++++----
> >  arch/arm/boot/dts/socfpga_vt.dts       |    8 ++++----
> >  3 files changed, 16 insertions(+), 16 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index 9706767..9957bae 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -26,10 +26,6 @@
> >  		ethernet1 = &gmac1;
> >  		serial0 = &uart0;
> >  		serial1 = &uart1;
> > -		timer0 = &timer0;
> > -		timer1 = &timer1;
> > -		timer2 = &timer2;
> > -		timer3 = &timer3;
> >  	};
> >
> 
> Yes. Do that.
> 
> >  	cpus {
> > @@ -486,28 +482,32 @@
> >  			interrupts = <1 13 0xf04>;
> >  		};
> >  
> > -		timer0: timer0 at ffc08000 {
> > +		timer at ffc08000 {
> 
> No. Why? Than I can not write something like
> 
> &timer0 {
> 	clock-frequency = <100000000>;
> };
> 
> and would have to reference the whole tree ala
> 
> / {
> 	soc {
> 		timer at ffc08000 {
> 			clock-frequency = <100000000>;
> 		};
> 	};
> };
> 
> in a boardspecific or SoC specific file (see below).

Agreed. Will adjust accordingly.

> 
> > diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
> > index 698dde9..c1af01c 100644
> > --- a/arch/arm/boot/dts/socfpga_cyclone5.dts
> > +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
> >  
> > diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
> > index 6f23121..72ff14c 100644
> > --- a/arch/arm/boot/dts/socfpga_vt.dts
> > +++ b/arch/arm/boot/dts/socfpga_vt.dts
> 
> Leads me to a question about terminology: Is the cyclone5 an actual board?
> AFAIK it is. And the Cyclone 5 FPGA is also called socfpga? Is that correct?
> But then, seeing that, in an other patch, you add two different sysmgr addresses to
> the socfpga_vt and socfpga_cyclone5, there are different socfpgas?

Yes, sofpga_cyclone5.dts is the devkit that is manufactured by Altera.
socfpga_vt.dts is a virtual platform for SOCFPGA. You can get the
virtual platform from Synopsis. It mimics everything except the FPGA. 

socfpga is the base SOC with a Cyclone 5 FPGA on it. I'll be upstreaming
socfpga_arria5 soon, which has the SOCFPGA + Arria 5 FPGA.

> 
> I want to write a devicetree for the SoCkit. It has a Cyclone 5 on it.
> So naturally I would now go and include the socfpga_cyclone5.dtsi, with all the
> cyclone5 stuff and just add my board specific stuff in a socfpga_sockit.dts.
> But there is no socfpga_cyclone5.dtsi, just the socfpga_cyclone5.dts, which itself
> seems to be a board...

socfpga.dtsi is the base DTSI for the platform. In hindsight, I should
have named it a bit different, but for now socfpga_cyclone5 is for the
board.

> 
> So, how should we reorder the current dts (as I tested with current mainline, the
> support is completely broken out of the box, but works fine with your patches that
> are floating around, there should be no users as of now)?

Not sure what you mean by broken. I was able to boot 3.11-rc7 just now
using an initramfs. As you can already tell, I'm doing my best to get
more support for the platform upstream, but it will take time.

In the meantim, you get our latest downstream kernel at:

git://git.rocketboards.org/linux-socfpga.git

Dinh

> 
> Something like:
> 
> socfpga.dtsi
>  -> socfpga_cyclone5.dtsi
>  --> socfpga_cyclone5_devboard.dts (?)
>  --> socfpga_sockit.dts
>  -> socfpga_???.dtsi
>  --> socfpga_vt.dts
> 
> ?
> 
> Thanks and regards,
> Steffen
> 

[PATCHv3 1/4] arm: dts: Add clock entries for timers in SOCFPGA

[Steffen Trumtrar]

Hi Dinh,

On Thu, Aug 29, 2013 at 10:55:18AM -0500, Dinh Nguyen wrote:
> Hi Steffen,
> > > @@ -486,28 +482,32 @@
> > >  			interrupts = <1 13 0xf04>;
> > >  		};
> > >  
> > > -		timer0: timer0 at ffc08000 {
> > > +		timer at ffc08000 {
> > 
> > No. Why? Than I can not write something like
> > 
> > &timer0 {
> > 	clock-frequency = <100000000>;
> > };
> > 
> > and would have to reference the whole tree ala
> > 
> > / {
> > 	soc {
> > 		timer at ffc08000 {
> > 			clock-frequency = <100000000>;
> > 		};
> > 	};
> > };
> > 
> > in a boardspecific or SoC specific file (see below).
> 
> Agreed. Will adjust accordingly.
> 

Good.

> > 
> > > diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
> > > index 698dde9..c1af01c 100644
> > > --- a/arch/arm/boot/dts/socfpga_cyclone5.dts
> > > +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
> > >  
> > > diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
> > > index 6f23121..72ff14c 100644
> > > --- a/arch/arm/boot/dts/socfpga_vt.dts
> > > +++ b/arch/arm/boot/dts/socfpga_vt.dts
> > 
> > Leads me to a question about terminology: Is the cyclone5 an actual board?
> > AFAIK it is. And the Cyclone 5 FPGA is also called socfpga? Is that correct?
> > But then, seeing that, in an other patch, you add two different sysmgr addresses to
> > the socfpga_vt and socfpga_cyclone5, there are different socfpgas?
> 
> Yes, sofpga_cyclone5.dts is the devkit that is manufactured by Altera.
> socfpga_vt.dts is a virtual platform for SOCFPGA. You can get the
> virtual platform from Synopsis. It mimics everything except the FPGA. 
> 

Uh, nice. I will check out the vt.

> socfpga is the base SOC with a Cyclone 5 FPGA on it. I'll be upstreaming
> socfpga_arria5 soon, which has the SOCFPGA + Arria 5 FPGA.
> 

Hm, okay. That might lead to confusion then...

> > 
> > I want to write a devicetree for the SoCkit. It has a Cyclone 5 on it.
> > So naturally I would now go and include the socfpga_cyclone5.dtsi, with all the
> > cyclone5 stuff and just add my board specific stuff in a socfpga_sockit.dts.
> > But there is no socfpga_cyclone5.dtsi, just the socfpga_cyclone5.dts, which itself
> > seems to be a board...
> 
> socfpga.dtsi is the base DTSI for the platform. In hindsight, I should
> have named it a bit different, but for now socfpga_cyclone5 is for the
> board.
> 

and we should make the socfpga_cyclone5 a dtsi. I can do that.
It's early in development and I see no reason not to fix it now.
We have seen quite a lot of rearrangment with the imx6 for example. No need to
duplicate it, if we know it beforehand.


> > 
> > So, how should we reorder the current dts (as I tested with current mainline, the
> > support is completely broken out of the box, but works fine with your patches that
> > are floating around, there should be no users as of now)?
> 
> Not sure what you mean by broken. I was able to boot 3.11-rc7 just now
> using an initramfs. As you can already tell, I'm doing my best to get
> more support for the platform upstream, but it will take time.
> 

Yeah, broken might have been a bit harsh :-D
But my first experience with the mainline kernel was a scrambled serial console
and hanging system as soon as you use the ethernet/ip=dhcp.
And the SD wasn't working for me, too. But those SD cards are really more problematic
than one might think, so...

But as I said: with your patch series, both is working. Looking forward to your
next versions of those patches.
Now I have a hanging system, when I add the at24 on i2c-0, what ever might be
the reason for that :-D

BTW: you don't happen to have any insight in what crazy things you do with the CRC32
in your prebootloader, do you? Been trying some time to calculate the crc, but never
got to the one the mkpimage generates. It doesn't seem to be what crc32 or chksum
calculate or the datasheet is missing some essential info for me to understand it.

Regards,
Steffen

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |