* [PATCH 1/5] ARM: imx: add soc revision helper functions
2013-09-25 8:30 [PATCH 0/5] ARM: imx6: export soc info via soc device Shawn Guo
@ 2013-09-25 8:30 ` Shawn Guo
2013-09-25 8:30 ` [PATCH 2/5] ARM: imx6q: use common soc revision helpers Shawn Guo
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2013-09-25 8:30 UTC (permalink / raw)
To: linux-arm-kernel
Similar to what we do for cpu type, the patch adds helper functions
imx_set_soc_revision() and imx_get_soc_revision() to maintain
imx_soc_revision in cpu.c.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/common.h | 2 ++
arch/arm/mach-imx/cpu.c | 12 ++++++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 4517fd7..d87fff1 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -81,6 +81,8 @@ extern int imx6q_revision(void);
extern int mx53_display_revision(void);
extern void imx_set_aips(void __iomem *);
extern int mxc_device_init(void);
+void imx_set_soc_revision(unsigned int rev);
+unsigned int imx_get_soc_revision(void);
enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index e70e3ac..51f6c51 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -8,11 +8,23 @@
unsigned int __mxc_cpu_type;
EXPORT_SYMBOL(__mxc_cpu_type);
+static unsigned int imx_soc_revision;
+
void mxc_set_cpu_type(unsigned int type)
{
__mxc_cpu_type = type;
}
+void imx_set_soc_revision(unsigned int rev)
+{
+ imx_soc_revision = rev;
+}
+
+unsigned int imx_get_soc_revision(void)
+{
+ return imx_soc_revision;
+}
+
void imx_print_silicon_rev(const char *cpu, int srev)
{
if (srev == IMX_CHIP_REVISION_UNKNOWN)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/5] ARM: imx6q: use common soc revision helpers
2013-09-25 8:30 [PATCH 0/5] ARM: imx6: export soc info via soc device Shawn Guo
2013-09-25 8:30 ` [PATCH 1/5] ARM: imx: add soc revision helper functions Shawn Guo
@ 2013-09-25 8:30 ` Shawn Guo
2013-09-25 8:30 ` [PATCH 3/5] ARM: imx: add a common function to initialize revision from anatop Shawn Guo
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2013-09-25 8:30 UTC (permalink / raw)
To: linux-arm-kernel
It calls imx_set_soc_revision() to set up soc revision in
imx6q_init_revision(), and replaces all the occurrences of
imx6q_revision() with common helper imx_get_soc_revision().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/clk-imx6q.c | 5 +++--
arch/arm/mach-imx/common.h | 1 -
arch/arm/mach-imx/mach-imx6q.c | 13 ++++---------
3 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 913ad85..c681566 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -300,7 +300,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
WARN_ON(!base);
/* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
- if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) {
+ if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
post_div_table[1].div = 1;
post_div_table[2].div = 1;
video_div_table[1].div = 1;
@@ -574,7 +574,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
- if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
+ if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
+ cpu_is_imx6dl()) {
clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
}
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index d87fff1..64b2b9f 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -77,7 +77,6 @@ extern void mxc_restart(enum reboot_mode, const char *);
extern void mxc_arch_reset_init(void __iomem *);
extern void mxc_arch_reset_init_dt(void);
extern int mx53_revision(void);
-extern int imx6q_revision(void);
extern int mx53_display_revision(void);
extern void imx_set_aips(void __iomem *);
extern int mxc_device_init(void);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 85a1b51..2efdbce 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -40,16 +40,10 @@
#include "cpuidle.h"
#include "hardware.h"
-static u32 chip_revision;
-
-int imx6q_revision(void)
-{
- return chip_revision;
-}
-
static void __init imx6q_init_revision(void)
{
u32 rev = imx_anatop_get_digprog();
+ u32 chip_revision;
switch (rev & 0xff) {
case 0:
@@ -66,6 +60,7 @@ static void __init imx6q_init_revision(void)
}
mxc_set_cpu_type(rev >> 16 & 0xff);
+ imx_set_soc_revision(chip_revision);
}
static void imx6q_restart(enum reboot_mode mode, const char *cmd)
@@ -264,7 +259,7 @@ static void __init imx6q_init_late(void)
* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
* to run cpuidle on them.
*/
- if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
+ if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
imx6q_cpuidle_init();
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
@@ -293,7 +288,7 @@ static void __init imx6q_timer_init(void)
of_clk_init(NULL);
clocksource_of_init();
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
- imx6q_revision());
+ imx_get_soc_revision());
}
static const char *imx6q_dt_compat[] __initdata = {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/5] ARM: imx: add a common function to initialize revision from anatop
2013-09-25 8:30 [PATCH 0/5] ARM: imx6: export soc info via soc device Shawn Guo
2013-09-25 8:30 ` [PATCH 1/5] ARM: imx: add soc revision helper functions Shawn Guo
2013-09-25 8:30 ` [PATCH 2/5] ARM: imx6q: use common soc revision helpers Shawn Guo
@ 2013-09-25 8:30 ` Shawn Guo
2013-09-25 8:30 ` [PATCH 4/5] ARM: imx: use imx_init_revision_from_anatop() on imx6sl Shawn Guo
2013-09-25 8:30 ` [PATCH 5/5] ARM: imx6: report soc info via soc device Shawn Guo
4 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2013-09-25 8:30 UTC (permalink / raw)
To: linux-arm-kernel
The patch creates a common function imx_init_revision_from_anatop() by
merging imx6q_init_revision() and imx_anatop_get_digprog(), so that any
SoC that encodes revision info in anatop can use it to initialize
revision.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/anatop.c | 27 +++++++++++++++++++++------
arch/arm/mach-imx/common.h | 2 +-
arch/arm/mach-imx/mach-imx6q.c | 25 +------------------------
3 files changed, 23 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index ad3b755..b2d600f 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -16,6 +16,7 @@
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include "common.h"
+#include "hardware.h"
#define REG_SET 0x4
#define REG_CLR 0x8
@@ -76,21 +77,35 @@ static void imx_anatop_usb_chrg_detect_disable(void)
BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
}
-u32 imx_anatop_get_digprog(void)
+void __init imx_init_revision_from_anatop(void)
{
struct device_node *np;
void __iomem *anatop_base;
- static u32 digprog;
-
- if (digprog)
- return digprog;
+ unsigned int revision;
+ u32 digprog;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
anatop_base = of_iomap(np, 0);
WARN_ON(!anatop_base);
digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG);
+ iounmap(anatop_base);
+
+ switch (digprog & 0xff) {
+ case 0:
+ revision = IMX_CHIP_REVISION_1_0;
+ break;
+ case 1:
+ revision = IMX_CHIP_REVISION_1_1;
+ break;
+ case 2:
+ revision = IMX_CHIP_REVISION_1_2;
+ break;
+ default:
+ revision = IMX_CHIP_REVISION_UNKNOWN;
+ }
- return digprog;
+ mxc_set_cpu_type(digprog >> 16 & 0xff);
+ imx_set_soc_revision(revision);
}
void __init imx_anatop_init(void)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 64b2b9f..282af93 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -82,6 +82,7 @@ extern void imx_set_aips(void __iomem *);
extern int mxc_device_init(void);
void imx_set_soc_revision(unsigned int rev);
unsigned int imx_get_soc_revision(void);
+void imx_init_revision_from_anatop(void);
enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */
@@ -138,7 +139,6 @@ extern void imx_gpc_restore_all(void);
extern void imx_anatop_init(void);
extern void imx_anatop_pre_suspend(void);
extern void imx_anatop_post_resume(void);
-extern u32 imx_anatop_get_digprog(void);
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_set_chicken_bit(void);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 2efdbce..ea01ac3 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -40,29 +40,6 @@
#include "cpuidle.h"
#include "hardware.h"
-static void __init imx6q_init_revision(void)
-{
- u32 rev = imx_anatop_get_digprog();
- u32 chip_revision;
-
- switch (rev & 0xff) {
- case 0:
- chip_revision = IMX_CHIP_REVISION_1_0;
- break;
- case 1:
- chip_revision = IMX_CHIP_REVISION_1_1;
- break;
- case 2:
- chip_revision = IMX_CHIP_REVISION_1_2;
- break;
- default:
- chip_revision = IMX_CHIP_REVISION_UNKNOWN;
- }
-
- mxc_set_cpu_type(rev >> 16 & 0xff);
- imx_set_soc_revision(chip_revision);
-}
-
static void imx6q_restart(enum reboot_mode mode, const char *cmd)
{
struct device_node *np;
@@ -276,7 +253,7 @@ static void __init imx6q_map_io(void)
static void __init imx6q_init_irq(void)
{
- imx6q_init_revision();
+ imx_init_revision_from_anatop();
imx_init_l2cache();
imx_src_init();
imx_gpc_init();
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/5] ARM: imx: use imx_init_revision_from_anatop() on imx6sl
2013-09-25 8:30 [PATCH 0/5] ARM: imx6: export soc info via soc device Shawn Guo
` (2 preceding siblings ...)
2013-09-25 8:30 ` [PATCH 3/5] ARM: imx: add a common function to initialize revision from anatop Shawn Guo
@ 2013-09-25 8:30 ` Shawn Guo
2013-09-25 8:30 ` [PATCH 5/5] ARM: imx6: report soc info via soc device Shawn Guo
4 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2013-09-25 8:30 UTC (permalink / raw)
To: linux-arm-kernel
Add imx6sl support into imx_init_revision_from_anatop(), so that it can
be used to initialize cpu type and revision on imx6sl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/imx6sl.dtsi | 4 +++-
arch/arm/mach-imx/anatop.c | 6 +++++-
arch/arm/mach-imx/mach-imx6sl.c | 1 +
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index f295290..17607b3 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -384,7 +384,9 @@
};
anatop: anatop at 020c8000 {
- compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
+ compatible = "fsl,imx6sl-anatop",
+ "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index b2d600f..4a40bbb 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -27,6 +27,7 @@
#define ANADIG_USB1_CHRG_DETECT 0x1b0
#define ANADIG_USB2_CHRG_DETECT 0x210
#define ANADIG_DIGPROG 0x260
+#define ANADIG_DIGPROG_IMX6SL 0x280
#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
@@ -83,11 +84,14 @@ void __init imx_init_revision_from_anatop(void)
void __iomem *anatop_base;
unsigned int revision;
u32 digprog;
+ u16 offset = ANADIG_DIGPROG;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
anatop_base = of_iomap(np, 0);
WARN_ON(!anatop_base);
- digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG);
+ if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
+ offset = ANADIG_DIGPROG_IMX6SL;
+ digprog = readl_relaxed(anatop_base + offset);
iounmap(anatop_base);
switch (digprog & 0xff) {
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 892b629..b1aaa47 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -46,6 +46,7 @@ static void __init imx6sl_init_machine(void)
static void __init imx6sl_init_irq(void)
{
+ imx_init_revision_from_anatop();
imx_init_l2cache();
imx_src_init();
imx_gpc_init();
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 5/5] ARM: imx6: report soc info via soc device
2013-09-25 8:30 [PATCH 0/5] ARM: imx6: export soc info via soc device Shawn Guo
` (3 preceding siblings ...)
2013-09-25 8:30 ` [PATCH 4/5] ARM: imx: use imx_init_revision_from_anatop() on imx6sl Shawn Guo
@ 2013-09-25 8:30 ` Shawn Guo
4 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2013-09-25 8:30 UTC (permalink / raw)
To: linux-arm-kernel
The patch enables soc bus infrastructure and adds a function
imx_soc_device_init() to report soc info via soc device interface for
imx6qdl and imx6sl. With the support, user space can get soc related
info by looking at sysfs like below.
$ cat /sys/devices/soc0/machine
Freescale i.MX6 Quad SABRE Smart Device Board
$ cat /sys/devices/soc0/family
Freescale i.MX
$ cat /sys/devices/soc0/soc_id
i.MX6Q
$ cat /sys/devices/soc0/revision
1.2
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/Kconfig | 1 +
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/cpu.c | 81 +++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/mach-imx6q.c | 8 +++-
arch/arm/mach-imx/mach-imx6sl.c | 8 +++-
arch/arm/mach-imx/mxc.h | 1 +
6 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 9f67338..e017915 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -11,6 +11,7 @@ config ARCH_MXC
select GENERIC_IRQ_CHIP
select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
select MULTI_IRQ_HANDLER
+ select SOC_BUS
select SPARSE_IRQ
select USE_OF
help
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 282af93..4f9aea9 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -83,6 +83,7 @@ extern int mxc_device_init(void);
void imx_set_soc_revision(unsigned int rev);
unsigned int imx_get_soc_revision(void);
void imx_init_revision_from_anatop(void);
+struct device *imx_soc_device_init(void);
enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 51f6c51..fae2c9a 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -1,6 +1,9 @@
#include <linux/module.h>
#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
#include "hardware.h"
#include "common.h"
@@ -56,3 +59,81 @@ void __init imx_set_aips(void __iomem *base)
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
}
+
+struct device * __init imx_soc_device_init(void)
+{
+ struct soc_device_attribute *soc_dev_attr;
+ struct soc_device *soc_dev;
+ struct device_node *root;
+ const char *soc_id;
+ int ret;
+
+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+ if (!soc_dev_attr)
+ return NULL;
+
+ soc_dev_attr->family = "Freescale i.MX";
+
+ root = of_find_node_by_path("/");
+ ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
+ of_node_put(root);
+ if (ret)
+ goto free_soc;
+
+ switch (__mxc_cpu_type) {
+ case MXC_CPU_MX1:
+ soc_id = "i.MX1";
+ break;
+ case MXC_CPU_MX21:
+ soc_id = "i.MX21";
+ break;
+ case MXC_CPU_MX25:
+ soc_id = "i.MX25";
+ break;
+ case MXC_CPU_MX27:
+ soc_id = "i.MX27";
+ break;
+ case MXC_CPU_MX31:
+ soc_id = "i.MX31";
+ break;
+ case MXC_CPU_MX35:
+ soc_id = "i.MX35";
+ break;
+ case MXC_CPU_MX51:
+ soc_id = "i.MX51";
+ break;
+ case MXC_CPU_MX53:
+ soc_id = "i.MX53";
+ break;
+ case MXC_CPU_IMX6SL:
+ soc_id = "i.MX6SL";
+ break;
+ case MXC_CPU_IMX6DL:
+ soc_id = "i.MX6DL";
+ break;
+ case MXC_CPU_IMX6Q:
+ soc_id = "i.MX6Q";
+ break;
+ default:
+ soc_id = "Unknown";
+ }
+ soc_dev_attr->soc_id = soc_id;
+
+ soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
+ (imx_soc_revision >> 4) & 0xf,
+ imx_soc_revision & 0xf);
+ if (!soc_dev_attr->revision)
+ goto free_soc;
+
+ soc_dev = soc_device_register(soc_dev_attr);
+ if (IS_ERR(soc_dev))
+ goto free_rev;
+
+ return soc_device_to_device(soc_dev);
+
+free_rev:
+ kfree(soc_dev_attr->revision);
+free_soc:
+ kfree(soc_dev_attr);
+ return NULL;
+}
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index ea01ac3..ebcfd8d 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -164,9 +164,15 @@ static void __init imx6q_1588_init(void)
static void __init imx6q_init_machine(void)
{
+ struct device *parent;
+
+ parent = imx_soc_device_init();
+ if (parent == NULL)
+ pr_warn("failed to initialize soc device\n");
+
imx6q_enet_phy_init();
- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
imx_anatop_init();
imx6q_pm_init();
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index b1aaa47..5c767f0 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -37,9 +37,15 @@ static void __init imx6sl_fec_init(void)
static void __init imx6sl_init_machine(void)
{
+ struct device *parent;
+
mxc_arch_reset_init_dt();
- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ parent = imx_soc_device_init();
+ if (parent == NULL)
+ pr_warn("failed to initialize soc device\n");
+
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
imx6sl_fec_init();
}
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 8629e5b..99e03ea 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -34,6 +34,7 @@
#define MXC_CPU_MX35 35
#define MXC_CPU_MX51 51
#define MXC_CPU_MX53 53
+#define MXC_CPU_IMX6SL 0x60
#define MXC_CPU_IMX6DL 0x61
#define MXC_CPU_IMX6Q 0x63
--
1.7.9.5
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