From: maxime.coquelin@st.com (Maxime COQUELIN)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 3/4] ARM: STi: Supply I2C configuration to STiH415 SoC
Date: Tue, 8 Oct 2013 18:42:55 +0200 [thread overview]
Message-ID: <1381250576-7916-4-git-send-email-maxime.coquelin@st.com> (raw)
In-Reply-To: <1381250576-7916-1-git-send-email-maxime.coquelin@st.com>
This patch supplies I2C configuration to STiH415 SoC.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
---
arch/arm/boot/dts/stih415-pinctrl.dtsi | 36 ++++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 53 ++++++++++++++++++++++++++++++++
2 files changed, 89 insertions(+)
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 1d322b2..e56449d 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -86,6 +86,24 @@
};
};
};
+
+ sbc_i2c0 {
+ pinctrl_sbc_i2c0_default: sbc_i2c0-default {
+ st,pins {
+ sda = <&PIO4 6 ALT1 BIDIR>;
+ scl = <&PIO4 5 ALT1 BIDIR>;
+ };
+ };
+ };
+
+ sbc_i2c1 {
+ pinctrl_sbc_i2c1_default: sbc_i2c1-default {
+ st,pins {
+ sda = <&PIO3 2 ALT2 BIDIR>;
+ scl = <&PIO3 1 ALT2 BIDIR>;
+ };
+ };
+ };
};
pin-controller-front {
@@ -143,6 +161,24 @@
reg = <0x7000 0x100>;
st,bank-name = "PIO12";
};
+
+ i2c0 {
+ pinctrl_i2c0_default: i2c0-default {
+ st,pins {
+ sda = <&PIO9 3 ALT1 BIDIR>;
+ scl = <&PIO9 2 ALT1 BIDIR>;
+ };
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1_default: i2c1-default {
+ st,pins {
+ sda = <&PIO12 1 ALT1 BIDIR>;
+ scl = <&PIO12 0 ALT1 BIDIR>;
+ };
+ };
+ };
};
pin-controller-rear {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 74ab8de..eb4fccb 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -9,6 +9,7 @@
#include "stih41x.dtsi"
#include "stih415-clock.dtsi"
#include "stih415-pinctrl.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
L2: cache-controller {
@@ -83,5 +84,57 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
};
+
+ i2c at fed40000 {
+ compatible = "st,comms-ssc-i2c";
+ reg = <0xfed40000 0x110>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&CLKS_ICN_REG_0>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+
+ status = "disabled";
+ };
+
+ i2c at fed41000 {
+ compatible = "st,comms-ssc-i2c";
+ reg = <0xfed41000 0x110>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&CLKS_ICN_REG_0>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+
+ status = "disabled";
+ };
+
+ i2c at fe540000 {
+ compatible = "st,comms-ssc-i2c";
+ reg = <0xfe540000 0x110>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&CLK_SYSIN>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
+
+ status = "disabled";
+ };
+
+ i2c at fe541000 {
+ compatible = "st,comms-ssc-i2c";
+ reg = <0xfe541000 0x110>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&CLK_SYSIN>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
+
+ status = "disabled";
+ };
};
};
--
1.7.9.5
next prev parent reply other threads:[~2013-10-08 16:42 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-08 16:42 [PATCH v4 0/4] Add I2C support to ST SoCs Maxime COQUELIN
2013-10-08 16:42 ` [PATCH v4 1/4] i2c: busses: i2c-st: Add ST I2C controller Maxime COQUELIN
2013-10-08 16:42 ` [PATCH v4 2/4] ARM: STi: Supply I2C configuration to STiH416 SoC Maxime COQUELIN
2013-10-08 16:42 ` Maxime COQUELIN [this message]
2013-10-08 16:42 ` [PATCH v4 4/4] ARM: STi: Add I2C config to B2000 and B2020 boards Maxime COQUELIN
2013-10-10 9:39 ` [PATCH v4 0/4] Add I2C support to ST SoCs Maxime COQUELIN
2013-10-10 10:03 ` Wolfram Sang
2013-10-10 13:33 ` Maxime COQUELIN
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