[PATCH 0/7] ARM: tegra: support LP1 suspend mode for Tegra124

[PATCH 0/7] ARM: tegra: support LP1 suspend mode for Tegra124

[Joseph Lo]

This series adds the LP1 support for Tegra124. (suspend to LP2 also
supported in this series)

Note:
This patch series depends on the patch series below.
* [PATCH 0/5] Tegra124 clock support
* [PATCH V2 0/6] ARM: tegra: basic support for Tegra124 SoC
* [PATCH] ARM: tegra: add clock properties for devices of Tegra124
* [PATCH 0/4] ARM: tegra: add CPU hot-plug and idle support for Tegra124

Verified on Cardhu, Dalmore and Venice2 and with THUMB2_KERNEL as well.

Joseph Lo (7):
  clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
  ARM: tegra: add flow controller to support suspend for Tegra124
  ARM: tegra: hook tegra_cpu_tear_down for Tegra124
  ARM: tegra: add LP1 support code for Tegra124
  ARM: tegra: hook the LP1 iram code area and sleep_core function for
    Tegra124
  ARM: tegra: enable Tegra RTC for Venice2
  ARM: tegra: enable LP1 suspend mode for Venice2

 arch/arm/boot/dts/tegra124-venice2.dts | 11 +++++++++++
 arch/arm/mach-tegra/Makefile           |  1 +
 arch/arm/mach-tegra/flowctrl.c         |  2 ++
 arch/arm/mach-tegra/iomap.h            |  3 +++
 arch/arm/mach-tegra/pm.c               | 12 +++++++++---
 arch/arm/mach-tegra/sleep-tegra30.S    | 36 +++++++++++++++++++++++++++-------
 drivers/clk/tegra/clk-tegra124.c       | 27 +++++++++++++++++++++++++
 7 files changed, 82 insertions(+), 10 deletions(-)

-- 
1.8.4

[PATCH 1/7] clk: tegra124: add suspend/resume function for tegra_cpu_car_ops

[Joseph Lo]

Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 drivers/clk/tegra/clk-tegra124.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index c1c9330..66eb1f8a 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -28,6 +28,7 @@
 #include "clk.h"
 #include "clk-id.h"
 
+#define CLK_SOURCE_CSITE 0x1d4
 #define CLK_SOURCE_EMC 0x19c
 #define CLK_SOURCE_XUSB_SS_SRC 0x610
 
@@ -109,6 +110,12 @@
 /* Tegra CPU clock and reset control regs */
 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
 
+#ifdef CONFIG_PM_SLEEP
+static struct cpu_clk_suspend_context {
+	u32 clk_csite_src;
+} tegra124_cpu_clk_sctx;
+#endif
+
 static void __iomem *clk_base;
 static void __iomem *pmc_base;
 
@@ -1139,9 +1146,29 @@ static void tegra124_disable_cpu_clock(u32 cpu)
 	/* flow controller would take care in the power sequence. */
 }
 
+#ifdef CONFIG_PM_SLEEP
+static void tegra124_cpu_clock_suspend(void)
+{
+	/* switch coresite to clk_m, save off original source */
+	tegra124_cpu_clk_sctx.clk_csite_src =
+				readl(clk_base + CLK_SOURCE_CSITE);
+	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
+}
+
+static void tegra124_cpu_clock_resume(void)
+{
+	writel(tegra124_cpu_clk_sctx.clk_csite_src,
+				clk_base + CLK_SOURCE_CSITE);
+}
+#endif
+
 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
 	.wait_for_reset	= tegra124_wait_cpu_in_reset,
 	.disable_clock	= tegra124_disable_cpu_clock,
+#ifdef CONFIG_PM_SLEEP
+	.suspend	= tegra124_cpu_clock_suspend,
+	.resume		= tegra124_cpu_clock_resume,
+#endif
 };
 
 static const struct of_device_id pmc_match[] __initconst = {
-- 
1.8.4

[PATCH 2/7] ARM: tegra: add flow controller to support suspend for Tegra124

[Joseph Lo]

Enable the configuration of flow controller to support the last CPU
(CPU0) suspend function with cluster power down.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/flowctrl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index 5348543..ce8ab8a 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -87,6 +87,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		/* clear wfe bitmap */
 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
 		/* clear wfi bitmap */
@@ -125,6 +126,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		/* clear wfe bitmap */
 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
 		/* clear wfi bitmap */
-- 
1.8.4

[PATCH 3/7] ARM: tegra: hook tegra_cpu_tear_down for Tegra124

[Joseph Lo]

Hook the tegra_cpu_tear_down function for Tegra124 to support platform
suspend.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/pm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 36ed88a..14e75b7 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -59,8 +59,10 @@ static void tegra_tear_down_cpu_init(void)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
 			tegra_tear_down_cpu = tegra30_tear_down_cpu;
 		break;
 	}
-- 
1.8.4

[PATCH 4/7] ARM: tegra: add LP1 support code for Tegra124

[Joseph Lo]

The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
need to update the difference of the register address, then we can
continue to share the code.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/iomap.h         |  3 +++
 arch/arm/mach-tegra/sleep-tegra30.S | 36 +++++++++++++++++++++++++++++-------
 2 files changed, 32 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index cbee57f..26b1c2a 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -105,6 +105,9 @@
 #define TEGRA_EMC1_BASE			0x7001A800
 #define TEGRA_EMC1_SIZE			SZ_2K
 
+#define TEGRA124_EMC_BASE		0x7001B000
+#define TEGRA124_EMC_SIZE		SZ_2K
+
 #define TEGRA_CSITE_BASE		0x70040000
 #define TEGRA_CSITE_SIZE		SZ_256K
 
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index c6fc15c..e65a831 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -408,8 +408,12 @@ _pll_m_c_x_done:
 	cmp	r10, #TEGRA30
 	movweq	r0, #:lower16:TEGRA_EMC_BASE	@ r0 reserved for emc base
 	movteq	r0, #:upper16:TEGRA_EMC_BASE
-	movwne	r0, #:lower16:TEGRA_EMC0_BASE
-	movtne	r0, #:upper16:TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA114
+	movweq	r0, #:lower16:TEGRA_EMC0_BASE
+	movteq	r0, #:upper16:TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA124
+	movweq	r0, #:lower16:TEGRA124_EMC_BASE
+	movteq	r0, #:upper16:TEGRA124_EMC_BASE
 
 exit_self_refresh:
 	ldr	r1, [r5, #0xC]		@ restore EMC_XM2VTTGENPADCTRL
@@ -554,15 +558,25 @@ tegra114_sdram_pad_address:
 	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL			@0x2c
 	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30
 
+tegra124_sdram_pad_address:
+	.word	TEGRA124_EMC_BASE + EMC_CFG				@0x0
+	.word	TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL			@0x4
+	.word	TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL		@0x8
+	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL		@0xc
+	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2		@0x10
+	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
+	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
+	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
+
 tegra30_sdram_pad_size:
 	.word	tegra114_sdram_pad_address - tegra30_sdram_pad_address
 
 tegra114_sdram_pad_size:
-	.word	tegra30_sdram_pad_size - tegra114_sdram_pad_address
+	.word	tegra124_sdram_pad_address - tegra114_sdram_pad_address
 
 	.type	tegra30_sdram_pad_save, %object
 tegra30_sdram_pad_save:
-	.rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
+	.rept (tegra124_sdram_pad_address - tegra114_sdram_pad_address) / 4
 	.long	0
 	.endr
 
@@ -698,8 +712,13 @@ tegra30_sdram_self_refresh:
 	cmp	r10, #TEGRA30
 	adreq	r2, tegra30_sdram_pad_address
 	ldreq	r3, tegra30_sdram_pad_size
-	adrne	r2, tegra114_sdram_pad_address
-	ldrne	r3, tegra114_sdram_pad_size
+	cmp	r10, #TEGRA114
+	adreq	r2, tegra114_sdram_pad_address
+	ldreq	r3, tegra114_sdram_pad_size
+	cmp	r10, #TEGRA124
+	adreq	r2, tegra124_sdram_pad_address
+	ldreq	r3, tegra30_sdram_pad_size
+
 	mov	r9, #0
 
 padsave:
@@ -717,7 +736,10 @@ padsave_done:
 
 	cmp	r10, #TEGRA30
 	ldreq	r0, =TEGRA_EMC_BASE	@ r0 reserved for emc base addr
-	ldrne	r0, =TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA114
+	ldreq	r0, =TEGRA_EMC0_BASE
+	cmp	r10, #TEGRA124
+	ldreq	r0, =TEGRA124_EMC_BASE
 
 enter_self_refresh:
 	cmp	r10, #TEGRA30
-- 
1.8.4

[PATCH 5/7] ARM: tegra: hook the LP1 iram code area and sleep_core function for Tegra124

[Joseph Lo]

To support LP1, we need to hook sleep_core function. That will turn off
MMU and jump to the IRAM to execute the rest of LP1 suspend function.
And we need the the LP1 IRAM addr to backup the original content and
replace it with LP1 low level support code.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/mach-tegra/Makefile | 1 +
 arch/arm/mach-tegra/pm.c     | 8 ++++++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index de3748e..019bb17 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -36,6 +36,7 @@ ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= cpuidle-tegra114.o
 endif
 obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= sleep-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 14e75b7..4ae0286 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -218,8 +218,10 @@ static bool tegra_lp1_iram_hook(void)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
 			tegra30_lp1_iram_hook();
 		break;
 	default:
@@ -246,8 +248,10 @@ static bool tegra_sleep_core_init(void)
 		break;
 	case TEGRA30:
 	case TEGRA114:
+	case TEGRA124:
 		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
 			tegra30_sleep_core_init();
 		break;
 	default:
-- 
1.8.4

[PATCH 6/7] ARM: tegra: enable Tegra RTC for Venice2

[Joseph Lo]

Enable the Tegra RTC device on Venice2. It also can be used as a wakeup
device when platform suspended.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/boot/dts/tegra124-venice2.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 5859ec2..279c7b5 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -14,6 +14,10 @@
 		status = "okay";
 	};
 
+	rtc at 7000e000 {
+		status = "okay";
+	};
+
 	pmc at 7000e400 {
 		nvidia,invert-interrupt;
 	};
-- 
1.8.4

[PATCH 7/7] ARM: tegra: enable LP1 suspend mode for Venice2

[Joseph Lo]

Enable LP1 suspend mode for Tegra124 Venice2 board.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
 arch/arm/boot/dts/tegra124-venice2.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 279c7b5..2a3615b 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -20,6 +20,13 @@
 
 	pmc at 7000e400 {
 		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <500>;
+		nvidia,cpu-pwr-off-time = <300>;
+		nvidia,core-pwr-good-time = <641 3845>;
+		nvidia,core-pwr-off-time = <61036>;
+		nvidia,core-power-req-active-high;
+		nvidia,sys-clock-req-active-high;
 	};
 
 	clocks {
-- 
1.8.4

[PATCH 1/7] clk: tegra124: add suspend/resume function for tegra_cpu_car_ops

[Joseph Lo]

On Wed, 2013-10-09 at 17:20 +0800, Joseph Lo wrote:
> Adding suspend/resume function for tegra_cpu_car_ops. We only save and
> restore the setting of the clock of CoreSight. Other clocks still need
> to be taken care by clock driver.
> 
> Cc: Mike Turquette <mturquette@linaro.org>
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
Sorry.
I forgot to mention this series depends on the patch series below.
[PATCH 0/5] Tegra124 clock support
[PATCH 1/4] clk: tegra124: add wait_for_reset and disable_clock for
tegra_cpu_car_ops

>  drivers/clk/tegra/clk-tegra124.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
> index c1c9330..66eb1f8a 100644
> --- a/drivers/clk/tegra/clk-tegra124.c
> +++ b/drivers/clk/tegra/clk-tegra124.c
> @@ -28,6 +28,7 @@
>  #include "clk.h"
>  #include "clk-id.h"
>  
> +#define CLK_SOURCE_CSITE 0x1d4
>  #define CLK_SOURCE_EMC 0x19c
>  #define CLK_SOURCE_XUSB_SS_SRC 0x610
>  
> @@ -109,6 +110,12 @@
>  /* Tegra CPU clock and reset control regs */
>  #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
>  
> +#ifdef CONFIG_PM_SLEEP
> +static struct cpu_clk_suspend_context {
> +	u32 clk_csite_src;
> +} tegra124_cpu_clk_sctx;
> +#endif
> +
>  static void __iomem *clk_base;
>  static void __iomem *pmc_base;
>  
> @@ -1139,9 +1146,29 @@ static void tegra124_disable_cpu_clock(u32 cpu)
>  	/* flow controller would take care in the power sequence. */
>  }
>  
> +#ifdef CONFIG_PM_SLEEP
> +static void tegra124_cpu_clock_suspend(void)
> +{
> +	/* switch coresite to clk_m, save off original source */
> +	tegra124_cpu_clk_sctx.clk_csite_src =
> +				readl(clk_base + CLK_SOURCE_CSITE);
> +	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
> +}
> +
> +static void tegra124_cpu_clock_resume(void)
> +{
> +	writel(tegra124_cpu_clk_sctx.clk_csite_src,
> +				clk_base + CLK_SOURCE_CSITE);
> +}
> +#endif
> +
>  static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
>  	.wait_for_reset	= tegra124_wait_cpu_in_reset,
>  	.disable_clock	= tegra124_disable_cpu_clock,
> +#ifdef CONFIG_PM_SLEEP
> +	.suspend	= tegra124_cpu_clock_suspend,
> +	.resume		= tegra124_cpu_clock_resume,
> +#endif
>  };
>  
>  static const struct of_device_id pmc_match[] __initconst = {

[PATCH 1/7] clk: tegra124: add suspend/resume function for tegra_cpu_car_ops

[Stephen Warren]

On 10/09/2013 03:20 AM, Joseph Lo wrote:
> Adding suspend/resume function for tegra_cpu_car_ops. We only save and
> restore the setting of the clock of CoreSight. Other clocks still need
> to be taken care by clock driver.

This series also mixes drivers/clk and arch/arm/mach-tegra changes. It
looks like there's no build-time dependency though, since this just
implements some extra hooks in tegra_cpu_car_ops, so I assume again this
clk patch will go through Mike's tree, and the rest of the patches
through the Tegra tree.

In the future, if there aren't any dependencies, it's best just to send
the two sets of changes separately.

Acked-by: Stephen Warren <swarren@nvidia.com>
(although it'd be nice to have Peter review it too)

[PATCH 4/7] ARM: tegra: add LP1 support code for Tegra124

[Stephen Warren]

On 10/09/2013 03:20 AM, Joseph Lo wrote:
> The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
> need to update the difference of the register address, then we can
> continue to share the code.

> diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S

>  tegra114_sdram_pad_size:
> -	.word	tegra30_sdram_pad_size - tegra114_sdram_pad_address
> +	.word	tegra124_sdram_pad_address - tegra114_sdram_pad_address

Why not put label tegra30_sdram_pad_address_end after the Tegra30 table
and tegra114_sdram_pad_address_end after the Tegra114 table, etc. That
way, you won't have to modify previous chips when you add a new one.

>  	.type	tegra30_sdram_pad_save, %object
>  tegra30_sdram_pad_save:

Shouldn't that name be tegra_xxx not tegra30_xxx, since I think the same
register save area is used for all SoCs?

> -	.rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
> +	.rept (tegra124_sdram_pad_address - tegra114_sdram_pad_address) / 4

I assume this is intended to reserve enough space to store all the saved
registers for the largest table of tegra30_sdram_pad_address,
tegra114_sdram_pad_address, tegra124_sdram_pad_address. I count more
entries in the existing Tegra114 table than the new Tegra124 table, so
I'm not sure this part of the change is correct.

Is there no way to do a max(tegra30 size, tegra114 size, tegra124 size)
so you don't have to pick manually which size to reserve here?

[PATCH 2/7] ARM: tegra: add flow controller to support suspend for Tegra124

[Stephen Warren]

On 10/09/2013 03:20 AM, Joseph Lo wrote:
> Enable the configuration of flow controller to support the last CPU
> (CPU0) suspend function with cluster power down.

I'd be tempted to squash together patches 2 and 3 since they're
basically doing the same kind of thing and are pretty trivial.

[PATCH 5/7] ARM: tegra: hook the LP1 iram code area and sleep_core function for Tegra124

[Stephen Warren]

On 10/09/2013 03:20 AM, Joseph Lo wrote:
> To support LP1, we need to hook sleep_core function. That will turn off
> MMU and jump to the IRAM to execute the rest of LP1 suspend function.
> And we need the the LP1 IRAM addr to backup the original content and
> replace it with LP1 low level support code.

Actually, I'd be tempted to squash all of patches 2-5 together.

[PATCH 6/7] ARM: tegra: enable Tegra RTC for Venice2

[Stephen Warren]

On 10/09/2013 03:20 AM, Joseph Lo wrote:
> Enable the Tegra RTC device on Venice2. It also can be used as a wakeup
> device when platform suspended.

> diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts

> +	rtc at 7000e000 {
> +		status = "okay";
> +	};

Does that mean this node has status = "disabled" in tegra124.dtsi? It
shouldn't have, since the RTC doesn't depend on any board-specific HW,
and hence can be enabled by default. We certainly have it enabled by
default on all previous SoCs.

I assume this was caused by one of the commits of yours I already
applied? Let's have a fixup patch to tegra124.dtsi.

[PATCH 4/7] ARM: tegra: add LP1 support code for Tegra124

[Joseph Lo]

On Thu, 2013-10-10 at 07:20 +0800, Stephen Warren wrote:
> On 10/09/2013 03:20 AM, Joseph Lo wrote:
> > The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
> > need to update the difference of the register address, then we can
> > continue to share the code.
> > -	.rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
> > +	.rept (tegra124_sdram_pad_address - tegra114_sdram_pad_address) / 4
> 
> I assume this is intended to reserve enough space to store all the saved
> registers for the largest table of tegra30_sdram_pad_address,
> tegra114_sdram_pad_address, tegra124_sdram_pad_address. I count more
> entries in the existing Tegra114 table than the new Tegra124 table, so
> I'm not sure this part of the change is correct.
> 
> Is there no way to do a max(tegra30 size, tegra114 size, tegra124 size)
> so you don't have to pick manually which size to reserve here?

I don't have a good way to achieve this, because we may have another new
SoC that may continue re-use these codes. Hence I need to keep
maintaining the max() function.

[PATCH 4/7] ARM: tegra: add LP1 support code for Tegra124

[Stephen Warren]

On 10/11/2013 01:38 AM, Joseph Lo wrote:
> On Thu, 2013-10-10 at 07:20 +0800, Stephen Warren wrote:
>> On 10/09/2013 03:20 AM, Joseph Lo wrote:
>>> The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
>>> need to update the difference of the register address, then we can
>>> continue to share the code.
>>> -	.rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
>>> +	.rept (tegra124_sdram_pad_address - tegra114_sdram_pad_address) / 4
>>
>> I assume this is intended to reserve enough space to store all the saved
>> registers for the largest table of tegra30_sdram_pad_address,
>> tegra114_sdram_pad_address, tegra124_sdram_pad_address. I count more
>> entries in the existing Tegra114 table than the new Tegra124 table, so
>> I'm not sure this part of the change is correct.
>>
>> Is there no way to do a max(tegra30 size, tegra114 size, tegra124 size)
>> so you don't have to pick manually which size to reserve here?
> 
> I don't have a good way to achieve this, because we may have another new
> SoC that may continue re-use these codes. Hence I need to keep
> maintaining the max() function.

Sure, but adding one entry to the max function is better than manually
calculating the size of each array and performing the max yourself.